diff options
Diffstat (limited to 'ecos/packages/devs/serial')
192 files changed, 57612 insertions, 0 deletions
diff --git a/ecos/packages/devs/serial/arm/aaed2000/current/ChangeLog b/ecos/packages/devs/serial/arm/aaed2000/current/ChangeLog new file mode 100644 index 0000000..b313235 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aaed2000/current/ChangeLog @@ -0,0 +1,41 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_aaed2000.cdl: Remove irrelevant doc link. + +2001-11-14 Jesper Skov <jskov@redhat.com> + + * src/aaed2000_serial.c (aaed2000_serial_DSR): Reworked a little + to fill/empty FIFO. + +2001-11-13 Jesper Skov <jskov@redhat.com> + + * src/aaed2000_serial.c: Removed ser1 structures. Fix reader. Make + DSR loop to empty FIFO. + +2001-11-12 Jesper Skov <jskov@redhat.com> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/aaed2000/current/cdl/ser_arm_aaed2000.cdl b/ecos/packages/devs/serial/arm/aaed2000/current/cdl/ser_arm_aaed2000.cdl new file mode 100644 index 0000000..97d8faf --- /dev/null +++ b/ecos/packages/devs/serial/arm/aaed2000/current/cdl/ser_arm_aaed2000.cdl @@ -0,0 +1,159 @@ +# ==================================================================== +# +# ser_arm_aaed2000.cdl +# +# eCos serial Agilent/AAED2000 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: jskov +# Date: 2001-11-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_AAED2000 { + display "ARM AAED2000 serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_ARM9_AAED2000 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + Agilent AAED2000." + + compile -library=libextras.a aaed2000_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_aaed2000.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AAED2000_SERIAL0 { + display "Agilent AAED2000-1 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Agilent AAED2000." + + cdl_option CYGDAT_IO_SERIAL_ARM_AAED2000_SERIAL0_NAME { + display "Device name for the Agilent AAED2000-1 serial port driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the Agilent AAED2000." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BAUD { + display "Baud rate for the Agilent AAED2000 serial port driver" + flavor data + legal_values { 1200 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the Agilent AAED2000." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BUFSIZE { + display "Buffer size for the Agilent AAED2000 serial port driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the Agilent AAED2000 serial driver." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AAED2000_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_AAED2000_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_AAED2000_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AAED2000_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_AAED2000_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_AAED2000_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"aaed2000\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_aaed2000.cdl diff --git a/ecos/packages/devs/serial/arm/aaed2000/current/src/aaed2000_serial.c b/ecos/packages/devs/serial/arm/aaed2000/current/src/aaed2000_serial.c new file mode 100644 index 0000000..477e463 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aaed2000/current/src/aaed2000_serial.c @@ -0,0 +1,338 @@ +//========================================================================== +// +// io/serial/arm/aaed2000_serial.c +// +// Agilent AAED2000 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas, jskov +// Contributors:gthomas, jskov +// Date: 2001-11-12 +// Purpose: AAED2000 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> // interrupt +#include <cyg/hal/hal_io.h> // register base +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#include "aaed2000_serial.h" + +typedef struct aaed2000_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} aaed2000_serial_info; + +static bool aaed2000_serial_init(struct cyg_devtab_entry *tab); +static bool aaed2000_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo aaed2000_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char aaed2000_serial_getc(serial_channel *chan); +static Cyg_ErrNo aaed2000_serial_set_config(serial_channel *chan, + cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void aaed2000_serial_start_xmit(serial_channel *chan); +static void aaed2000_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 aaed2000_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void aaed2000_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(aaed2000_serial_funs, + aaed2000_serial_putc, + aaed2000_serial_getc, + aaed2000_serial_set_config, + aaed2000_serial_start_xmit, + aaed2000_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_AAED2000_SERIAL0 +static aaed2000_serial_info aaed2000_serial_info0 = {0x80000800, + CYGNUM_HAL_INTERRUPT_UART3INTR}; +#if CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BUFSIZE > 0 +static unsigned char aaed2000_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BUFSIZE]; +static unsigned char aaed2000_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(aaed2000_serial_channel0, + aaed2000_serial_funs, + aaed2000_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &aaed2000_serial_out_buf0[0], sizeof(aaed2000_serial_out_buf0), + &aaed2000_serial_in_buf0[0], sizeof(aaed2000_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(aaed2000_serial_channel0, + aaed2000_serial_funs, + aaed2000_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AAED2000_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(aaed2000_serial_io0, + CYGDAT_IO_SERIAL_ARM_AAED2000_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + aaed2000_serial_init, + aaed2000_serial_lookup, // Serial driver may need initializing + &aaed2000_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AAED2000_SERIAL0 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +aaed2000_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = aaed2000_chan->base; + unsigned short baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr, _intm; + if (baud_divisor == 0) return false; + + // Register writes don't take effect till the UART is enabled. + HAL_WRITE_UINT32(base+AAEC_UART_CTRL, AAEC_UART_CTRL_ENAB); + + // Disable port interrupts while changing hardware + HAL_READ_UINT32(base+AAEC_UART_INTM, _intm); + HAL_WRITE_UINT32(base+AAEC_UART_INTM, 0); + + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT32(base+AAEC_UART_BAUD, baud_divisor); + if (init) { + _lcr |= AAEC_UART_LCR_FIFO; // Enable FIFO + if (chan->out_cbuf.len != 0) { + _intm = AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS; + } else { + _intm = 0; + } + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + + // Set line control and (re)enable interrupts + HAL_WRITE_UINT32(base+AAEC_UART_LCR, _lcr); + HAL_WRITE_UINT32(base+AAEC_UART_INTM, _intm); + + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +aaed2000_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("AAED2000 SERIAL init - dev: 0x%08x.%d\n", + aaed2000_chan->base, aaed2000_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(aaed2000_chan->int_num, + 1, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + aaed2000_serial_ISR, + aaed2000_serial_DSR, + &aaed2000_chan->serial_interrupt_handle, + &aaed2000_chan->serial_interrupt); + cyg_drv_interrupt_attach(aaed2000_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(aaed2000_chan->int_num); + } + aaed2000_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +aaed2000_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +aaed2000_serial_putc(serial_channel *chan, unsigned char c) +{ + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = aaed2000_chan->base; + cyg_uint32 _status; + + HAL_READ_UINT32(base+AAEC_UART_STATUS, _status); + if (_status & AAEC_UART_STATUS_TxFF) { + // No space + return false; + } else { + // Transmit buffer is empty + HAL_WRITE_UINT32(base+AAEC_UART_DATA, (cyg_uint32)c); + return true; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +aaed2000_serial_getc(serial_channel *chan) +{ + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = aaed2000_chan->base; + cyg_uint32 _status; + cyg_uint32 _c; + + do { + HAL_READ_UINT32(base+AAEC_UART_STATUS, _status); + } while (_status & AAEC_UART_STATUS_RxFE); + + HAL_READ_UINT32(base+AAEC_UART_DATA, _c); + return (unsigned char)_c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +aaed2000_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != aaed2000_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +aaed2000_serial_start_xmit(serial_channel *chan) +{ + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = aaed2000_chan->base; + cyg_uint32 _intm; + + HAL_READ_UINT32(base+AAEC_UART_INTM, _intm); + _intm |= AAEC_UART_INT_TIS; + HAL_WRITE_UINT32(base+AAEC_UART_INTM, _intm); +} + +// Disable the transmitter on the device +static void +aaed2000_serial_stop_xmit(serial_channel *chan) +{ + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = aaed2000_chan->base; + cyg_uint32 _intm; + + HAL_READ_UINT32(base+AAEC_UART_INTM, _intm); + _intm &= ~AAEC_UART_INT_TIS; + HAL_WRITE_UINT32(base+AAEC_UART_INTM, _intm); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +aaed2000_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(aaed2000_chan->int_num); + cyg_drv_interrupt_acknowledge(aaed2000_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +aaed2000_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = aaed2000_chan->base; + cyg_uint32 _intres, _c; + + HAL_READ_UINT32(base+AAEC_UART_INTRES, _intres); + _intres &= (AAEC_UART_INT_TIS | AAEC_UART_INT_RIS | AAEC_UART_INT_RTIS); + while (_intres) { + + // Empty Rx FIFO + if (_intres & (AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS)) { + HAL_READ_UINT32(base+AAEC_UART_DATA, _c); + (chan->callbacks->rcv_char)(chan, (unsigned char)_c); + } + + // Fill into Tx FIFO. xmt_char will mask the interrupt when it + // runs out of chars, so doing this in a loop is OK. + if (_intres & AAEC_UART_INT_TIS) { + (chan->callbacks->xmt_char)(chan); + } + + HAL_READ_UINT32(base+AAEC_UART_INTRES, _intres); + _intres &= (AAEC_UART_INT_TIS | AAEC_UART_INT_RIS | AAEC_UART_INT_RTIS); + } + + cyg_drv_interrupt_unmask(aaed2000_chan->int_num); +} diff --git a/ecos/packages/devs/serial/arm/aaed2000/current/src/aaed2000_serial.h b/ecos/packages/devs/serial/arm/aaed2000/current/src/aaed2000_serial.h new file mode 100644 index 0000000..32a7eb4 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aaed2000/current/src/aaed2000_serial.h @@ -0,0 +1,105 @@ +#ifndef CYGONCE_ARM_AAED2000_SERIAL_H +#define CYGONCE_ARM_AAED2000_SERIAL_H + +// ==================================================================== +// +// aaed2000_serial.h +// +// Device I/O - Description of Agilent AAED2000 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas, jskov +// Contributors:gthomas, jskov +// Date: 2001-11-12 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +static unsigned char select_word_length[] = { + AAEC_UART_LCR_WL5, // 5 bits / word (char) + AAEC_UART_LCR_WL6, + AAEC_UART_LCR_WL7, + AAEC_UART_LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + 0, // 1 stop bit + AAEC_UART_LCR_S2, // 1.5 stop bit (I think) + AAEC_UART_LCR_S2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + 0, // No parity + AAEC_UART_LCR_PEN|AAEC_UART_LCR_EP, // Even parity + AAEC_UART_LCR_PEN, // Odd parity + 0, // Mark parity + 0, // Space parity +}; + +// Baud rate values, based on 7.3728MHz clock +// #define BAUD_RATE(_n_) ((7372800/((_n_)*16))-1) + +static unsigned short select_baud[] = { + 0, // Unused + 0x23ff, // 50 + 0x17ff, // 75 + 0x105c, // 110 + 0x0d60, // 134.5 + 0x0bff, // 150 + 0x08ff, // 200 + 0x05ff, // 300 + 0x02ff, // 600 + 0x017f, // 1200 + 0x00ff, // 1800 + 0x00bf, // 2400 + 0x007f, // 3600 + 0x005f, // 4800 + 0x003f, // 7200 + 0x002f, // 9600 + 0x001f, // 14400 + 0x0017, // 19200 + 0x000b, // 38400 + 0x0007, // 57600 + 0x0003, // 115200 + 0x0001, // 230400 +}; + +#endif // CYGONCE_ARM_AAED2000_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/aeb/current/ChangeLog b/ecos/packages/devs/serial/arm/aeb/current/ChangeLog new file mode 100644 index 0000000..6f9b108 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aeb/current/ChangeLog @@ -0,0 +1,1190 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_aeb.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_aeb.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_arm_aeb.cdl: Moved testing parameters here. + +2000-09-06 Gary Thomas <gthomas@redhat.com> + + * src/aeb_serial.h: Define baud rates for 57600 & 115200. + Note: these are untested at this time. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/aeb_serial.c (aeb_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_arm_aeb.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/aeb/current/cdl/ser_arm_aeb.cdl b/ecos/packages/devs/serial/arm/aeb/current/cdl/ser_arm_aeb.cdl new file mode 100644 index 0000000..1c4a2f8 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aeb/current/cdl/ser_arm_aeb.cdl @@ -0,0 +1,210 @@ +# ==================================================================== +# +# ser_arm_aeb.cdl +# +# eCos serial ARM/AEB configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_AEB { + display "ARM AEB-1 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_AEB + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + ARM AEB-1." + + compile -library=libextras.a aeb_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_aeb.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_AEB_SERIAL0 { + display "ARM AEB-1 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM AEB-1 + port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_AEB_SERIAL0_NAME { + display "Device name for the ARM AEB-1 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the ARM + AEB-1 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BAUD { + display "Baud rate for the ARM AEB-1 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM AEB-1 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BUFSIZE { + display "Buffer size for the ARM AEB-1 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the ARM AEB-1 port 0." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_AEB_SERIAL1 { + display "ARM AEB-1 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM + AEB-1 port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_AEB_SERIAL1_NAME { + display "Device name for the ARM AEB-1 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + ARM AEB-1 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BAUD { + display "Baud rate for the ARM AEB-1 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM AEB-1 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BUFSIZE { + display "Buffer size for the ARM AEB-1 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ARM AEB-1 port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_AEB_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_AEB_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_AEB_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AEB_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_AEB_SERIAL1 + + implements CYGINT_IO_SERIAL_TEST_SKIP_38400 + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_AEB_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armaeb\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_aeb.cdl diff --git a/ecos/packages/devs/serial/arm/aeb/current/src/aeb_serial.c b/ecos/packages/devs/serial/arm/aeb/current/src/aeb_serial.c new file mode 100644 index 0000000..761e456 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aeb/current/src/aeb_serial.c @@ -0,0 +1,344 @@ +//========================================================================== +// +// io/serial/arm/aeb_serial.c +// +// ARM AEB-1 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: AEB-1 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_AEB + +#include "aeb_serial.h" + +typedef struct aeb_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} aeb_serial_info; + +static bool aeb_serial_init(struct cyg_devtab_entry *tab); +static bool aeb_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo aeb_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char aeb_serial_getc(serial_channel *chan); +static Cyg_ErrNo aeb_serial_set_config(serial_channel *chan, + cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void aeb_serial_start_xmit(serial_channel *chan); +static void aeb_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 aeb_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void aeb_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(aeb_serial_funs, + aeb_serial_putc, + aeb_serial_getc, + aeb_serial_set_config, + aeb_serial_start_xmit, + aeb_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_AEB_SERIAL0 +static aeb_serial_info aeb_serial_info0 = {0xFFFF0000, + CYGNUM_HAL_INTERRUPT_UART0}; +#if CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BUFSIZE > 0 +static unsigned char aeb_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BUFSIZE]; +static unsigned char aeb_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(aeb_serial_channel0, + aeb_serial_funs, + aeb_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &aeb_serial_out_buf0[0], sizeof(aeb_serial_out_buf0), + &aeb_serial_in_buf0[0], sizeof(aeb_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(aeb_serial_channel0, + aeb_serial_funs, + aeb_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AEB_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(aeb_serial_io0, + CYGDAT_IO_SERIAL_ARM_AEB_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + aeb_serial_init, + aeb_serial_lookup, // Serial driver may need initializing + &aeb_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AEB_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_AEB_SERIAL1 +static aeb_serial_info aeb_serial_info1 = {0xFFFF0400, + CYGNUM_HAL_INTERRUPT_UART1}; +#if CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BUFSIZE > 0 +static unsigned char aeb_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BUFSIZE]; +static unsigned char aeb_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(aeb_serial_channel1, + aeb_serial_funs, + aeb_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &aeb_serial_out_buf1[0], sizeof(aeb_serial_out_buf1), + &aeb_serial_in_buf1[0], sizeof(aeb_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(aeb_serial_channel1, + aeb_serial_funs, + aeb_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(aeb_serial_io1, + CYGDAT_IO_SERIAL_ARM_AEB_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + aeb_serial_init, + aeb_serial_lookup, // Serial driver may need initializing + &aeb_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AEB_SERIAL1 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +aeb_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; + unsigned short baud_divisor = select_baud[new_config->baud]; + unsigned char _lcr, _ier; + if (baud_divisor == 0) return false; + _ier = port->REG_IER; + port->REG_IER = 0; // Disable port interrupts while changing hardware + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + port->REG_LCR = _lcr; + port->REG_LCR |= LCR_DL; + port->REG_MDL = baud_divisor >> 8; + port->REG_LDL = baud_divisor & 0xFF; + port->REG_LCR &= ~LCR_DL; + if (init) { + port->REG_FCR = 0x07; // Enable and clear FIFO + if (chan->out_cbuf.len != 0) { + port->REG_IER = IER_RCV; + } else { + port->REG_IER = 0; + } + port->REG_MCR = MCR_INT|MCR_DTR|MCR_RTS; // Master interrupt enable + } else { + port->REG_IER = _ier; + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +aeb_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("AEB SERIAL init - dev: %x.%d\n", aeb_chan->base, aeb_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(aeb_chan->int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + aeb_serial_ISR, + aeb_serial_DSR, + &aeb_chan->serial_interrupt_handle, + &aeb_chan->serial_interrupt); + cyg_drv_interrupt_attach(aeb_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(aeb_chan->int_num); + } + aeb_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +aeb_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +aeb_serial_putc(serial_channel *chan, unsigned char c) +{ + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; + if (port->REG_LSR & LSR_THE) { +// Transmit buffer is empty + port->REG_THR = c; + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +aeb_serial_getc(serial_channel *chan) +{ + unsigned char c; + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; + while ((port->REG_LSR & LSR_RSR) == 0) ; // Wait for char + c = port->REG_RHR; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +aeb_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != aeb_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +aeb_serial_start_xmit(serial_channel *chan) +{ + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; + port->REG_IER |= IER_XMT; // Enable xmit interrupt +} + +// Disable the transmitter on the device +static void +aeb_serial_stop_xmit(serial_channel *chan) +{ + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; + port->REG_IER &= ~IER_XMT; // Disable xmit interrupt +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +aeb_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(aeb_chan->int_num); + cyg_drv_interrupt_acknowledge(aeb_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +aeb_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; + unsigned char isr; + isr = port->REG_ISR & 0x0E; + if (isr == ISR_Tx) { + (chan->callbacks->xmt_char)(chan); + } else if (isr == ISR_Rx) { + (chan->callbacks->rcv_char)(chan, port->REG_RHR); + } + cyg_drv_interrupt_unmask(aeb_chan->int_num); +} +#endif diff --git a/ecos/packages/devs/serial/arm/aeb/current/src/aeb_serial.h b/ecos/packages/devs/serial/arm/aeb/current/src/aeb_serial.h new file mode 100644 index 0000000..e436d39 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aeb/current/src/aeb_serial.h @@ -0,0 +1,162 @@ +#ifndef CYGONCE_ARM_AEB_SERIAL_H +#define CYGONCE_ARM_AEB_SERIAL_H + +// ==================================================================== +// +// aeb_serial.h +// +// Device I/O - Description of ARM AEB-1 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on ARM AEB-1 + +struct serial_port { + unsigned char _byte[32]; +}; + +#define REG(n) _byte[n*4] + +// Receive control registers +#define REG_RHR REG(0) // Receive holding register +#define REG_ISR REG(2) // Interrupt status register +#define REG_LSR REG(5) // Line status register +#define REG_MSR REG(6) // Modem status register +#define REG_SCR REG(7) // Scratch register + +// Transmit control registers +#define REG_THR REG(0) // Transmit holding register +#define REG_IER REG(1) // Interrupt enable register +#define REG_FCR REG(2) // FIFO control register +#define REG_LCR REG(3) // Line control register +#define REG_MCR REG(4) // Modem control register +#define REG_LDL REG(0) // LSB of baud rate +#define REG_MDL REG(1) // MSB of baud rate + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_Tx 0x02 +#define ISR_Rx 0x04 + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// Baud rate values, based on raw 24MHz clock + +static unsigned short select_baud[] = { + 0, // Unused + 10000*3, // 50 + 6667*3, // 75 + 4545*3, // 110 + 3717*3, // 134.5 + 3333*3, // 150 + 0, // 200 + 1667*3, // 300 + 833*3, // 600 + 417*3, // 1200 + 277*3, // 1800 + 208*3, // 2400 + 139*3, // 3600 + 104*3, // 4800 + 69*3, // 7200 + 52*3, // 9600 + (69*3)/2, // 14400 + 26*3, // 19200 + 13*3, // 38400 + 26, // 57600 + 13, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_ARM_AEB_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/aim711/current/ChangeLog b/ecos/packages/devs/serial/arm/aim711/current/ChangeLog new file mode 100755 index 0000000..785a5a7 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aim711/current/ChangeLog @@ -0,0 +1,36 @@ +2004-09-09 John Dallaway <jld@ecoscentric.com> + + * cdl/ser_arm_aim711.cdl: Implement CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510 and + CYGPKG_IO_SERIAL_ARM_AIM711_16X5X as CDL components rather than packages. + [ patch from Roland Cassebohm ] + + * cdl/ser_arm_aim711_16x5x.cdl, cdl/ser_arm_aim711_s3c4510.cdl: Remove obsolete + files. + +2003-10-30 Roland Cassebohm <roland.cassebohm@visionsystems.de> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/aim711/current/cdl/ser_arm_aim711.cdl b/ecos/packages/devs/serial/arm/aim711/current/cdl/ser_arm_aim711.cdl new file mode 100755 index 0000000..75b5968 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aim711/current/cdl/ser_arm_aim711.cdl @@ -0,0 +1,297 @@ +# ==================================================================== +# +# ser_arm_aim711.cdl +# +# eCos serial ARM Industrial Module AIM 711 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Lars.Lindqvist@combitechsystems.com, rcassebohm +# Contributors: jlarmour, rcassebohm +# Date: 2004-09-09 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_AIM711 { + display "ARM Industrial Module AIM 711 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_AIM711 + + include_dir cyg/io + description " + This package contains serial device drivers for the + ARM Industrial Module AIM 711." + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_aim711.h>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/ser_arm_aim711_16x5x.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_aim711.h>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_ARM_S3C4510_INL <cyg/io/ser_arm_aim711_s3c4510.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_ARM_S3C4510_CFG <pkgconf/io_serial_arm_aim711.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include <pkgconf/io_serial_arm_s3c4510.h>"; + puts $::cdl_header "#include <pkgconf/io_serial_generic_16x5x.h>"; + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_16X5X { + display "ARM Industrial Module AIM 711 16x5x serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_AIM711 + default_value 1 + + requires CYGPKG_ERROR + description " + This package contains serial device drivers for the + ARM Industrial Module AIM 711 for the 16550 serial + interface on board." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0 { + display "AIM 711 16X5X serial port 0 driver (COM1)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the AIM 711 16X5X + port 0, which is COM1 on the AIM 711." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_NAME { + display "Device name for the AIM 711 16X5X serial port 0 driver (COM1)" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option sets the name of the serial device for the AIM 711 + 16X5X port 0 (COM1)." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BAUD { + display "Baud rate for the AIM 711 16X5X serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + AIM 711 16X5X port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BUFSIZE { + display "Buffer size for the AIM 711 16X5X serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the AIM 711 16X5X port 0." + } + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510 { + display "ARM Industrial Module AIM 711 S3C4510 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_AIM711 + default_value 1 + + requires CYGPKG_ERROR + description " + This package contains serial device drivers for the + ARM Industrial Module AIM 711 for the internal serial + interface of the S3C4510." + + # FIXME: This really belongs in the SERIAL_ARM_S3C4510 package + cdl_interface CYGINT_IO_SERIAL_ARM_S3C4510_REQUIRED { + display "Generic s3c4510 serial driver required" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0 { + display "AIM 711 S3C4510 serial port 0 driver (service adapter)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the AIM 711 S3C4510 + port 0, which is on the AIM 711 the port on the service adapter." + + implements CYGINT_IO_SERIAL_ARM_S3C4510_REQUIRED + + cdl_option CYGDAT_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_NAME { + display "Device name for the AIM 711 S3C4510 serial port 0 driver (service adapter)" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the AIM 711 + S3C4510 port 0 (service adapter)." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BAUD { + display "Baud rate for the AIM 711 S3C4510 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + AIM 711 S3C4510 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BUFSIZE { + display "Buffer size for the AIM 711 S3C4510 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the AIM 711 S3C4510 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1 { + display "AIM 711 S3C4510 serial port 1 driver (COM2)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the AIM 711 + S3C4510 port 1, which is the COM2 on the AIM 711." + + implements CYGINT_IO_SERIAL_ARM_S3C4510_REQUIRED + + cdl_option CYGDAT_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_NAME { + display "Device name for the AIM 711 S3C4510 serial port 1 driver (COM2)" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the name of serial device for the + AIM 711 S3C4510 port 1 (COM2)." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BAUD { + display "Baud rate for the AIM 711 S3C4510 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + AIM 711 S3C4510 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BUFSIZE { + display "Buffer size for the AIM 711 S3C4510 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the AIM 711 S3C4510 port 1." + } + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_AIM711_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_AIM711_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AIM711_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"arm16x5x\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty2\"" + } + } +} + +# EOF ser_arm_aim711.cdl diff --git a/ecos/packages/devs/serial/arm/aim711/current/include/ser_arm_aim711_16x5x.inl b/ecos/packages/devs/serial/arm/aim711/current/include/ser_arm_aim711_16x5x.inl new file mode 100755 index 0000000..8768981 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aim711/current/include/ser_arm_aim711_16x5x.inl @@ -0,0 +1,124 @@ +//========================================================================== +// +// ser_arm_aim711_16x5x.inl +// +// ARM Industrial Module AIM 711 Serial I/O Interface Module +// (interrupt driven) for use with 16x5x driver. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2001-06-08 +// Purpose: Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification, based on raw 7.3728 MHz clock + +static unsigned short select_baud[] = { + 0, // Unused + 9216, // 50 + 6144, // 75 + 4189, // 110 + 3426, // 134.5 + 3072, // 150 + 2304, // 200 + 1537, // 300 + 768, // 600 + 384, // 1200 + 256, // 1800 + 192, // 2400 + 128, // 3600 + 96, // 4800 + 64, // 7200 + 48, // 9600 + 32, // 14400 + 24, // 19200 + 12, // 38400 + 8, // 57600 + 4, // 115200 + 2, // 230400 + 1, // 460800 +}; + +#ifdef CYGPKG_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0 +static pc_serial_info aim711_16x5x_serial_info0 = {0x7fd0008, + CYGNUM_HAL_INTERRUPT_EXT0}; +#if CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BUFSIZE > 0 +static unsigned char aim711_16x5x_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BUFSIZE]; +static unsigned char aim711_16x5x_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(aim711_16x5x_serial_channel0, + pc_serial_funs, + aim711_16x5x_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &aim711_16x5x_serial_out_buf0[0], sizeof(aim711_16x5x_serial_out_buf0), + &aim711_16x5x_serial_in_buf0[0], sizeof(aim711_16x5x_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(aim711_16x5x_serial_channel0, + pc_serial_funs, + aim711_16x5x_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(aim711_16x5x_serial_io0, + CYGDAT_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &aim711_16x5x_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AIM711_16X5X_SERIAL0 + +// EOF ser_arm_aim711_16x5x.inl diff --git a/ecos/packages/devs/serial/arm/aim711/current/include/ser_arm_aim711_s3c4510.inl b/ecos/packages/devs/serial/arm/aim711/current/include/ser_arm_aim711_s3c4510.inl new file mode 100755 index 0000000..024bfb0 --- /dev/null +++ b/ecos/packages/devs/serial/arm/aim711/current/include/ser_arm_aim711_s3c4510.inl @@ -0,0 +1,140 @@ +// ==================================================================== +// +// ser_arm_aim711_s3c4510.inl +// +// ARM Industrial Module AIM 711 Serial I/O Interface Module +// (interrupt driven) for use with s3c4510 driver. +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Lars.Lindqvist@combitechsystems.com +// Contributors: jlarmour +// Date: 2001-10-19 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/hal.h> // Value CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED needed +#include <cyg/hal/hal_intr.h> + +#define CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED CYGNUM_HAL_CPUCLOCK + +#ifdef CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0 +static s3c4510_serial_info s3c4510_serial_info0 = {0x07FFd000, + CYGNUM_HAL_INTERRUPT_UART0_TX, + CYGNUM_HAL_INTERRUPT_UART0_RX}; +#if CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BUFSIZE > 0 +static unsigned char s3c4510_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BUFSIZE]; +static unsigned char s3c4510_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(s3c4510_serial_channel0, + s3c4510_serial_funs, + s3c4510_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &s3c4510_serial_out_buf0[0], sizeof(s3c4510_serial_out_buf0), + &s3c4510_serial_in_buf0[0], sizeof(s3c4510_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(s3c4510_serial_channel0, + s3c4510_serial_funs, + s3c4510_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(s3c4510_serial_io0, + CYGDAT_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + s3c4510_serial_init, + s3c4510_serial_lookup, // Serial driver may need initializing + &s3c4510_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1 +static s3c4510_serial_info s3c4510_serial_info1 = {0x07FFe000, + CYGNUM_HAL_INTERRUPT_UART1_TX, + CYGNUM_HAL_INTERRUPT_UART1_RX}; +#if CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BUFSIZE > 0 +static unsigned char s3c4510_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BUFSIZE]; +static unsigned char s3c4510_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(s3c4510_serial_channel1, + s3c4510_serial_funs, + s3c4510_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &s3c4510_serial_out_buf1[0], sizeof(s3c4510_serial_out_buf1), + &s3c4510_serial_in_buf1[0], sizeof(s3c4510_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(s3c4510_serial_channel1, + s3c4510_serial_funs, + s3c4510_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(s3c4510_serial_io1, + CYGDAT_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + s3c4510_serial_init, + s3c4510_serial_lookup, // Serial driver may need initializing + &s3c4510_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510_SERIAL1 + +// EOF ser_arm_aim711_s3c4510.inl diff --git a/ecos/packages/devs/serial/arm/at91/current/ChangeLog b/ecos/packages/devs/serial/arm/at91/current/ChangeLog new file mode 100644 index 0000000..3528435 --- /dev/null +++ b/ecos/packages/devs/serial/arm/at91/current/ChangeLog @@ -0,0 +1,102 @@ +2007-06-01 Jim Seymour <jim@cipher.com> + + * src/at91_serial.c (at91_serial_DSR): Remove CYG_FAIL if receive + buffer fills up; eliminate compiler warning when setting "end" + pointer. + +2006-03-05 Oliver Munz <munz@speag.ch> + + * src/at91_serial.c (at91_serial_ISR): Only call the DSR if there + is work to do. + +2006-02-28 Andrew Lunn <andrew.lunn@ascom.ch> + Oliver Munz <munz@speag.ch> + + * src/at91_serial.c (at91_serial_config_port): Enable the DMA + if the control register exists. + +2006-02-19 Andrew Lunn <andrew.lunn@ascom.ch> + + * src/at91_serial.c (at91_serial_lookup): Enable the peripheral + clock at lookup time to keep the power usage low. + +2004-11-10 Sebastian Block <sebastianblock@gmx.net> + + * src/at91_serial.c: Added third port + +2004-01-26 Andrew Lunn <andrew.lunn@ascom.ch> + + * src/at91_serial.c (at91_serial_getc_polled) + * src/ay91_serial.c (at91_serial_putc_polled): + Only define these functions if polled IO is configured so + avoiding compiler warnings. + +2004-01-16 Thomas Koeller <thomas.koeller@baslerweb.com> + + * src/at91_serial.c: If both a transmitter and a receiver + interrupt arrive at the same time, process the receiver + interrupt first. + +2003-11-21 Thomas Koeller <thomas.koeller@baslerweb.com> + + * src/at91_serial.c: Fix endless loop that would occur if + high-level driver was not ready to accept data received. + +2003-11-07 Thomas Koeller <thomas.koeller@baslerweb.com> + + * src/at91_serial.c: + * cdl/ser_arm_at91.cdl: Major rewrite to achieve reliable + operation at higher baud rates. + +2003-10-16 Nick Garnett <nickg@balti.calivar.com> + + * src/at91_serial.c (at91_serial_config_port): Added update of + channel configuration, which was missing. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_at91.cdl: Remove irrelevant doc link. + +2001-09-20 Jesper Skov <jskov@redhat.com> + + * src/at91_serial.c (at91_serial_init): Use valid interrupt priority. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_at91.cdl: + Fix 234000->230400 typo. + +2001-08-14 Jonathan Larmour <jlarmour@redhat.com> + + * src/at91_serial.c (at91_serial_stop_xmit): Write to IDR, not IER. + (at91_serial_ISR): Return CYG_ISR_HANDLED. + +2001-07-24 Gary Thomas <gthomas@redhat.com> + + * src/at91_serial.h: + * src/at91_serial.c: + * cdl/ser_arm_at91.cdl: New file(s) - initial package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/at91/current/cdl/ser_arm_at91.cdl b/ecos/packages/devs/serial/arm/at91/current/cdl/ser_arm_at91.cdl new file mode 100644 index 0000000..914c05b --- /dev/null +++ b/ecos/packages/devs/serial/arm/at91/current/cdl/ser_arm_at91.cdl @@ -0,0 +1,292 @@ +# ==================================================================== +# +# ser_arm_at91.cdl +# +# eCos serial Atmel AT91 (ARM) configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Contributors: tkoeller +# Date: 2001-07-24 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_AT91 { + display "Atmel AT91 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_AT91 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + Atmel AT91." + + implements CYGINT_IO_SERIAL_BLOCK_TRANSFER + + compile -library=libextras.a at91_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_at91.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0 { + display "Atmel AT91 serial port 0 driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for the Atmel AT91 + port 0 (serial A)." + + cdl_option CYGDAT_IO_SERIAL_ARM_AT91_SERIAL0_NAME { + display "Device name for Atmel AT91 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + Atmel AT91 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BAUD { + display "Baud rate for the Atmel AT91 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Atmel AT91 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE { + display "Buffer size for the Atmel AT91 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the Atmel AT91 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_RCV_CHUNK_SIZE { + display "Receive data chunk size" + flavor data + legal_values 1 to 65519 + default_value 1 + description " + This parameter can be used to reduce the number of interrupts + that must be processed by the driver. An interrupt will only + be generated if either this many data bytes have been received + or the receiver has been idle for some time. This reduces + overall system load at the expense of making the driver less + responsive and using slightly more memory for buffering data. + Setting this parameter to 1 will give standard behavior." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1 { + display "Atmel AT91 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Atmel AT91 + port 1 (serial B)." + + cdl_option CYGDAT_IO_SERIAL_ARM_AT91_SERIAL1_NAME { + display "Device name for Atmel AT91 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device for the + Atmel AT91 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BAUD { + display "Baud rate for the Atmel AT91 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Atmel AT91 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE { + display "Buffer size for the Atmel AT91 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the Atmel AT91 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_RCV_CHUNK_SIZE { + display "Receive data chunk size" + flavor data + legal_values 1 to 65519 + default_value 1 + description " + This parameter can be used to reduce the number of interrupts + that must be processed by the driver. An interrupt will only + be generated if either this many data bytes have been received + or the receiver has been idle for some time. This reduces + overall system load at the expense of making the driver less + responsive and using slightly more memory for buffering data. + Setting this parameter to 1 will give standard behavior." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2 { + display "Atmel AT91 serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Atmel AT91 + port 2 (serial C)." + + cdl_option CYGDAT_IO_SERIAL_ARM_AT91_SERIAL2_NAME { + display "Device name for Atmel AT91 serial port 1 driver" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the name of the serial device for the + Atmel AT91 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BAUD { + display "Baud rate for the Atmel AT91 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Atmel AT91 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE { + display "Buffer size for the Atmel AT91 serial port 2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the Atmel AT91 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_RCV_CHUNK_SIZE { + display "Receive data chunk size" + flavor data + legal_values 1 to 65519 + default_value 1 + description " + This parameter can be used to reduce the number of interrupts + that must be processed by the driver. An interrupt will only + be generated if either this many data bytes have been received + or the receiver has been idle for some time. This reduces + overall system load at the expense of making the driver less + responsive and using slightly more memory for buffering data. + Setting this parameter to 1 will give standard behavior." + } +} + + + cdl_component CYGPKG_IO_SERIAL_ARM_AT91_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_AT91_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_AT91_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_AT91_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_AT91_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"eb40\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_at91.cdl diff --git a/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.c b/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.c new file mode 100644 index 0000000..26b0d14 --- /dev/null +++ b/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.c @@ -0,0 +1,650 @@ +//========================================================================== +// +// devs/serial/arm/at91/at91_serial.c +// +// Atmel AT91/EB40 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, tkoeller, sblock +// Date: 2001-07-24 +// Purpose: Atmel AT91/EB40 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/infra.h> +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <pkgconf/kernel.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> + +externC void * memcpy( void *, const void *, size_t ); + +#ifdef CYGPKG_IO_SERIAL_ARM_AT91 + +#include "at91_serial.h" + +#define RCVBUF_EXTRA 16 +#define RCV_TIMEOUT 10 + +#define SIFLG_NONE 0x00 +#define SIFLG_TX_READY 0x01 +#define SIFLG_XMIT_BUSY 0x02 +#define SIFLG_XMIT_CONTINUE 0x04 + +typedef struct at91_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + CYG_WORD stat; + int transmit_size; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; + cyg_uint8 *rcv_buffer[2]; + cyg_uint16 rcv_chunk_size; + cyg_uint8 curbuf; + cyg_uint8 flags; +} at91_serial_info; + +static bool at91_serial_init(struct cyg_devtab_entry *tab); +static bool at91_serial_putc_interrupt(serial_channel *chan, unsigned char c); +#if (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE == 0) +static bool at91_serial_putc_polled(serial_channel *chan, unsigned char c); +#endif +static Cyg_ErrNo at91_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char at91_serial_getc_interrupt(serial_channel *chan); +#if (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE == 0) +static unsigned char at91_serial_getc_polled(serial_channel *chan); +#endif +static Cyg_ErrNo at91_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void at91_serial_start_xmit(serial_channel *chan); +static void at91_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 at91_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void at91_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +#if (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE > 0) +static SERIAL_FUNS(at91_serial_funs_interrupt, + at91_serial_putc_interrupt, + at91_serial_getc_interrupt, + at91_serial_set_config, + at91_serial_start_xmit, + at91_serial_stop_xmit + ); +#endif + +#if (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE == 0) +static SERIAL_FUNS(at91_serial_funs_polled, + at91_serial_putc_polled, + at91_serial_getc_polled, + at91_serial_set_config, + at91_serial_start_xmit, + at91_serial_stop_xmit + ); +#endif + +#ifdef CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0 +static cyg_uint8 at91_serial_rcv_buffer_0 + [2][CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_RCV_CHUNK_SIZE + RCVBUF_EXTRA]; +static at91_serial_info at91_serial_info0 = { + base : (CYG_ADDRWORD) AT91_USART0, + int_num : CYGNUM_HAL_INTERRUPT_USART0, + rcv_chunk_size : CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_RCV_CHUNK_SIZE, + rcv_buffer : {at91_serial_rcv_buffer_0[0], at91_serial_rcv_buffer_0[1]} +}; + +#if CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE > 0 +static unsigned char at91_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE]; +static unsigned char at91_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(at91_serial_channel0, + at91_serial_funs_interrupt, + at91_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &at91_serial_out_buf0[0], sizeof(at91_serial_out_buf0), + &at91_serial_in_buf0[0], sizeof(at91_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(at91_serial_channel0, + at91_serial_funs_polled, + at91_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(at91_serial_io0, + CYGDAT_IO_SERIAL_ARM_AT91_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + at91_serial_init, + at91_serial_lookup, // Serial driver may need initializing + &at91_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1 + +#ifdef CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1 +static cyg_uint8 at91_serial_rcv_buffer_1 + [2][CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_RCV_CHUNK_SIZE + RCVBUF_EXTRA]; +static at91_serial_info at91_serial_info1 = { + base : (CYG_ADDRWORD) AT91_USART1, + int_num : CYGNUM_HAL_INTERRUPT_USART1, + rcv_chunk_size : CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_RCV_CHUNK_SIZE, + rcv_buffer : {at91_serial_rcv_buffer_1[0], at91_serial_rcv_buffer_1[1]} +}; +#if CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE > 0 +static unsigned char at91_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE]; +static unsigned char at91_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(at91_serial_channel1, + at91_serial_funs_interrupt, + at91_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &at91_serial_out_buf1[0], sizeof(at91_serial_out_buf1), + &at91_serial_in_buf1[0], sizeof(at91_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(at91_serial_channel1, + at91_serial_funs_polled, + at91_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(at91_serial_io1, + CYGDAT_IO_SERIAL_ARM_AT91_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + at91_serial_init, + at91_serial_lookup, // Serial driver may need initializing + &at91_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1 + + +#ifdef CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2 + +static cyg_uint8 at91_serial_rcv_buffer_2 + [2][CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_RCV_CHUNK_SIZE + RCVBUF_EXTRA]; +static at91_serial_info at91_serial_info2 = { + base : (CYG_ADDRWORD) AT91_USART2, + int_num : CYGNUM_HAL_INTERRUPT_USART2, + rcv_chunk_size : CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_RCV_CHUNK_SIZE, + rcv_buffer : {at91_serial_rcv_buffer_2[0], at91_serial_rcv_buffer_2[1]} +}; + +#if CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE > 0 +static unsigned char at91_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE]; +static unsigned char at91_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(at91_serial_channel2, + at91_serial_funs_interrupt, + at91_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &at91_serial_out_buf2[0], sizeof(at91_serial_out_buf2), + &at91_serial_in_buf2[0], sizeof(at91_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(at91_serial_channel2, + at91_serial_funs_polled, + at91_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(at91_serial_io2, + CYGDAT_IO_SERIAL_ARM_AT91_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + at91_serial_init, + at91_serial_lookup, // Serial driver may need initializing + &at91_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2 + + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +at91_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + at91_serial_info * const at91_chan = (at91_serial_info *)chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + cyg_uint32 parity = select_parity[new_config->parity]; + cyg_uint32 word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5]; + cyg_uint32 stop_bits = select_stop_bits[new_config->stop]; + + if ((word_length == 0xFF) || + (parity == 0xFF) || + (stop_bits == 0xFF)) { + return false; // Unsupported configuration + } + + // Reset device + HAL_WRITE_UINT32(base + AT91_US_CR, AT91_US_CR_RxRESET | AT91_US_CR_TxRESET); + + // Configuration + HAL_WRITE_UINT32(base + AT91_US_MR, parity | word_length | stop_bits); + + // Baud rate + HAL_WRITE_UINT32(base + AT91_US_BRG, AT91_US_BAUD(select_baud[new_config->baud])); + + // Disable all interrupts + HAL_WRITE_UINT32(base + AT91_US_IDR, 0xFFFFFFFF); + + // Start receiver + at91_chan->curbuf = 0; + HAL_WRITE_UINT32(base + AT91_US_RPR, (CYG_ADDRESS) at91_chan->rcv_buffer[0]); + HAL_WRITE_UINT32(base + AT91_US_RTO, RCV_TIMEOUT); + HAL_WRITE_UINT32(base + AT91_US_IER, AT91_US_IER_ENDRX | AT91_US_IER_TIMEOUT); + HAL_WRITE_UINT32(base + AT91_US_RCR, at91_chan->rcv_chunk_size); + + // Enable RX and TX + HAL_WRITE_UINT32( + base + AT91_US_CR, + AT91_US_CR_RxENAB | AT91_US_CR_TxENAB | AT91_US_CR_RSTATUS | AT91_US_CR_STTTO + ); + + // Enable the DMA is the control register exists +#ifdef AT91_US_PTCR + HAL_WRITE_UINT32(base + AT91_US_PTCR, + AT91_US_PTCR_RXTEN | + AT91_US_PTCR_TXTEN); +#endif + + if (new_config != &chan->config) { + chan->config = *new_config; + } + + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +at91_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel * const chan = (serial_channel *) tab->priv; + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + int res; + +#ifdef CYGDBG_IO_INIT + diag_printf("AT91 SERIAL init - dev: %x.%d\n", at91_chan->base, at91_chan->int_num); +#endif + at91_chan->curbuf = 0; + at91_chan->flags = SIFLG_NONE; + at91_chan->stat = 0; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(at91_chan->int_num, + 4, // Priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + at91_serial_ISR, + at91_serial_DSR, + &at91_chan->serial_interrupt_handle, + &at91_chan->serial_interrupt); + cyg_drv_interrupt_attach(at91_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(at91_chan->int_num); + } + res = at91_serial_config_port(chan, &chan->config, true); + return res; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +at91_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel * const chan = (serial_channel *) (*tab)->priv; + +#ifdef AT91_PMC_PCER + // Enable the peripheral clock to the device + at91_serial_info * const at91_chan = (at91_serial_info *)chan->dev_priv; + HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, + (1 << at91_chan->int_num)); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +at91_serial_putc_interrupt(serial_channel *chan, unsigned char c) +{ + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const bool res = (at91_chan->flags & SIFLG_XMIT_BUSY) == 0; + + if (res) { + const CYG_ADDRWORD base = at91_chan->base; + HAL_WRITE_UINT32(base + AT91_US_THR, c); + at91_chan->flags |= SIFLG_XMIT_BUSY; + } + return res; +} + +#if (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE == 0) +static bool +at91_serial_putc_polled(serial_channel *chan, unsigned char c) +{ + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + CYG_WORD32 w; + + while (HAL_READ_UINT32(base + AT91_US_CSR, w), (w & AT91_US_IER_TxRDY) == 0) + CYG_EMPTY_STATEMENT; + HAL_WRITE_UINT32(base + AT91_US_THR, c); + return true; +} +#endif + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +at91_serial_getc_interrupt(serial_channel *chan) +{ + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + CYG_WORD32 c; + + // Read data + HAL_READ_UINT32(base + AT91_US_RHR, c); + return (unsigned char) c; +} + +#if (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL1) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2) && CYGNUM_IO_SERIAL_ARM_AT91_SERIAL2_BUFSIZE == 0) +static unsigned char +at91_serial_getc_polled(serial_channel *chan) +{ + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + CYG_WORD32 c; + + while (HAL_READ_UINT32(base + AT91_US_CSR, c), (c & AT91_US_IER_RxRDY) == 0) + CYG_EMPTY_STATEMENT; + // Read data + HAL_READ_UINT32(base + AT91_US_RHR, c); + return (unsigned char) c; +} +#endif +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +at91_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != at91_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +at91_serial_start_xmit(serial_channel *chan) +{ + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + unsigned char * chars; + xmt_req_reply_t res; + + cyg_drv_dsr_lock(); + if ((at91_chan->flags & SIFLG_XMIT_CONTINUE) == 0) { + res = (chan->callbacks->data_xmt_req)(chan, 0xffff, &at91_chan->transmit_size, &chars); + switch (res) + { + case CYG_XMT_OK: + HAL_WRITE_UINT32(base + AT91_US_TPR, (CYG_WORD32) chars); + HAL_WRITE_UINT32(base + AT91_US_TCR, at91_chan->transmit_size); + at91_chan->flags |= SIFLG_XMIT_CONTINUE; + HAL_WRITE_UINT32(base + AT91_US_IER, AT91_US_IER_ENDTX); + break; + case CYG_XMT_DISABLED: + (chan->callbacks->xmt_char)(chan); // Kick transmitter + at91_chan->flags |= SIFLG_XMIT_CONTINUE; + HAL_WRITE_UINT32(base + AT91_US_IER, AT91_US_IER_TxRDY); + break; + default: + // No data or unknown error - can't do anything about it + break; + } + } + cyg_drv_dsr_unlock(); +} + +// Disable the transmitter on the device +static void +at91_serial_stop_xmit(serial_channel *chan) +{ + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + HAL_WRITE_UINT32(base + AT91_US_IDR, AT91_US_IER_TxRDY | AT91_US_IER_ENDTX); + at91_chan->flags &= ~SIFLG_XMIT_CONTINUE; +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +at91_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel * const chan = (serial_channel *) data; + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + CYG_WORD32 stat, mask; + cyg_uint32 retcode = 0; + + HAL_READ_UINT32(base + AT91_US_CSR, stat); + HAL_READ_UINT32(base + AT91_US_IMR, mask); + stat &= mask; + + if (stat & (AT91_US_IER_ENDRX | AT91_US_IER_TIMEOUT)) { + cyg_uint32 x; + HAL_WRITE_UINT32(base + AT91_US_IDR, AT91_US_IER_ENDRX | AT91_US_IER_TIMEOUT); + HAL_WRITE_UINT32(base + AT91_US_RCR, 0); + HAL_WRITE_UINT32(base + AT91_US_RTO, 0); + HAL_READ_UINT32(base + AT91_US_RPR, x); + HAL_WRITE_UINT32( + base + AT91_US_RCR, + (CYG_ADDRESS) at91_chan->rcv_buffer[at91_chan->curbuf] + + at91_chan->rcv_chunk_size + RCVBUF_EXTRA - x + ); + retcode = CYG_ISR_CALL_DSR; + } + + if (stat & (AT91_US_IER_TxRDY | AT91_US_IER_ENDTX)) { + HAL_WRITE_UINT32(base + AT91_US_IDR, AT91_US_IER_TxRDY | AT91_US_IER_ENDTX); + retcode = CYG_ISR_CALL_DSR; + } + at91_chan->stat |= stat; + + cyg_drv_interrupt_acknowledge(vector); + return retcode; +} + +// Serial I/O - high level interrupt handler (DSR) +static void +at91_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel * const chan = (serial_channel *) data; + at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = at91_chan->base; + CYG_WORD32 stat; + + cyg_drv_interrupt_mask(vector); + stat = at91_chan->stat; + at91_chan->stat = 0; + cyg_drv_interrupt_unmask(vector); + + if (stat & (AT91_US_IER_ENDRX | AT91_US_IER_TIMEOUT)) { + const cyg_uint8 cb = at91_chan->curbuf, nb = cb ^ 0x01; + const cyg_uint8 * p = at91_chan->rcv_buffer[cb], * end; + cyg_uint32 temp_word; + + at91_chan->curbuf = nb; + HAL_WRITE_UINT32(base + AT91_US_RCR, 0); + HAL_READ_UINT32(base + AT91_US_RPR, temp_word); + end = (const cyg_uint8 *)temp_word; + HAL_WRITE_UINT32(base + AT91_US_RTO, RCV_TIMEOUT); + HAL_WRITE_UINT32(base + AT91_US_CR, AT91_US_CR_RSTATUS | AT91_US_CR_STTTO); + HAL_WRITE_UINT32(base + AT91_US_RPR, (CYG_ADDRESS) at91_chan->rcv_buffer[nb]); + HAL_WRITE_UINT32(base + AT91_US_RCR, at91_chan->rcv_chunk_size); + HAL_WRITE_UINT32( + base + AT91_US_IER, + AT91_US_IER_ENDRX | AT91_US_IER_TIMEOUT + ); + + while (p < end) { + rcv_req_reply_t res; + int space_avail; + unsigned char *space; + + res = (chan->callbacks->data_rcv_req)( + chan, + end - at91_chan->rcv_buffer[cb], + &space_avail, + &space + ); + + switch (res) + { + case CYG_RCV_OK: + memcpy(space, p, space_avail); + (chan->callbacks->data_rcv_done)(chan, space_avail); + p += space_avail; + break; + case CYG_RCV_DISABLED: + (chan->callbacks->rcv_char)(chan, *p++); + break; + default: + // Buffer full or unknown error, can't do anything about it + // Discard data + p = end; + break; + } + } + } + + if (stat & AT91_US_IER_TxRDY) { + at91_chan->flags &= ~SIFLG_XMIT_BUSY; + (chan->callbacks->xmt_char)(chan); + if (at91_chan->flags & SIFLG_XMIT_CONTINUE) + HAL_WRITE_UINT32(base + AT91_US_IER, AT91_US_IER_TxRDY); + } + + if (stat & AT91_US_IER_ENDTX) { + (chan->callbacks->data_xmt_done)(chan, at91_chan->transmit_size); + if (at91_chan->flags & SIFLG_XMIT_CONTINUE) { + unsigned char * chars; + xmt_req_reply_t res; + + res = (chan->callbacks->data_xmt_req)(chan, 0xffff, &at91_chan->transmit_size, &chars); + + switch (res) + { + case CYG_XMT_OK: + HAL_WRITE_UINT32(base + AT91_US_TPR, (CYG_WORD32) chars); + HAL_WRITE_UINT32(base + AT91_US_TCR, at91_chan->transmit_size); + at91_chan->flags |= SIFLG_XMIT_CONTINUE; + HAL_WRITE_UINT32(base + AT91_US_IER, AT91_US_IER_ENDTX); + break; + default: + // No data or unknown error - can't do anything about it + // CYG_XMT_DISABLED should not happen here! + break; + } + } + } +} +#endif diff --git a/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.h b/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.h new file mode 100644 index 0000000..4227143 --- /dev/null +++ b/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_ARM_AT91_SERIAL_H +#define CYGONCE_ARM_AT91_SERIAL_H + +// ==================================================================== +// +// at91_serial.h +// +// Device I/O - Description of Atmel AT91/EB40 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2001-07-24 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Atmel AT91/EB40 + +#include <cyg/hal/plf_io.h> // Register definitions + +#define AT91_UART_RX_INTS (AT91_US_IER_RxRDY) + +static cyg_uint32 select_word_length[] = { + AT91_US_MR_LENGTH_5, + AT91_US_MR_LENGTH_6, + AT91_US_MR_LENGTH_7, + AT91_US_MR_LENGTH_8 +}; + +static cyg_uint32 select_stop_bits[] = { + 0, + AT91_US_MR_STOP_1, // 1 stop bit + AT91_US_MR_STOP_1_5, // 1.5 stop bit + AT91_US_MR_STOP_2 // 2 stop bits +}; + +static cyg_uint32 select_parity[] = { + AT91_US_MR_PARITY_NONE, // No parity + AT91_US_MR_PARITY_EVEN, // Even parity + AT91_US_MR_PARITY_ODD, // Odd parity + AT91_US_MR_PARITY_MARK, // Mark (1) parity + AT91_US_MR_PARITY_SPACE // Space (0) parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +#endif // CYGONCE_ARM_AT91_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/cerfpda/current/ChangeLog b/ecos/packages/devs/serial/arm/cerfpda/current/ChangeLog new file mode 100644 index 0000000..0af182b --- /dev/null +++ b/ecos/packages/devs/serial/arm/cerfpda/current/ChangeLog @@ -0,0 +1,32 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_cerfpda.cdl: Remove irrelevant doc link. + +2002-02-04 Gary Thomas <gthomas@redhat.com> + + * include/arm_sa1110_cerfpda_ser.inl: + * cdl/ser_arm_cerfpda.cdl: New file(s) - port to Intrinsyc CerfPDA. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/cerfpda/current/cdl/ser_arm_cerfpda.cdl b/ecos/packages/devs/serial/arm/cerfpda/current/cdl/ser_arm_cerfpda.cdl new file mode 100644 index 0000000..0e7001c --- /dev/null +++ b/ecos/packages/devs/serial/arm/cerfpda/current/cdl/ser_arm_cerfpda.cdl @@ -0,0 +1,130 @@ +# ==================================================================== +# +# ser_arm_cerfpda.cdl +# +# eCos serial CERFPDA configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-07 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_CERFPDA { + display "Cerfpda 16x5x serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_SA11X0_CERFPDA + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial 16x5x device drivers for the + Cerfpda." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4" + } + + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_sa11x0_cerfpda_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_cerfpda.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + + cdl_component CYGPKG_IO_SERIAL_ARM_CERFPDA_SERIAL1 { + display "Cerfpda serial port 1 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + Cerfpda port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_CERFPDA_SERIAL1_NAME { + display "Device name for cerfpda serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device + for the Cerfpda port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BAUD { + display "Baud rate for the cerfpda serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the Cerfpda port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BUFSIZE { + display "Buffer size for the cerfpda serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal + buffers used for the cerfpda port 1." + } + } + +} + +# EOF ser_arm_cerfpda.cdl diff --git a/ecos/packages/devs/serial/arm/cerfpda/current/include/arm_sa1110_cerfpda_ser.inl b/ecos/packages/devs/serial/arm/cerfpda/current/include/arm_sa1110_cerfpda_ser.inl new file mode 100644 index 0000000..a06c6c5 --- /dev/null +++ b/ecos/packages/devs/serial/arm/cerfpda/current/include/arm_sa1110_cerfpda_ser.inl @@ -0,0 +1,122 @@ +//========================================================================== +// +// io/serial/arm/arm_sa1110_cerpda_ser.inl +// +// Cerfpda Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jlarmour +// Date: 1999-02-04 +// Purpose: Cerfpda Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/cerfpda.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 18432,// 75 + 12657,// 110 + 10278,// 134.5 + 9216, // 150 + 6912, // 200 + 4608, // 300 + 2304, // 600 + 1152, // 1200 + 768, // 1800 + 576, // 2400 + 384, // 3600 + 288, // 4800 + 192, // 7200 + 144, // 9600 + 96, // 14400 + 72, // 19200 + 36, // 38400 + 24, // 57600 + 12, // 115200 + 6, // 230400 +}; + +#ifdef CYGPKG_IO_SERIAL_ARM_CERFPDA_SERIAL1 +static pc_serial_info cerfpda_serial_info1 = {0x18000000, SA1110_IRQ_GPIO_16X5X}; +#if CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BUFSIZE > 0 +static unsigned char cerfpda_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BUFSIZE]; +static unsigned char cerfpda_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cerfpda_serial_channel1, + pc_serial_funs, + cerfpda_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cerfpda_serial_out_buf1[0], sizeof(cerfpda_serial_out_buf1), + &cerfpda_serial_in_buf1[0], sizeof(cerfpda_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(cerfpda_serial_channel1, + pc_serial_funs, + cerfpda_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CERFPDA_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cerfpda_serial_io1, + CYGDAT_IO_SERIAL_ARM_CERFPDA_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &cerfpda_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_CERFPDA_SERIAL1 + +// EOF arm_sa1110_cerfpda_ser.inl diff --git a/ecos/packages/devs/serial/arm/cma230/current/ChangeLog b/ecos/packages/devs/serial/arm/cma230/current/ChangeLog new file mode 100644 index 0000000..58908f3 --- /dev/null +++ b/ecos/packages/devs/serial/arm/cma230/current/ChangeLog @@ -0,0 +1,1187 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_cma230.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_cma230.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * src/cma230_serial.c: Fix typo. + + * cdl/ser_arm_cma230.cdl: Testing parameters moved here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/cma230_serial.c (cma230_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_arm_cma230.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/cma230/current/cdl/ser_arm_cma230.cdl b/ecos/packages/devs/serial/arm/cma230/current/cdl/ser_arm_cma230.cdl new file mode 100644 index 0000000..8b9dd3d --- /dev/null +++ b/ecos/packages/devs/serial/arm/cma230/current/cdl/ser_arm_cma230.cdl @@ -0,0 +1,207 @@ +# ==================================================================== +# +# ser_arm_cma230.cdl +# +# eCos serial ARM/CMA230 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_CMA230 { + display "Cogent ARM/CMA230 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_CMA230 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + Cogent ARM/CMA230." + + compile -library=libextras.a cma230_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_cma230.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_A { + display "Cogent ARM/CMA230 serial port A driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Cogent + ARM/CMA230 port A." + + cdl_option CYGDAT_IO_SERIAL_ARM_CMA230_SERIAL_A_NAME { + display "Device name for Cogent ARM/CMA230 serial port A" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the Cogent + ARM/CMA230 port A." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BAUD { + display "Baud rate for the Cogent ARM/CMA230 serial port A driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Cogent ARM/CMA230 port A." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BUFSIZE { + display "Buffer size for the Cogent ARM/CMA230 serial port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the Cogent ARM/CMA230 port A." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_B { + display "Cogent ARM/CMA230 serial port B driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Cogent + ARM/CMA230 port B." + + cdl_option CYGDAT_IO_SERIAL_ARM_CMA230_SERIAL_B_NAME { + display "Device name for Cogent ARM/CMA230 serial port B" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the Cogent + ARM/CMA230 port B." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BAUD { + display "Baud rate for the Cogent ARM/CMA230 serial port B driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Cogent ARM/CMA230 port B." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BUFSIZE { + display "Buffer size for the Cogent ARM/CMA230 serial port B driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the Cogent ARM/CMA230 port B." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_CMA230_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_CMA230_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_CMA230_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_CMA230_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_A + + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_CMA230_SERIAL_A_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armcma\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_cma230.cdl diff --git a/ecos/packages/devs/serial/arm/cma230/current/src/cma230_serial.c b/ecos/packages/devs/serial/arm/cma230/current/src/cma230_serial.c new file mode 100644 index 0000000..c024f18 --- /dev/null +++ b/ecos/packages/devs/serial/arm/cma230/current/src/cma230_serial.c @@ -0,0 +1,344 @@ +//========================================================================== +// +// io/serial/arm/cma230_serial.c +// +// Cogent CMA230 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: CMA230 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/hal/hal_cma230.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_CMA230 + +#include "cma230_serial.h" + +typedef struct cma230_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} cma230_serial_info; + +static bool cma230_serial_init(struct cyg_devtab_entry *tab); +static bool cma230_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo cma230_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char cma230_serial_getc(serial_channel *chan); +static Cyg_ErrNo cma230_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void cma230_serial_start_xmit(serial_channel *chan); +static void cma230_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 cma230_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void cma230_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(cma230_serial_funs, + cma230_serial_putc, + cma230_serial_getc, + cma230_serial_set_config, + cma230_serial_start_xmit, + cma230_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_A +static cma230_serial_info cma230_serial_info0 = {CMA101_DUARTA, + CYGNUM_HAL_INTERRUPT_SERIAL_A}; +#if CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BUFSIZE > 0 +static unsigned char cma230_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BUFSIZE]; +static unsigned char cma230_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cma230_serial_channel0, + cma230_serial_funs, + cma230_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cma230_serial_out_buf0[0], sizeof(cma230_serial_out_buf0), + &cma230_serial_in_buf0[0], sizeof(cma230_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(cma230_serial_channel0, + cma230_serial_funs, + cma230_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cma230_serial_io0, + CYGDAT_IO_SERIAL_ARM_CMA230_SERIAL_A_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + cma230_serial_init, + cma230_serial_lookup, // Serial driver may need initializing + &cma230_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_A + +#ifdef CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_B +static cma230_serial_info cma230_serial_info1 = {CMA101_DUARTB, + CYGNUM_HAL_INTERRUPT_SERIAL_B}; +#if CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BUFSIZE > 0 +static unsigned char cma230_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BUFSIZE]; +static unsigned char cma230_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cma230_serial_channel1, + cma230_serial_funs, + cma230_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cma230_serial_out_buf1[0], sizeof(cma230_serial_out_buf1), + &cma230_serial_in_buf1[0], sizeof(cma230_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(cma230_serial_channel1, + cma230_serial_funs, + cma230_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CMA230_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cma230_serial_io1, + CYGDAT_IO_SERIAL_ARM_CMA230_SERIAL_B_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + cma230_serial_init, + cma230_serial_lookup, // Serial driver may need initializing + &cma230_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_CMA230_SERIAL_B + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +cma230_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)cma230_chan->base; + unsigned short baud_divisor = select_baud[new_config->baud]; + unsigned char _lcr, _ier; + if (baud_divisor == 0) return false; // Invalid configuration + _ier = port->ier; + port->ier = 0; // Disable port interrupts while changing hardware + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + port->lcr = _lcr; + port->lcr |= LCR_DL; + port->mdl = baud_divisor >> 8; + port->ldl = baud_divisor & 0xFF; + port->lcr &= ~LCR_DL; + if (init) { + port->fcr = 0x07; // Enable and clear FIFO + if (chan->out_cbuf.len != 0) { + port->ier = IER_RCV; + } else { + port->ier = 0; + } + port->mcr = MCR_INT|MCR_DTR|MCR_RTS; // Master interrupt enable + } else { + port->ier = _ier; + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +cma230_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("CMA230 SERIAL init - dev: %x.%d\n", cma230_chan->base, cma230_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(cma230_chan->int_num, + 99, // Priority - what goes here? + (cyg_addrword_t)chan, // Data item passed to interrupt handler + cma230_serial_ISR, + cma230_serial_DSR, + &cma230_chan->serial_interrupt_handle, + &cma230_chan->serial_interrupt); + cyg_drv_interrupt_attach(cma230_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(cma230_chan->int_num); + } + cma230_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +cma230_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +cma230_serial_putc(serial_channel *chan, unsigned char c) +{ + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)cma230_chan->base; + if (port->lsr & LSR_THE) { +// Transmit buffer is empty + port->thr = c; + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +cma230_serial_getc(serial_channel *chan) +{ + unsigned char c; + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)cma230_chan->base; + while ((port->lsr & LSR_RSR) == 0) ; // Wait for char + c = port->rhr; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +cma230_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != cma230_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +cma230_serial_start_xmit(serial_channel *chan) +{ + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)cma230_chan->base; + port->ier |= IER_XMT; // Enable xmit interrupt +} + +// Disable the transmitter on the device +static void +cma230_serial_stop_xmit(serial_channel *chan) +{ + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)cma230_chan->base; + port->ier &= ~IER_XMT; // Disable xmit interrupt +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +cma230_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(cma230_chan->int_num); + cyg_drv_interrupt_acknowledge(cma230_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +cma230_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cma230_serial_info *cma230_chan = (cma230_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)cma230_chan->base; + unsigned char isr; + isr = port->isr & 0x0E; + if (isr == ISR_Tx) { + (chan->callbacks->xmt_char)(chan); + } else if (isr == ISR_Rx) { + (chan->callbacks->rcv_char)(chan, port->rhr); + } + cyg_drv_interrupt_unmask(cma230_chan->int_num); +} +#endif diff --git a/ecos/packages/devs/serial/arm/cma230/current/src/cma230_serial.h b/ecos/packages/devs/serial/arm/cma230/current/src/cma230_serial.h new file mode 100644 index 0000000..0eb5e4c --- /dev/null +++ b/ecos/packages/devs/serial/arm/cma230/current/src/cma230_serial.h @@ -0,0 +1,161 @@ +#ifndef CYGONCE_ARM_CMA230_SERIAL_H +#define CYGONCE_ARM_CMA230_SERIAL_H + +// ==================================================================== +// +// cma230_serial.h +// +// Device I/O - Description of Cogent CMA230 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-05-20 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Cogent CMA230 + +struct serial_port { + unsigned char _byte[32]; +}; + +#define reg(n) _byte[n*8] + +// Receive control registers +#define rhr reg(0) // Receive holding register +#define isr reg(2) // Interrupt status register +#define lsr reg(5) // Line status register +#define msr reg(6) // Modem status register +#define scr reg(7) // Scratch register + +// Transmit control registers +#define thr reg(0) // Transmit holding register +#define ier reg(1) // Interrupt enable register +#define fcr reg(2) // FIFO control register +#define lcr reg(3) // Line control register +#define mcr reg(4) // Modem control register +#define ldl reg(0) // LSB of baud rate +#define mdl reg(1) // MSB of baud rate + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_Tx 0x02 +#define ISR_Rx 0x04 + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// The Cogent board has a 3.6864 MHz crystal +static unsigned short select_baud[] = { + 0, // Unused + 4608, // 50 + 0, // 75 + 2094, // 110 + 0, // 134.5 + 1536, // 150 + 0, // 200 + 768, // 300 + 384, // 600 + 182, // 1200 + 0, // 1800 + 96, // 2400 + 0, // 3600 + 48, // 4800 + 32, // 7200 + 24, // 9600 + 16, // 14400 + 12, // 19200 + 6, // 38400 + 4, // 57600 + 2, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_ARM_CMA230_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/e7t/current/ChangeLog b/ecos/packages/devs/serial/arm/e7t/current/ChangeLog new file mode 100644 index 0000000..cf6da8b --- /dev/null +++ b/ecos/packages/devs/serial/arm/e7t/current/ChangeLog @@ -0,0 +1,38 @@ +2004-02-11 Roland Caßebohm <roland.cassebohm@visionsystem.de> + + * src/e7t_serial.c: The UART doesn't generate an interrupt befor the + first time a character was send. Changed e7t_serial_start_xmit() + to first try to send characters. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_e7t.cdl: Remove irrelevant doc link. + +2001-10-19 Lars Lindqvist <Lars.Lindqvist@combitechsystems.com> +2001-10-19 Jonathan Larmour <jlarmour@redhat.com> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/e7t/current/cdl/ser_arm_e7t.cdl b/ecos/packages/devs/serial/arm/e7t/current/cdl/ser_arm_e7t.cdl new file mode 100644 index 0000000..fbeea37 --- /dev/null +++ b/ecos/packages/devs/serial/arm/e7t/current/cdl/ser_arm_e7t.cdl @@ -0,0 +1,209 @@ +# ==================================================================== +# +# ser_arm_e7t.cdl +# +# eCos serial ARM/AEB-2 (E7T) configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Lars.Lindqvist@combitechsystems.com +# Contributors: jlarmour +# Date: 2001-10-19 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_E7T { + display "ARM E7T serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_E7T + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This package contains serial device drivers for the + ARM AEB-2 (E7T)." + + compile -library=libextras.a e7t_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_e7t.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_E7T_SERIAL0 { + display "ARM E7T serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM E7T + port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_E7T_SERIAL0_NAME { + display "Deviccce name for the ARM E7T serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the ARM + E7T port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BAUD { + display "Baud rate for the ARM E7T serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM E7T port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BUFSIZE { + display "Buffer size for the ARM E7T serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the ARM E7T port 0." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_E7T_SERIAL1 { + display "ARM E7T serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM + E7T port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_E7T_SERIAL1_NAME { + display "Device name for the ARM E7T serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + ARM E7T port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BAUD { + display "Baud rate for the ARM E7T serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM E7T port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BUFSIZE { + display "Buffer size for the ARM E7T serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ARM E7T port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_E7T_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_E7T_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_E7T_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_E7T_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_E7T_SERIAL1 + + implements CYGINT_IO_SERIAL_TEST_SKIP_38400 + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_E7T_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"arme7t\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_e7t.cdl diff --git a/ecos/packages/devs/serial/arm/e7t/current/src/e7t_serial.c b/ecos/packages/devs/serial/arm/e7t/current/src/e7t_serial.c new file mode 100644 index 0000000..3de6647 --- /dev/null +++ b/ecos/packages/devs/serial/arm/e7t/current/src/e7t_serial.c @@ -0,0 +1,376 @@ +//========================================================================== +// +// io/serial/arm/e7t_serial.c +// +// ARM AEB-2 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Lars.Lindqvist@combitechsystems.com +// Contributors: jlarmour +// Date: 2001-10-19 +// Purpose: ARM AEB-2 Serial I/O Interface Module (interrupt driven) +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/io/serialio.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_E7T + +#include "e7t_serial.h" + +typedef struct e7t_serial_info { + CYG_ADDRWORD base; + CYG_WORD tx_int_num; + CYG_WORD rx_int_num; + cyg_interrupt serial_tx_interrupt; + cyg_interrupt serial_rx_interrupt; + cyg_handle_t serial_tx_interrupt_handle; + cyg_handle_t serial_rx_interrupt_handle; + bool tx_enabled; +} e7t_serial_info; + +static bool e7t_serial_init(struct cyg_devtab_entry *tab); +static bool e7t_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo e7t_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char e7t_serial_getc(serial_channel *chan); +static Cyg_ErrNo e7t_serial_set_config(serial_channel *chan, + cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void e7t_serial_start_xmit(serial_channel *chan); +static void e7t_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 e7t_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void e7t_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 e7t_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void e7t_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(e7t_serial_funs, + e7t_serial_putc, + e7t_serial_getc, + e7t_serial_set_config, + e7t_serial_start_xmit, + e7t_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_E7T_SERIAL0 +static e7t_serial_info e7t_serial_info0 = {0x07FFd000, + CYGNUM_HAL_INTERRUPT_UART0_TX, + CYGNUM_HAL_INTERRUPT_UART0_RX}; +#if CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BUFSIZE > 0 +static unsigned char e7t_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BUFSIZE]; +static unsigned char e7t_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(e7t_serial_channel0, + e7t_serial_funs, + e7t_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &e7t_serial_out_buf0[0], sizeof(e7t_serial_out_buf0), + &e7t_serial_in_buf0[0], sizeof(e7t_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(e7t_serial_channel0, + e7t_serial_funs, + e7t_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_E7T_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(e7t_serial_io0, + CYGDAT_IO_SERIAL_ARM_E7T_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + e7t_serial_init, + e7t_serial_lookup, // Serial driver may need initializing + &e7t_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_E7T_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_E7T_SERIAL1 +static e7t_serial_info e7t_serial_info1 = {0x07FFe000, + CYGNUM_HAL_INTERRUPT_UART1_TX, + CYGNUM_HAL_INTERRUPT_UART1_RX}; +#if CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BUFSIZE > 0 +static unsigned char e7t_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BUFSIZE]; +static unsigned char e7t_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(e7t_serial_channel1, + e7t_serial_funs, + e7t_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &e7t_serial_out_buf1[0], sizeof(e7t_serial_out_buf1), + &e7t_serial_in_buf1[0], sizeof(e7t_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(e7t_serial_channel1, + e7t_serial_funs, + e7t_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_E7T_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(e7t_serial_io1, + CYGDAT_IO_SERIAL_ARM_E7T_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + e7t_serial_init, + e7t_serial_lookup, // Serial driver may need initializing + &e7t_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_E7T_SERIAL1 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +e7t_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)e7t_chan->base; + cyg_uint32 word_length = select_word_length[(new_config->word_length)-CYGNUM_SERIAL_WORD_LENGTH_5]; + cyg_uint32 stop_bits = select_stop_bits[(new_config->stop)-CYGNUM_SERIAL_STOP_1]; + cyg_uint32 parity_mode = select_parity[(new_config->parity)-CYGNUM_SERIAL_PARITY_NONE]; + cyg_uint32 baud_divisor = select_baud[(new_config->baud)-CYGNUM_SERIAL_BAUD_50]; + cyg_uint32 res = word_length | stop_bits | parity_mode | ULCON_SCI | ULCON_IROFF; + if ((word_length|stop_bits|parity_mode|baud_divisor) == U_NOT_SUPP) { + return false; + }; + port->REG_ULCON = res; + port->REG_UCON = UCON_RXMINT | UCON_RXSIOFF | UCON_TXMINT | UCON_DSROFF | UCON_SBKOFF | UCON_LPBOFF; + port->REG_UBRDIV = baud_divisor; + if (new_config != &chan->config) { + chan->config = *new_config; + }; + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +e7t_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("E7T SERIAL init - dev: %x.%d.%d\n", e7t_chan->base, e7t_chan->tx_int_num, e7t_chan->rx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { // If bufferlength > 0 then interrupts are used for tx + cyg_drv_interrupt_create(e7t_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + e7t_serial_tx_ISR, + e7t_serial_tx_DSR, + &e7t_chan->serial_tx_interrupt_handle, + &e7t_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(e7t_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_mask(e7t_chan->tx_int_num); + e7t_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { // If bufferlength > 0 then interrupts are used for rx + cyg_drv_interrupt_create(e7t_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + e7t_serial_rx_ISR, + e7t_serial_rx_DSR, + &e7t_chan->serial_rx_interrupt_handle, + &e7t_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(e7t_chan->serial_rx_interrupt_handle); + cyg_drv_interrupt_unmask(e7t_chan->rx_int_num); + } + e7t_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +e7t_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +e7t_serial_putc(serial_channel *chan, unsigned char c) +{ + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)e7t_chan->base; + + if (port->REG_USTAT & USTAT_TBE) { + // Transmit buffer is empty + port->REG_UTXBUF = c; + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +e7t_serial_getc(serial_channel *chan) +{ + unsigned char c; + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)e7t_chan->base; + while ((port->REG_USTAT & USTAT_RDR) == 0) ; // Wait for char + c = port->REG_URXBUF; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +e7t_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != e7t_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +e7t_serial_start_xmit(serial_channel *chan) +{ + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + e7t_chan->tx_enabled = true; + (chan->callbacks->xmt_char)(chan); + if (e7t_chan->tx_enabled) { + cyg_drv_interrupt_unmask(e7t_chan->tx_int_num); + } +} + +// Disable the transmitter on the device +static void +e7t_serial_stop_xmit(serial_channel *chan) +{ + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(e7t_chan->tx_int_num); + e7t_chan->tx_enabled = false; +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +e7t_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(e7t_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(e7t_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +e7t_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (e7t_chan->tx_enabled) { + cyg_drv_interrupt_unmask(e7t_chan->tx_int_num); + } +} + +// Serial I/O - low level rx interrupt handler (ISR) +static cyg_uint32 +e7t_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(e7t_chan->rx_int_num); + cyg_drv_interrupt_acknowledge(e7t_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +e7t_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + e7t_serial_info *e7t_chan = (e7t_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)e7t_chan->base; + (chan->callbacks->rcv_char)(chan, port->REG_URXBUF); + cyg_drv_interrupt_unmask(e7t_chan->rx_int_num); +} + +#endif // CYGPKG_IO_SERIAL_ARM_E7T + +// EOF e7t_serial.c diff --git a/ecos/packages/devs/serial/arm/e7t/current/src/e7t_serial.h b/ecos/packages/devs/serial/arm/e7t/current/src/e7t_serial.h new file mode 100644 index 0000000..336d99d --- /dev/null +++ b/ecos/packages/devs/serial/arm/e7t/current/src/e7t_serial.h @@ -0,0 +1,196 @@ +#ifndef CYGONCE_ARM_E7T_SERIAL_H +#define CYGONCE_ARM_E7T_SERIAL_H +// ==================================================================== +// +// e7t_serial.h +// +// Device I/O - Description of ARM AEB-2 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Lars.Lindqvist@combitechsystems.com +// Contributors: jlarmour +// Date: 2001-10-19 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/hal.h> // Value CYGNUM_HAL_ARM_E7T_CLOCK_SPEED needed +#include <cyg/infra/cyg_type.h> // base types + +// Description of serial ports on ARM AEB-2 + +struct serial_port { + cyg_uint32 _reg[8]; +}; + +#define REG(n) _reg[n] + +// Misc values +#define U_NOT_SUPP (0xFFFFFFFF) // Used to indicate unsupported parameter values + +// Registers +#define REG_ULCON REG(0) // Line control registers +#define REG_UCON REG(1) // Control registers +#define REG_USTAT REG(2) // Status registers +#define REG_UTXBUF REG(3) // Transmit buffer registers +#define REG_URXBUF REG(4) // Receive buffer registers +#define REG_UBRDIV REG(5) // Baud rate divisor registers + +// Line Control Register Values +#define ULCON_WL5 (0x00000000 << 0) // Word length 5 +#define ULCON_WL6 (0x00000001 << 0) // Word length 6 +#define ULCON_WL7 (0x00000002 << 0) // Word length 7 +#define ULCON_WL8 (0x00000003 << 0) // Word length 8 +#define ULCON_STB1 (0x00000000 << 2) // One stop bit +#define ULCON_STB2 (0x00000001 << 2) // Two stop bits +#define ULCON_PMDOFF (0x00000000 << 3) // No parity +#define ULCON_PMDODD (0x00000004 << 3) // Odd parity +#define ULCON_PMDEVEN (0x00000005 << 3) // Even parity +#define ULCON_PMDFC1 (0x00000006 << 3) // Parity forced/checked as 1 +#define ULCON_PMDFC0 (0x00000007 << 3) // Parity forced/checked as 0 +#define ULCON_SCI (0x00000000 << 6) // Internal clock +#define ULCON_SCE (0x00000001 << 6) // External clock +#define ULCON_IROFF (0x00000000 << 7) // Normal mode +#define ULCON_IRON (0x00000001 << 7) // IR mode + +// Control Register Values +#define UCON_RXMOFF (0x00000000 << 0) // Disable Rx mode +#define UCON_RXMINT (0x00000001 << 0) // Interrupt request Rx mode +#define UCON_RXMDMA0 (0x00000002 << 0) // GDMA channel 0 request Rx mode +#define UCON_RXMDMA1 (0x00000003 << 0) // GDMA channel 1 request Rx mode +#define UCON_RXSIOFF (0x00000000 << 2) // Rx status interrupt disabled +#define UCON_RXSION (0x00000001 << 2) // Rx status interrupt enabled +#define UCON_TXMOFF (0x00000000 << 3) // Disable Tx mode +#define UCON_TXMINT (0x00000001 << 3) // Interrupt request Tx mode +#define UCON_TXMDMA0 (0x00000002 << 3) // GDMA channel 0 request Tx mode +#define UCON_TXMDMA1 (0x00000003 << 3) // GDMA channel 1 request Tx mode +#define UCON_DSROFF (0x00000000 << 5) // Data set ready output off +#define UCON_DSRON (0x00000001 << 5) // Data set ready output on +#define UCON_SBKOFF (0x00000000 << 6) // No break sent +#define UCON_SBKON (0x00000001 << 6) // Break sent +#define UCON_LPBOFF (0x00000000 << 7) // Loop back mode off +#define UCON_LPBON (0x00000001 << 7) // Loop back mode on + +// Status Register Values +#define USTAT_OV (0x00000001 << 0) // Overrun error +#define USTAT_PE (0x00000001 << 1) // Parity error +#define USTAT_FE (0x00000001 << 2) // Frame error + +#define USTAT_BKD (0x00000001 << 3) // Break detect +#define USTAT_DTR (0x00000001 << 4) // Data terminal ready +#define USTAT_RDR (0x00000001 << 5) // Receive data ready +#define USTAT_TBE (0x00000001 << 6) // Transmit buffer register empty +#define USTAT_TC (0x00000001 << 7) // Transmit complete + +// Baud rate divisor registers +#define UBRDIV_50 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/16/50)-1)<<4)|1) +#define UBRDIV_75 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/16/75)-1)<<4)|1) +#define UBRDIV_110 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/16/110)-1)<<4)|1) +#define UBRDIV_134_5 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/8/269)-1)<<4)|1) +#define UBRDIV_150 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/16/150)-1)<<4)|1) +#define UBRDIV_200 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/16/200)-1)<<4)|1) +#define UBRDIV_300 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/16/300)-1)<<4)|1) +#define UBRDIV_600 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/600)-1)<<4)|0) +#define UBRDIV_1200 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/1200)-1)<<4)|0) +#define UBRDIV_1800 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/1800)-1)<<4)|0) +#define UBRDIV_2400 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/2400)-1)<<4)|0) +#define UBRDIV_3600 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/3600)-1)<<4)|0) +#define UBRDIV_4800 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/4800)-1)<<4)|0) +#define UBRDIV_7200 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/7200)-1)<<4)|0) +#define UBRDIV_9600 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/9600)-1)<<4)|0) +#define UBRDIV_14400 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/14400)-1)<<4)|0) +#define UBRDIV_19200 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/19200)-1)<<4)|0) +#define UBRDIV_38400 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/38400)-1)<<4)|0) +#define UBRDIV_57600 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/57600)-1)<<4)|0) +#define UBRDIV_115200 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/115200)-1)<<4)|0) +#define UBRDIV_230400 ((((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/1/16/230400)-1)<<4)|0) + + +// Arrays used for conversion of eCos serial driver +// configuration parameters to parameters for E7T + +static cyg_uint32 select_word_length[] = { + ULCON_WL5, // 5 bits / word (char) + ULCON_WL6, + ULCON_WL7, + ULCON_WL8 +}; + +static cyg_uint32 select_stop_bits[] = { + ULCON_STB1, // 1 stop bit + U_NOT_SUPP, // 1.5 stop bit not supported + ULCON_STB2 // 2 stop bits +}; + +static cyg_uint32 select_parity[] = { + ULCON_PMDOFF, // No parity + ULCON_PMDEVEN, // Even parity + ULCON_PMDODD, // Odd parity + ULCON_PMDFC1, // Mark parity + ULCON_PMDFC0, // Space parity +}; + +static cyg_uint32 select_baud[] = { + UBRDIV_50, // 50 + UBRDIV_75, // 75 + UBRDIV_110, // 110 + UBRDIV_134_5, // 134.5 + UBRDIV_150, // 150 + UBRDIV_200, // 200 + UBRDIV_300, // 300 + UBRDIV_600, // 600 + UBRDIV_1200, // 1200 + UBRDIV_1800, // 1800 + UBRDIV_2400, // 2400 + UBRDIV_3600, // 3600 + UBRDIV_4800, // 4800 + UBRDIV_7200, // 7200 + UBRDIV_9600, // 9600 + UBRDIV_14400, // 14400 + UBRDIV_19200, // 19200 + UBRDIV_38400, // 38400 + UBRDIV_57600, // 57600 + UBRDIV_115200, // 115200 + UBRDIV_230400, // 230400 +}; + +#endif // CYGONCE_ARM_E7T_SERIAL_H + +// EOF e7t_serial.h diff --git a/ecos/packages/devs/serial/arm/ebsa285/current/ChangeLog b/ecos/packages/devs/serial/arm/ebsa285/current/ChangeLog new file mode 100644 index 0000000..9194fef --- /dev/null +++ b/ecos/packages/devs/serial/arm/ebsa285/current/ChangeLog @@ -0,0 +1,1198 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_ebsa285.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_ebsa285.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_arm_ebsa285.cdl: Testing parameters moved here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/ebsa285_serial.c (ebsa285_serial_set_config): Now use keys + to make more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-12 Hugo Tyson <hmt@cygnus.co.uk> + + * src/ebsa285_serial.c (ebsa285_serial_init): Fix silly debug + message - enabled by serial1 test permutation. + +2000-04-12 Hugo Tyson <hmt@cygnus.co.uk> + + * src/ebsa285_serial.c (ebsa285_serial_tx_DSR): Record + whether tx is to be enabled in ebsa285_chan->tx_active, so that + the DSR does not universally unmask it regardless. That led to an + interrupt loop, when the DSR callback had turned off the tx. + Also removed a typo - rx data was being read twice! + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_arm_ebsa285.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/ebsa285/current/cdl/ser_arm_ebsa285.cdl b/ecos/packages/devs/serial/arm/ebsa285/current/cdl/ser_arm_ebsa285.cdl new file mode 100644 index 0000000..3d64d6f --- /dev/null +++ b/ecos/packages/devs/serial/arm/ebsa285/current/cdl/ser_arm_ebsa285.cdl @@ -0,0 +1,163 @@ +# ==================================================================== +# +# ser_arm_ebsa285.cdl +# +# eCos serial ARM/EBSA285 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): hmt +# Original data: gthomas +# Contributors: jskov +# Date: 2000-04-04 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_ARM_EBSA285 { + display "Intel StrongARM/EBSA285 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_EBSA285 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + StrongARM/EBSA285." + + compile -library=libextras.a ebsa285_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_ebsa285.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_EBSA285_SERIAL { + display "Intel StrongARM/EBSA285 serial driver" + flavor bool + default_value 1 + description " + The serial device driver for the Intel StrongARM/EBSA285. + There is only one serial device on this board." + + cdl_option CYGDAT_IO_SERIAL_ARM_EBSA285_SERIAL_NAME { + display "Device name for the Intel StrongARM/EBSA285 serial port" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + Intel StrongARM/EBSA285 serial port." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BAUD { + display "Baud rate for the Intel StrongARM/EBSA285 serial port" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 \ + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Intel StrongARM/EBSA285 serial port." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BUFSIZE { + display "Buffer size for the Intel StrongARM/EBSA285 serial driver" + flavor data + default_value 128 + legal_values 0 to 8192 + description " + This option specifies the size of the internal buffers used + for the Intel StrongARM/EBSA285 serial port." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_EBSA285_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_EBSA285_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_EBSA285_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_EBSA285_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_EBSA285_SERIAL + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_EBSA285_SERIAL_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"arm285\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_ebsa285.cdl diff --git a/ecos/packages/devs/serial/arm/ebsa285/current/src/ebsa285_serial.c b/ecos/packages/devs/serial/arm/ebsa285/current/src/ebsa285_serial.c new file mode 100644 index 0000000..cec6599 --- /dev/null +++ b/ecos/packages/devs/serial/arm/ebsa285/current/src/ebsa285_serial.c @@ -0,0 +1,453 @@ +//========================================================================== +// +// devs/serial/arm/ebsa285/current/src/ebsa285_serial.c +// +// ARM EBSA285 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-07-26 +// Purpose: EBSA285 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_EBSA285 + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#include <cyg/hal/hal_ebsa285.h> // Hardware definitions + +// ------------------------------------------------------------------------ +// Baud rates and the like, table-driven setup +#define FCLK_MHZ 50 + +struct _baud { + unsigned char divisor_high, divisor_low; +}; + +// The indexing of this table must match the enum in serialio.h +// The arithmetic is (clock/4)/(baud * 16) - 1 + +#define NONE {0,0} +const static struct _baud bauds[] = { +#if (FCLK_MHZ == 50) + NONE, // unused + NONE, // 50 + NONE, // 75 + NONE, // 110 + NONE, // 134.5 + NONE, // 150 + NONE, // 200 + { 0xA, 0x2B }, // 300 2603 = 0x0A2B + { 0x5, 0x15 }, // 600 1301 = 0x0515 + { 0x2, 0x8A }, // 1200 650 = 0x028A + { 0x1, 0xB1 }, // 1800 433 = 0x01B1 + { 0x1, 0x45 }, // 2400 325 = 0x0145 + { 0x0, 0xD8 }, // 3600 216 = 0x00D8 + { 0x0, 0xA2 }, // 4800 162 = 0x00A2 + { 0x0, 0x6B }, // 7200 107 = 0x006B + { 0x0, 0x50 }, // 9600 80 = 0x0050 + { 0x0, 0x35 }, // 14400 53 = 0x0035 + { 0x0, 0x28 }, // 19200 40 = 0x0028 + { 0x0, 0x13 }, // 38400 19 = 0x0013 + NONE, // 57600 + NONE, // 115200 + NONE // 230400 +#elif (FCLK_MHZ == 60) +#error NOT SUPPORTED - these figures are more for documentation + { /* 300, */ 0xC, 0x34}, /* 2603 = 0x0A2B */ + { /* 600, */ 0x6, 0x19}, /* 1301 = 0x0515 */ + { /* 1200, */ 0x3, 0x0C}, /* 650 = 0x028A */ + { /* 2400, */ 0x1, 0x86}, /* 325 = 0x0145 */ + { /* 4800, */ 0x0, 0xC2}, /* 162 = 0x00A2 */ + { /* 9600, */ 0x0, 0x61}, /* 80 = 0x0050 */ + { /* 19200, */ 0x0, 0x30}, /* 40 = 0x0028 */ + { /* 38400, */ 0x0, 0x17}, /* 19 = 0x0013 */ +#endif +}; + +static int select_word_length[] = { + SA110_UART_DATA_LENGTH_5_BITS, // 5 bits + SA110_UART_DATA_LENGTH_6_BITS, // 6 bits + SA110_UART_DATA_LENGTH_7_BITS, // 7 bits + SA110_UART_DATA_LENGTH_8_BITS // 8 bits +}; + +static int select_stop_bits[] = { + -1, // unused + SA110_UART_STOP_BITS_ONE, // 1 stop bit + -1, // 1.5 stop bit + SA110_UART_STOP_BITS_TWO // 2 stop bits +}; + +static int select_parity[] = { + SA110_UART_PARITY_DISABLED, // No parity + SA110_UART_PARITY_ENABLED | SA110_UART_PARITY_EVEN, // Even parity + SA110_UART_PARITY_ENABLED | SA110_UART_PARITY_ODD, // Odd parity + -1, // Mark parity + -1 // Space parity +}; + +// ------------------------------------------------------------------------ +// some forward references + +struct ebsa285_serial_interrupt { + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +}; + +typedef struct ebsa285_serial_info { + struct ebsa285_serial_interrupt rx; + struct ebsa285_serial_interrupt tx; + int tx_active; +} ebsa285_serial_info; + +static bool ebsa285_serial_init(struct cyg_devtab_entry *tab); +static bool ebsa285_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo ebsa285_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char ebsa285_serial_getc(serial_channel *chan); +static Cyg_ErrNo ebsa285_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); + +static void ebsa285_serial_start_xmit(serial_channel *chan); +static void ebsa285_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 ebsa285_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void ebsa285_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 ebsa285_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void ebsa285_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(ebsa285_serial_funs, + ebsa285_serial_putc, + ebsa285_serial_getc, + ebsa285_serial_set_config, + ebsa285_serial_start_xmit, + ebsa285_serial_stop_xmit + ); + + +// ------------------------------------------------------------------------ +// this is dummy in config: there is only one device on the EBSA285 +#ifdef CYGPKG_IO_SERIAL_ARM_EBSA285_SERIAL + +static ebsa285_serial_info ebsa285_serial_info1 = { + { CYGNUM_HAL_INTERRUPT_SERIAL_RX }, + { CYGNUM_HAL_INTERRUPT_SERIAL_TX }, + 0 +}; + +#if CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BUFSIZE > 0 +static unsigned char ebsa285_serial_out_buf[CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BUFSIZE]; +static unsigned char ebsa285_serial_in_buf[CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(ebsa285_serial_channel, + ebsa285_serial_funs, + ebsa285_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &ebsa285_serial_out_buf[0], sizeof(ebsa285_serial_out_buf), + &ebsa285_serial_in_buf[0], sizeof(ebsa285_serial_in_buf) + ); +#else +static SERIAL_CHANNEL(ebsa285_serial_channel, + ebsa285_serial_funs, + ebsa285_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_EBSA285_SERIAL_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(ebsa285_serial_io, + CYGDAT_IO_SERIAL_ARM_EBSA285_SERIAL_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + ebsa285_serial_init, + ebsa285_serial_lookup, // Serial driver may need initializing + &ebsa285_serial_channel + ); +#endif // CYGPKG_IO_SERIAL_ARM_EBSA285_SERIAL + +// ------------------------------------------------------------------------ + + +// ------------------------------------------------------------------------ +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +ebsa285_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + int dummy, h, m, l; + + // Make sure everything is off + *SA110_UART_CONTROL_REGISTER = SA110_UART_DISABLED | SA110_SIR_DISABLED; + + // Read the RXStat to drain the fifo + dummy = *SA110_UART_RXSTAT; + + // Set the baud rate - this also turns the uart on. + // + // Note that the ordering of these writes is critical, + // and the writes to the H_BAUD_CONTROL and CONTROL_REGISTER + // are necessary to force the UART to update its register + // contents. + + l = bauds[new_config->baud].divisor_low; // zeros in unused slots here + m = bauds[new_config->baud].divisor_high; // and here + h = SA110_UART_BREAK_DISABLED | + select_stop_bits[new_config->stop] | // -1s in unused slots for these + select_parity[new_config->parity] | // and these + SA110_UART_FIFO_ENABLED | // and these below + select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + + if ( 0 != (l + m) && h >= 0 && h < 256 ) { + *SA110_UART_L_BAUD_CONTROL = l; + *SA110_UART_M_BAUD_CONTROL = m; + *SA110_UART_H_BAUD_CONTROL = h; + init = true; // AOK + } + else if ( init ) { + // put in some sensible defaults + *SA110_UART_L_BAUD_CONTROL = 0x13; // bp->divisor_low; + *SA110_UART_M_BAUD_CONTROL = 0x00; // bp->divisor_high; + *SA110_UART_H_BAUD_CONTROL = SA110_UART_BREAK_DISABLED | + SA110_UART_PARITY_DISABLED | + SA110_UART_STOP_BITS_ONE | + SA110_UART_FIFO_ENABLED | + SA110_UART_DATA_LENGTH_8_BITS; + } + + // All set, re-enable the device: + *SA110_UART_CONTROL_REGISTER = SA110_UART_ENABLED | SA110_SIR_DISABLED; + + if (init && new_config != &chan->config) { + // record the new setup + chan->config = *new_config; + } + // All done + return init; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +ebsa285_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("EBSA285 SERIAL init - dev: %x\n", ebsa285_chan); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + + // first for rx + cyg_drv_interrupt_create(ebsa285_chan->rx.int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + ebsa285_serial_rx_ISR, + ebsa285_serial_rx_DSR, + &ebsa285_chan->rx.serial_interrupt_handle, + &ebsa285_chan->rx.serial_interrupt); + cyg_drv_interrupt_attach(ebsa285_chan->rx.serial_interrupt_handle); + cyg_drv_interrupt_unmask(ebsa285_chan->rx.int_num); + + // then for tx + cyg_drv_interrupt_create(ebsa285_chan->tx.int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + ebsa285_serial_tx_ISR, + ebsa285_serial_tx_DSR, + &ebsa285_chan->tx.serial_interrupt_handle, + &ebsa285_chan->tx.serial_interrupt); + cyg_drv_interrupt_attach(ebsa285_chan->tx.serial_interrupt_handle); + // DO NOT cyg_drv_interrupt_unmask(ebsa285_chan->tx.int_num); + ebsa285_chan->tx_active = 0; + } + (void)ebsa285_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +ebsa285_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +ebsa285_serial_putc(serial_channel *chan, unsigned char c) +{ + if ((*SA110_UART_FLAG_REGISTER & SA110_TX_FIFO_STATUS_MASK) == SA110_TX_FIFO_BUSY) + return false; // No space + + *SA110_UART_DATA_REGISTER = c; // Transmit buffer is empty + return true; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +ebsa285_serial_getc(serial_channel *chan) +{ + unsigned char c; + while ((*SA110_UART_FLAG_REGISTER & SA110_RX_FIFO_STATUS_MASK) == SA110_RX_FIFO_EMPTY) + ; // wait for char + c = (char)(*SA110_UART_DATA_REGISTER & 0xFF); + // no error checking... no way to return the info + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +ebsa285_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != ebsa285_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device (nope, already in use by hal_diag) +static void +ebsa285_serial_start_xmit(serial_channel *chan) +{ + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; + ebsa285_chan->tx_active = 1; + cyg_drv_interrupt_unmask(ebsa285_chan->tx.int_num); +} + +// Disable the transmitter on the device (nope, remains in use by hal_diag) +static void +ebsa285_serial_stop_xmit(serial_channel *chan) +{ + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(ebsa285_chan->tx.int_num); + ebsa285_chan->tx_active = 0; +} + +// Serial I/O - low level interrupt handlers (ISR) +static cyg_uint32 +ebsa285_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(ebsa285_chan->rx.int_num); + cyg_drv_interrupt_acknowledge(ebsa285_chan->rx.int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +static cyg_uint32 +ebsa285_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(ebsa285_chan->tx.int_num); + cyg_drv_interrupt_acknowledge(ebsa285_chan->tx.int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handlers (DSR) +static void +ebsa285_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; + if ((*SA110_UART_FLAG_REGISTER & SA110_RX_FIFO_STATUS_MASK) != SA110_RX_FIFO_EMPTY) { + char c; + int status; + c = (char)(*SA110_UART_DATA_REGISTER & 0xFF); + status = *SA110_UART_RXSTAT; + if ( 0 == (status & (SA110_UART_FRAMING_ERROR_MASK | + SA110_UART_PARITY_ERROR_MASK | + SA110_UART_OVERRUN_ERROR_MASK)) ) + (chan->callbacks->rcv_char)(chan, c); + } + cyg_drv_interrupt_unmask(ebsa285_chan->rx.int_num); +} + +static void +ebsa285_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; + if ((*SA110_UART_FLAG_REGISTER & SA110_TX_FIFO_STATUS_MASK) != SA110_TX_FIFO_BUSY) { + (chan->callbacks->xmt_char)(chan); + } + if ( ebsa285_chan->tx_active ) // it might be halted in callback above + cyg_drv_interrupt_unmask(ebsa285_chan->tx.int_num); +} +#endif // CYGPKG_IO_SERIAL_ARM_EBSA285 + +// ------------------------------------------------------------------------ +// EOF ebsa285_serial.c diff --git a/ecos/packages/devs/serial/arm/edb7xxx/current/ChangeLog b/ecos/packages/devs/serial/arm/edb7xxx/current/ChangeLog new file mode 100644 index 0000000..8b71da0 --- /dev/null +++ b/ecos/packages/devs/serial/arm/edb7xxx/current/ChangeLog @@ -0,0 +1,1189 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_edb7xxx.cdl: Remove irrelevant doc link. + +2001-10-12 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_edb7xxx.cdl: Clarify package description strings. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_edb7xxx.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_arm_edb7xxx.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/edb7xxx_serial.c (edb7xxx_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_arm_edb7xxx.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/edb7xxx/current/cdl/ser_arm_edb7xxx.cdl b/ecos/packages/devs/serial/arm/edb7xxx/current/cdl/ser_arm_edb7xxx.cdl new file mode 100644 index 0000000..2d69ba0 --- /dev/null +++ b/ecos/packages/devs/serial/arm/edb7xxx/current/cdl/ser_arm_edb7xxx.cdl @@ -0,0 +1,208 @@ +# ==================================================================== +# +# ser_arm_edb7xxx.cdl +# +# eCos serial ARM/EDB7XXX configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_EDB7XXX { + display "Cirrus Logic ARM based boards serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_EDB7XXX + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + Cirrus Logic ARM based development boards." + + compile -library=libextras.a edb7xxx_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_edb7xxx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL1 { + display "Cirrus Logic EDB7XXX serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Cirrus Logic EDB7XXX + port 1." + + + cdl_option CYGDAT_IO_SERIAL_ARM_EDB7XXX_SERIAL1_NAME { + display "Device name for the Cirrus Logic EDB7XXX serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the ARM + EDB7XXX port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BAUD { + display "Baud rate for the Cirrus Logic EDB7XXX serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the ARM + EDB7XXX port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BUFSIZE { + display "Buffer size for the Cirrus Logic EDB7XXX serial port 1 driver" + flavor data + default_value 128 + legal_values 0 to 8192 + description " + This option specifies the size of the internal buffers used + for the Cirrus Logic EDB7XXX port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL2 { + display "Cirrus Logic EDB7XXX serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM + EDB7XXX port 2." + + cdl_option CYGDAT_IO_SERIAL_ARM_EDB7XXX_SERIAL2_NAME { + display "Device name for the Cirrus Logic EDB7XXX serial port 2 driver" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the name of serial device for the ARM + EDB7XXX port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BAUD { + display "Baud rate for the Cirrus Logic EDB7XXX serial port 2 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Cirrus Logic EDB7XXX port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BUFSIZE { + display "Buffer size for the Cirrus Logic EDB7XXX serial port 2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the Cirrus Logic EDB7XXX port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_EDB7XXX_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_EDB7XXX_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_EDB7XXX_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_EDB7XXX_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL1 + + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_EDB7XXX_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armedb7xxx\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_edb7xxx.cdl diff --git a/ecos/packages/devs/serial/arm/edb7xxx/current/src/edb7xxx_serial.c b/ecos/packages/devs/serial/arm/edb7xxx/current/src/edb7xxx_serial.c new file mode 100644 index 0000000..a2db2d1 --- /dev/null +++ b/ecos/packages/devs/serial/arm/edb7xxx/current/src/edb7xxx_serial.c @@ -0,0 +1,408 @@ +//========================================================================== +// +// io/serial/arm/edb7xxx_serial.c +// +// Cirrus Logic EDB7XXX Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: EDB7XXX Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_EDB7XXX + +#include "edb7xxx_serial.h" + +typedef struct edb7xxx_serial_info { + CYG_ADDRWORD data, // Pointer to data register + control, // Pointer to baud rate/line control register + stat, // Pointer to system flags for this port + syscon; // Pointer to system control for this port + CYG_WORD tx_int_num, // Transmit interrupt number + rx_int_num, // Receive interrupt number + ms_int_num; // Modem Status Change interrupt number + cyg_interrupt serial_tx_interrupt, + serial_rx_interrupt, + serial_ms_interrupt; + cyg_handle_t serial_tx_interrupt_handle, + serial_rx_interrupt_handle, + serial_ms_interrupt_handle; + bool tx_enabled; +} edb7xxx_serial_info; + +static bool edb7xxx_serial_init(struct cyg_devtab_entry *tab); +static bool edb7xxx_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo edb7xxx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char edb7xxx_serial_getc(serial_channel *chan); +static Cyg_ErrNo edb7xxx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void edb7xxx_serial_start_xmit(serial_channel *chan); +static void edb7xxx_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 edb7xxx_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void edb7xxx_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 edb7xxx_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void edb7xxx_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 edb7xxx_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void edb7xxx_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(edb7xxx_serial_funs, + edb7xxx_serial_putc, + edb7xxx_serial_getc, + edb7xxx_serial_set_config, + edb7xxx_serial_start_xmit, + edb7xxx_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL1 +static edb7xxx_serial_info edb7xxx_serial_info1 = {UARTDR1, // Data register + UBLCR1, // Port control + SYSFLG1, // Status + SYSCON1, // System config + CYGNUM_HAL_INTERRUPT_UTXINT1, // Tx interrupt + CYGNUM_HAL_INTERRUPT_URXINT1, // Rx interrupt + 0 /*CYGNUM_HAL_INTERRUPT_UMSINT*/}; // Modem control +#if CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BUFSIZE > 0 +static unsigned char edb7xxx_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BUFSIZE]; +static unsigned char edb7xxx_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(edb7xxx_serial_channel1, + edb7xxx_serial_funs, + edb7xxx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &edb7xxx_serial_out_buf1[0], sizeof(edb7xxx_serial_out_buf1), + &edb7xxx_serial_in_buf1[0], sizeof(edb7xxx_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(edb7xxx_serial_channel1, + edb7xxx_serial_funs, + edb7xxx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(edb7xxx_serial_io1, + CYGDAT_IO_SERIAL_ARM_EDB7XXX_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + edb7xxx_serial_init, + edb7xxx_serial_lookup, // Serial driver may need initializing + &edb7xxx_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL2 + +#ifdef CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL2 +static edb7xxx_serial_info edb7xxx_serial_info2 = {UARTDR2, // Data register + UBLCR2, // Port control + SYSFLG2, // Status + SYSCON2, // System config + CYGNUM_HAL_INTERRUPT_UTXINT2, // Tx interrupt + CYGNUM_HAL_INTERRUPT_URXINT2, // Rx interrupt + 0}; // No modem control +#if CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BUFSIZE > 0 +static unsigned char edb7xxx_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BUFSIZE]; +static unsigned char edb7xxx_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(edb7xxx_serial_channel2, + edb7xxx_serial_funs, + edb7xxx_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &edb7xxx_serial_out_buf2[0], sizeof(edb7xxx_serial_out_buf2), + &edb7xxx_serial_in_buf2[0], sizeof(edb7xxx_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(edb7xxx_serial_channel2, + edb7xxx_serial_funs, + edb7xxx_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_EDB7XXX_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(edb7xxx_serial_io2, + CYGDAT_IO_SERIAL_ARM_EDB7XXX_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + edb7xxx_serial_init, + edb7xxx_serial_lookup, // Serial driver may need initializing + &edb7xxx_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_ARM_EDB7XXX_SERIAL2 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +edb7xxx_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + volatile cyg_uint32 *syscon = (volatile cyg_uint32 *)edb7xxx_chan->syscon; + volatile cyg_uint32 *blcfg = (volatile cyg_uint32 *)edb7xxx_chan->control; + unsigned int baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr; + if (baud_divisor == 0) return false; + // Disable port interrupts while changing hardware + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity] | + UBLCR_FIFOEN | UART_BITRATE(baud_divisor); +#ifdef CYGDBG_IO_INIT + diag_printf("Set CTL: %x = %x\n", blcfg, _lcr); +#endif + *blcfg = _lcr; + *syscon |= SYSCON1_UART1EN; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +edb7xxx_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("EDB7XXX SERIAL init - dev: %x.%d\n", edb7xxx_chan->control, edb7xxx_chan->tx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(edb7xxx_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + edb7xxx_serial_tx_ISR, + edb7xxx_serial_tx_DSR, + &edb7xxx_chan->serial_tx_interrupt_handle, + &edb7xxx_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(edb7xxx_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num); + edb7xxx_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + cyg_drv_interrupt_create(edb7xxx_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + edb7xxx_serial_rx_ISR, + edb7xxx_serial_rx_DSR, + &edb7xxx_chan->serial_rx_interrupt_handle, + &edb7xxx_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(edb7xxx_chan->serial_rx_interrupt_handle); + cyg_drv_interrupt_unmask(edb7xxx_chan->rx_int_num); + } + edb7xxx_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +edb7xxx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +edb7xxx_serial_putc(serial_channel *chan, unsigned char c) +{ + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + volatile cyg_uint8 *data = (volatile cyg_uint8 *)edb7xxx_chan->data; + volatile cyg_uint32 *stat = (volatile cyg_uint32 *)edb7xxx_chan->stat; + if ((*stat & SYSFLG1_UTXFF1) == 0) { +// Transmit buffer/FIFO is not full + *data = c; + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +edb7xxx_serial_getc(serial_channel *chan) +{ + unsigned char c; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + volatile cyg_uint32 *data = (volatile cyg_uint32 *)edb7xxx_chan->data; + volatile cyg_uint32 *stat = (volatile cyg_uint32 *)edb7xxx_chan->stat; + while (*stat & SYSFLG1_URXFE1) ; // Wait for char + c = *data; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +edb7xxx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != edb7xxx_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +edb7xxx_serial_start_xmit(serial_channel *chan) +{ + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + edb7xxx_chan->tx_enabled = true; + cyg_drv_interrupt_unmask(edb7xxx_chan->tx_int_num); +} + +// Disable the transmitter on the device +static void +edb7xxx_serial_stop_xmit(serial_channel *chan) +{ + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num); + edb7xxx_chan->tx_enabled = false; +} + +// Serial I/O - low level Tx interrupt handler (ISR) +static cyg_uint32 +edb7xxx_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(edb7xxx_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Tx interrupt handler (DSR) +static void +edb7xxx_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (edb7xxx_chan->tx_enabled) { + cyg_drv_interrupt_unmask(edb7xxx_chan->tx_int_num); + } +} + +// Serial I/O - low level Rx interrupt handler (ISR) +static cyg_uint32 +edb7xxx_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(edb7xxx_chan->rx_int_num); + cyg_drv_interrupt_acknowledge(edb7xxx_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Rx interrupt handler (DSR) +static void +edb7xxx_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + volatile cyg_uint32 *datreg = (volatile cyg_uint32 *)edb7xxx_chan->data; + volatile cyg_uint32 *stat = (volatile cyg_uint32 *)edb7xxx_chan->stat; + while (!(*stat & SYSFLG1_URXFE1)) + (chan->callbacks->rcv_char)(chan, *datreg); + cyg_drv_interrupt_unmask(edb7xxx_chan->rx_int_num); +} + +// Serial I/O - low level Ms interrupt handler (ISR) +static cyg_uint32 +edb7xxx_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(edb7xxx_chan->ms_int_num); + cyg_drv_interrupt_acknowledge(edb7xxx_chan->ms_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Ms interrupt handler (DSR) +static void +edb7xxx_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ +} +#endif // CYGPKG_IO_SERIAL_ARM_EDB7XXX + diff --git a/ecos/packages/devs/serial/arm/edb7xxx/current/src/edb7xxx_serial.h b/ecos/packages/devs/serial/arm/edb7xxx/current/src/edb7xxx_serial.h new file mode 100644 index 0000000..2be9b47 --- /dev/null +++ b/ecos/packages/devs/serial/arm/edb7xxx/current/src/edb7xxx_serial.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_ARM_EDB7XXX_SERIAL_H +#define CYGONCE_ARM_EDB7XXX_SERIAL_H + +// ==================================================================== +// +// edb7xxx_serial.h +// +// Device I/O - Description of Cirrus Logic EDB7XXX serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Cirrus Logic EDB7XXX + +#include <cyg/hal/hal_edb7xxx.h> // Hardware definitions + +static unsigned int select_word_length[] = { + UBLCR_WRDLEN5, // 5 bits / word (char) + UBLCR_WRDLEN6, + UBLCR_WRDLEN7, + UBLCR_WRDLEN8 +}; + +static unsigned int select_stop_bits[] = { + 0, + 0, // 1 stop bit + 0, // 1.5 stop bit + UBLCR_XSTOP // 2 stop bits +}; + +static unsigned int select_parity[] = { + 0, // No parity + UBLCR_PRTEN|UBLCR_EVENPRT, // Even parity + UBLCR_PRTEN, // Odd parity + 0, // Mark parity + 0, // Space parity +}; + +// Baud rate values, based on PLL clock + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_ARM_EDB7XXX_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/gps4020/current/ChangeLog b/ecos/packages/devs/serial/arm/gps4020/current/ChangeLog new file mode 100644 index 0000000..4d23b04 --- /dev/null +++ b/ecos/packages/devs/serial/arm/gps4020/current/ChangeLog @@ -0,0 +1,29 @@ +2003-11-10 Gary Thomas <gary@mlbassoc.com> + + * src/gps4020_serial.c: + + * cdl/ser_arm_gps4020.cdl: New package - serial driver for GPS4020 + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/gps4020/current/cdl/ser_arm_gps4020.cdl b/ecos/packages/devs/serial/arm/gps4020/current/cdl/ser_arm_gps4020.cdl new file mode 100644 index 0000000..ba4fc97 --- /dev/null +++ b/ecos/packages/devs/serial/arm/gps4020/current/cdl/ser_arm_gps4020.cdl @@ -0,0 +1,208 @@ +# ==================================================================== +# +# ser_arm_gps4020.cdl +# +# eCos GPS4020 serial driver configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_GPS4020 { + display "GPS4020 serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_GPS4020 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + GPS-4020 board." + + compile -library=libextras.a gps4020_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_gps4020.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL1 { + display "GPS4020 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the GPS4020 + port 1." + + + cdl_option CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL1_NAME { + display "Device name for the GPS4020 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the ARM + GPS4020 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BAUD { + display "Baud rate for the GPS4020 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 57600 + description " + This option specifies the default baud rate (speed) for the ARM + GPS4020 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE { + display "Buffer size for the GPS4020 serial port 1 driver" + flavor data + default_value 128 + legal_values 0 to 8192 + description " + This option specifies the size of the internal buffers used + for the GPS4020 port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 { + display "GPS4020 serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM + GPS4020 port 2." + + cdl_option CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL2_NAME { + display "Device name for the GPS4020 serial port 2 driver" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the name of serial device for the ARM + GPS4020 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BAUD { + display "Baud rate for the GPS4020 serial port 2 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 57600 + description " + This option specifies the default baud rate (speed) for the + GPS4020 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE { + display "Buffer size for the GPS4020 serial port 2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the GPS4020 port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_GPS4020_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_GPS4020_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL1 + + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"gps4020\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_gps4020.cdl diff --git a/ecos/packages/devs/serial/arm/gps4020/current/src/gps4020_serial.c b/ecos/packages/devs/serial/arm/gps4020/current/src/gps4020_serial.c new file mode 100644 index 0000000..74ee83e --- /dev/null +++ b/ecos/packages/devs/serial/arm/gps4020/current/src/gps4020_serial.c @@ -0,0 +1,463 @@ +//========================================================================== +// +// io/serial/arm/gps4020_serial.c +// +// GPS4020 Serial I/O Interface Module +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: GPS4020 Serial I/O module +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_if.h> + +#include <cyg/hal/gps4020.h> // Hardware definitions + +static short select_word_length[] = { + -1, // 5 bits / word (char) + -1, // 6 bits / word + SMR_LENGTH_7, // 7 bits/word + SMR_LENGTH_8 // 8 bits/word +}; + +static short select_stop_bits[] = { + -1, + SMR_STOP_1, // 1 stop bit + -1, // 1.5 stop bit + SMR_STOP_2 // 2 stop bits +}; + +static short select_parity[] = { + SMR_PARITY_OFF, // No parity + SMR_PARITY_ON|SMR_PARITY_EVEN, // Even parity + SMR_PARITY_ON|SMR_PARITY_ODD, // Odd parity + -1, // Mark parity + -1, // Space parity +}; + +// Baud rate values, based on internal system (20MHz) clock +// Note: the extra *10 stuff is for rounding. Since these values +// are so small, a little error here can make/break the calculation +#define BAUD_DIVISOR(baud) (((((20000000*10)/(16*baud))+5)/10)-1) +static cyg_int32 select_baud[] = { + 0, // Unused + BAUD_DIVISOR(50), // 50 + BAUD_DIVISOR(75), // 75 + BAUD_DIVISOR(110), // 110 + 0, // 134.5 + BAUD_DIVISOR(150), // 150 + BAUD_DIVISOR(200), // 200 + BAUD_DIVISOR(300), // 300 + BAUD_DIVISOR(600), // 600 + BAUD_DIVISOR(1200), // 1200 + BAUD_DIVISOR(1800), // 1800 + BAUD_DIVISOR(2400), // 2400 + BAUD_DIVISOR(3600), // 3600 + BAUD_DIVISOR(4800), // 4800 + BAUD_DIVISOR(7200), // 7200 + BAUD_DIVISOR(9600), // 9600 + BAUD_DIVISOR(14400), // 14400 + BAUD_DIVISOR(19200), // 19200 + BAUD_DIVISOR(38400), // 38400 + BAUD_DIVISOR(57600), // 57600 + BAUD_DIVISOR(115200), // 115200 + BAUD_DIVISOR(230400), // 230400 +}; + +typedef struct gps4020_serial_info { + CYG_ADDRWORD regs; // Pointer to UART registers + CYG_WORD tx_int_num, // Transmit interrupt number + rx_int_num, // Receive interrupt number + ms_int_num; // Modem Status Change interrupt number + cyg_interrupt serial_tx_interrupt, + serial_rx_interrupt, + serial_ms_interrupt; + cyg_handle_t serial_tx_interrupt_handle, + serial_rx_interrupt_handle, + serial_ms_interrupt_handle; + bool tx_enabled; +} gps4020_serial_info; + +static bool gps4020_serial_init(struct cyg_devtab_entry *tab); +static bool gps4020_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo gps4020_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char gps4020_serial_getc(serial_channel *chan); +static Cyg_ErrNo gps4020_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void gps4020_serial_start_xmit(serial_channel *chan); +static void gps4020_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 gps4020_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void gps4020_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 gps4020_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void gps4020_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#if 0 // FIXME - handle modem & errors +static cyg_uint32 gps4020_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void gps4020_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#endif + +static SERIAL_FUNS(gps4020_serial_funs, + gps4020_serial_putc, + gps4020_serial_getc, + gps4020_serial_set_config, + gps4020_serial_start_xmit, + gps4020_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL1 +static gps4020_serial_info gps4020_serial_info1 = {GPS4020_UART1, // Data register + CYGNUM_HAL_INTERRUPT_UART1_TX, // Tx interrupt + CYGNUM_HAL_INTERRUPT_UART1_RX, // Rx interrupt + CYGNUM_HAL_INTERRUPT_UART1_ERR, // Modem & Error interrupt + }; +#if CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE > 0 +static unsigned char gps4020_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE]; +static unsigned char gps4020_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(gps4020_serial_channel1, + gps4020_serial_funs, + gps4020_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &gps4020_serial_out_buf1[0], sizeof(gps4020_serial_out_buf1), + &gps4020_serial_in_buf1[0], sizeof(gps4020_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(gps4020_serial_channel1, + gps4020_serial_funs, + gps4020_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(gps4020_serial_io1, + CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + gps4020_serial_init, + gps4020_serial_lookup, // Serial driver may need initializing + &gps4020_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 + +#ifdef CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 +static gps4020_serial_info gps4020_serial_info2 = {GPS4020_UART2, // Data register + CYGNUM_HAL_INTERRUPT_UART2_TX, // Tx interrupt + CYGNUM_HAL_INTERRUPT_UART2_RX, // Rx interrupt + CYGNUM_HAL_INTERRUPT_UART2_ERR, // Modem & Error interrupt + }; +#if CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE > 0 +static unsigned char gps4020_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE]; +static unsigned char gps4020_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(gps4020_serial_channel2, + gps4020_serial_funs, + gps4020_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &gps4020_serial_out_buf2[0], sizeof(gps4020_serial_out_buf2), + &gps4020_serial_in_buf2[0], sizeof(gps4020_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(gps4020_serial_channel2, + gps4020_serial_funs, + gps4020_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(gps4020_serial_io2, + CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + gps4020_serial_init, + gps4020_serial_lookup, // Serial driver may need initializing + &gps4020_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +gps4020_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + unsigned int baud_divisor = select_baud[new_config->baud]; + short word_len = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + short stop_bits = select_stop_bits[new_config->stop]; + short parity = select_parity[new_config->parity]; + short mode = word_len | stop_bits | parity; + int prescale = 0; + + if (mode >= 0) { + while (baud_divisor > 0xFF) { + prescale++; + baud_divisor >>= 1; + } +#ifdef CYGDBG_IO_INIT + diag_printf("I/O MODE: %x, BAUD: %x\n", mode, baud_divisor); + CYGACC_CALL_IF_DELAY_US((cyg_int32)2*100000); +#endif + regs->mode = mode | SMR_DIV(prescale); + regs->baud = baud_divisor; + regs->modem_control = SMR_DTR | SMR_RTS; + regs->control = SCR_TEN | SCR_REN | SCR_TIE | SCR_RIE; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; + } else { + return false; + } +} + +// Function to initialize the device. Called at bootstrap time. +static bool +gps4020_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("GPS4020 SERIAL init - dev: %x.%d\n", gps4020_chan->regs, gps4020_chan->tx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(gps4020_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + gps4020_serial_tx_ISR, + gps4020_serial_tx_DSR, + &gps4020_chan->serial_tx_interrupt_handle, + &gps4020_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(gps4020_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_mask(gps4020_chan->tx_int_num); + gps4020_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + cyg_drv_interrupt_create(gps4020_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + gps4020_serial_rx_ISR, + gps4020_serial_rx_DSR, + &gps4020_chan->serial_rx_interrupt_handle, + &gps4020_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(gps4020_chan->serial_rx_interrupt_handle); + cyg_drv_interrupt_unmask(gps4020_chan->rx_int_num); + } + gps4020_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +gps4020_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +gps4020_serial_putc(serial_channel *chan, unsigned char c) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + + if ((regs->status & SSR_TxEmpty) != 0) { + // Transmit buffer/FIFO is not full + regs->TxRx = c; + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +gps4020_serial_getc(serial_channel *chan) +{ + unsigned char c; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + + while ((regs->status & SSR_RxFull) == 0) ; // Wait for character + c = regs->TxRx; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +gps4020_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != gps4020_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +gps4020_serial_start_xmit(serial_channel *chan) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + gps4020_chan->tx_enabled = true; + cyg_drv_interrupt_unmask(gps4020_chan->tx_int_num); +} + +// Disable the transmitter on the device +static void +gps4020_serial_stop_xmit(serial_channel *chan) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->tx_int_num); + gps4020_chan->tx_enabled = false; +} + +// Serial I/O - low level Tx interrupt handler (ISR) +static cyg_uint32 +gps4020_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(gps4020_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Tx interrupt handler (DSR) +static void +gps4020_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (gps4020_chan->tx_enabled) { + cyg_drv_interrupt_unmask(gps4020_chan->tx_int_num); + } +} + +// Serial I/O - low level Rx interrupt handler (ISR) +static cyg_uint32 +gps4020_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->rx_int_num); + cyg_drv_interrupt_acknowledge(gps4020_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Rx interrupt handler (DSR) +static void +gps4020_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + + while ((regs->status & SSR_RxFull) != 0) + (chan->callbacks->rcv_char)(chan, regs->TxRx); + cyg_drv_interrupt_unmask(gps4020_chan->rx_int_num); +} + +#if 0 // FIXME - handle modem & errors +// Serial I/O - low level Ms interrupt handler (ISR) +static cyg_uint32 +gps4020_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->ms_int_num); + cyg_drv_interrupt_acknowledge(gps4020_chan->ms_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Ms interrupt handler (DSR) +static void +gps4020_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ +} +#endif + diff --git a/ecos/packages/devs/serial/arm/integrator/current/ChangeLog b/ecos/packages/devs/serial/arm/integrator/current/ChangeLog new file mode 100644 index 0000000..a8b5209 --- /dev/null +++ b/ecos/packages/devs/serial/arm/integrator/current/ChangeLog @@ -0,0 +1,47 @@ +2003-03-18 Gary Thomas <gary@mlbassoc.com> + + * src/integrator_serial_with_ints.c (integrator_serial_set_config): + Flag for CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE is 32 bits. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_integrator.cdl: Remove irrelevant doc link. + +2002-03-06 Nick Garnett <nickg@redhat.com> + + * cdl/ser_arm_integrator.cdl: + Disable testing of 57600 and 115200 baud rates. The CPUs we are + currently using (ARM7TDMI and ARM966E) have no cache and are too + slow to handle the higher baud rates in the FIFO-free UARTs we + have. In the future we may need to revisit this an make it + conditional on the CPU available. + +2001-10-30 Philippe Robin <Philippe.Robin@arm.com> +2001-10-30 Jonathan Larmour <jlarmour@redhat.com> + + * New package for ARM Integrator serial driver derived from + ARM PID serial driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/integrator/current/cdl/ser_arm_integrator.cdl b/ecos/packages/devs/serial/arm/integrator/current/cdl/ser_arm_integrator.cdl new file mode 100644 index 0000000..44049a9 --- /dev/null +++ b/ecos/packages/devs/serial/arm/integrator/current/cdl/ser_arm_integrator.cdl @@ -0,0 +1,177 @@ +# ==================================================================== +# +# ser_arm_integrator.cdl +# +# eCos serial ARM/INTEGRATOR configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): David A Rusling +# Original data: David A Rusling +# Contributors: Philippe Robin +# Date: November 7, 2000 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_INTEGRATOR { + display "ARM INTEGRATOR serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_INTEGRATOR + + requires CYGPKG_ERROR + include_dir cyg/io + description " + This option enables the serial device drivers for the + ARM INTEGRATOR." + + compile -library=libextras.a integrator_serial_with_ints.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_integrator.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL0 { + display "ARM INTEGRATOR serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM INTEGRATOR + port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_NAME { + display "Device name for ARM INTEGRATOR serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + ARM INTEGRATOR port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BAUD { + display "Baud rate for the ARM INTEGRATOR serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 234000 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM INTEGRATOR port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BUFSIZE { + display "Buffer size for the ARM INTEGRATOR serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ARM INTEGRATOR port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL1 { + display "ARM INTEGRATOR serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM INTEGRATOR + port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_NAME { + display "Device name for ARM INTEGRATOR serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device for the + ARM INTEGRATOR port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BAUD { + display "Baud rate for the ARM INTEGRATOR serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 234000 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM INTEGRATOR port 1." + } + } + + cdl_option CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BUFSIZE { + display "Buffer size for the ARM INTEGRATOR serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ARM INTEGRATOR port 1." + } + + cdl_component CYGPKG_IO_SERIAL_ARM_INTEGRATOR_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL0 + + # The combination of non-FIFO UARTs and no cache means that some + # Integrator based systems are too slow to handle the higher baud rates. + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"arminteg\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_integrator.cdl diff --git a/ecos/packages/devs/serial/arm/integrator/current/src/integrator_serial.h b/ecos/packages/devs/serial/arm/integrator/current/src/integrator_serial.h new file mode 100644 index 0000000..57bd6eb --- /dev/null +++ b/ecos/packages/devs/serial/arm/integrator/current/src/integrator_serial.h @@ -0,0 +1,213 @@ +#ifndef CYGONCE_ARM_INTEGRATOR_SERIAL_H +#define CYGONCE_ARM_INTEGRATOR_SERIAL_H + +// ==================================================================== +// +// integrator_serial.h +// +// Device I/O - Description of ARM INTEGRATOR serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): David A Rusling +// Contributors: Philippe Robin +// Date: November 7, 2000 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on ARM INTEGRATOR7T + +struct serial_port { + unsigned char _byte[32]; +}; + +// Little-endian version +#if (CYG_BYTEORDER == CYG_LSBFIRST) + +#define reg(n) _byte[n*4] + +#else // Big-endian version + +#define reg(n) _byte[(n*4)^3] + +#endif + +/* ------------------------------------------------------------------------------- + * From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03) + * ------------------------------------------------------------------------------- + * UART Register Offsets. + * + */ +#define AMBA_UARTDR 0x00 /* Data read or written from the interface. */ +#define AMBA_UARTRSR 0x04 /* Receive status register (Read). */ +#define AMBA_UARTECR 0x04 /* Error clear register (Write). */ +#define AMBA_UARTLCR_H 0x08 /* Line control register, high byte. */ +#define AMBA_UARTLCR_M 0x0C /* Line control register, middle byte. */ +#define AMBA_UARTLCR_L 0x10 /* Line control register, low byte. */ +#define AMBA_UARTCR 0x14 /* Control register. */ +#define AMBA_UARTFR 0x18 /* Flag register (Read only). */ +#define AMBA_UARTIIR 0x1C /* Interrupt indentification register (Read). */ +#define AMBA_UARTICR 0x1C /* Interrupt clear register (Write). */ +#define AMBA_UARTILPR 0x20 /* IrDA low power counter register. */ + +#define AMBA_UARTRSR_OE 0x08 +#define AMBA_UARTRSR_BE 0x04 +#define AMBA_UARTRSR_PE 0x02 +#define AMBA_UARTRSR_FE 0x01 + +#define AMBA_UARTFR_TXFF 0x20 +#define AMBA_UARTFR_RXFE 0x10 +#define AMBA_UARTFR_BUSY 0x08 +#define AMBA_UARTFR_TMSK (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY) + +#define AMBA_UARTCR_RTIE 0x40 +#define AMBA_UARTCR_TIE 0x20 +#define AMBA_UARTCR_RIE 0x10 +#define AMBA_UARTCR_MSIE 0x08 +#define AMBA_UARTCR_IIRLP 0x04 +#define AMBA_UARTCR_SIREN 0x02 +#define AMBA_UARTCR_UARTEN 0x01 + +#define AMBA_UARTLCR_H_WLEN_8 0x60 +#define AMBA_UARTLCR_H_WLEN_7 0x40 +#define AMBA_UARTLCR_H_WLEN_6 0x20 +#define AMBA_UARTLCR_H_WLEN_5 0x00 +#define AMBA_UARTLCR_H_FEN 0x10 +#define AMBA_UARTLCR_H_STP2 0x08 +#define AMBA_UARTLCR_H_EPS 0x04 +#define AMBA_UARTLCR_H_PEN 0x02 +#define AMBA_UARTLCR_H_BRK 0x01 + +#define AMBA_UARTIIR_RTIS 0x08 +#define AMBA_UARTIIR_TIS 0x04 +#define AMBA_UARTIIR_RIS 0x02 +#define AMBA_UARTIIR_MIS 0x01 + +#define ARM_BAUD_460800 1 +#define ARM_BAUD_230400 3 +#define ARM_BAUD_115200 7 +#define ARM_BAUD_57600 15 +#define ARM_BAUD_38400 23 +#define ARM_BAUD_19200 47 +#define ARM_BAUD_14400 63 +#define ARM_BAUD_9600 95 +#define ARM_BAUD_4800 191 +#define ARM_BAUD_2400 383 +#define ARM_BAUD_1200 767 + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x20 +#define LCR_WL7 0x40 +#define LCR_WL8 0x60 + +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x00 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x08 + +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x06 // Parity mode - even +#define LCR_PO 0x02 // Parity mode - odd +#define LCR_PM 0x00 // Forced "mark" parity +#define LCR_PS 0x00 // Forced "space" parity + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + ARM_BAUD_1200, // 1200 + 0, // 1800 + ARM_BAUD_2400, // 2400 + 0, // 3600 + ARM_BAUD_4800, // 4800 + 0, // 7200 + ARM_BAUD_9600, // 9600 + ARM_BAUD_14400, // 14400 + ARM_BAUD_19200, // 19200 + ARM_BAUD_38400, // 38400 + ARM_BAUD_57600, // 57600 + ARM_BAUD_115200, // 115200 + ARM_BAUD_230400, // 230400 +}; + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +#endif // CYGONCE_ARM_INTEGRATOR_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/integrator/current/src/integrator_serial_with_ints.c b/ecos/packages/devs/serial/arm/integrator/current/src/integrator_serial_with_ints.c new file mode 100644 index 0000000..4d2a2b7 --- /dev/null +++ b/ecos/packages/devs/serial/arm/integrator/current/src/integrator_serial_with_ints.c @@ -0,0 +1,410 @@ +//========================================================================== +// +// io/serial/arm/integrator_serial_with_ints.c +// +// ARM INTEGRATOR Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): David A Rusling +// Contributors: Philippe Robin +// Date: November 7, 2000 +// Purpose: INTEGRATOR Serial I/O module (interrupt driven) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io.h> +#include <pkgconf/io_serial.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_INTEGRATOR +#include "integrator_serial.h" + +typedef struct integrator_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} integrator_serial_info; + +static bool integrator_serial_init(struct cyg_devtab_entry *tab); +static bool integrator_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo integrator_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char integrator_serial_getc(serial_channel *chan); +static Cyg_ErrNo integrator_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void integrator_serial_start_xmit(serial_channel *chan); +static void integrator_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 integrator_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void integrator_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(integrator_serial_funs, + integrator_serial_putc, + integrator_serial_getc, + integrator_serial_set_config, + integrator_serial_start_xmit, + integrator_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL0 +#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ +static integrator_serial_info integrator_serial_info0 = {INTEGRATOR_UART0_BASE, CYGNUM_HAL_INTERRUPT_UARTINT0}; +#if CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BUFSIZE > 0 +static unsigned char integrator_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BUFSIZE]; +static unsigned char integrator_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(integrator_serial_channel0, + integrator_serial_funs, + integrator_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &integrator_serial_out_buf0[0], sizeof(integrator_serial_out_buf0), + &integrator_serial_in_buf0[0], sizeof(integrator_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(integrator_serial_channel0, + integrator_serial_funs, + integrator_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(integrator_serial_io0, + CYGDAT_IO_SERIAL_ARM_INTEGRATOR_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + integrator_serial_init, + integrator_serial_lookup, // Serial driver may need initializing + &integrator_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL1 +#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ +static integrator_serial_info integrator_serial_info1 = {INTEGRATOR_UART1_BASE, CYGNUM_HAL_INTERRUPT_UARTINT1}; +#if CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BUFSIZE > 0 +static unsigned char integrator_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BUFSIZE]; +static unsigned char integrator_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(integrator_serial_channel1, + integrator_serial_funs, + integrator_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &integrator_serial_out_buf1[0], sizeof(integrator_serial_out_buf1), + &integrator_serial_in_buf1[0], sizeof(integrator_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(integrator_serial_channel1, + integrator_serial_funs, + integrator_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(integrator_serial_io1, + CYGDAT_IO_SERIAL_ARM_INTEGRATOR_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + integrator_serial_init, + integrator_serial_lookup, // Serial driver may need initializing + &integrator_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_INTEGRATOR_SERIAL1 + +#define GET_INTERRUPT_STATUS(p) IO_READ((p) + AMBA_UARTIIR) +#define GET_STATUS(p) (IO_READ((p) + AMBA_UARTFR)) +#define GET_CHAR(p) (IO_READ((p) + AMBA_UARTDR)) +#define PUT_CHAR(p, c) (IO_WRITE(((p) + AMBA_UARTDR), (c))) +#define IO_READ(p) ((*(volatile unsigned int *)(p)) & 0xFF) +#define IO_WRITE(p, c) (*(unsigned int *)(p) = (c)) +#define RX_DATA(s) (((s) & AMBA_UARTFR_RXFE) == 0) +#define TX_READY(s) (((s) & AMBA_UARTFR_TXFF) == 0) +#define TX_EMPTY(p) ((GET_STATUS(p) & AMBA_UARTFR_TMSK) == 0) + +// debugging help +static int chars_rx = 0 ; +static int chars_tx = 0 ; + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +integrator_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + unsigned int port = (unsigned int)integrator_chan->base; + unsigned short baud_divisor = select_baud[new_config->baud]; + unsigned char _lcr ; + + // don't do this baud rate... + if (baud_divisor == 0) return false; // Invalid configuration + + // first, disable everything + IO_WRITE(port + AMBA_UARTCR, 0x0); + + // Set baud rate + IO_WRITE(port + AMBA_UARTLCR_M, ((baud_divisor & 0xf00) >> 8)); + IO_WRITE(port + AMBA_UARTLCR_L, (baud_divisor & 0xff)); + + // ----------v----------v----------v----------v---------- + // NOTE: MUST BE WRITTEN LAST (AFTER UARTLCR_M & UARTLCR_L) + // ----------^----------^----------^----------^---------- + _lcr = + select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity] | AMBA_UARTLCR_H_FEN ; + IO_WRITE(port + AMBA_UARTLCR_H, _lcr); + + // finally, enable the uart + IO_WRITE(port + AMBA_UARTCR, (AMBA_UARTCR_RIE | AMBA_UARTCR_RTIE | AMBA_UARTCR_UARTEN)); + + // save the configuration + if (new_config != &chan->config) { + chan->config = *new_config; + } + + // success + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +integrator_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("INTEGRATOR SERIAL init - dev: %x.%d\n", integrator_chan->base, integrator_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(integrator_chan->int_num, + 99, // Priority - what goes here? + (cyg_addrword_t)chan, // Data item passed to interrupt handler + integrator_serial_ISR, + integrator_serial_DSR, + &integrator_chan->serial_interrupt_handle, + &integrator_chan->serial_interrupt); + cyg_drv_interrupt_attach(integrator_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(integrator_chan->int_num); + } + integrator_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +integrator_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +integrator_serial_putc(serial_channel *chan, unsigned char c) +{ + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + unsigned int status = GET_STATUS(integrator_chan->base) ; + + if (TX_READY(status)) { +// Transmit buffer is empty + PUT_CHAR(integrator_chan->base, c) ; + chars_tx++ ; + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +integrator_serial_getc(serial_channel *chan) +{ + unsigned char c; + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + unsigned int status ; + + do { + status = GET_STATUS(integrator_chan->base) ; + } while (!RX_DATA(status)) ; // Wait for char + + chars_rx++ ; + + // get it + c = GET_CHAR(integrator_chan->base) ; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +integrator_serial_set_config(serial_channel *chan, cyg_uint32 key, const void *xbuf, + cyg_uint32 *len) +{ + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != integrator_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW +#ifdef FIXME + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + volatile struct serial_port *port = (volatile struct serial_port *)integrator_chan->base; + cyg_uint32 *f = (cyg_uint32 *)xbuf; + unsigned char mask=0; + if ( *len < *f ) + return -EINVAL; + + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) + mask = MCR_RTS; + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX ) + mask |= MCR_DTR; + if (*f) // we should throttle + port->REG_mcr &= ~mask; + else // we should no longer throttle + port->REG_mcr |= mask; + } + break; + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + // Nothing to do because we do support both RTSCTS and DSRDTR flow + // control. + // Other targets would clear any unsupported flags here. + // We just return ENOERR. + break; +#else +#error "Flow control for Integrator not integrated!" +#endif +#endif + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +integrator_serial_start_xmit(serial_channel *chan) +{ + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + + IO_WRITE(integrator_chan->base + AMBA_UARTCR, + IO_READ(integrator_chan->base + AMBA_UARTCR) | AMBA_UARTCR_TIE); +} + +// Disable the transmitter on the device +static void +integrator_serial_stop_xmit(serial_channel *chan) +{ + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + + IO_WRITE(integrator_chan->base + AMBA_UARTCR, + IO_READ(integrator_chan->base + AMBA_UARTCR) & ~AMBA_UARTCR_TIE); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +integrator_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(integrator_chan->int_num); + cyg_drv_interrupt_acknowledge(integrator_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +integrator_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + integrator_serial_info *integrator_chan = (integrator_serial_info *)chan->dev_priv; + volatile unsigned char isr = GET_INTERRUPT_STATUS(integrator_chan->base) ; + + while ((isr & (AMBA_UARTIIR_RTIS | AMBA_UARTIIR_TIS | AMBA_UARTIIR_RIS)) != 0) { + if (isr & AMBA_UARTIIR_TIS) { + (chan->callbacks->xmt_char)(chan); + } else if (isr & AMBA_UARTIIR_RTIS) { + chars_rx++ ; + (chan->callbacks->rcv_char)(chan, GET_CHAR(integrator_chan->base)); + } else if (isr & AMBA_UARTIIR_RIS) { + chars_rx++ ; + (chan->callbacks->rcv_char)(chan, GET_CHAR(integrator_chan->base)); + } + isr = GET_INTERRUPT_STATUS(integrator_chan->base) ; + } + cyg_drv_interrupt_unmask(integrator_chan->int_num); +} +#endif diff --git a/ecos/packages/devs/serial/arm/iop310/current/ChangeLog b/ecos/packages/devs/serial/arm/iop310/current/ChangeLog new file mode 100644 index 0000000..4acc098 --- /dev/null +++ b/ecos/packages/devs/serial/arm/iop310/current/ChangeLog @@ -0,0 +1,41 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_iop310.cdl: Remove irrelevant doc link. + +2002-11-12 Gary Thomas <gary@mlbassoc.com> + + * include/arm_iop310_ser.inl: + * cdl/ser_arm_iop310.cdl: New Xscale platforms layout. + +2001-09-03 Jesper Skov <jskov@redhat.com> + + * include/arm_iq80310_ser.inl: Fix interrupt vector name typos. + +2000-10-25 Mark Salter <msalter@redhat.com> + + * include/arm_iq80310_ser.inl: Initial checkin. + * cdl/ser_arm_iq80310.cdl: Ditto. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/iop310/current/cdl/ser_arm_iop310.cdl b/ecos/packages/devs/serial/arm/iop310/current/cdl/ser_arm_iop310.cdl new file mode 100644 index 0000000..b9d5e23 --- /dev/null +++ b/ecos/packages/devs/serial/arm/iop310/current/cdl/ser_arm_iop310.cdl @@ -0,0 +1,197 @@ +# ==================================================================== +# +# ser_arm_iop310.cdl +# +# eCos serial IQ80200/80310 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: msalter, gthomas +# Contributors: +# Date: 2000-10-10 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310 { + display "XScale IOP310 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_XSCALE_IOP310 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Xscale board using the IOP310 chipset." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 1" + } + + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_iop310_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_xscale_iop310.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL0 { + display "ARM Xscale IOP310 serial port 0 driver" + flavor bool + default_value 1 + active_if { CYGHWR_HAL_ARM_IQ80310_SERIAL_PORTA != 0 } + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + Xscale IOP310 port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_IOP310_SERIAL0_NAME { + display "Device name for IOP310 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the Xscale IOP310 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BAUD { + display "Baud rate for the Xscale IOP310 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the Xscale IOP310 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BUFSIZE { + display "Buffer size for the Xscale IOP310 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the Xscale IOP310 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL1 { + display "ARM Xscale IOP310 serial port 1 driver" + flavor bool + default_value 1 + active_if { CYGHWR_HAL_ARM_IQ80310_SERIAL_PORTB != 0 } + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the Xscale + IOP310 port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_IOP310_SERIAL1_NAME { + display "Device name for IOP310 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device + for the Xscale IOP310 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BAUD { + display "Baud rate for the Xscale IOP310 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the Xscale IOP310 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BUFSIZE { + display "Buffer size for the Xscale IOP310 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the Xscale IOP310 port 1." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_IOP310_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_IOP310_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"iop310\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_iop310.cdl diff --git a/ecos/packages/devs/serial/arm/iop310/current/include/arm_iop310_ser.inl b/ecos/packages/devs/serial/arm/iop310/current/include/arm_iop310_ser.inl new file mode 100644 index 0000000..c6eb5c2 --- /dev/null +++ b/ecos/packages/devs/serial/arm/iop310/current/include/arm_iop310_ser.inl @@ -0,0 +1,161 @@ +//========================================================================== +// +// io/serial/arm/arm_iop310_ser.inl +// +// Cyclone IOP310 Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2000-10-10 +// Purpose: IOP310 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 1047, // 110 + 0, // 134.5 + 768, // 150 + 0, // 200 + 384, // 300 + 192, // 600 + 96, // 1200 + 24, // 1800 + 48, // 2400 + 0, // 3600 + 24, // 4800 + 16, // 7200 + 12, // 9600 + 8, // 14400 + 6, // 19200 + 3, // 38400 + 2, // 57600 + 1, // 115200 +}; + +#ifdef CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL0 +static pc_serial_info iop310_serial_info0 = {IOP310_SERIAL_PORT_A, + CYGNUM_HAL_INTERRUPT_SERIAL_A}; +#if CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BUFSIZE > 0 +static unsigned char iop310_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BUFSIZE]; +static unsigned char iop310_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(iop310_serial_channel0, + pc_serial_funs, + iop310_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &iop310_serial_out_buf0[0], sizeof(iop310_serial_out_buf0), + &iop310_serial_in_buf0[0], sizeof(iop310_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(iop310_serial_channel0, + pc_serial_funs, + iop310_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(iop310_serial_io0, + CYGDAT_IO_SERIAL_ARM_IOP310_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &iop310_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL1 +static pc_serial_info iop310_serial_info1 = {IOP310_SERIAL_PORT_B, + CYGNUM_HAL_INTERRUPT_SERIAL_B}; +#if CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BUFSIZE > 0 +static unsigned char iop310_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BUFSIZE]; +static unsigned char iop310_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(iop310_serial_channel1, + pc_serial_funs, + iop310_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &iop310_serial_out_buf1[0], sizeof(iop310_serial_out_buf1), + &iop310_serial_in_buf1[0], sizeof(iop310_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(iop310_serial_channel1, + pc_serial_funs, + iop310_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_IOP310_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(iop310_serial_io1, + CYGDAT_IO_SERIAL_ARM_IOP310_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &iop310_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_IOP310_SERIAL1 + +// EOF arm_iop310_ser.inl diff --git a/ecos/packages/devs/serial/arm/iq80321/current/ChangeLog b/ecos/packages/devs/serial/arm/iq80321/current/ChangeLog new file mode 100644 index 0000000..8c31537 --- /dev/null +++ b/ecos/packages/devs/serial/arm/iq80321/current/ChangeLog @@ -0,0 +1,33 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_iq80321.cdl: Remove irrelevant doc link. + +2002-01-25 Nick Garnett <nickg@redhat.com> + + * include/arm_iq80321_ser.inl: + * cdl/ser_arm_iq80321.cdl: + IQ80321 files created, by copying the IQ80310 versions and editing. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/iq80321/current/cdl/ser_arm_iq80321.cdl b/ecos/packages/devs/serial/arm/iq80321/current/cdl/ser_arm_iq80321.cdl new file mode 100644 index 0000000..41396aa --- /dev/null +++ b/ecos/packages/devs/serial/arm/iq80321/current/cdl/ser_arm_iq80321.cdl @@ -0,0 +1,150 @@ +# ==================================================================== +# +# ser_arm_iq80321.cdl +# +# eCos serial IQ80321 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: msalter +# Contributors: +# Date: 2000-10-10 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_IQ80321 { + display "XScale IQ80321 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_XSCALE_IQ80321 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + IQ80321 evaluation board." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 1" + } + + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_iq80321_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_iq80321.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_IQ80321_SERIAL0 { + display "ARM IQ80321 serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the Cyclone + IQ80321 port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_IQ80321_SERIAL0_NAME { + display "Device name for IQ80321 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the Cyclone IQ80321 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BAUD { + display "Baud rate for the Cyclone IQ80321 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 } + default_value 115200 + description " + This option specifies the default baud rate (speed) + for the Cyclone IQ80321 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BUFSIZE { + display "Buffer size for the Cyclone IQ80321 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the Cyclone IQ80321 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_IQ80321_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_IQ80321_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_IQ80321_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"iq80321\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_iq80321.cdl diff --git a/ecos/packages/devs/serial/arm/iq80321/current/include/arm_iq80321_ser.inl b/ecos/packages/devs/serial/arm/iq80321/current/include/arm_iq80321_ser.inl new file mode 100644 index 0000000..3affcf2 --- /dev/null +++ b/ecos/packages/devs/serial/arm/iq80321/current/include/arm_iq80321_ser.inl @@ -0,0 +1,122 @@ +//========================================================================== +// +// io/serial/arm/arm_iq80321_ser.inl +// +// IQ80321 Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2000-10-10 +// Purpose: IQ80321 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/iq80321.h> // platform definitions + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 1047, // 110 + 0, // 134.5 + 768, // 150 + 0, // 200 + 384, // 300 + 192, // 600 + 96, // 1200 + 24, // 1800 + 48, // 2400 + 0, // 3600 + 24, // 4800 + 16, // 7200 + 12, // 9600 + 8, // 14400 + 6, // 19200 + 3, // 38400 + 2, // 57600 + 1, // 115200 +}; + +#ifdef CYGPKG_IO_SERIAL_ARM_IQ80321_SERIAL0 +static pc_serial_info iq80321_serial_info0 = {IQ80321_UART_ADDR, + CYGNUM_HAL_INTERRUPT_UART}; +#if CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BUFSIZE > 0 +static unsigned char iq80321_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BUFSIZE]; +static unsigned char iq80321_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(iq80321_serial_channel0, + pc_serial_funs, + iq80321_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &iq80321_serial_out_buf0[0], sizeof(iq80321_serial_out_buf0), + &iq80321_serial_in_buf0[0], sizeof(iq80321_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(iq80321_serial_channel0, + pc_serial_funs, + iq80321_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_IQ80321_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(iq80321_serial_io0, + CYGDAT_IO_SERIAL_ARM_IQ80321_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &iq80321_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_IQ80321_SERIAL0 + +// EOF arm_iq80321_ser.inl diff --git a/ecos/packages/devs/serial/arm/lpc24xx/current/ChangeLog b/ecos/packages/devs/serial/arm/lpc24xx/current/ChangeLog new file mode 100755 index 0000000..90a9c0e --- /dev/null +++ b/ecos/packages/devs/serial/arm/lpc24xx/current/ChangeLog @@ -0,0 +1,39 @@ +2011-12-21 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_arm_lpc24xx.cdl: + Fixed interrupt priority. [ Bugzilla 1001432 ] + +2010-12-29 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_arm_lpc24xx.cdl: + * include/arm_lpc24xx_ser.inl: + Added support for LPC17XX CPUs. + +2008-07-07 Uwe Kindler <uwe_kindler@web.de> + + * include/arm_lpc24xx_ser.inl: + Serial driver for ARM LPC24XX, using generic 16X5X driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl b/ecos/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl new file mode 100755 index 0000000..87a2f5f --- /dev/null +++ b/ecos/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl @@ -0,0 +1,192 @@ +# ==================================================================== +# +# ser_arm_lpc24xx.cdl +# +# eCos serial ARM LPC24XX / Cortex-M LPC17XX configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Uwe Kindler +# Original data: gthomas, jskov +# Contributors: ilijak +# Date: 2008-07-06 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX { + display "ARM LPC24XX / Cortex-M LPC17XX serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if ( CYGPKG_HAL_ARM_LPC24XX || CYGPKG_HAL_CORTEXM_LPC17XX ) + implements CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the ARM + LPC24XX and Cortex-M LPC17XX." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4" + } + + requires { + is_active(CYGPKG_HAL_CORTEXM_LPC17XX) + implies CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME == "1" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_lpc24xx_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_lpc24xx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + # For backward compatibility with LPC24XX platforms + cdl_option CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN { + display "Interrupt priority levels" + flavor data + calculated { CYGNUM_HAL_IRQ_PRIORITY_MIN ? CYGNUM_HAL_IRQ_PRIORITY_MIN : 15 } + description " + For backward compatibility with LPC 24XX plarforms that + do not have CYGNUM_HAL_IRQ_PRIORITY_MIN defined." + } + + # Support up to 4 on-chip UART modules. The number may vary between + # processor variants so it is easy to update this here + for { set ::channel 0 } { $::channel < 4 } { incr ::channel } { + + cdl_interface CYGINT_IO_SERIAL_LPC24XX_UART[set ::channel] { + display "Platform provides UART [set ::channel]" + flavor bool + description " + This interface will be implemented if the specific + LPC24XX / LPC17XX processor being used has on-chip UART + [set ::channel], and if that UART is accessible on the + target hardware." + } + + cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel] { + display "ARM LPC24XX / Cortex LPC17XX UART [set ::channel] driver" + flavor bool + active_if CYGINT_IO_SERIAL_LPC24XX_UART[set ::channel] + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + ARM LPC24XX / LPC17XX UART [set ::channel]." + + cdl_option CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_NAME { + display "Device name for UART [set ::channel]" + flavor data + default_value [format {"\"/dev/ser%d\""} $::channel] + description " + This option specifies the name of the serial device + for the ARM LPC24XX / LPC17XX UART [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_BAUD { + display "Baud rate for UART [set ::channel]" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 + 2400 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the ARM LPC24XX / LPC17XX UART [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_BUFSIZE { + display "Buffer size for the UART [set ::channel]" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the ARM LPC24XX / LPC17XX UART [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_INTPRIO { + display "Interrupt priority of UART [set ::channel]" + flavor data + legal_values 0 to CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN + default_value CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN + description " + This option selects the interupt priority for + the UART [set ::channel] interrupts. The + reset value of these registers defaults all interrupt + to the lowest priority, allowing a single write to + elevate the priority of an individual interrupt." + } + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armlpc24xx\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_lpc24xx.cdl diff --git a/ecos/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl b/ecos/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl new file mode 100755 index 0000000..a178846 --- /dev/null +++ b/ecos/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl @@ -0,0 +1,350 @@ +//========================================================================== +// +// io/serial/arm/arm_lpc24xx_ser.inl +// +// ARM LPC24XX / Cortex-M LPC17XX Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Uwe Kindler +// Contributors: gthomas, jlarmour, ilijak +// Date: 2008-06-07 +// Purpose: LPC24XX and LPC17XX Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + + +//========================================================================== +// INCLUDES +//========================================================================== +#include <cyg/hal/hal_intr.h> + +#ifdef CYGPKG_HAL_CORTEXM_LPC17XX +# include <cyg/hal/lpc17xx_misc.h> +#else +# include <cyg/hal/lpc24xx_misc.h> +#endif + +//========================================================================== +// STATIC DATA +//========================================================================== +// Baud rate specification +static const unsigned int select_baud[] = +{ + 9999, // Unused + 50, + 75, + 110, + 134.5, + 150, + 200, + 300, + 600, + 1200, + 1800, + 2400, + 3600, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400 +}; + + +//========================================================================== +// Return baudrate devisor for certain baudrate +//========================================================================== +unsigned short lpc24xx_baud_generator(pc_serial_info *ser_chan, + cyg_serial_baud_rate_t baud) +{ + cyg_uint8 pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART0; + switch (ser_chan->base) + { + case CYGARC_HAL_LPC24XX_REG_UART0_BASE: + pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART0; + break; + + case CYGARC_HAL_LPC24XX_REG_UART1_BASE: + pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART1; + break; + + case CYGARC_HAL_LPC24XX_REG_UART2_BASE: + pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART2; + break; + + case CYGARC_HAL_LPC24XX_REG_UART3_BASE: + pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART3; + break; + + default: + CYG_FAIL("Invalid UART base address"); + } // (ser_chan->base) + + return CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(pclk_id, select_baud[baud]); +} + + +#define CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(_ser_chan_, _baud_) \ + lpc24xx_baud_generator((_ser_chan_), (_baud_)) + + + +//========================================================================== +// SERIAL CHANNEL 0 +//========================================================================== +#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL0 +static pc_serial_info lpc24xx_serial_info0 = +{ + CYGARC_HAL_LPC24XX_REG_UART0_BASE, + CYGNUM_HAL_INTERRUPT_UART0, + CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_INTPRIO +}; + +#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BUFSIZE > 0 +static unsigned char +lpc24xx_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BUFSIZE]; +static unsigned char +lpc24xx_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel0, + pc_serial_funs, + lpc24xx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &lpc24xx_serial_out_buf0[0], + sizeof(lpc24xx_serial_out_buf0), + &lpc24xx_serial_in_buf0[0], + sizeof(lpc24xx_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(lpc24xx_serial_channel0, + pc_serial_funs, + lpc24xx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(lpc24xx_serial_io0, + CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL0_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &lpc24xx_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL0 + + +//========================================================================== +// SERIAL CHANNEL 1 +//========================================================================== +#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL1 +static pc_serial_info lpc24xx_serial_info1 = +{ + CYGARC_HAL_LPC24XX_REG_UART1_BASE, + CYGNUM_HAL_INTERRUPT_UART1, + CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_INTPRIO +}; + +#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BUFSIZE > 0 +static unsigned char +lpc24xx_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BUFSIZE]; +static unsigned char +lpc24xx_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel1, + pc_serial_funs, + lpc24xx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &lpc24xx_serial_out_buf1[0], + sizeof(lpc24xx_serial_out_buf1), + &lpc24xx_serial_in_buf1[0], + sizeof(lpc24xx_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(lpc24xx_serial_channel1, + pc_serial_funs, + lpc24xx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(lpc24xx_serial_io1, + CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL1_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &lpc24xx_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL1 + + +//========================================================================== +// SERIAL CHANNEL 2 +//========================================================================== +#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL2 +static pc_serial_info lpc24xx_serial_info2 = +{ + CYGARC_HAL_LPC24XX_REG_UART2_BASE, + CYGNUM_HAL_INTERRUPT_UART2, + CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_INTPRIO +}; + +#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BUFSIZE > 0 +static unsigned char +lpc24xx_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BUFSIZE]; +static unsigned char +lpc24xx_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel2, + pc_serial_funs, + lpc24xx_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &lpc24xx_serial_out_buf2[0], + sizeof(lpc24xx_serial_out_buf2), + &lpc24xx_serial_in_buf2[0], + sizeof(lpc24xx_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(lpc24xx_serial_channel2, + pc_serial_funs, + lpc24xx_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(lpc24xx_serial_io2, + CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL2_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &lpc24xx_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL2 + + +//========================================================================== +// SERIAL CHANNEL 3 +//========================================================================== +#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL3 +static pc_serial_info lpc24xx_serial_info3 = +{ + CYGARC_HAL_LPC24XX_REG_UART3_BASE, + CYGNUM_HAL_INTERRUPT_UART3, + CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_INTPRIO +}; + +#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BUFSIZE > 0 +static unsigned char +lpc24xx_serial_out_buf3[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BUFSIZE]; +static unsigned char +lpc24xx_serial_in_buf3[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel3, + pc_serial_funs, + lpc24xx_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &lpc24xx_serial_out_buf3[0], + sizeof(lpc24xx_serial_out_buf3), + &lpc24xx_serial_in_buf3[0], + sizeof(lpc24xx_serial_in_buf3) + ); +#else +static SERIAL_CHANNEL(lpc24xx_serial_channel3, + pc_serial_funs, + lpc24xx_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(lpc24xx_serial_io3, + CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL3_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &lpc24xx_serial_channel3 + ); +#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL3 + + +//---------------------------------------------------------------------------- +// EOF arm_lpc2xxx_ser.inl diff --git a/ecos/packages/devs/serial/arm/lpc2xxx/current/ChangeLog b/ecos/packages/devs/serial/arm/lpc2xxx/current/ChangeLog new file mode 100644 index 0000000..6406ae3 --- /dev/null +++ b/ecos/packages/devs/serial/arm/lpc2xxx/current/ChangeLog @@ -0,0 +1,46 @@ +2008-11-23 Martin Laabs <martin.laabs@mailbox.tu-dresden.de> + Andrew Lunn <andrew@lunn.ch> + + * cdl/ser_arm_lpc2xxx.cdl: + * include/arm_lpc2xxx_ser.inl: Ensure the serial interrupts are + using different priorities, otherwise we get spurious interrupts. + +2007-06-22 Alexander Aganichev <aaganichev@gmail.com> + + * cdl/ser_arm_lpc2xxx.cdl: + Added requirement of + CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME option. + +2004-11-15 Jani Monoses <jani@iv.ro> + + * include/arm_lpc2xxx_ser.inl: + Get rid of unused external function declaration. + +2004-09-12 Jani Monoses <jani@iv.ro> + + * include/arm_lpc2xxx_ser.inl: + Serial driver for ARM LPC2XXX, using generic 16X5X driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/lpc2xxx/current/cdl/ser_arm_lpc2xxx.cdl b/ecos/packages/devs/serial/arm/lpc2xxx/current/cdl/ser_arm_lpc2xxx.cdl new file mode 100644 index 0000000..8afb6b8 --- /dev/null +++ b/ecos/packages/devs/serial/arm/lpc2xxx/current/cdl/ser_arm_lpc2xxx.cdl @@ -0,0 +1,226 @@ +# ==================================================================== +# +# ser_arm_lpc2xxx.cdl +# +# eCos serial ARM/LPC2XXX configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-07 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_ARM_LPC2XXX { + display "ARM LPC2XXX serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_LPC2XXX + implements CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + ARM LPC2XXX." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4" + } + + requires { CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME == "1" } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_lpc2xxx_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_lpc2xxx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL0 { + display "ARM LPC2XXX serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the ARM + LPC2XXX port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL0_NAME { + display "Device name for ARM LPC2XXX serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the ARM LPC2XXX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BAUD { + display "Baud rate for the ARM LPC2XXX serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the ARM LPC2XXX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BUFSIZE { + display "Buffer size for the ARM LPC2XXX serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the ARM LPC2XXX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_INTPRIO { + display "Interrupt priority of the serial port 0 ISR" + flavor data + legal_values 0 to 15 + default_value 14 + requires { is_active(CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_INTPRIO) + implies CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_INTPRIO != + CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_INTPRIO + } + description " + This option specifies the interrupt priority of the + ISR of the serial port 0 interrupt in the VIC. + Slot 0 has the highest priority and slot 15 the lowest." + } + + + } + + cdl_component CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL1 { + display "ARM LPC2XXX serial port 1 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the ARM + LPC2XXX port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL1_NAME { + display "Device name for ARM LPC2XXX serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device + for the ARM LPC2XXX port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BAUD { + display "Baud rate for the ARM LPC2XXX serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the ARM LPC2XXX port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BUFSIZE { + display "Buffer size for the ARM LPC2XXX serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal + buffers used for the ARM LPC2XXX port 1." + } + + + cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_INTPRIO { + display "Interrupt priority of the serial port 1 ISR" + flavor data + legal_values 0 to 15 + default_value 15 + description " + This option specifies the interrupt priority of the + ISR of the serial port 1 interrupt in the VIC. + Slot 0 has the highest priority and slot 15 the lowest." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_LPC2XXX_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armlpc2xxx\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_lpc2xxx.cdl diff --git a/ecos/packages/devs/serial/arm/lpc2xxx/current/include/arm_lpc2xxx_ser.inl b/ecos/packages/devs/serial/arm/lpc2xxx/current/include/arm_lpc2xxx_ser.inl new file mode 100644 index 0000000..89efb49 --- /dev/null +++ b/ecos/packages/devs/serial/arm/lpc2xxx/current/include/arm_lpc2xxx_ser.inl @@ -0,0 +1,185 @@ +//========================================================================== +// +// io/serial/arm/arm_lpc2xxx_ser.inl +// +// ARM LPC2XXX Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jani +// Contributors: gthomas, jlarmour +// Date: 1999-02-04 +// Purpose: LPC2XXX Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned int select_baud[] = { + 9999, // Unused + 50, + 75, + 110, + 134.5, + 150, + 200, + 300, + 600, + 1200, + 1800, + 2400, + 3600, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400 +}; + +// we need dynamically generated divider values because they depend on the +// value of pclk which in turn is changeable + +#define CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR \ + CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR + +#ifdef CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL0 +static pc_serial_info lpc2xxx_serial_info0 = + { CYGARC_HAL_LPC2XXX_REG_UART0_BASE, + CYGNUM_HAL_INTERRUPT_UART0, + CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_INTPRIO + }; + +#if CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BUFSIZE > 0 +static unsigned char +lpc2xxx_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BUFSIZE]; +static unsigned char +lpc2xxx_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(lpc2xxx_serial_channel0, + pc_serial_funs, + lpc2xxx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &lpc2xxx_serial_out_buf0[0], + sizeof(lpc2xxx_serial_out_buf0), + &lpc2xxx_serial_in_buf0[0], + sizeof(lpc2xxx_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(lpc2xxx_serial_channel0, + pc_serial_funs, + lpc2xxx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(lpc2xxx_serial_io0, + CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL0_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &lpc2xxx_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL1 +static pc_serial_info lpc2xxx_serial_info1 = + { CYGARC_HAL_LPC2XXX_REG_UART1_BASE, + CYGNUM_HAL_INTERRUPT_UART1, + CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_INTPRIO + }; +#if CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BUFSIZE > 0 +static unsigned char +lpc2xxx_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BUFSIZE]; +static unsigned char +lpc2xxx_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(lpc2xxx_serial_channel1, + pc_serial_funs, + lpc2xxx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &lpc2xxx_serial_out_buf1[0], + sizeof(lpc2xxx_serial_out_buf1), + &lpc2xxx_serial_in_buf1[0], + sizeof(lpc2xxx_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(lpc2xxx_serial_channel1, + pc_serial_funs, + lpc2xxx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(lpc2xxx_serial_io1, + CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL1_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &lpc2xxx_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL1 + +// EOF arm_lpc2xxx_ser.inl diff --git a/ecos/packages/devs/serial/arm/pid/current/ChangeLog b/ecos/packages/devs/serial/arm/pid/current/ChangeLog new file mode 100644 index 0000000..c3fae52 --- /dev/null +++ b/ecos/packages/devs/serial/arm/pid/current/ChangeLog @@ -0,0 +1,213 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_pid.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_pid.cdl: + Fix 234000->230400 typo. + +2000-09-18 Jesper Skov <jskov@redhat.com> + + * src/pid_serial.h: [removed] + * src/pid_serial_with_ints.c: [removed] Moved driver to generic + 16x5x package. + * include/arm_arm7_pid_ser.inl: [added] Make use of generic + driver. + * cdl/ser_arm_pid.cdl: Matching changes. + + * ChangeLog: Cleaned out non-pid entries. + +2000-08-24 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/pid_serial_with_ints.c (pid_serial_DSR): Remove accidental + OVERRUNERR check duplication + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/pid_serial_with_ints.c: Throughout, add support for line status + and modem status callbacks, hardware RTS/CTS and DSR/DTR flow control + (pid_serial_set_config): Now use keys to make + more flexible. + + * src/pid_serial.h: Add more line status, interrupt status and modem + status register definitions + + * cdl/ser_arm_pid.cdl: Implements flow control and line status + interfaces + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-06-09 Jesper Skov <jskov@redhat.com> + + * src/pid_serial_with_ints.c: + * src/pid_serial.h: + Cleaned up defines and made DSR handle all received characters. + (Dave Airlie (airlied at parthus dot com)) + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_arm_pid.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/arm/pid_serial.h: Added BE support. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv + interrupts properly (can't ignore them even with TO bit set). + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + Check for receive interrupt before reading. + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + Update CDL to follow naming conventions. + + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change + so that the physical port is not modified unless the provided + configuration is valid. + + * src/arm/pid_serial_with_ints.c: + Add configury for baud rate and buffer size. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo + in comment. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + Update device names to match CDL. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Add 'CYGDBG_IO_INIT' for control + of init messages. + + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/pid/current/cdl/ser_arm_pid.cdl b/ecos/packages/devs/serial/arm/pid/current/cdl/ser_arm_pid.cdl new file mode 100644 index 0000000..b408b60 --- /dev/null +++ b/ecos/packages/devs/serial/arm/pid/current/cdl/ser_arm_pid.cdl @@ -0,0 +1,195 @@ +# ==================================================================== +# +# ser_arm_pid.cdl +# +# eCos serial ARM/PID configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-07 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_PID { + display "ARM PID serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_PID + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + ARM PID." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4" + } + + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_arm7_pid_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_pid.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_PID_SERIAL0 { + display "ARM PID serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the ARM + PID port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_PID_SERIAL0_NAME { + display "Device name for ARM PID serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the ARM PID port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BAUD { + display "Baud rate for the ARM PID serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the ARM PID port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BUFSIZE { + display "Buffer size for the ARM PID serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the ARM PID port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_PID_SERIAL1 { + display "ARM PID serial port 1 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the ARM + PID port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_PID_SERIAL1_NAME { + display "Device name for ARM PID serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device + for the ARM PID port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BAUD { + display "Baud rate for the ARM PID serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the ARM PID port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BUFSIZE { + display "Buffer size for the ARM PID serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal + buffers used for the ARM PID port 1." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_PID_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_PID_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_PID_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armpid\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_arm_pid.cdl diff --git a/ecos/packages/devs/serial/arm/pid/current/include/arm_arm7_pid_ser.inl b/ecos/packages/devs/serial/arm/pid/current/include/arm_arm7_pid_ser.inl new file mode 100644 index 0000000..1880af6 --- /dev/null +++ b/ecos/packages/devs/serial/arm/pid/current/include/arm_arm7_pid_ser.inl @@ -0,0 +1,162 @@ +//========================================================================== +// +// io/serial/arm/arm_arm7_pid_ser.inl +// +// ARM PID Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jlarmour +// Date: 1999-02-04 +// Purpose: PID Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 1047, // 110 + 0, // 134.5 + 768, // 150 + 0, // 200 + 384, // 300 + 192, // 600 + 96, // 1200 + 24, // 1800 + 48, // 2400 + 0, // 3600 + 24, // 4800 + 16, // 7200 + 12, // 9600 + 8, // 14400 + 6, // 19200 + 3, // 38400 + 2, // 57600 + 1, // 115200 + 0, // 230400 +}; + +#ifdef CYGPKG_IO_SERIAL_ARM_PID_SERIAL0 +static pc_serial_info pid_serial_info0 = {0x0D800000, + CYGNUM_HAL_INTERRUPT_SERIALA}; +#if CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BUFSIZE > 0 +static unsigned char pid_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BUFSIZE]; +static unsigned char pid_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pid_serial_channel0, + pc_serial_funs, + pid_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pid_serial_out_buf0[0], sizeof(pid_serial_out_buf0), + &pid_serial_in_buf0[0], sizeof(pid_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(pid_serial_channel0, + pc_serial_funs, + pid_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_PID_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pid_serial_io0, + CYGDAT_IO_SERIAL_ARM_PID_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pid_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_PID_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_PID_SERIAL1 +static pc_serial_info pid_serial_info1 = {0x0D800020, + CYGNUM_HAL_INTERRUPT_SERIALB}; +#if CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BUFSIZE > 0 +static unsigned char pid_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BUFSIZE]; +static unsigned char pid_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pid_serial_channel1, + pc_serial_funs, + pid_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pid_serial_out_buf1[0], sizeof(pid_serial_out_buf1), + &pid_serial_in_buf1[0], sizeof(pid_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(pid_serial_channel1, + pc_serial_funs, + pid_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_PID_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pid_serial_io1, + CYGDAT_IO_SERIAL_ARM_PID_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pid_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_PID_SERIAL1 + +// EOF arm_arm7_pid_ser.inl diff --git a/ecos/packages/devs/serial/arm/pxa2x0/current/ChangeLog b/ecos/packages/devs/serial/arm/pxa2x0/current/ChangeLog new file mode 100644 index 0000000..0f8e620 --- /dev/null +++ b/ecos/packages/devs/serial/arm/pxa2x0/current/ChangeLog @@ -0,0 +1,37 @@ +2006-11-21 Alexander Neundorf <alexander.neundorf@jenoptik.com> + + * generic PXA 2X0 serial IO support, based on the IQ80321 driver + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_iq80321.cdl: Remove irrelevant doc link. + +2002-01-25 Nick Garnett <nickg@redhat.com> + + * include/arm_iq80321_ser.inl: + * cdl/ser_arm_iq80321.cdl: + IQ80321 files created, by copying the IQ80310 versions and editing. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/pxa2x0/current/cdl/ser_arm_xscale_pxa2x0.cdl b/ecos/packages/devs/serial/arm/pxa2x0/current/cdl/ser_arm_xscale_pxa2x0.cdl new file mode 100644 index 0000000..6c044db --- /dev/null +++ b/ecos/packages/devs/serial/arm/pxa2x0/current/cdl/ser_arm_xscale_pxa2x0.cdl @@ -0,0 +1,154 @@ +# ==================================================================== +# +# ser_arm_xscale_pxa2x0.cdl +# +# eCos serial PXA 2X0 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: msalter +# Contributors: Alexander Neundorf +# Date: 21st November 2006 (last modification) +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0 { + display "PXA2X0 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_XSCALE_PXA2X0 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for pxa." + doc redirect/ecos-device-drivers.html + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4" + } + + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_xscale_pxa2x0_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_xscale_pxa2x0.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0 { + display "ARM XSCALE PXA2X0 serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + implements CYGNUM_SERIAL_FLOW_RTSCTS_RX + implements CYGNUM_SERIAL_FLOW_RTSCTS_TX + + + description " + This option includes the serial device driver for the PXA 2X0." + + cdl_option CYGDAT_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_NAME { + display "Device name for PXA 2X0 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the PXA 2X0 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BAUD { + display "Baud rate for the PXA2X0 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 } + default_value 115200 + description " + This option specifies the default baud rate (speed) + for the PXA2X0 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BUFSIZE { + display "Buffer size for the serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for port 0." + } + } + + + cdl_component CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"pxa2x0\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } + +} + +# EOF ser_arm_xscale_pxa2x0.cdl diff --git a/ecos/packages/devs/serial/arm/pxa2x0/current/include/arm_xscale_pxa2x0_ser.inl b/ecos/packages/devs/serial/arm/pxa2x0/current/include/arm_xscale_pxa2x0_ser.inl new file mode 100644 index 0000000..0050c9d --- /dev/null +++ b/ecos/packages/devs/serial/arm/pxa2x0/current/include/arm_xscale_pxa2x0_ser.inl @@ -0,0 +1,122 @@ +//========================================================================== +// +// io/serial/arm/arm_xscale_pxa2x0_ser.inl +// +// Generic PXA 2X0 Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter, Alexander Neundorf +// Date: 21st November 2006 +// Purpose: PXA2X0 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + 0, // 1200 + 0, // 1800 + 0, // 2400 + 0, // 3600 + 0, // 4800 + 0, // 7200 + 0, // 9600 + 64, // 14400 + 48, // 19200 + 24, // 38400 + 16, // 57600 + 8, // 115200 +}; + +#ifdef CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0 +static pc_serial_info pxa2x0_serial_info0 = {PXA2X0_FFUART_BASE, + CYGNUM_HAL_INTERRUPT_FFUART}; +#if CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BUFSIZE > 0 +static unsigned char pxa2x0_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BUFSIZE]; +static unsigned char pxa2x0_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pxa2x0_serial_channel0, + pc_serial_funs, + pxa2x0_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pxa2x0_serial_out_buf0[0], sizeof(pxa2x0_serial_out_buf0), + &pxa2x0_serial_in_buf0[0], sizeof(pxa2x0_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(pxa2x0_serial_channel0, + pc_serial_funs, + pxa2x0_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pxa2x0_serial_io0, + CYGDAT_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pxa2x0_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0_SERIAL0 + + +// EOF arm_xscale_pxa2x0_ser.inl diff --git a/ecos/packages/devs/serial/arm/s3c4510/current/ChangeLog b/ecos/packages/devs/serial/arm/s3c4510/current/ChangeLog new file mode 100755 index 0000000..c886cef --- /dev/null +++ b/ecos/packages/devs/serial/arm/s3c4510/current/ChangeLog @@ -0,0 +1,38 @@ +2004-02-11 Roland Caßebohm <roland.cassebohm@visionsystem.de> + + * src/s3c4510_serial.c: The UART doesn't generate an interrupt + before the first time a character was send. Changed + s3c4510_serial_start_xmit() to first try to send characters. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_s3c4510.cdl: Remove irrelevant doc link. + +2001-10-19 Lars Lindqvist <Lars.Lindqvist@combitechsystems.com> +2001-10-19 Jonathan Larmour <jlarmour@redhat.com> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/s3c4510/current/cdl/ser_arm_s3c4510.cdl b/ecos/packages/devs/serial/arm/s3c4510/current/cdl/ser_arm_s3c4510.cdl new file mode 100755 index 0000000..8795163 --- /dev/null +++ b/ecos/packages/devs/serial/arm/s3c4510/current/cdl/ser_arm_s3c4510.cdl @@ -0,0 +1,112 @@ +# ==================================================================== +# +# ser_arm_s3c4510.cdl +# +# eCos serial ARM/S3C4510 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Lars.Lindqvist@combitechsystems.com +# Contributors: jlarmour +# Date: 2001-10-19 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_S3C4510 { + display "ARM S3C4510 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + + active_if CYGINT_IO_SERIAL_ARM_S3C4510_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This package contains serial device drivers for the + ARM S3C4510." + + compile -library=libextras.a s3c4510_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_s3c4510.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_ARM_S3C4510_CFG"; + } + + cdl_component CYGPKG_IO_SERIAL_ARM_S3C4510_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_S3C4510_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_S3C4510_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + +} + +# EOF ser_arm_s3c4510.cdl diff --git a/ecos/packages/devs/serial/arm/s3c4510/current/src/s3c4510_serial.c b/ecos/packages/devs/serial/arm/s3c4510/current/src/s3c4510_serial.c new file mode 100755 index 0000000..5ef4cc0 --- /dev/null +++ b/ecos/packages/devs/serial/arm/s3c4510/current/src/s3c4510_serial.c @@ -0,0 +1,296 @@ +//========================================================================== +// +// io/serial/arm/s3c4510_serial.c +// +// ARM S3C4510 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Lars.Lindqvist@combitechsystems.com +// Contributors: jlarmour +// Date: 2001-10-19 +// Purpose: ARM S3C4510 Serial I/O Interface Module (interrupt driven) +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/io/serialio.h> +#include <cyg/infra/diag.h> + +#if defined(CYGPKG_IO_SERIAL_ARM_S3C4510) && defined(CYGDAT_IO_SERIAL_ARM_S3C4510_INL) + +typedef struct s3c4510_serial_info { + CYG_ADDRWORD base; + CYG_WORD tx_int_num; + CYG_WORD rx_int_num; + cyg_interrupt serial_tx_interrupt; + cyg_interrupt serial_rx_interrupt; + cyg_handle_t serial_tx_interrupt_handle; + cyg_handle_t serial_rx_interrupt_handle; + bool tx_enabled; +} s3c4510_serial_info; + +static bool s3c4510_serial_init(struct cyg_devtab_entry *tab); +static bool s3c4510_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo s3c4510_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char s3c4510_serial_getc(serial_channel *chan); +static Cyg_ErrNo s3c4510_serial_set_config(serial_channel *chan, + cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void s3c4510_serial_start_xmit(serial_channel *chan); +static void s3c4510_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 s3c4510_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void s3c4510_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 s3c4510_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void s3c4510_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(s3c4510_serial_funs, + s3c4510_serial_putc, + s3c4510_serial_getc, + s3c4510_serial_set_config, + s3c4510_serial_start_xmit, + s3c4510_serial_stop_xmit + ); + +#include CYGDAT_IO_SERIAL_ARM_S3C4510_INL + +#include "s3c4510_serial.h" + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +s3c4510_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)s3c4510_chan->base; + cyg_uint32 word_length = select_word_length[(new_config->word_length)-CYGNUM_SERIAL_WORD_LENGTH_5]; + cyg_uint32 stop_bits = select_stop_bits[(new_config->stop)-CYGNUM_SERIAL_STOP_1]; + cyg_uint32 parity_mode = select_parity[(new_config->parity)-CYGNUM_SERIAL_PARITY_NONE]; + cyg_uint32 baud_divisor = select_baud[(new_config->baud)-CYGNUM_SERIAL_BAUD_50]; + cyg_uint32 res = word_length | stop_bits | parity_mode | ULCON_SCI | ULCON_IROFF; + if ((word_length|stop_bits|parity_mode|baud_divisor) == U_NOT_SUPP) { + return false; + }; + port->REG_ULCON = res; + port->REG_UCON = UCON_RXMINT | UCON_RXSIOFF | UCON_TXMINT | UCON_DSROFF | UCON_SBKOFF | UCON_LPBOFF; + port->REG_UBRDIV = baud_divisor; + if (new_config != &chan->config) { + chan->config = *new_config; + }; + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +s3c4510_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("S3C4510 SERIAL init - dev: %x.%d.%d\n", s3c4510_chan->base, s3c4510_chan->tx_int_num, s3c4510_chan->rx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { // If bufferlength > 0 then interrupts are used for tx + cyg_drv_interrupt_create(s3c4510_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + s3c4510_serial_tx_ISR, + s3c4510_serial_tx_DSR, + &s3c4510_chan->serial_tx_interrupt_handle, + &s3c4510_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(s3c4510_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_mask(s3c4510_chan->tx_int_num); + s3c4510_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { // If bufferlength > 0 then interrupts are used for rx + cyg_drv_interrupt_create(s3c4510_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + s3c4510_serial_rx_ISR, + s3c4510_serial_rx_DSR, + &s3c4510_chan->serial_rx_interrupt_handle, + &s3c4510_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(s3c4510_chan->serial_rx_interrupt_handle); + cyg_drv_interrupt_unmask(s3c4510_chan->rx_int_num); + } + s3c4510_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +s3c4510_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +s3c4510_serial_putc(serial_channel *chan, unsigned char c) +{ + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)s3c4510_chan->base; + + if (port->REG_USTAT & USTAT_TBE) { + // Transmit buffer is empty + port->REG_UTXBUF = c; + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +s3c4510_serial_getc(serial_channel *chan) +{ + unsigned char c; + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)s3c4510_chan->base; + while ((port->REG_USTAT & USTAT_RDR) == 0) ; // Wait for char + c = port->REG_URXBUF; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +s3c4510_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != s3c4510_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +s3c4510_serial_start_xmit(serial_channel *chan) +{ + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + s3c4510_chan->tx_enabled = true; + (chan->callbacks->xmt_char)(chan); + if (s3c4510_chan->tx_enabled) { + cyg_drv_interrupt_unmask(s3c4510_chan->tx_int_num); + } +} + +// Disable the transmitter on the device +static void +s3c4510_serial_stop_xmit(serial_channel *chan) +{ + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(s3c4510_chan->tx_int_num); + s3c4510_chan->tx_enabled = false; +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +s3c4510_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(s3c4510_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(s3c4510_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +s3c4510_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (s3c4510_chan->tx_enabled) { + cyg_drv_interrupt_unmask(s3c4510_chan->tx_int_num); + } +} + +// Serial I/O - low level rx interrupt handler (ISR) +static cyg_uint32 +s3c4510_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(s3c4510_chan->rx_int_num); + cyg_drv_interrupt_acknowledge(s3c4510_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +s3c4510_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + s3c4510_serial_info *s3c4510_chan = (s3c4510_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)s3c4510_chan->base; + (chan->callbacks->rcv_char)(chan, port->REG_URXBUF); + cyg_drv_interrupt_unmask(s3c4510_chan->rx_int_num); +} + +#endif // CYGPKG_IO_SERIAL_ARM_S3C4510 && CYGDAT_IO_SERIAL_ARM_S3C4510_INL + +// EOF s3c4510_serial.c diff --git a/ecos/packages/devs/serial/arm/s3c4510/current/src/s3c4510_serial.h b/ecos/packages/devs/serial/arm/s3c4510/current/src/s3c4510_serial.h new file mode 100755 index 0000000..66e837f --- /dev/null +++ b/ecos/packages/devs/serial/arm/s3c4510/current/src/s3c4510_serial.h @@ -0,0 +1,195 @@ +#ifndef CYGONCE_ARM_S3C4510_SERIAL_H +#define CYGONCE_ARM_S3C4510_SERIAL_H +// ==================================================================== +// +// s3c4510_serial.h +// +// Device I/O - Description of ARM S3C4510 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Lars.Lindqvist@combitechsystems.com +// Contributors: jlarmour +// Date: 2001-10-19 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/hal.h> // Value CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED needed +#include <cyg/infra/cyg_type.h> // base types + +// Description of serial ports on ARM S3C4510 + +struct serial_port { + cyg_uint32 _reg[8]; +}; + +#define REG(n) _reg[n] + +// Misc values +#define U_NOT_SUPP (0xFFFFFFFF) // Used to indicate unsupported parameter values + +// Registers +#define REG_ULCON REG(0) // Line control registers +#define REG_UCON REG(1) // Control registers +#define REG_USTAT REG(2) // Status registers +#define REG_UTXBUF REG(3) // Transmit buffer registers +#define REG_URXBUF REG(4) // Receive buffer registers +#define REG_UBRDIV REG(5) // Baud rate divisor registers + +// Line Control Register Values +#define ULCON_WL5 (0x00000000 << 0) // Word length 5 +#define ULCON_WL6 (0x00000001 << 0) // Word length 6 +#define ULCON_WL7 (0x00000002 << 0) // Word length 7 +#define ULCON_WL8 (0x00000003 << 0) // Word length 8 +#define ULCON_STB1 (0x00000000 << 2) // One stop bit +#define ULCON_STB2 (0x00000001 << 2) // Two stop bits +#define ULCON_PMDOFF (0x00000000 << 3) // No parity +#define ULCON_PMDODD (0x00000004 << 3) // Odd parity +#define ULCON_PMDEVEN (0x00000005 << 3) // Even parity +#define ULCON_PMDFC1 (0x00000006 << 3) // Parity forced/checked as 1 +#define ULCON_PMDFC0 (0x00000007 << 3) // Parity forced/checked as 0 +#define ULCON_SCI (0x00000000 << 6) // Internal clock +#define ULCON_SCE (0x00000001 << 6) // External clock +#define ULCON_IROFF (0x00000000 << 7) // Normal mode +#define ULCON_IRON (0x00000001 << 7) // IR mode + +// Control Register Values +#define UCON_RXMOFF (0x00000000 << 0) // Disable Rx mode +#define UCON_RXMINT (0x00000001 << 0) // Interrupt request Rx mode +#define UCON_RXMDMA0 (0x00000002 << 0) // GDMA channel 0 request Rx mode +#define UCON_RXMDMA1 (0x00000003 << 0) // GDMA channel 1 request Rx mode +#define UCON_RXSIOFF (0x00000000 << 2) // Rx status interrupt disabled +#define UCON_RXSION (0x00000001 << 2) // Rx status interrupt enabled +#define UCON_TXMOFF (0x00000000 << 3) // Disable Tx mode +#define UCON_TXMINT (0x00000001 << 3) // Interrupt request Tx mode +#define UCON_TXMDMA0 (0x00000002 << 3) // GDMA channel 0 request Tx mode +#define UCON_TXMDMA1 (0x00000003 << 3) // GDMA channel 1 request Tx mode +#define UCON_DSROFF (0x00000000 << 5) // Data set ready output off +#define UCON_DSRON (0x00000001 << 5) // Data set ready output on +#define UCON_SBKOFF (0x00000000 << 6) // No break sent +#define UCON_SBKON (0x00000001 << 6) // Break sent +#define UCON_LPBOFF (0x00000000 << 7) // Loop back mode off// Baud rate divisor registers +#define UCON_LPBON (0x00000001 << 7) // Loop back mode on^M + +// Status Register Values +#define USTAT_OV (0x00000001 << 0) // Overrun error +#define USTAT_PE (0x00000001 << 1) // Parity error +#define USTAT_FE (0x00000001 << 2) // Frame error + +#define USTAT_BKD (0x00000001 << 3) // Break detect +#define USTAT_DTR (0x00000001 << 4) // Data terminal ready +#define USTAT_RDR (0x00000001 << 5) // Receive data ready +#define USTAT_TBE (0x00000001 << 6) // Transmit buffer register empty +#define USTAT_TC (0x00000001 << 7) // Transmit complete + +// Baud rate divisor registers +#define UBRDIV_50 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/50)-1)<<4)|1) +#define UBRDIV_75 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/75)-1)<<4)|1) +#define UBRDIV_110 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/110)-1)<<4)|1) +#define UBRDIV_134_5 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/8/269)-1)<<4)|1) +#define UBRDIV_150 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/150)-1)<<4)|1) +#define UBRDIV_200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/200)-1)<<4)|1) +#define UBRDIV_300 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/300)-1)<<4)|1) +#define UBRDIV_600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/600)-1)<<4)|0) +#define UBRDIV_1200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/1200)-1)<<4)|0) +#define UBRDIV_1800 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/1800)-1)<<4)|0) +#define UBRDIV_2400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/2400)-1)<<4)|0) +#define UBRDIV_3600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/3600)-1)<<4)|0) +#define UBRDIV_4800 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/4800)-1)<<4)|0) +#define UBRDIV_7200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/7200)-1)<<4)|0) +#define UBRDIV_9600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/9600)-1)<<4)|0) +#define UBRDIV_14400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/14400)-1)<<4)|0) +#define UBRDIV_19200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/19200)-1)<<4)|0) +#define UBRDIV_38400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/38400)-1)<<4)|0) +#define UBRDIV_57600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/57600)-1)<<4)|0) +#define UBRDIV_115200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/115200)-1)<<4)|0) +#define UBRDIV_230400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/230400)-1)<<4)|0) + +// Arrays used for conversion of eCos serial driver +// configuration parameters to parameters for S3C4510 + +static cyg_uint32 select_word_length[] = { + ULCON_WL5, // 5 bits / word (char) + ULCON_WL6, + ULCON_WL7, + ULCON_WL8 +}; + +static cyg_uint32 select_stop_bits[] = { + ULCON_STB1, // 1 stop bit + U_NOT_SUPP, // 1.5 stop bit not supported + ULCON_STB2 // 2 stop bits +}; + +static cyg_uint32 select_parity[] = { + ULCON_PMDOFF, // No parity + ULCON_PMDEVEN, // Even parity + ULCON_PMDODD, // Odd parity + ULCON_PMDFC1, // Mark parity + ULCON_PMDFC0, // Space parity +}; + +static cyg_uint32 select_baud[] = { + UBRDIV_50, // 50 + UBRDIV_75, // 75 + UBRDIV_110, // 110 + UBRDIV_134_5, // 134.5 + UBRDIV_150, // 150 + UBRDIV_200, // 200 + UBRDIV_300, // 300 + UBRDIV_600, // 600 + UBRDIV_1200, // 1200 + UBRDIV_1800, // 1800 + UBRDIV_2400, // 2400 + UBRDIV_3600, // 3600 + UBRDIV_4800, // 4800 + UBRDIV_7200, // 7200 + UBRDIV_9600, // 9600 + UBRDIV_14400, // 14400 + UBRDIV_19200, // 19200 + UBRDIV_38400, // 38400 + UBRDIV_57600, // 57600 + UBRDIV_115200, // 115200 + UBRDIV_230400, // 230400 +}; + +#endif // CYGONCE_ARM_S3C4510_SERIAL_H + +// EOF s3c4510_serial.h diff --git a/ecos/packages/devs/serial/arm/sa11x0/current/ChangeLog b/ecos/packages/devs/serial/arm/sa11x0/current/ChangeLog new file mode 100644 index 0000000..4b13179 --- /dev/null +++ b/ecos/packages/devs/serial/arm/sa11x0/current/ChangeLog @@ -0,0 +1,65 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_arm_sa11x0.cdl: Remove irrelevant doc link. + +2001-10-09 Hugo Tyson <hmt@redhat.com> + + * src/sa11x0_serial.c (sa11x0_serial_DSR): Acknowledge the + interrupts for start or end of a line break, otherwise messing + with the wiring can cause an interrupt loop and hang the target. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_sa11x0.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_arm_sa11x0.cdl: Testing parameters moved here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sa11x0_serial.c (sa11x0_serial_set_config): Now use keys to make + more flexible. + +2000-06-29 Jesper Skov <jskov@redhat.com> + + * src/sa11x0_serial.h: + * src/sa11x0_serial.c: + Registers renamed. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-05-10 Gary Thomas <gthomas@redhat.com> + + * cdl/ser_arm_sa11x0.cdl: + * src/sa11x0_serial.h: + * src/sa11x0_serial.c: New file(s). + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl b/ecos/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl new file mode 100644 index 0000000..979219b --- /dev/null +++ b/ecos/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl @@ -0,0 +1,204 @@ +# ==================================================================== +# +# ser_arm_sa11x0.cdl +# +# eCos serial ARM/SA11x0 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Contributors: +# Date: 2000-05-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_SA11X0 { + display "ARM SA11X0 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_SA11X0 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + StrongARM SA11X0." + + compile -library=libextras.a sa11x0_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_sa11x0.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL0 { + display "ARM SA11X0 serial port 0 driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for the ARM SA11X0 + port 0 (UART 3)." + + cdl_option CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL0_NAME { + display "Device name for ARM SA11X0 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + ARM SA11X0 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BAUD { + display "Baud rate for the ARM SA11X0 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM SA11X0 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE { + display "Buffer size for the ARM SA11X0 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ARM SA11X0 port 0." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1 { + display "ARM SA11X0 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM SA11X0 + port 1 (UART 1)." + + cdl_option CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL1_NAME { + display "Device name for ARM SA11X0 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device for the + ARM SA11X0 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BAUD { + display "Baud rate for the ARM SA11X0 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + ARM SA11X0 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE { + display "Buffer size for the ARM SA11X0 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ARM SA11X0 port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_SA11X0_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_SA11X0_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"assabet\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_sa11x0.cdl diff --git a/ecos/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.c b/ecos/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.c new file mode 100644 index 0000000..51c256a --- /dev/null +++ b/ecos/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.c @@ -0,0 +1,354 @@ +//========================================================================== +// +// io/serial/arm/sa11x0/sa11x0_serial.c +// +// StrongARM SA11x0 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2000-05-08 +// Purpose: StrongARM SA11x0 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <pkgconf/kernel.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_SA11X0 + +#include "sa11x0_serial.h" + +typedef struct sa11x0_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} sa11x0_serial_info; + +static bool sa11x0_serial_init(struct cyg_devtab_entry *tab); +static bool sa11x0_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo sa11x0_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char sa11x0_serial_getc(serial_channel *chan); +static Cyg_ErrNo sa11x0_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void sa11x0_serial_start_xmit(serial_channel *chan); +static void sa11x0_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 sa11x0_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sa11x0_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(sa11x0_serial_funs, + sa11x0_serial_putc, + sa11x0_serial_getc, + sa11x0_serial_set_config, + sa11x0_serial_start_xmit, + sa11x0_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL0 +static sa11x0_serial_info sa11x0_serial_info0 = {(CYG_ADDRWORD)SA11X0_UART3_CONTROL0, + CYGNUM_HAL_INTERRUPT_UART3}; +#if CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE > 0 +static unsigned char sa11x0_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE]; +static unsigned char sa11x0_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sa11x0_serial_channel0, + sa11x0_serial_funs, + sa11x0_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sa11x0_serial_out_buf0[0], sizeof(sa11x0_serial_out_buf0), + &sa11x0_serial_in_buf0[0], sizeof(sa11x0_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(sa11x0_serial_channel0, + sa11x0_serial_funs, + sa11x0_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sa11x0_serial_io0, + CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sa11x0_serial_init, + sa11x0_serial_lookup, // Serial driver may need initializing + &sa11x0_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1 + +#ifdef CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1 +static sa11x0_serial_info sa11x0_serial_info1 = {(CYG_ADDRWORD)SA11X0_UART1_CONTROL0, + CYGNUM_HAL_INTERRUPT_UART1}; +#if CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE > 0 +static unsigned char sa11x0_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE]; +static unsigned char sa11x0_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sa11x0_serial_channel1, + sa11x0_serial_funs, + sa11x0_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sa11x0_serial_out_buf1[0], sizeof(sa11x0_serial_out_buf1), + &sa11x0_serial_in_buf1[0], sizeof(sa11x0_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(sa11x0_serial_channel1, + sa11x0_serial_funs, + sa11x0_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sa11x0_serial_io1, + CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sa11x0_serial_init, + sa11x0_serial_lookup, // Serial driver may need initializing + &sa11x0_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +sa11x0_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base; + unsigned char parity = select_parity[new_config->parity]; + unsigned char word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5]; + unsigned char stop_bits = select_stop_bits[new_config->stop]; + int baud = SA11X0_UART_BAUD_RATE_DIVISOR(select_baud[new_config->baud]); + if ((word_length == 0xFF) || + (parity == 0xFF) || + (stop_bits == 0xFF)) { + return false; // Unsupported configuration + } + // Disable Receiver and Transmitter (clears FIFOs) + port->ctl3 = SA11X0_UART_RX_DISABLED | + SA11X0_UART_TX_DISABLED; + + // Clear sticky (writable) status bits. + port->stat0 = SA11X0_UART_RX_IDLE | + SA11X0_UART_RX_BEGIN_OF_BREAK | + SA11X0_UART_RX_END_OF_BREAK; + + // Set parity, word length, stop bits + port->ctl0 = parity | + word_length | + stop_bits; + + // Set the desired baud rate. + port->ctl1 = (baud >> 8) & SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK; + port->ctl2 = baud & SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK; + + // Enable the receiver (with interrupts) and the transmitter. + port->ctl3 = SA11X0_UART_RX_ENABLED | + SA11X0_UART_TX_ENABLED | + SA11X0_UART_RX_FIFO_INT_ENABLED; + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +sa11x0_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + int res; +#ifdef CYGDBG_IO_INIT + diag_printf("SA11X0 SERIAL init - dev: %x.%d\n", sa11x0_chan->base, sa11x0_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(sa11x0_chan->int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sa11x0_serial_ISR, + sa11x0_serial_DSR, + &sa11x0_chan->serial_interrupt_handle, + &sa11x0_chan->serial_interrupt); + cyg_drv_interrupt_attach(sa11x0_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(sa11x0_chan->int_num); + } + res = sa11x0_serial_config_port(chan, &chan->config, true); + return res; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +sa11x0_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +sa11x0_serial_putc(serial_channel *chan, unsigned char c) +{ + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base; + if (port->stat1 & SA11X0_UART_TX_FIFO_NOT_FULL) { + port->data = c; + return true; + } else { + return false; // Couldn't send, tx was busy + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +sa11x0_serial_getc(serial_channel *chan) +{ + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base; + return port->data; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +sa11x0_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != sa11x0_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +sa11x0_serial_start_xmit(serial_channel *chan) +{ + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base; + (chan->callbacks->xmt_char)(chan); // Kick transmitter (if necessary) + port->ctl3 |= SA11X0_UART_TX_FIFO_INT_ENABLED; +} + +// Disable the transmitter on the device +static void +sa11x0_serial_stop_xmit(serial_channel *chan) +{ + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base; + port->ctl3 &= ~SA11X0_UART_TX_FIFO_INT_ENABLED; +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +sa11x0_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(vector); + cyg_drv_interrupt_acknowledge(vector); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +sa11x0_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base; + unsigned int stat0 = port->stat0; + if (stat0 & SA11X0_UART_TX_SERVICE_REQUEST) { + (chan->callbacks->xmt_char)(chan); + } + if (stat0 & SA11X0_UART_RX_INTS) { + while (port->stat1 & SA11X0_UART_RX_FIFO_NOT_EMPTY) { + (chan->callbacks->rcv_char)(chan, port->data); + } + port->stat0 = SA11X0_UART_RX_IDLE; // Need to clear this manually + } + if (stat0 & (SA11X0_UART_RX_BEGIN_OF_BREAK | + SA11X0_UART_RX_END_OF_BREAK ) ) { + // Need to clear any of these manually also or noise + // from plugging in can cause an interrupt loop! + port->stat0 = stat0 & (SA11X0_UART_RX_BEGIN_OF_BREAK | + SA11X0_UART_RX_END_OF_BREAK ); + } + cyg_drv_interrupt_unmask(vector); +} +#endif diff --git a/ecos/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.h b/ecos/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.h new file mode 100644 index 0000000..33f2d5f --- /dev/null +++ b/ecos/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.h @@ -0,0 +1,122 @@ +#ifndef CYGONCE_ARM_SA11X0_SERIAL_H +#define CYGONCE_ARM_SA11X0_SERIAL_H + +// ==================================================================== +// +// sa11x0_serial.h +// +// Device I/O - Description of StrongARM SA11x0 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2000-05-08 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on StrongARM SA11x0 + +#include <cyg/hal/hal_sa11x0.h> // Register definitions + +struct serial_port { + unsigned long ctl0; // 0x00 + unsigned long ctl1; // 0x04 + unsigned long ctl2; // 0x08 + unsigned long ctl3; // 0x0C + unsigned long _unused0; + unsigned long data; // 0x14 + unsigned long _unused1; + unsigned long stat0; // 0x1C + unsigned long stat1; // 0x20 +}; + +#define SA11X0_UART_RX_INTS (SA11X0_UART_RX_SERVICE_REQUEST|SA11X0_UART_RX_IDLE) + +static unsigned char select_word_length[] = { + 0xFF, // 5 bits / word (char) + 0xFF, + SA11X0_UART_DATA_BITS_7, + SA11X0_UART_DATA_BITS_8 +}; + +static unsigned char select_stop_bits[] = { + 0, + SA11X0_UART_STOP_BITS_1, // 1 stop bit + 0xFF, // 1.5 stop bit + SA11X0_UART_STOP_BITS_2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + SA11X0_UART_PARITY_DISABLED, // No parity + SA11X0_UART_PARITY_ENABLED| // Even parity + SA11X0_UART_PARITY_EVEN, + SA11X0_UART_PARITY_ENABLED| // Odd parity + SA11X0_UART_PARITY_ODD, + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +#endif // CYGONCE_ARM_SA11X0_SERIAL_H diff --git a/ecos/packages/devs/serial/arm/smdk2410/current/ChangeLog b/ecos/packages/devs/serial/arm/smdk2410/current/ChangeLog new file mode 100644 index 0000000..8353195 --- /dev/null +++ b/ecos/packages/devs/serial/arm/smdk2410/current/ChangeLog @@ -0,0 +1,7 @@ +2003-08-06 Michael Anburaj <embeddedeng@hotmail.com> + + * cdl/ser_arm_smdk2410.cdl: + * src/smdk2410_serial.c: + * src/smdk2410_serial.h: + New package to support the serial device on a Samsung + ARM9/SMDK2410 development board. diff --git a/ecos/packages/devs/serial/arm/smdk2410/current/cdl/ser_arm_smdk2410.cdl b/ecos/packages/devs/serial/arm/smdk2410/current/cdl/ser_arm_smdk2410.cdl new file mode 100644 index 0000000..5aea95f --- /dev/null +++ b/ecos/packages/devs/serial/arm/smdk2410/current/cdl/ser_arm_smdk2410.cdl @@ -0,0 +1,198 @@ +# ==================================================================== +# +# ser_arm_smdk2410.cdl +# +# eCos serial ARM/SMDK2410 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): michael anburaj <michaelanburaj@hotmail.com> +# Contributors: michael anburaj <michaelanburaj@hotmail.com> +# Date: 2003-08-01 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_SMDK2410 { + display "Samsung ARM9/SMDK2410 board serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_ARM9_SMDK2410 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + Samsung SMDK2410 and S3c2410x (ARM9) based development boards." + + compile -library=libextras.a smdk2410_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_smdk2410.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL0 { + display "Samsung SMDK2410 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Samsung SMDK2410 port 0." + + cdl_option CYGDAT_IO_SERIAL_ARM_SMDK2410_SERIAL0_NAME { + display "Device name for the Samsung SMDK2410 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of serial device for the Samsung SMDK2410 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BAUD { + display "Baud rate for the Samsung SMDK2410 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the Samsung SMDK2410 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BUFSIZE { + display "Buffer size for the Samsung SMDK2410 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the Samsung SMDK2410 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL1 { + display "Samsung SMDK2410 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Samsung SMDK2410 port 1." + + cdl_option CYGDAT_IO_SERIAL_ARM_SMDK2410_SERIAL1_NAME { + display "Device name for the Samsung SMDK2410 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the Samsung SMDK2410 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BAUD { + display "Baud rate for the Samsung SMDK2410 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the Samsung SMDK2410 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BUFSIZE { + display "Buffer size for the Samsung SMDK2410 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the Samsung SMDK2410 port 1." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_SMDK2410_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_SMDK2410_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_SMDK2410_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_SMDK2410_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL1 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_SMDK2410_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"smdk2410\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_smdk2410.cdl diff --git a/ecos/packages/devs/serial/arm/smdk2410/current/src/smdk2410_serial.c b/ecos/packages/devs/serial/arm/smdk2410/current/src/smdk2410_serial.c new file mode 100644 index 0000000..8880412 --- /dev/null +++ b/ecos/packages/devs/serial/arm/smdk2410/current/src/smdk2410_serial.c @@ -0,0 +1,384 @@ +//========================================================================== +// +// io/serial/arm/smdk2410_serial.c +// +// Samsung SMDK2410 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: SMDK2410 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> // interrupt +#include <cyg/hal/hal_io.h> // register base +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_SMDK2410 + +#include "smdk2410_serial.h" + +typedef struct smdk2410_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_uint32 bit_sub_rxd; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} smdk2410_serial_info; + +static bool smdk2410_serial_init(struct cyg_devtab_entry *tab); +static bool smdk2410_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo smdk2410_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char smdk2410_serial_getc(serial_channel *chan); +static Cyg_ErrNo smdk2410_serial_set_config(serial_channel *chan, + cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void smdk2410_serial_start_xmit(serial_channel *chan); +static void smdk2410_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 smdk2410_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void smdk2410_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(smdk2410_serial_funs, + smdk2410_serial_putc, + smdk2410_serial_getc, + smdk2410_serial_set_config, + smdk2410_serial_start_xmit, + smdk2410_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL0 +static smdk2410_serial_info smdk2410_serial_info0 = {(cyg_uint32)ULCON0, + CYGNUM_HAL_INTERRUPT_UART0, + BIT_SUB_RXD0}; +#if CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BUFSIZE > 0 +static unsigned char smdk2410_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BUFSIZE]; +static unsigned char smdk2410_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(smdk2410_serial_channel0, + smdk2410_serial_funs, + smdk2410_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &smdk2410_serial_out_buf0[0], sizeof(smdk2410_serial_out_buf0), + &smdk2410_serial_in_buf0[0], sizeof(smdk2410_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(smdk2410_serial_channel0, + smdk2410_serial_funs, + smdk2410_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(smdk2410_serial_io0, + CYGDAT_IO_SERIAL_ARM_SMDK2410_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + smdk2410_serial_init, + smdk2410_serial_lookup, // Serial driver may need initializing + &smdk2410_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL1 +static smdk2410_serial_info smdk2410_serial_info1 = {(cyg_uint32)ULCON1, + CYGNUM_HAL_INTERRUPT_UART1, + BIT_SUB_RXD1}; +#if CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BUFSIZE > 0 +static unsigned char smdk2410_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BUFSIZE]; +static unsigned char smdk2410_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(smdk2410_serial_channel1, + smdk2410_serial_funs, + smdk2410_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &smdk2410_serial_out_buf1[0], sizeof(smdk2410_serial_out_buf1), + &smdk2410_serial_in_buf1[0], sizeof(smdk2410_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(smdk2410_serial_channel1, + smdk2410_serial_funs, + smdk2410_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SMDK2410_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(smdk2410_serial_io1, + CYGDAT_IO_SERIAL_ARM_SMDK2410_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + smdk2410_serial_init, + smdk2410_serial_lookup, // Serial driver may need initializing + &smdk2410_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_SMDK2410_SERIAL1 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +smdk2410_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = smdk2410_chan->base; + unsigned short baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr; + + if (baud_divisor == 0) return false; + + if (init) { + //UART FIFO control register + HAL_WRITE_UINT32(base+OFS_UFCON, (3<<6) | (3<<4) | (1<<2) | (1<<1) | (1<<0)); + + //UART modem control register + HAL_WRITE_UINT32(base+OFS_UMCON, 0); + } + + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT32(base+OFS_ULCON, _lcr); + + //UART control register, Enable Rx Timeout Int + HAL_WRITE_UINT32(base+OFS_UCON, 0x085); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +smdk2410_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + cyg_uint32 _intsubm; +#ifdef CYGDBG_IO_INIT + diag_printf("SMDK2410 SERIAL init - dev: 0x%08x.%d\n", + smdk2410_chan->base, smdk2410_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(smdk2410_chan->int_num, + 1, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + smdk2410_serial_ISR, + smdk2410_serial_DSR, + &smdk2410_chan->serial_interrupt_handle, + &smdk2410_chan->serial_interrupt); + cyg_drv_interrupt_attach(smdk2410_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(smdk2410_chan->int_num); + + HAL_READ_UINT32(INTSUBMSK, _intsubm); + _intsubm &= ~(smdk2410_chan->bit_sub_rxd<<0); // BIT_SUB_RXD + HAL_WRITE_UINT32(INTSUBMSK, _intsubm); + } + smdk2410_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +smdk2410_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +smdk2410_serial_putc(serial_channel *chan, unsigned char c) +{ + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = smdk2410_chan->base; + cyg_uint32 _status; + + HAL_READ_UINT32(base+OFS_UFSTAT, _status); + if (_status & 0x200) { + // No space + return false; + } else { + // Transmit buffer is not full + HAL_WRITE_UINT8(base+OFS_UTXH, (cyg_uint32)c); + return true; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +smdk2410_serial_getc(serial_channel *chan) +{ + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = smdk2410_chan->base; + cyg_uint32 _status; + cyg_uint8 _c; + + do { + HAL_READ_UINT32(base+OFS_UFSTAT, _status); + } while ((_status & 0xf) == 0); + + HAL_READ_UINT8(base+OFS_URXH, _c); + return (unsigned char)_c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +smdk2410_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != smdk2410_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +smdk2410_serial_start_xmit(serial_channel *chan) +{ + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + cyg_uint32 _intsubm; + + HAL_READ_UINT32(INTSUBMSK, _intsubm); + _intsubm &= ~(smdk2410_chan->bit_sub_rxd<<1); // BIT_SUB_TXD + HAL_WRITE_UINT32(INTSUBMSK, _intsubm); +} + +// Disable the transmitter on the device +static void +smdk2410_serial_stop_xmit(serial_channel *chan) +{ + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + cyg_uint32 _intsubm; + + HAL_READ_UINT32(INTSUBMSK, _intsubm); + _intsubm |= (smdk2410_chan->bit_sub_rxd<<1); // BIT_SUB_TXD + HAL_WRITE_UINT32(INTSUBMSK, _intsubm); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +smdk2410_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(smdk2410_chan->int_num); + cyg_drv_interrupt_acknowledge(smdk2410_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +smdk2410_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; + CYG_ADDRWORD base = smdk2410_chan->base; + cyg_uint32 _intsubpnd, _status, _c; + cyg_uint32 _rxd_bit = (smdk2410_chan->bit_sub_rxd<<0), _txd_bit=(smdk2410_chan->bit_sub_rxd<<1); + + HAL_READ_UINT32(SUBSRCPND, _intsubpnd); + + // Empty Rx FIFO + if (_intsubpnd & _rxd_bit) { + HAL_READ_UINT32(base+OFS_UFSTAT, _status); + while((_status & 0x0f) != 0) { + HAL_READ_UINT8(base+OFS_URXH, _c); + (chan->callbacks->rcv_char)(chan, (unsigned char)_c); + HAL_READ_UINT32(base+OFS_UFSTAT, _status); + } + HAL_WRITE_UINT32(SUBSRCPND, _rxd_bit); + } + + // Fill into Tx FIFO. xmt_char will mask the interrupt when it + // runs out of chars, so doing this in a loop is OK. + if (_intsubpnd & _txd_bit) { + (chan->callbacks->xmt_char)(chan); + HAL_WRITE_UINT32(SUBSRCPND, _txd_bit); + } + + cyg_drv_interrupt_unmask(smdk2410_chan->int_num); +} + +#endif // CYGPKG_IO_SERIAL_ARM_SMDK2410 + +// EOF smdk2410_serial.c diff --git a/ecos/packages/devs/serial/arm/smdk2410/current/src/smdk2410_serial.h b/ecos/packages/devs/serial/arm/smdk2410/current/src/smdk2410_serial.h new file mode 100644 index 0000000..abeab11 --- /dev/null +++ b/ecos/packages/devs/serial/arm/smdk2410/current/src/smdk2410_serial.h @@ -0,0 +1,127 @@ +#ifndef CYGONCE_ARM_SMDK2410_SERIAL_H +#define CYGONCE_ARM_SMDK2410_SERIAL_H + +// ==================================================================== +// +// smdk2410_serial.h +// +// Device I/O - Description of Samsung SMDK2410 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Baud rate divisor registers values +// (PCLK/16./BAUD_RATE+0.5) -1) +#define UBRDIV_50 ((PCLK/16./50)-1) +#define UBRDIV_75 ((PCLK/16./75)-1) +#define UBRDIV_110 ((PCLK/16./110)-1) +#define UBRDIV_134_5 ((PCLK/16./134.5)-1) +#define UBRDIV_150 ((PCLK/16./150)-1) +#define UBRDIV_200 ((PCLK/16./200)-1) +#define UBRDIV_300 ((PCLK/16./300)-1) +#define UBRDIV_600 ((PCLK/16./600)-1) +#define UBRDIV_1200 ((PCLK/16./1200)-1) +#define UBRDIV_1800 ((PCLK/16./1800)-1) +#define UBRDIV_2400 ((PCLK/16./2400)-1) +#define UBRDIV_3600 ((PCLK/16./3600)-1) +#define UBRDIV_4800 ((PCLK/16./4800)-1) +#define UBRDIV_7200 ((PCLK/16./7200)-1) +#define UBRDIV_9600 ((PCLK/16./9600)-1) +#define UBRDIV_14400 ((PCLK/16./14400)-1) +#define UBRDIV_19200 ((PCLK/16./19200)-1) +#define UBRDIV_38400 ((PCLK/16./38400)-1) +#define UBRDIV_57600 ((PCLK/16./57600)-1) +#define UBRDIV_115200 ((PCLK/16./115200)-1) +#define UBRDIV_230400 ((PCLK/16./230400)-1) + +static unsigned char select_word_length[] = { + VAL_ULCON_WL_5, + VAL_ULCON_WL_6, + VAL_ULCON_WL_7, + VAL_ULCON_WL_8 +}; + +static unsigned char select_stop_bits[] = { + 0, // Unused + VAL_ULCON_SB_1, // 1 stop bit + 0, // 1.5 stop bit (not supported) + VAL_ULCON_SB_2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + VAL_ULCON_PM_N, // No parity + VAL_ULCON_PM_E, // Even parity + VAL_ULCON_PM_O, // Odd parity + VAL_ULCON_PM_FC1, // Mark parity + VAL_ULCON_PM_FC0, // Space parity +}; + +// Baud rate values, based on PCLK +static unsigned short select_baud[] = { + 0, // Unused + UBRDIV_50, // 50 + UBRDIV_75, // 75 + UBRDIV_110, // 110 + UBRDIV_134_5, // 134.5 + UBRDIV_150, // 150 + UBRDIV_200, // 200 + UBRDIV_300, // 300 + UBRDIV_600, // 600 + UBRDIV_1200, // 1200 + UBRDIV_1800, // 1800 + UBRDIV_2400, // 2400 + UBRDIV_3600, // 3600 + UBRDIV_4800, // 4800 + UBRDIV_7200, // 7200 + UBRDIV_9600, // 9600 + UBRDIV_14400, // 14400 + UBRDIV_19200, // 19200 + UBRDIV_38400, // 38400 + UBRDIV_57600, // 57600 + UBRDIV_115200,// 115200 + UBRDIV_230400,// 230400 +}; + +#endif // CYGONCE_ARM_SMDK2410_SERIAL_H diff --git a/ecos/packages/devs/serial/coldfire/mcf5272/current/ChangeLog b/ecos/packages/devs/serial/coldfire/mcf5272/current/ChangeLog new file mode 100644 index 0000000..dcc83f1 --- /dev/null +++ b/ecos/packages/devs/serial/coldfire/mcf5272/current/ChangeLog @@ -0,0 +1,39 @@ +2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch> + + * src/mcf5272_serial.c (MCF5272_uart_init): Fix compiler warning + with diag_printf(). + +2005-06-24 Enrico Piria <epiriaNOSPAM@NOSPAMfastwebnet.it> + + * src/mcf5272_serial.c: + * src/mcf5272_serial.h: + * cdl/mcf5272_serial.cdl: + Rework of the original driver contributed by Wade Jensen. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mcf5272_uart.cdl: Remove irrelevant doc link. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/coldfire/mcf5272/current/cdl/mcf5272_serial.cdl b/ecos/packages/devs/serial/coldfire/mcf5272/current/cdl/mcf5272_serial.cdl new file mode 100644 index 0000000..cfc5a0c --- /dev/null +++ b/ecos/packages/devs/serial/coldfire/mcf5272/current/cdl/mcf5272_serial.cdl @@ -0,0 +1,192 @@ +# ==================================================================== +# +# ser_MCF5272_uart.cdl +# +# eCos serial driver for MCF5272 UART +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_COLDFIRE_MCF5272 { + display "Serial driver for MCF5272 UART" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + requires CYGPKG_ERROR + include_dir cyg/io + description " + This option enables the serial device drivers for the + ColdFire MCF5272." + + compile -library=libextras.a mcf5272_serial.c + + cdl_component CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0 { + display "MCF5272 UART serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description "This option includes the serial device driver + for the MCF5272 UART port 0." + + cdl_option CYGDAT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_NAME { + display "Device name for the MCF5272 UART serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of serial device for the + MCF5272 UART port 0." + } + + cdl_option CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BAUD { + display "Baud rate for the MCF5272 UART serial port 0" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 19200 + description " + This option specifies the default baud rate (speed) for the + MCF5272 UART port 0." + } + + cdl_option CYGOPT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_AUTOBAUD { + display "Enable automatic baud rate detection for the MCF5272 UART serial port 0." + flavor bool + default_value 0 + active_if CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BUFSIZE > 0 + description " + This option enables automatic baud rate detection for + MCF5272 UART port 0. Sending a BREAK character on the + line will start the detection. The first character following + the BREAK should occupy an odd position in the character table + (like \'a\'). This option requires interrupts to be enabled + for the port." + } + + cdl_option CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BUFSIZE { + display "Buffer size for the MCF5272 UART serial port 0" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MCF5272 UART port 0. If the size specified is 0, the + driver will not use interrupts." + } + + cdl_option CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_PRIORITY { + display "Interrupt priority level for MCF5272 UART serial port 0" + flavor data + legal_values 1 to 6 + default_value 2 + active_if CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BUFSIZE > 0 + description " + This option specifies the priority associated to interrupts + coming from the MCF5272 UART port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1 { + display "MCF5272 UART serial port 1 driver" + flavor bool + default_value 0 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description "This option includes the serial device driver for the + MCF5272 UART port 1." + + cdl_option CYGDAT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_NAME { + display "Device name for the MCF5272 UART serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + MCF5272 UART port 1." + } + + cdl_option CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BAUD { + display "Baud rate for the MCF5272 UART serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 19200 + description " + This option specifies the default baud rate (speed) for the + MCF5272 UART port 1." + } + + cdl_option CYGOPT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_AUTOBAUD { + display "Enable automatic baud rate detection for the MCF5272 UART serial port 1." + flavor bool + default_value 0 + active_if CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BUFSIZE > 0 + description " + This option enables automatic baud rate detection for + MCF5272 UART port 1. Sending a BREAK character on the + line will start the detection. The first character following + the BREAK should occupy an odd position in the character table + (like \'a\'). This option requires interrupts to be enabled + for the port." + } + + cdl_option CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BUFSIZE { + display "Buffer size for the MCF5272 UART serial port 1" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MCF5272 UART port 1. If the size specified is 0, the + driver will not use interrupts." + } + + cdl_option CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_PRIORITY { + display "Interrupt priority level for MCF5272 UART serial port 1" + flavor data + legal_values 1 to 6 + default_value 2 + active_if CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BUFSIZE > 0 + description " + This option specifies the priority associated to interrupts + coming from the MCF5272 UART port 1." + } + } +} + diff --git a/ecos/packages/devs/serial/coldfire/mcf5272/current/src/mcf5272_serial.c b/ecos/packages/devs/serial/coldfire/mcf5272/current/src/mcf5272_serial.c new file mode 100644 index 0000000..7e0033b --- /dev/null +++ b/ecos/packages/devs/serial/coldfire/mcf5272/current/src/mcf5272_serial.c @@ -0,0 +1,1138 @@ +//========================================================================== +// +// devs/serial/coldfire/mcf5272/mcf5272_serial.c +// +// ColdFire MCF5272 UART Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Wade Jensen, Enrico Piria +// Contributors: +// Date: 2005-06-25 +// Purpose: MCF5272 Serial I/O module (interrupt driven version). +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <string.h> // memset, strcmp + +#include "mcf5272_serial.h" + + +// Use this macro to determine if at least one of the ports uses +// autobaud detection. +#if defined(CYGOPT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_AUTOBAUD) || \ + defined(CYGOPT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_AUTOBAUD) +#define REQUESTED_AUTOBAUD +#endif + +// Autobaud states +typedef enum autobaud_states_t +{ + AB_IDLE = 0, // Normal state. Autobaud process hasn't been initiated yet. + AB_BEGIN_BREAK, // Detected a start of the break. + AB_BEGIN, // Detected the end of the break and has set up the autobaud. + AB_DISABLED // Autobaud detection disabled for this port. +} autobaud_states_t; + +typedef struct MCF5272_uart_info_t +{ + volatile mcf5272_uart_t *base; // Base address of the UART registers + cyg_uint32 uart_vector; // UART interrupt vector number + + cyg_interrupt serial_interrupt; // Interrupt context + cyg_handle_t serial_interrupt_handle; // Interrupt handle + + volatile cyg_uint8 imr_mirror; // Interrupt mask register mirror + + cyg_serial_info_t config; // The channel configuration + + autobaud_states_t autobaud_state; // The autobaud state + + +} MCF5272_uart_info_t; + +// Function prototypes for the MCF5272 UART ISR and DSR. +static cyg_uint32 MCF5272_uart_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void MCF5272_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +// Function prototypes for the serial functions. +static bool MCF5272_uart_init(struct cyg_devtab_entry * tab); +static Cyg_ErrNo MCF5272_uart_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, const char *name); +static bool MCF5272_uart_putc(serial_channel *chan, unsigned char c); +static unsigned char MCF5272_uart_getc(serial_channel *chan); +Cyg_ErrNo MCF5272_uart_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void MCF5272_uart_start_xmit(serial_channel *chan); +static void MCF5272_uart_stop_xmit(serial_channel * chan); + +// Declare the serial functions that are called by the common serial +// driver layer. +static SERIAL_FUNS +( + MCF5272_uart_funs, + MCF5272_uart_putc, + MCF5272_uart_getc, + MCF5272_uart_set_config, + MCF5272_uart_start_xmit, + MCF5272_uart_stop_xmit +); + + +// Definition for channel 0 UART configuration. +//*********************************************** +#ifdef CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0 + +// Data structure contains channel information. +static MCF5272_uart_info_t MCF5272_uart_channel_info_0; + +// If the channel buffer size is zero, do not include interrupt UART processing +#if CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BUFSIZE > 0 + +// Allocate receive and transmit buffer. The size of the buffer is +// configured by the configtool. +static unsigned char +MCF5272_uart_out_buf0[CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BUFSIZE]; +static unsigned char +MCF5272_uart_in_buf0[CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BUFSIZE]; + +// Channel function table. We register the UART functions here so +// that uppper serial drivers can call the serial driver's routines. +static SERIAL_CHANNEL_USING_INTERRUPTS( + MCF5272_uart_channel_0, + MCF5272_uart_funs, + MCF5272_uart_channel_info_0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + MCF5272_uart_out_buf0, sizeof(MCF5272_uart_out_buf0), + MCF5272_uart_in_buf0, sizeof(MCF5272_uart_in_buf0) +); + +#else + +// Don't use interrupt processing for the UART. +static SERIAL_CHANNEL( + MCF5272_uart_channel_0, + MCF5272_uart_funs, + MCF5272_uart_channel_info_0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT +); +#endif + +DEVTAB_ENTRY( + MCF5272_uart_io0, + CYGDAT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, // The table of I/O functions. + MCF5272_uart_init, // UART initialization function. + MCF5272_uart_lookup, // The UART lookup function. This + // function typically sets + // up the device for actual use, + // turning on interrupts, + // configuring the port, etc. + &MCF5272_uart_channel_0 +); +#endif // ifdef CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0 + + +// Definition for channel 1 UART configuration. +//*********************************************** +#ifdef CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1 + +// Data structure contains channel informtion. +static MCF5272_uart_info_t MCF5272_uart_channel_info_1; + +// If the channel buffer size is zero, do not include interrupt UART processing +#if CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BUFSIZE > 0 + +// Allocate receive and transmit buffer. The size of the buffer is +// configured by the configtool. +static unsigned char +MCF5272_uart_out_buf1[CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BUFSIZE]; +static unsigned char +MCF5272_uart_in_buf1[CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BUFSIZE]; + +// Channel function table. We register the UART functions here so +// that uppper serial drivers can call the serial driver's routines. +static SERIAL_CHANNEL_USING_INTERRUPTS( + MCF5272_uart_channel_1, + MCF5272_uart_funs, + MCF5272_uart_channel_info_1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + MCF5272_uart_out_buf1, sizeof(MCF5272_uart_out_buf1), + MCF5272_uart_in_buf1, sizeof(MCF5272_uart_in_buf1) +); + +#else + +static SERIAL_CHANNEL( + MCF5272_uart_channel_1, + MCF5272_uart_funs, + MCF5272_uart_channel_info_1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT +); +#endif + +DEVTAB_ENTRY( + MCF5272_uart_io1, + CYGDAT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, // The table of I/O functions. + MCF5272_uart_init, // UART initialization function. + MCF5272_uart_lookup, // The UART lookup function. This function + // typically sets up the device for actual use, + // turing on interrupts, configuring the port, etc. + &MCF5272_uart_channel_1 +); +#endif // ifdef CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1 + + +// Function Prototypes + +// Internal function to actually configure the hardware to desired +// baud rate, etc. +static bool MCF5272_uart_config_port(serial_channel*, cyg_serial_info_t*); +static void MCF5272_uart_start_xmit(serial_channel*); + + +// The table contains dividers to divide the clock to configure an +// approppriate baud rate for the UART. + +#define DIVIDER(_baudrate_) \ + ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / ((_baudrate_) * 32)) + +static unsigned long dividers_table[]= +{ + 0, + DIVIDER(50), // CYGNUM_SERIAL_BAUD_50 = 1 + DIVIDER(75), // CYGNUM_SERIAL_BAUD_75 + DIVIDER(110), // CYGNUM_SERIAL_BAUD_110 + DIVIDER(134.5), // CYGNUM_SERIAL_BAUD_134_5 + DIVIDER(150), // CYGNUM_SERIAL_BAUD_150 + DIVIDER(200), // CYGNUM_SERIAL_BAUD_200 + DIVIDER(300), // CYGNUM_SERIAL_BAUD_300 + DIVIDER(600), // CYGNUM_SERIAL_BAUD_600 + DIVIDER(1200), // CYGNUM_SERIAL_BAUD_1200 + DIVIDER(1800), // CYGNUM_SERIAL_BAUD_1800 + DIVIDER(2400), // CYGNUM_SERIAL_BAUD_2400 + DIVIDER(3600), // CYGNUM_SERIAL_BAUD_3600 + DIVIDER(4800), // CYGNUM_SERIAL_BAUD_4800 + DIVIDER(7200), // CYGNUM_SERIAL_BAUD_7200 + DIVIDER(9600), // CYGNUM_SERIAL_BAUD_9600 + DIVIDER(14400), // CYGNUM_SERIAL_BAUD_14400 + DIVIDER(19200), // CYGNUM_SERIAL_BAUD_19200 + DIVIDER(38400), // CYGNUM_SERIAL_BAUD_38400 + DIVIDER(57600), // CYGNUM_SERIAL_BAUD_57600 + DIVIDER(115200), // CYGNUM_SERIAL_BAUD_115200 + DIVIDER(230400) // CYGNUM_SERIAL_BAUD_230400 +}; + + +// **************************************************************************** +// MCF5272_uart_init() - This routine is called during bootstrap to set up the +// UART driver. +// +// INPUT: +// Pointer to the the device table. +// +// RETURN: +// Returns true if the initialization is successful. Otherwise, it retuns +// false. + +static bool MCF5272_uart_init(struct cyg_devtab_entry * tab) +{ + serial_channel *chan = (serial_channel *) tab->priv; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + int priority_level = 0; + + +#ifdef CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0 + + // Instantiation of the UART channel 0 data structure. This data + // structure contains channel information. + if (strcmp(tab->name, CYGDAT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_NAME) + == 0) + { + + cyg_uint32 pbcnt; + + // A priority makes sense only if interrupts are enabled +#ifdef CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_PRIORITY + priority_level = CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_PRIORITY; +#else + priority_level = 0; +#endif + + // Initialize the UART information data to all zeros + memset(port, sizeof(MCF5272_uart_info_t), 0); + + // Set the base address of the UART registers to differentiate + // itself from the different registers for the other UART port. + port->base = (mcf5272_uart_t *) &MCF5272_DEVS->uart[0]; + + // Set the UART interrupt vector number + port->uart_vector = CYGNUM_HAL_INTERRUPT_UART1; + +#ifdef CYGOPT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0_AUTOBAUD + + // Set the autobaud state to idle + port->autobaud_state = AB_IDLE; +#else + // Disable autobaud detection for this port + port->autobaud_state = AB_DISABLED; +#endif + + // Initialize the UART 0 output pins + HAL_READ_UINT32(&MCF5272_DEVS->gpio.pbcnt, pbcnt); + HAL_WRITE_UINT32(&MCF5272_DEVS->gpio.pbcnt, + MCF5272_GPIO_PBCNT_URT0_EN | + (pbcnt & ~MCF5272_GPIO_PBCNT_URT0_MSK)); + } +#endif // CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL0 + +#ifdef CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1 + + // Instantiation of the UART channel 1 data strucutre. This data + // structure contains channel information. + if (strcmp(tab->name, CYGDAT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_NAME) + == 0) + { + cyg_uint32 pdcnt; + + // A priority makes sense only if interrupts are enabled +#ifdef CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_PRIORITY + priority_level = CYGNUM_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_PRIORITY; +#else + priority_level = 0; +#endif + + // Initialize the UART information data to all zeros + memset(port, sizeof(MCF5272_uart_info_t), 0); + + // Set the base address of the UART registers to differentiate + // itself from the different regusters for the other UART port. + port->base = (mcf5272_uart_t *) &MCF5272_DEVS->uart[1]; + + // Set the UART interrupt vector number + port->uart_vector = CYGNUM_HAL_INTERRUPT_UART2; + +#ifdef CYGOPT_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1_AUTOBAUD + + // Set the autobaud state to idle + port->autobaud_state = AB_IDLE; +#else + // Disable autobaud detection for this port + port->autobaud_state = AB_DISABLED; +#endif + + // Initialize the UART 1 output pins + HAL_READ_UINT32(&MCF5272_DEVS->gpio.pdcnt, pdcnt); + HAL_WRITE_UINT32(&MCF5272_DEVS->gpio.pdcnt, + MCF5272_GPIO_PDCNT_URT1_EN | + (pdcnt & ~MCF5272_GPIO_PDCNT_URT1_MSK)); + + } +#endif // CYGPKG_IO_SERIAL_COLDFIRE_MCF5272_CHANNEL1 + + + if (chan->out_cbuf.len > 0) + { + // If the the buffer is greater than zero, then the driver will + // use interrupt driven I/O. Hence, the driver creates an + // interrupt context for the UART device. + + cyg_drv_interrupt_create(port->uart_vector, + priority_level, // Priority + (cyg_addrword_t)chan, // Data item passed + // to interrupt handler + MCF5272_uart_ISR, + MCF5272_uart_DSR, + &port->serial_interrupt_handle, + &port->serial_interrupt); + + cyg_drv_interrupt_attach(port->serial_interrupt_handle); + + cyg_drv_interrupt_unmask(port->uart_vector); + } + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + +#ifdef CYGDBG_IO_INIT + diag_printf("MCF5272 UART init - dev: %p.%d\n", port->base, + port->uart_vector); +#endif + + // Configure Serial device + return (MCF5272_uart_config_port(chan, &chan->config)); +} + + +// *************************************************************************** +// MCF5272_uart_config_port() - Configure the UART port. +// +// Internal function to actually configure the hardware to desired baud rate, +// etc. +// +// INPUT: +// chan - The channel information. +// new_confg - The port configuration which include the desired +// baud rate, etc. +// +// RETURN: +// Returns true if the port configuration is successful. Otherwise, +// it retuns false. + +static bool MCF5272_uart_config_port(serial_channel *chan, + cyg_serial_info_t *new_config) +{ + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + cyg_uint8 mode_reg = 0; + cyg_uint32 ubgs; + + + // If we are configuring the port once again, disable all interrupts + HAL_WRITE_UINT8(&port->base->uisr_uimr, 0); + + // If the baud rate is null, we don't configure the port + if (new_config->baud == 0) return false; + + // Get the divider from the baudrate table which will use to + // configure the port's baud rate. + ubgs = (cyg_uint16) dividers_table[new_config->baud]; + + // Save the configuration value for later use + port->config = *new_config; + + // We first write the reset values into the device and then configure + // the device the way we want to use it. + + // Reset Transmitter + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_RESET_TX); + + // Reset Receiver + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_RESET_RX); + + // Reset Mode Register + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_RESET_MR); + + // Translate the parity configuration to UART mode bits + switch(port->config.parity) + { + default: + case CYGNUM_SERIAL_PARITY_NONE: + mode_reg = 0 | MCF5272_UART_UMR1_PM_NONE; + break; + + case CYGNUM_SERIAL_PARITY_EVEN: + mode_reg = 0 | MCF5272_UART_UMR1_PM_EVEN; + break; + + case CYGNUM_SERIAL_PARITY_ODD: + mode_reg = 0 | MCF5272_UART_UMR1_PM_ODD; + break; + + case CYGNUM_SERIAL_PARITY_MARK: + mode_reg = 0 | MCF5272_UART_UMR1_PM_FORCE_HI; + break; + + case CYGNUM_SERIAL_PARITY_SPACE: + mode_reg = 0 | MCF5272_UART_UMR1_PM_FORCE_LO; + break; + } + + // Translate the number of bits per character configuration to + // UART mode bits + switch(port->config.word_length) + { + case CYGNUM_SERIAL_WORD_LENGTH_5: + mode_reg |= MCF5272_UART_UMR1_BC_5; + break; + + case CYGNUM_SERIAL_WORD_LENGTH_6: + mode_reg |= MCF5272_UART_UMR1_BC_6; + break; + + case CYGNUM_SERIAL_WORD_LENGTH_7: + mode_reg |= MCF5272_UART_UMR1_BC_7; + break; + + default: + case CYGNUM_SERIAL_WORD_LENGTH_8: + mode_reg |= MCF5272_UART_UMR1_BC_8; + break; + } + + // Enable HW flow control for receiver + if(port->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX) + mode_reg |= MCF5272_UART_UMR1_RXRTS; + + // Configure the parity, HW flow control and the bits per character. + // After this write MR pointer points to mode register 2. + HAL_WRITE_UINT8(&port->base->umr, mode_reg); + + // Translate the stop bit length to UART mode bits + switch(port->config.stop) + { + default: + case CYGNUM_SERIAL_STOP_1: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_1; + break; + + case CYGNUM_SERIAL_STOP_1_5: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_15; + break; + + case CYGNUM_SERIAL_STOP_2: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_2; + break; + } + + // Enable HW flow control for transmitter + if(port->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX) + mode_reg |= MCF5272_UART_UMR2_TXCTS; + + // No echo or loopback + mode_reg |= MCF5272_UART_UMR2_CM_NORMAL; + + // Write to mode register 2 + HAL_WRITE_UINT8(&port->base->umr, mode_reg); + + // Set Rx and Tx baud by timer + HAL_WRITE_UINT8(&port->base->usr_ucsr, 0 | MCF5272_UART_UCSR_RCS(0xD) | + MCF5272_UART_UCSR_TCS(0xD)); + + // Mask all UART interrupts + HAL_WRITE_UINT8(&port->base->uisr_uimr, 0); + + // Program the baud settings to the device + HAL_WRITE_UINT8(&port->base->udu, (cyg_uint8)((ubgs & 0xFF00) >> 8)); + HAL_WRITE_UINT8(&port->base->udl, (cyg_uint8)(ubgs & 0x00FF)); + + // Enable receiver and transmitter + HAL_WRITE_UINT8(&port->base->ucr, 0 | MCF5272_UART_UCR_TXRXEN); + + // Enable both transmit and receive interrupt + port->imr_mirror = MCF5272_UART_UIMR_TXRDY | MCF5272_UART_UIMR_FFULL_RXRDY; + + // Enable break interrupt only if autobaud is enabled + if (port->autobaud_state != AB_DISABLED) + port->imr_mirror |= MCF5272_UART_UIMR_DB; + + HAL_WRITE_UINT8(&port->base->uisr_uimr, port->imr_mirror); + + // Return true to indicate a successful configuration + return true; +} + + +// *************************************************************************** +// MCF5272_uart_lookup() - This routine is called when the device is "looked" +// up (i.e. attached) +// +// INPUT: +// tab - pointer to a pointer of the device table. +// sub_tab - Pointer to the sub device table. +// name - name of the device. +// +// RETURN: +// Always return ENOERR. + +static Cyg_ErrNo MCF5272_uart_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + + +// *************************************************************************** +// MCF5272_uart_putc() - Send a character to the device output buffer. +// +// INPUT: +// chan - pointer to the serial private data. +// c - the character to output. +// +// RETURN: +// 'true' if character is sent to device, return 'false' when we've +// ran out of buffer space in the device itself. + +static bool MCF5272_uart_putc(serial_channel *chan, unsigned char c) +{ + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + cyg_uint8 usr_ucsr; + + // Make sure the transmitter is not full. If it is full, return false. + HAL_READ_UINT8(&port->base->usr_ucsr, usr_ucsr); + if (!(usr_ucsr & MCF5272_UART_USR_TXRDY)) + return false; + + // Send the character + HAL_WRITE_UINT8(&port->base->urb_utb, c); + + return true ; +} + + +// *************************************************************************** +// MCF5272_uart_getc() - Fetch a character from the device input buffer and +// return it to the calling routine. Wait until there +// is a character ready. +// +// INPUT: +// chan - pointer to the serial private data. +// +// RETURN: +// the character read from the UART. + +static unsigned char MCF5272_uart_getc(serial_channel *chan) +{ + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + cyg_uint8 usr_ucsr, urb_utb; + + // Wait until character has been received + do + { + HAL_READ_UINT8(&port->base->usr_ucsr, usr_ucsr); + } + while (!(usr_ucsr & MCF5272_UART_USR_RXRDY)) ; + + // Read the character from the FIFO queue + HAL_READ_UINT8(&port->base->urb_utb, urb_utb); + + return urb_utb; +} + + +// *************************************************************************** +// MCF5272_uart_set_config() - Set up the device characteristics; baud rate, +// etc. +// +// INPUT: +// chan - pointer to the serial private data. +// key - configuration key (command). +// xbuf - pointer to the configuration buffer. +// len - the length of the configuration buffer. +// +// RETURN: +// NOERR - If the configuration is successful. +// EINVAL - If the argument is invalid. + +Cyg_ErrNo MCF5272_uart_set_config(serial_channel *chan, + cyg_uint32 key, + const void *xbuf, + cyg_uint32 *len) +{ + cyg_serial_info_t *config = (cyg_serial_info_t *) xbuf; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + + switch (key) + { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + // Set serial configuration + if (*len < sizeof(cyg_serial_info_t)) + return EINVAL; + + *len = sizeof(cyg_serial_info_t); + + if (!MCF5272_uart_config_port(chan, config)) + return EINVAL; + } + break; + + case CYG_IO_GET_CONFIG_SERIAL_INFO: + // Retrieve UART configuration + *config = port->config; + break; + +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + cyg_uint32 *f = (cyg_uint32 *)xbuf; + + if (*len < sizeof(*f)) + return -EINVAL; + + // we should throttle + if (*f) HAL_WRITE_UINT8(&port->base->uop0, MCF5272_UART_UOP0_RTS); + // we should no longer throttle + else HAL_WRITE_UINT8(&port->base->uop1, MCF5272_UART_UOP1_RTS); + } + break; + + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + // We only support RTSCTS (and software) flow control. + // We clear any unsupported flags here and + // then return -ENOSUPP - the higher layer can then query + // what flags are set and decide what to do. + { + unsigned int flags_mask; + cyg_uint8 umr1_mask, umr2_mask; + + // These are the control flow modes we support + flags_mask = (CYGNUM_SERIAL_FLOW_RTSCTS_RX | + CYGNUM_SERIAL_FLOW_RTSCTS_RX); +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_SOFTWARE + flags_mask |= (CYGNUM_SERIAL_FLOW_XONXOFF_RX | + CYGNUM_SERIAL_FLOW_XONXOFF_TX); +#endif + if (chan->config.flags & ~flags_mask) + { + chan->config.flags &= flags_mask; + return -ENOSUPP; + } + + // For security, mask UART interrupt while we change configuration + cyg_drv_interrupt_mask(port->uart_vector); + + // Reset mode register pointer + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_RESET_MR); + + // Read mode register 1 + HAL_READ_UINT8(&port->base->umr, umr1_mask); + + // Read mode register 2 + HAL_READ_UINT8(&port->base->umr, umr2_mask); + + if (chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX) + umr1_mask |= MCF5272_UART_UMR1_RXRTS; + else umr1_mask &= ~MCF5272_UART_UMR1_RXRTS; + + if (chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX) + umr2_mask |= MCF5272_UART_UMR2_TXCTS; + else umr2_mask &= ~MCF5272_UART_UMR2_TXCTS; + + // Reset mode register pointer + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_RESET_MR); + + // Write mode register 1 + HAL_WRITE_UINT8(&port->base->umr, umr1_mask); + + // Write mode register 2 + HAL_WRITE_UINT8(&port->base->umr, umr2_mask); + + // Unmask UART interrupt + cyg_drv_interrupt_unmask(port->uart_vector); + } + break; +#endif // CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + + default: + return EINVAL; + } + + return ENOERR; +} + + +// *************************************************************************** +// MCF5272_uart_start_xmit() - Enable the transmitter on the device. +// +// INPUT: +// chan - pointer to the serial private data. + +static void MCF5272_uart_start_xmit(serial_channel *chan) +{ + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + + + // Mask UART interrupt to prevent race conditions + cyg_drv_interrupt_mask(port->uart_vector); + + // Enable the UART transmitter. + // Eventually, preserve the ongoing autobaud calculation. +#ifdef REQUESTED_AUTOBAUD + if(port->autobaud_state == AB_BEGIN) + HAL_WRITE_UINT8(&port->base->ucr, (MCF5272_UART_UCR_TX_ENABLED | + MCF5272_UART_UCR_ENAB)); + else +#endif + { + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_TX_ENABLED); + } + + // Enable transmitter interrupt + port->imr_mirror |= MCF5272_UART_UIMR_TXRDY; + HAL_WRITE_UINT8(&port->base->uisr_uimr, port->imr_mirror); + + // Unmask UART interrupt + cyg_drv_interrupt_unmask(port->uart_vector); +} + + +// *************************************************************************** +// MCF5272_uart_stop_xmit() - Disable the transmitter on the device +// +// INPUT: +// chan - pointer to the serial private data. + +static void MCF5272_uart_stop_xmit(serial_channel * chan) +{ + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + + + // Mask UART interrupt to prevent race conditions + cyg_drv_interrupt_mask(port->uart_vector); + + // Disable transmitter interrupt + port->imr_mirror &= ~MCF5272_UART_UIMR_TXRDY; + HAL_WRITE_UINT8(&port->base->uisr_uimr, port->imr_mirror); + + // Disable the UART transmitter. + // Eventually, preserve the ongoing autobaud calculation. + // !!!!!!!!!!!!! + // !!!WARNING!!! + // !!!!!!!!!!!!! + // If the transmitter is disabled + // the diag_printf routines will poll forever to transmit the + // a character. Hence, don't ever disable the transmitter if + // you want it to work with diag_printf. +#ifdef REQUESTED_AUTOBAUD + if(port->autobaud_state == AB_BEGIN) + HAL_WRITE_UINT8(&port->base->ucr, (MCF5272_UART_UCR_TX_DISABLED | + MCF5272_UART_UCR_ENAB)); + else +#endif + { + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_TX_DISABLED); + } + + // Unmask UART interrupt + cyg_drv_interrupt_unmask(port->uart_vector); +} + + +// *************************************************************************** +// MCF5272_uart_ISR() - UART I/O interrupt interrupt service routine (ISR). +// +// INPUT: +// vector - the interrupt vector number. +// data - user parameter. +// +// RETURN: +// returns CYG_ISR_CALL_DSR to call the DSR. + +static cyg_uint32 MCF5272_uart_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *) data; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + + + // Write the value in the interrupt status register back + // to the mask register to disable the interrupt temporarily. + HAL_WRITE_UINT8(&port->base->uisr_uimr, 0); + + // Cause DSR to run + return CYG_ISR_CALL_DSR; +} + + +// *************************************************************************** +// MCF5272_uart_DSR() - Defered Service Routine (DSR) - This routine processes +// the interrupt from the device. +// +// INPUT: +// vector - The interrupt vector number. +// count - The nunber of DSR requests. +// data - Device specific information. +// +// The autobaud feature is implemented by means of a simple finite state +// machine which can take the following states: +// AB_DISABLED: autobaud is disabled. +// AB_IDLE: no autobaud calculation is in progress. If autobaud calculation +// has completed, retrieve the new baud rate. +// AB_BEGIN_BREAK: the start of a break character was detected. +// AB_BEGIN: the end of a break character was detected. Start autobaud +// calculation. +// +// The state diagram is the following: +// AB_IDLE --> AB_BEGIN_BREAK --> AB_BEGIN --> Back to AB_IDLE +// The state AB_DISABLED is isolated and means that the autobaud feature is +// not active for that port. + +static void MCF5272_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *) data; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *) chan->dev_priv; + volatile cyg_uint8 isr; + cyg_uint8 uisr_uimr; + + + while (1) + { + // First of all, the exit condition + + // Retrieve the interrupt status bits. We use these status bits to + // figure out what process should we perform: read from the UART or + // inform of a completion of a data transmission. + HAL_READ_UINT8(&port->base->uisr_uimr, uisr_uimr); + isr = uisr_uimr & port->imr_mirror; + + // If there are no more events pending, exit the loop + if (!isr) break; + +#ifdef REQUESTED_AUTOBAUD + switch (port->autobaud_state) + { + case AB_DISABLED: + // Nothing to check for + break; + + case AB_BEGIN_BREAK: + if (isr & MCF5272_UART_UISR_DB) + { + // Detected the end of a break, set the state to + // AB_BEGIN, and setup autobaud detection. + port->autobaud_state = AB_BEGIN; + + // Initialize divider + HAL_WRITE_UINT8(&port->base->udu, 0); + HAL_WRITE_UINT8(&port->base->udl, 0); + + // Reset the Delta Break bit in the UISR and + //Enable autobaud + HAL_WRITE_UINT8(&port->base->ucr, + MCF5272_UART_UCR_RESET_BKCHGINT); + + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_ENAB); + + // Enable autobaud completion interrupt + port->imr_mirror |= MCF5272_UART_UIMR_ABC; + + // Disable the delta break interrupt so we can't receive + // anymore break interrupt. + port->imr_mirror &= ~MCF5272_UART_UIMR_DB; + + } + break; + + case AB_BEGIN: + if (isr & MCF5272_UART_UISR_ABC) + { + int count; + unsigned int threshold; + cyg_uint8 uabu, uabl; + + // Retrieve the detected baud rate + HAL_READ_UINT8(&port->base->uabu, uabu); + HAL_READ_UINT8(&port->base->uabl, uabl); + + cyg_uint16 divider = (uabu << 8) + uabl; + + // Search in the list to find a match + for (count = sizeof(dividers_table)/ + sizeof(unsigned long) - 1; + count > 1; count--) + { + if (divider < dividers_table[count - 1]) break; + } + + // Modify baud rate only if it is in range + if (count > 1) + { + // Set the baud rate to the nearest standard rate + threshold = (dividers_table[count] + + dividers_table[count - 1]) / 2; + port->config.baud = (divider < threshold) ? count : + count - 1; + } + + divider = dividers_table[port->config.baud]; + + // Program the baud settings to the device + HAL_WRITE_UINT8(&port->base->udu, + (cyg_uint8)((divider & 0xFF00) >> 8)); + HAL_WRITE_UINT8(&port->base->udl, + (cyg_uint8)(divider & 0x00FF)); + + // Autobaud completion + port->autobaud_state = AB_IDLE; + + // Disable autobaud + HAL_WRITE_UINT8(&port->base->ucr, MCF5272_UART_UCR_NONE); + +#if 0 + // In case patch submitted July 11, 2005 gets committed +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + // Inform upper layers of the new baud rate + { + cyg_serial_line_status_t stat; + + stat.which = CYGNUM_SERIAL_STATUS_NEWBAUDRATE; + stat.value = port->config.baud; + + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif +#endif + // Ignore autobaud completion interrupt + port->imr_mirror &= ~MCF5272_UART_UIMR_ABC; + + // Reenable delta break interrupt + port->imr_mirror |= MCF5272_UART_UIMR_DB; + + } + break; + + default: + case AB_IDLE: + if (isr & MCF5272_UART_UISR_DB) + { + // Detected the begin of a break, set the state to + // AB_BEGIN_BREAK + port->autobaud_state = AB_BEGIN_BREAK; + + // Reset the delta break bit in the UISR + HAL_WRITE_UINT8(&port->base->ucr, + MCF5272_UART_UCR_RESET_BKCHGINT); + } + break; + } +#endif // REQUESTED_AUTOBAUD + + // Receive character interrupt + if ((isr & MCF5272_UART_UISR_RXRDY)) + { + char c; + cyg_uint8 usr_ucsr; +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + cyg_serial_line_status_t stat; +#endif + + // Read all the characters in the fifo + while (1) + { + // First of all, the exit condition + + // If there are no more characters waiting, exit the loop + HAL_READ_UINT8(&port->base->uisr_uimr, uisr_uimr); + if (!(uisr_uimr & MCF5272_UART_UISR_RXRDY)) break; + + // Read port status + HAL_READ_UINT8(&port->base->usr_ucsr, usr_ucsr); + + // Received break + if (usr_ucsr & MCF5272_UART_USR_RB) + { + // Ignore break character + HAL_READ_UINT8(&port->base->urb_utb, c); +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_BREAK; + (chan->callbacks->indicate_status)(chan, &stat); +#endif + continue; + } + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + // Overrun error + if (usr_ucsr & MCF5272_UART_USR_OE) + { + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + // Framing error + if (usr_ucsr & MCF5272_UART_USR_FE) + { + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + // Parity error + if (usr_ucsr & MCF5272_UART_USR_PE) + { + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + + // Read the character from the UART + HAL_READ_UINT8(&port->base->urb_utb, c); + + // Pass the read character to the upper layer + (chan->callbacks->rcv_char)(chan, c); + } + } + + // Transmit complete interrupt + if ((isr & MCF5272_UART_UISR_TXRDY)) + { + // Transmit holding register is empty + (chan->callbacks->xmt_char)(chan); + } + } + + // Unmask all the UART interrupts that were masked in the ISR, so + // that we can receive the next interrupt. + HAL_WRITE_UINT8(&port->base->uisr_uimr, port->imr_mirror); +} diff --git a/ecos/packages/devs/serial/coldfire/mcf5272/current/src/mcf5272_serial.h b/ecos/packages/devs/serial/coldfire/mcf5272/current/src/mcf5272_serial.h new file mode 100644 index 0000000..b075a14 --- /dev/null +++ b/ecos/packages/devs/serial/coldfire/mcf5272/current/src/mcf5272_serial.h @@ -0,0 +1,141 @@ +#ifndef CYGONCE_MCF5272_SERIAL_H +#define CYGONCE_MCF5272_SERIAL_H + +//========================================================================== +// +// devs/serial/coldfire/mcf5272/mcf5272_serial.h +// +// ColdFire MCF5272 serial I/O module definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria, Wade Jensen +// Contributors: +// Date: 2005-06-25 +// Purpose: MCF5272 serial I/O module definitions. +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + + +#include <pkgconf/io_serial_coldfire_mcf5272.h> + +// Bit level definitions and macros +#define MCF5272_UART_UMR1_RXRTS (0x80) +#define MCF5272_UART_UMR1_RXIRQ (0x40) +#define MCF5272_UART_UMR1_ERR (0x20) +#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5272_UART_UMR1_PM_NONE (0x10) +#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5272_UART_UMR1_PM_ODD (0x04) +#define MCF5272_UART_UMR1_PM_EVEN (0x00) +#define MCF5272_UART_UMR1_BC_5 (0x00) +#define MCF5272_UART_UMR1_BC_6 (0x01) +#define MCF5272_UART_UMR1_BC_7 (0x02) +#define MCF5272_UART_UMR1_BC_8 (0x03) + +#define MCF5272_UART_UMR2_CM_NORMAL (0x00) +#define MCF5272_UART_UMR2_CM_ECHO (0x40) +#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5272_UART_UMR2_CM_REMOTE_LOO (0xC0) +#define MCF5272_UART_UMR2_TXRTS (0x20) +#define MCF5272_UART_UMR2_TXCTS (0x10) +#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F) +// Stop Bit Length +#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) + +#define MCF5272_UART_USR_RB (0x80) +#define MCF5272_UART_USR_FE (0x40) +#define MCF5272_UART_USR_PE (0x20) +#define MCF5272_UART_USR_OE (0x10) +#define MCF5272_UART_USR_TXEMP (0x08) +#define MCF5272_UART_USR_TXRDY (0x04) +#define MCF5272_UART_USR_FFULL (0x02) +#define MCF5272_UART_USR_RXRDY (0x01) + +// Rx Clk Select +#define MCF5272_UART_UCSR_RCS(a) (((a) & 0x0f) << 4) +// Tx Clk Select +#define MCF5272_UART_UCSR_TCS(a) ((a) & 0x0f) + + +#define MCF5272_UART_UCR_NONE (0x00) +#define MCF5272_UART_UCR_ENAB (0x80) +#define MCF5272_UART_UCR_STOP_BREAK (0x70) +#define MCF5272_UART_UCR_START_BREAK (0x60) +#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5272_UART_UCR_RESET_ERROR (0x40) +#define MCF5272_UART_UCR_RESET_TX (0x30) +#define MCF5272_UART_UCR_RESET_RX (0x20) +#define MCF5272_UART_UCR_RESET_MR (0x10) +#define MCF5272_UART_UCR_TX_DISABLED (0x08) +#define MCF5272_UART_UCR_TX_ENABLED (0x04) +#define MCF5272_UART_UCR_RX_DISABLED (0x02) +#define MCF5272_UART_UCR_RX_ENABLED (0x01) + +#define MCF5272_UART_UCR_TXRXEN \ + (MCF5272_UART_UCR_TX_ENABLED | MCF5272_UART_UCR_RX_ENABLED) + +#define MCF5272_UART_UCCR_COS (0x10) +#define MCF5272_UART_UCCR_CTS (0x01) + +#define MCF5272_UART_UACR_BRG (0x80) +#define MCF5272_UART_UACR_CTMS_TIMER (0x60) +#define MCF5272_UART_UACR_IEC (0x01) + +#define MCF5272_UART_UISR_COS (0x80) +#define MCF5272_UART_UISR_ABC (0x40) +#define MCF5272_UART_UISR_DB (0x04) +#define MCF5272_UART_UISR_RXRDY (0x02) +#define MCF5272_UART_UISR_TXRDY (0x01) + +#define MCF5272_UART_UIMR_COS (0x80) +#define MCF5272_UART_UIMR_ABC (0x40) +#define MCF5272_UART_UIMR_DB (0x04) +#define MCF5272_UART_UIMR_FFULL_RXRDY (0x02) +#define MCF5272_UART_UIMR_TXRDY (0x01) + +#define MCF5272_UART_UOP0_RTS (0x01) +#define MCF5272_UART_UOP1_RTS (0x01) + +// --------------------------------------------------------------------------- +// End of mcf5272_serial.h +#endif // CYGONCE_MCF5272_SERIAL_H diff --git a/ecos/packages/devs/serial/cortexm/a2fxxx/current/ChangeLog b/ecos/packages/devs/serial/cortexm/a2fxxx/current/ChangeLog new file mode 100644 index 0000000..0dffdc0 --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/a2fxxx/current/ChangeLog @@ -0,0 +1,30 @@ +2011-03-20 Christophe Coutand <ecos@hotmail.co.uk> + + * cdl/ser_cortexm_a2fxxx.cdl + * include/ser_cortexm_a2fxxx.inl + New package -- Actel smartfusion Serial Driver + [Bugzilla 1001291] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/cortexm/a2fxxx/current/cdl/ser_cortexm_a2fxxx.cdl b/ecos/packages/devs/serial/cortexm/a2fxxx/current/cdl/ser_cortexm_a2fxxx.cdl new file mode 100644 index 0000000..fe6fcdb --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/a2fxxx/current/cdl/ser_cortexm_a2fxxx.cdl @@ -0,0 +1,219 @@ +# ==================================================================== +# +# ser_cortexm_a2fxxx.cdl +# +# eCos serial Cortex-M3/Actel Smartfusion configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): ccoutand +# Original data: gthomas +# Contributors: +# Date: 2011-03-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_CORTEXM_A2FXXX { + display "Cortex-M3/Actel Smartfusion serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_CORTEXM_A2FXXX + implements CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Cortex-M3/Actel Smartfusion." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4" + } + + requires { CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME == "1" } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/ser_cortexm_a2fxxx.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_cortexm_a2fxxx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0 { + display "Cortex-M3/Actel Smartfusion serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + Cortex-M3/Actel Smartfusion port 0." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_NAME { + display "Device name for the serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the Cortex-M3/Actel Smartfusion port 0." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BAUD { + display "Baud rate for the serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the Cortex-M3/Actel Smartfusion port 0." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE { + display "Buffer size for the serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the Cortex-M3/Actel Smartfusion port 0." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_INTPRIO { + display "Interrupt priority of the serial port 0 ISR" + flavor data + default_value { CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP } + requires { is_active(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO) + implies CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_INTPRIO != + CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO } + description " + This option specifies the interrupt priority of the + ISR of the serial port 1 interrupt in the NVIC." + } + + } + + cdl_component CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1 { + display "Cortex-M3/Actel Smartfusion serial port 1 driver" + flavor bool + default_value 0 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + Cortex-M3/Actel Smartfusion port 1." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_NAME { + display "Device name for the serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device + for the Cortex-M3/Actel Smartfusion port 1." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BAUD { + display "Baud rate for the serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the Cortex-M3/Actel Smartfusion port 1." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE { + display "Buffer size for the serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal + buffers used for the Cortex-M3/Actel Smartfusion port 1." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO { + display "Interrupt priority of the serial port 1 ISR" + flavor data + default_value { CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP } + description " + This option specifies the interrupt priority of the + ISR of the serial port 1 interrupt in the NVIC." + } + } + + cdl_component CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"a2fxxx\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_cortexm_a2fxx.cdl diff --git a/ecos/packages/devs/serial/cortexm/a2fxxx/current/include/ser_cortexm_a2fxxx.inl b/ecos/packages/devs/serial/cortexm/a2fxxx/current/include/ser_cortexm_a2fxxx.inl new file mode 100644 index 0000000..7d7ab23 --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/a2fxxx/current/include/ser_cortexm_a2fxxx.inl @@ -0,0 +1,210 @@ +//========================================================================== +// +// ser_cortexm_a2fxxx.inl +// +// eCos serial Cortex-M3/Actel Smartfusion I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-03-20 +// Purpose: Cortex-M3/Actel Smartfusion Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +// Baud rate specification +static const unsigned int select_baud[] = +{ + 9999, // Unused + 50, + 75, + 110, + 134.5, + 150, + 200, + 300, + 600, + 1200, + 1800, + 2400, + 3600, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400 +}; + + +//----------------------------------------------------------------------------- +// Return baudrate devisor for certain baudrate + +unsigned short a2fxxx_baud_generator(pc_serial_info *ser_chan, + cyg_serial_baud_rate_t baud) +{ + cyg_uint8 pclk_id = 0; + switch (ser_chan->base) + { + case CYGHWR_HAL_A2FXXX_UART0: + pclk_id = 0; + break; + + case CYGHWR_HAL_A2FXXX_UART1: + pclk_id = 1; + break; + default: + CYG_FAIL("Invalid UART base address"); + } // (ser_chan->base) + + return CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR(pclk_id, select_baud[baud]); +} + + +#define CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(_ser_chan_, _baud_) \ + a2fxxx_baud_generator((_ser_chan_), (_baud_)) + + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0 +static pc_serial_info a2fxxx_serial_info0 = + { CYGHWR_HAL_A2FXXX_UART0, + CYGNUM_HAL_INTERRUPT_UART0, + CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_INTPRIO + }; + +#if CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE > 0 +static unsigned char +a2fxxx_serial_out_buf0[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE]; +static unsigned char +a2fxxx_serial_in_buf0[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(a2fxxx_serial_channel0, + pc_serial_funs, + a2fxxx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &a2fxxx_serial_out_buf0[0], + sizeof(a2fxxx_serial_out_buf0), + &a2fxxx_serial_in_buf0[0], + sizeof(a2fxxx_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(a2fxxx_serial_channel0, + pc_serial_funs, + a2fxxx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(a2fxxx_serial_io0, + CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &a2fxxx_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1 +static pc_serial_info a2fxxx_serial_info1 = + { CYGHWR_HAL_A2FXXX_UART1, + CYGNUM_HAL_INTERRUPT_UART1, + CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO + }; +#if CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE > 0 +static unsigned char +a2fxxx_serial_out_buf1[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE]; +static unsigned char +a2fxxx_serial_in_buf1[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(a2fxxx_serial_channel1, + pc_serial_funs, + a2fxxx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &a2fxxx_serial_out_buf1[0], + sizeof(a2fxxx_serial_out_buf1), + &a2fxxx_serial_in_buf1[0], + sizeof(a2fxxx_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(a2fxxx_serial_channel1, + pc_serial_funs, + a2fxxx_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(a2fxxx_serial_io1, + CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_NAME, + 0, // Does not depend on a lower + // level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &a2fxxx_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1 + +// EOF ser_cortexm_a2fxxx.inl diff --git a/ecos/packages/devs/serial/cortexm/stm32/current/ChangeLog b/ecos/packages/devs/serial/cortexm/stm32/current/ChangeLog new file mode 100644 index 0000000..4c8561e --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/stm32/current/ChangeLog @@ -0,0 +1,70 @@ +2012-04-02 Jonathan Larmour <jifl@eCosCentric.com> + + * src/stm32_serial.h: Revert unnecessary change in previous + commit, reinstating previous code. + * src/stm32_serial.c (stm32_serial_config_port): Ditto. + +2011-12-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_cortexm_stm32.cdl: Default baud rates to the HAL + diag console channel. Add support for serial port 5 + (USART6 in STM32 speak). Select serial/tty test devices better + according to the configuration. + * src/stm32_serial.c: Support serial port 5. Make use of AFIO + remap specific to F1 processors. + +2010-12-31 John Dallaway <john@dallaway.org.uk> + + * src/stm32_serial.c, src/stm32_serial.h: Set the M bit when + configuring for 8 data bits + parity bit. [ Bugzilla 1001068 ] + +2009-12-03 Nick Garnett <nickg@ecoscentric.com> + + * cdl/ser_cortexm_stm32.cdl: + * src/stm32_serial.c (stm32_serial_info, stm32_serial_info0) + (stm32_serial_info1, stm32_serial_info2, stm32_serial_info3) + (stm32_serial_info4, stm32_serial_init): + Add configuration options to set serial ISR interrupt priorities. + +2009-07-02 Nick Garnett <nickg@ecoscentric.com> + + * src/stm32_serial.c (stm32_serial_info) + (stm32_serial_config_port): Add support for UART pin remap. + +2009-06-29 Nick Garnett <nickg@ecoscentric.com> + + * src/stm32_serial.c (stm32_serial_info) + (stm32_serial_config_port): Add support for individual clock + enable on each UART. + +2008-10-07 Nick Garnett <nickg@ecoscentric.com> + + * cdl/ser_cortexm_stm32.cdl: + * src/stm32_serial.h: + * src/stm32_serial.c: + New package: serial driver support for ST STM32 + microcontrollers. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl b/ecos/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl new file mode 100644 index 0000000..a5b1e91 --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl @@ -0,0 +1,422 @@ +# ==================================================================== +# +# ser_cortexm_stm32.cdl +# +# eCos serial ST STM32 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2008, 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): nickg +# Date: 2008-09-10 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_CORTEXM_STM32 { + display "ST STM32 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_CORTEXM_STM32 + + requires CYGPKG_ERROR + include_dir cyg/io + description " + This option enables the serial device drivers for the + ST STM32." + + compile -library=libextras.a stm32_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_cortexm_stm32.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 { + display "ST STM32 serial port 0 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART0>0 + description " + This option includes the serial device driver for the ST STM32 + port 0." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL0_NAME { + display "Device name for ST STM32 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BAUD { + display "Baud rate for the ST STM32 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value { CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE { + display "Buffer size for the ST STM32 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_INT_PRI { + display "Interrupt priority for STM32 serial port 0" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 { + display "ST STM32 serial port 1 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART1>0 + description " + This option includes the serial device driver for the ST STM32 + port 1." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL1_NAME { + display "Device name for ST STM32 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BAUD { + display "Baud rate for the ST STM32 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE { + display "Buffer size for the ST STM32 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_INT_PRI { + display "Interrupt priority for STM32 serial port 1" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 { + display "ST STM32 serial port 2 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART2>0 + description " + This option includes the serial device driver for the ST STM32 + port 2." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL2_NAME { + display "Device name for ST STM32 serial port 2 driver" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BAUD { + display "Baud rate for the ST STM32 serial port 2 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE { + display "Buffer size for the ST STM32 serial port 2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_INT_PRI { + display "Interrupt priority for STM32 serial port 2" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 { + display "ST STM32 serial port 3 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART3>0 + description " + This option includes the serial device driver for the ST STM32 + port 3." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL3_NAME { + display "Device name for ST STM32 serial port 3 driver" + flavor data + default_value {"\"/dev/ser3\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 3." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BAUD { + display "Baud rate for the ST STM32 serial port 3 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 3." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE { + display "Buffer size for the ST STM32 serial port 3 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 3." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_INT_PRI { + display "Interrupt priority for STM32 serial port 3" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 { + display "ST STM32 serial port 4 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART4>0 + description " + This option includes the serial device driver for the ST STM32 + port 4." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL4_NAME { + display "Device name for ST STM32 serial port 4 driver" + flavor data + default_value {"\"/dev/ser4\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 4." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BAUD { + display "Baud rate for the ST STM32 serial port 4 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 4." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE { + display "Buffer size for the ST STM32 serial port 4 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 4." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_INT_PRI { + display "Interrupt priority for STM32 serial port 4" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 { + display "ST STM32 serial port 5 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART5>0 + description " + This option includes the serial device driver for the ST STM32 + port 5." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME { + display "Device name for ST STM32 serial port 5 driver" + flavor data + default_value {"\"/dev/ser5\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 5." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD { + display "Baud rate for the ST STM32 serial port 5 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 5." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE { + display "Buffer size for the ST STM32 serial port 5 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 5." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_INT_PRI { + display "Interrupt priority for STM32 serial port 5" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + + + cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_CORTEXM_STM32_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_CORTEXM_STM32_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_TESTING { + display "Testing parameters" + flavor none + + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_38400 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL0_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL1_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL2_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL3_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL4_NAME : \ + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME } + } + + cdl_option CYGPRI_SER_TEST_TTY_DEV { + display "TTY-mode serial device used for testing" + flavor data + default_value { CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 ? "\"/dev/tty0\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 ? "\"/dev/tty1\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 ? "\"/dev/tty2\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 ? "\"/dev/tty3\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 ? "\"/dev/tty4\"" : \ + "\"/dev/tty5\"" } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"stm32\"" + } + } +} + +# EOF ser_cortexm_stm32.cdl diff --git a/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c b/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c new file mode 100644 index 0000000..8572d62 --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c @@ -0,0 +1,946 @@ +//========================================================================== +// +// devs/serial/cortexm/stm32/stm32_serial.c +// +// ST STM32 Serial I/O Interface Module +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998-2002, 2004-2006, 2008-2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-09-10 +// Purpose: ST STM32 Serial I/O module +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/infra.h> +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <pkgconf/kernel.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> + + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32 + +#include "stm32_serial.h" + +//========================================================================== + +#define STM32_RXBUFSIZE 16 + +typedef struct stm32_serial_info +{ + CYG_WORD uart; + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_int32 int_pri; + cyg_int32 rx_pin; + cyg_int32 tx_pin; + cyg_int32 rts_pin; + cyg_int32 cts_pin; + cyg_int32 clk_enable; +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + cyg_int32 remap; +#endif + + cyg_bool tx_active; + + volatile cyg_uint8 buf[STM32_RXBUFSIZE]; + volatile int buf_head; + volatile int buf_tail; + + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} stm32_serial_info; + +//========================================================================== + +static bool stm32_serial_init(struct cyg_devtab_entry *tab); +static bool stm32_serial_putc_interrupt(serial_channel *chan, unsigned char c); +#if (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0) +static bool stm32_serial_putc_polled(serial_channel *chan, unsigned char c); +#endif +static Cyg_ErrNo stm32_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char stm32_serial_getc_interrupt(serial_channel *chan); +#if (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0) +static unsigned char stm32_serial_getc_polled(serial_channel *chan); +#endif +static Cyg_ErrNo stm32_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void stm32_serial_start_xmit(serial_channel *chan); +static void stm32_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 stm32_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void stm32_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +//========================================================================== + +#if (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE > 0) +static SERIAL_FUNS(stm32_serial_funs_interrupt, + stm32_serial_putc_interrupt, + stm32_serial_getc_interrupt, + stm32_serial_set_config, + stm32_serial_start_xmit, + stm32_serial_stop_xmit + ); +#endif + +#if (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0) +static SERIAL_FUNS(stm32_serial_funs_polled, + stm32_serial_putc_polled, + stm32_serial_getc_polled, + stm32_serial_set_config, + stm32_serial_start_xmit, + stm32_serial_stop_xmit + ); +#endif + +//========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 +static stm32_serial_info stm32_serial_info0 = { + uart : 0, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART1, + int_num : CYGNUM_HAL_INTERRUPT_UART1, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART1_RX, + tx_pin : CYGHWR_HAL_STM32_UART1_TX, + rts_pin : CYGHWR_HAL_STM32_UART1_RTS, + cts_pin : CYGHWR_HAL_STM32_UART1_CTS, + clk_enable : CYGHWR_HAL_STM32_UART1_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART1_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART1_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf0[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE]; +static unsigned char stm32_serial_in_buf0[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel0, + stm32_serial_funs_interrupt, + stm32_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf0[0], sizeof(stm32_serial_out_buf0), + &stm32_serial_in_buf0[0], sizeof(stm32_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel0, + stm32_serial_funs_polled, + stm32_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io0, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 + +//========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 +static stm32_serial_info stm32_serial_info1 = { + uart : 1, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART2, + int_num : CYGNUM_HAL_INTERRUPT_UART2, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART2_RX, + tx_pin : CYGHWR_HAL_STM32_UART2_TX, + rts_pin : CYGHWR_HAL_STM32_UART2_RTS, + cts_pin : CYGHWR_HAL_STM32_UART2_CTS, + clk_enable : CYGHWR_HAL_STM32_UART2_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART2_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART2_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf1[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE]; +static unsigned char stm32_serial_in_buf1[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel1, + stm32_serial_funs_interrupt, + stm32_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf1[0], sizeof(stm32_serial_out_buf1), + &stm32_serial_in_buf1[0], sizeof(stm32_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel1, + stm32_serial_funs_polled, + stm32_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io1, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 + +//========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 +static stm32_serial_info stm32_serial_info2 = { + uart : 2, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART3, + int_num : CYGNUM_HAL_INTERRUPT_UART3, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART3_RX, + tx_pin : CYGHWR_HAL_STM32_UART3_TX, + rts_pin : CYGHWR_HAL_STM32_UART3_RTS, + cts_pin : CYGHWR_HAL_STM32_UART3_CTS, + clk_enable : CYGHWR_HAL_STM32_UART3_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART3_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART3_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf2[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE]; +static unsigned char stm32_serial_in_buf2[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel2, + stm32_serial_funs_interrupt, + stm32_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf2[0], sizeof(stm32_serial_out_buf2), + &stm32_serial_in_buf2[0], sizeof(stm32_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel2, + stm32_serial_funs_polled, + stm32_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io2, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 + +//========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 +static stm32_serial_info stm32_serial_info3 = { + uart : 3, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART4, + int_num : CYGNUM_HAL_INTERRUPT_UART4, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART4_RX, + tx_pin : CYGHWR_HAL_STM32_UART4_TX, + rts_pin : CYGHWR_HAL_STM32_UART4_RTS, + cts_pin : CYGHWR_HAL_STM32_UART4_CTS, + clk_enable : CYGHWR_HAL_STM32_UART4_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART4_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART4_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf3[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE]; +static unsigned char stm32_serial_in_buf3[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel3, + stm32_serial_funs_interrupt, + stm32_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf3[0], sizeof(stm32_serial_out_buf3), + &stm32_serial_in_buf3[0], sizeof(stm32_serial_in_buf3) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel3, + stm32_serial_funs_polled, + stm32_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io3, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL3_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel3 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 + +//========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 +static stm32_serial_info stm32_serial_info4 = { + uart : 4, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART5, + int_num : CYGNUM_HAL_INTERRUPT_UART5, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART5_RX, + tx_pin : CYGHWR_HAL_STM32_UART5_TX, + rts_pin : CYGHWR_HAL_STM32_UART5_RTS, + cts_pin : CYGHWR_HAL_STM32_UART5_CTS, + clk_enable : CYGHWR_HAL_STM32_UART5_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART5_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART5_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf4[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE]; +static unsigned char stm32_serial_in_buf4[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel4, + stm32_serial_funs_interrupt, + stm32_serial_info4, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf4[0], sizeof(stm32_serial_out_buf4), + &stm32_serial_in_buf4[0], sizeof(stm32_serial_in_buf4) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel4, + stm32_serial_funs_polled, + stm32_serial_info4, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io4, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL4_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel4 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 + + +//========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 +static stm32_serial_info stm32_serial_info5 = { + uart : 5, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART6, + int_num : CYGNUM_HAL_INTERRUPT_UART6, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART6_RX, + tx_pin : CYGHWR_HAL_STM32_UART6_TX, + rts_pin : CYGHWR_HAL_STM32_UART6_RTS, + cts_pin : CYGHWR_HAL_STM32_UART6_CTS, + clk_enable : CYGHWR_HAL_STM32_UART6_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART6_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART6_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf5[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE]; +static unsigned char stm32_serial_in_buf5[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel5, + stm32_serial_funs_interrupt, + stm32_serial_info5, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf5[0], sizeof(stm32_serial_out_buf5), + &stm32_serial_in_buf5[0], sizeof(stm32_serial_in_buf5) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel5, + stm32_serial_funs_polled, + stm32_serial_info5, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io5, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel5 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 + + +//========================================================================== +// Internal function to actually configure the hardware to desired baud +// rate, etc. + +static bool +stm32_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *)chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 parity = select_parity[new_config->parity]; + cyg_uint32 word_length = ((new_config->word_length == CYGNUM_SERIAL_WORD_LENGTH_8) && + (new_config->parity != CYGNUM_SERIAL_PARITY_NONE)) ? + CYGHWR_HAL_STM32_UART_CR1_M_9 : CYGHWR_HAL_STM32_UART_CR1_M_8; + cyg_uint32 stop_bits = select_stop_bits[new_config->stop]; + cyg_uint32 cr1 = 0; + cyg_uint32 cr2 = 0; + cyg_uint32 cr3 = 0; + + // Set up FIFO buffer + stm32_chan->buf_head = stm32_chan->buf_tail = 0; + + // Set up GPIO pins + CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->rx_pin ); + CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->tx_pin ); + CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->rts_pin ); + CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->cts_pin ); + + // Enable clock + CYGHWR_HAL_STM32_CLOCK_ENABLE( stm32_chan->clk_enable ); + + // Handle any pin remapping +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + if( stm32_chan->remap != 0 ) + { + CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO; + cyg_uint32 mapr; + CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK ); + HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr ); + mapr |= stm32_chan->remap; + HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr ); + } +#endif + + // Select line parameters + cr1 |= parity|word_length; + cr2 |= stop_bits; + + cr1 |= CYGHWR_HAL_STM32_UART_CR1_TE | CYGHWR_HAL_STM32_UART_CR1_RE; + + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 ); + + // Set up baud rate + hal_stm32_uart_setbaud( base, select_baud[new_config->baud] ); + + // Enable the uart + cr1 |= CYGHWR_HAL_STM32_UART_CR1_UE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + + +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + // Handle RTS by hand but leave CTS to be handled by the UART hardware + if ( (new_config->flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX) && stm32_chan->cts_pin != CYGHWR_HAL_STM32_GPIO_NONE ) + { + cr3 |= CYGHWR_HAL_STM32_UART_CR3_CTSE; + } +#endif + + if(1) + { + // Enable receive and error interrupts + + cr1 |= CYGHWR_HAL_STM32_UART_CR1_RXNEIE; + cr3 |= CYGHWR_HAL_STM32_UART_CR3_EIE; + + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + } + + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR3, cr3 ); + + stm32_chan->tx_active = false; + + if (new_config != &chan->config) + chan->config = *new_config; + + return true; +} + +//========================================================================== +// Function to initialize the device. Called at bootstrap time. + +static bool +stm32_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel * const chan = (serial_channel *) tab->priv; + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + int res; + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(stm32_chan->int_num, + stm32_chan->int_pri, + (cyg_addrword_t)chan, + stm32_serial_ISR, + stm32_serial_DSR, + &stm32_chan->serial_interrupt_handle, + &stm32_chan->serial_interrupt); + cyg_drv_interrupt_attach(stm32_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(stm32_chan->int_num); + + } + + res = stm32_serial_config_port(chan, &chan->config, true); + return res; +} + +//========================================================================== +// This routine is called when the device is "looked" up (i.e. attached) + +static Cyg_ErrNo +stm32_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel * const chan = (serial_channel *) (*tab)->priv; + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +//========================================================================== +// Send a character to the device output buffer. +// Return 'true' if character is sent to device + +static bool +stm32_serial_putc_interrupt(serial_channel *chan, unsigned char c) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 status; + + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, status ); + + if (status & CYGHWR_HAL_STM32_UART_SR_TXE) + { + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + return true; + } + + return false; +} + +//========================================================================== + +static bool +stm32_serial_putc_polled(serial_channel *chan, unsigned char c) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 status; + + do { + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, status ); + } while ((status & CYGHWR_HAL_STM32_UART_SR_TXE) == 0); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + + return true; +} + +//========================================================================== +// Fetch a character from the device input buffer + +static unsigned char +stm32_serial_getc_interrupt(serial_channel *chan) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + CYG_WORD32 c; + + // Read data + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c); + return (unsigned char) (c&0xFF); +} + +//========================================================================== + +static unsigned char +stm32_serial_getc_polled(serial_channel *chan) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 stat; + cyg_uint32 c; + + do { + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, stat ); + } while ((stat & CYGHWR_HAL_STM32_UART_SR_RXNE) == 0); + + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c); + + return (unsigned char) (c&0xFF); +} + +//========================================================================== +// Set up the device characteristics; baud rate, etc. + +static Cyg_ErrNo +stm32_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != stm32_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + cyg_uint32 *f = (cyg_uint32 *)xbuf; + + if ( *len < sizeof(*f) ) + return -EINVAL; + + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) + { + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + + // Note that the RTS line is active-low, so set it to 1 + // to throttle and 0 to allow the data to flow. + if( *f ) + CYGHWR_HAL_STM32_GPIO_OUT( stm32_chan->rts_pin, 1 ); + else + CYGHWR_HAL_STM32_GPIO_OUT( stm32_chan->rts_pin, 0 ); + } + } + break; + + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + { + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + Cyg_ErrNo result = ENOERR; + + // If the client is asking for DSR/DTR, refuse to do it. + if (0 != (chan->config.flags & (CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX))) + { + chan->config.flags &= ~(CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX); + result = -ENOSUPP; + } + + // If the client is asking for RTS/CTS then only allow it if + // the port has RTS/CTS lines attached to it. + if (0 != (chan->config.flags & (CYGNUM_SERIAL_FLOW_RTSCTS_RX | CYGNUM_SERIAL_FLOW_RTSCTS_TX))) + { + if( stm32_chan->rts_pin != CYGHWR_HAL_STM32_GPIO_NONE && + stm32_chan->cts_pin != CYGHWR_HAL_STM32_GPIO_NONE ) + { + chan->config.flags &= (CYGNUM_SERIAL_FLOW_RTSCTS_RX | CYGNUM_SERIAL_FLOW_RTSCTS_TX); + } + else + { + chan->config.flags &= ~(CYGNUM_SERIAL_FLOW_RTSCTS_RX | CYGNUM_SERIAL_FLOW_RTSCTS_TX); + result = -ENOSUPP; + } + } + return result; + } + +#endif + + default: + return -EINVAL; + } + return ENOERR; +} + +//========================================================================== +// Enable the transmitter on the device + +static void +stm32_serial_start_xmit(serial_channel *chan) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 cr1; + + if( !stm32_chan->tx_active ) + { + stm32_chan->tx_active = true; + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + cr1 |= CYGHWR_HAL_STM32_UART_CR1_TXEIE; + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + } + +} + +//========================================================================== +// Disable the transmitter on the device + +static void +stm32_serial_stop_xmit(serial_channel *chan) +{ + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 cr1; + + if( stm32_chan->tx_active ) + { + stm32_chan->tx_active = false; + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_TXEIE; + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + } + +} + +//========================================================================== +// Serial I/O - low level interrupt handler (ISR) +// +// This ISR does rather more than other serial driver ISRs. Normally, +// the ISR just masks the interrupt vector and schedules the DSR, +// which then handles all IO. However, if the processor is running out +// of external RAM it is too slow to handle higher baud rates using +// that technique. Something that is exacerbated by the lack of FIFOs +// in the USART hardware. +// +// Instead, this ISR receives any incoming data into a circular +// buffer, essentially providing the FIFO lacking in the +// hardware. Transmission is still offloaded to the DSR. Only TX +// interrupts are masked while this is done to prevent an interrupt +// loop, and to avoid blocking RX interrupts. + +static cyg_uint32 +stm32_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel * const chan = (serial_channel *) data; + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + cyg_uint32 stat; + cyg_uint32 ret = CYG_ISR_HANDLED; + cyg_drv_interrupt_acknowledge(vector); + + HAL_READ_UINT32(base + CYGHWR_HAL_STM32_UART_SR, stat); + + if( stat & CYGHWR_HAL_STM32_UART_SR_RXNE ) + { + cyg_uint32 c; + + while( stat & CYGHWR_HAL_STM32_UART_SR_RXNE ) + { + int next = stm32_chan->buf_head+1; + + if( next == STM32_RXBUFSIZE ) next = 0; + + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c); + + if( next != stm32_chan->buf_tail ) + { + stm32_chan->buf[stm32_chan->buf_head] = c&0xFF; + stm32_chan->buf_head = next; + ret |= CYG_ISR_CALL_DSR; + } + else + { + // TODO: deal with buffer overflow + } + + HAL_READ_UINT32(base + CYGHWR_HAL_STM32_UART_SR, stat); + } + } + else if( stat & CYGHWR_HAL_STM32_UART_SR_TXE ) + { + cyg_uint32 cr1; + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_TXEIE; + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + + ret |= CYG_ISR_CALL_DSR; + } + + + if( stat & CYGHWR_HAL_STM32_UART_SR_CTS ) + { + // Clear CTS status if we see it. + stat &= ~CYGHWR_HAL_STM32_UART_SR_CTS; + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_SR, stat ); + } + + if( stat & (CYGHWR_HAL_STM32_UART_SR_FE|CYGHWR_HAL_STM32_UART_SR_NE|CYGHWR_HAL_STM32_UART_SR_ORE) ) + { + // TODO: Handle hardware errors + } + + return ret; +} + +//========================================================================== +// Serial I/O - high level interrupt handler (DSR) + +static void +stm32_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel * const chan = (serial_channel *) data; + stm32_serial_info * const stm32_chan = (stm32_serial_info *) chan->dev_priv; + const CYG_ADDRWORD base = stm32_chan->base; + CYG_WORD32 stat; + + while( stm32_chan->buf_head != stm32_chan->buf_tail ) + { + int next = stm32_chan->buf_tail+1; + cyg_uint8 c; + + if( next == STM32_RXBUFSIZE ) next = 0; + c = stm32_chan->buf[stm32_chan->buf_tail]; + stm32_chan->buf_tail = next; + + (chan->callbacks->rcv_char)(chan, c); + } + + HAL_READ_UINT32(base + CYGHWR_HAL_STM32_UART_SR, stat); + + if( stm32_chan->tx_active && stat & CYGHWR_HAL_STM32_UART_SR_TXE ) + { + cyg_uint32 cr1; + + (chan->callbacks->xmt_char)(chan); + + if( stm32_chan->tx_active ) + { + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + cr1 |= CYGHWR_HAL_STM32_UART_CR1_TXEIE; + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + } + } +} + +//========================================================================== +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32 +// end of stm32_serial.c diff --git a/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h b/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h new file mode 100644 index 0000000..a43994d --- /dev/null +++ b/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h @@ -0,0 +1,105 @@ +#ifndef CYGONCE_CORTEXM_STM32_SERIAL_H +#define CYGONCE_CORTEXM_STM32_SERIAL_H + +// ==================================================================== +// +// stm32_serial.h +// +// Device I/O - Description of ST STM32 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-09-10 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <cyg/hal/hal_io.h> // Register definitions + +// ==================================================================== +// Translate system stop bit selector into control register bits. + +static cyg_uint32 select_stop_bits[] = { + CYGHWR_HAL_STM32_UART_CR2_STOP_0_5, // 0.5 stop bits + CYGHWR_HAL_STM32_UART_CR2_STOP_1, // 1 stop bit + CYGHWR_HAL_STM32_UART_CR2_STOP_1_5, // 1.5 stop bit + CYGHWR_HAL_STM32_UART_CR2_STOP_2 // 2 stop bit +}; + +// Translate system parity selector into local values. +static cyg_uint32 select_parity[] = { + 0, // No parity + CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_EVEN, // Even parity + CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_ODD, // Odd parity + 0, // Mark (1) parity -- not supported + 0 // Space (0) parity -- not supported +}; + +// ==================================================================== +// Translate system baud selector into direct baud rate value. This is +// then used to calculate the clock divisor from the PCLK clock. + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +// ==================================================================== +#endif // CYGONCE_CORTEXM_STM32_SERIAL_H diff --git a/ecos/packages/devs/serial/freescale/esci/drv/current/ChangeLog b/ecos/packages/devs/serial/freescale/esci/drv/current/ChangeLog new file mode 100644 index 0000000..1522d50 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/esci/drv/current/ChangeLog @@ -0,0 +1,46 @@ +2007-01-10 Ilija Koco <ilijak@siva.com.mk> + + * ser_freescale_esci_h.cdl: CYGPKG_IO_SERIAL_FREESCALE_ESCI_H + moved in a new directory due ecosadmin.tcl issue + reported by John Dallaway + +2006-08-31 Ilija Koco <ilijak@siva.com.mk> + + * ser_freescale_esci.cdl: driver now requires at least 1 selected + channel + +2006-08-08 Ilija Koco <ilijak@siva.com.mk> + + * ser_esci.h : platform dependent clock related macros + removed and placed in platform/var header + +2006-05-24 Ilija Koco <ilijak@siva.com.mk> + + * cdl/ser_freescale_esci.cdl: + * include/ser_esci.h: + * src/ser_esci.c + New package + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/freescale/esci/drv/current/cdl/ser_freescale_esci.cdl b/ecos/packages/devs/serial/freescale/esci/drv/current/cdl/ser_freescale_esci.cdl new file mode 100644 index 0000000..7bf77e3 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/esci/drv/current/cdl/ser_freescale_esci.cdl @@ -0,0 +1,305 @@ +# ==================================================================== +# +# ser_freescale_esci.cdl +# +# eCos serial Freescale/esci configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Koco <ilijak@siva.com.mk> +# Original data: +# Contributors: +# Date: 2006-04-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_FREESCALE_ESCI { + display "eSCI device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + + requires CYGPKG_IO_SERIAL_FREESCALE_ESCI_H + + requires (CYGPKG_ERROR && (CYGPKG_IO_SERIAL_FREESCALE_ESCI_A || \ + CYGPKG_IO_SERIAL_FREESCALE_ESCI_B || \ + CYGPKG_IO_SERIAL_FREESCALE_ESCI_C || \ + CYGPKG_IO_SERIAL_FREESCALE_ESCI_D) \ + ) + + include_dir cyg/devs + + description " + This option enables the serial device drivers for the + Freescale eSCI - Enhanced Serial Communication Interface. + eSCI is on-chip serial controller found on some freescale + microcontrollers such as: MAC7100 familly, etc. + " + compile -library=libextras.a ser_esci.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_freescale_esci.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_ESCI_A { + display "eSCI port A driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for the eSCI port A." + + cdl_option CYGDAT_IO_SERIAL_FREESCALE_ESCI_A_NAME { + display "Device name for eSCI port A" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name for the eSCI port A." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BAUD { + display "Baud rate for the eSCI serial port A driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 + 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + eSCI port A." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE { + display "Buffer size for the sSCI port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the eSCI port A." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_PRIORITY { + display "eSCI port A INTC priority" + flavor data + legal_values 0 to 15 + default_value 7 + description " + INTC has 16 interrupt levels: 0 (lowest) to 15 (highest). + " + } + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_ESCI_B { + display "eSCI port B driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for the eSCI port B." + + cdl_option CYGDAT_IO_SERIAL_FREESCALE_ESCI_B_NAME { + display "Device name for eSCI port B" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the eSCI port B." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BAUD { + display "Baud rate for the eSCI serial port A driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 + 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + eSCI port B." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE { + display "Buffer size for the sSCI port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the eSCI port B." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_PRIORITY { + display "eSCI prot B INTC priority" + flavor data + legal_values 0 to 15 + default_value 7 + description " + INTC has 16 interrupt levels: 0 (lowest) to 15 (highest). + " + } + + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_ESCI_C { + display "eSCI port C driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for the eSCI port C." + + cdl_option CYGDAT_IO_SERIAL_FREESCALE_ESCI_C_NAME { + display "Device name for eSCI port C" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the eSCI port C." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BAUD { + display "Baud rate for the eSCI serial port A driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 + 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + eSCI port C." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE { + display "Buffer size for the sSCI port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the eSCI port C." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_PRIORITY { + display "eSCI prot B INTC priority" + flavor data + legal_values 0 to 15 + default_value 6 + description " + INTC has 16 interrupt levels: 0 (lowest) to 15 (highest). + " + } + + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_ESCI_D { + display "eSCI port D driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for the eSCI port D." + + cdl_option CYGDAT_IO_SERIAL_FREESCALE_ESCI_D_NAME { + display "Device name for eSCI port D" + flavor data + default_value {"\"/dev/ser3\""} + description " + This option specifies the device name for the eSCI port D." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BAUD { + display "Baud rate for the eSCI serial port A driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 + 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + eSCI port D." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE { + display "Buffer size for the sSCI port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the eSCI port D." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_PRIORITY { + display "eSCI prot B INTC priority" + flavor data + legal_values 0 to 15 + default_value 6 + description " + INTC has 16 interrupt levels: 0 (lowest) to 15 (highest). + " + } + } + + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_ESCI_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_FREESCALE_ESCI_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_FREESCALE_ESCI_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_freescale_esci.cdl diff --git a/ecos/packages/devs/serial/freescale/esci/drv/current/src/ser_esci.c b/ecos/packages/devs/serial/freescale/esci/drv/current/src/ser_esci.c new file mode 100644 index 0000000..97092d2 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/esci/drv/current/src/ser_esci.c @@ -0,0 +1,548 @@ +//========================================================================== +// +// ser_esci.c +// +// Freescale sSCI Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-04-20 +// Purpose: eSCI Serial I/O module (interrupt driven version) +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arbiter.h> +#include <cyg/hal/var_io.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> +#include <cyg/devs/ser_esci.h> + +// Only build this driver for if ESCI is needed. +#ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI + +typedef struct esci_serial_info { + CYG_ADDRWORD esci_base; // Base address of the esci port + CYG_WORD interrupt_num; // INTC interrupt vector + cyg_priority_t interrupt_priority; // INTC interupt priority + cyg_interrupt interrupt_obj; // Interrupt object + cyg_handle_t interrupt_handle; // Interrupt handle +} esci_serial_info; + +static bool esci_serial_init(struct cyg_devtab_entry * tab); +static bool esci_serial_putc(serial_channel * chan, unsigned char c); +static Cyg_ErrNo esci_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, + const char * name); +static unsigned char esci_serial_getc(serial_channel *chan); +static Cyg_ErrNo esci_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void esci_serial_start_xmit(serial_channel *chan); +static void esci_serial_stop_xmit(serial_channel *chan); + +// Interrupt servers +static cyg_uint32 esci_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void esci_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(esci_serial_funs, + esci_serial_putc, + esci_serial_getc, + esci_serial_set_config, + esci_serial_start_xmit, + esci_serial_stop_xmit); + +// Available baud rates +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 bps unsupported + 0, // 75 bps unsupported + 0, // 110 bps unsupported + 0, // 134_5 bps unsupported + 0, // 150 bps unsupported + 0, // 200 bps unsupported + FREESCALE_ESCI_BAUD(300), // 300 bps + FREESCALE_ESCI_BAUD(600), // 600 bps + FREESCALE_ESCI_BAUD(1200), // 1200 bps + 0, // 1800 bps unsupported + FREESCALE_ESCI_BAUD(2400), // 2400 bps + 0, // 3600 bps unsupported + FREESCALE_ESCI_BAUD(4800), // 4800 bps + 0, // 7200 bps unsupported + FREESCALE_ESCI_BAUD(9600), // 9600 bps + FREESCALE_ESCI_BAUD(14400), // 14400 bps + FREESCALE_ESCI_BAUD(19200), // 19200 bps + FREESCALE_ESCI_BAUD(38400), // 38400 bps + FREESCALE_ESCI_BAUD(57600), // 57600 bps + FREESCALE_ESCI_BAUD(115200), // 115200 bps + 0 // 230400 bps unsupported +}; + +#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_A +static esci_serial_info esci_serial_info0 = { + esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_PRIORITY +}; +#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE > 0 +static unsigned char + esci_serial_out_buf0[CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE]; +static unsigned char + esci_serial_in_buf0[CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS( + esci_serial_channel0, + esci_serial_funs, + esci_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &esci_serial_out_buf0[0], + sizeof(esci_serial_out_buf0), + &esci_serial_in_buf0[0], + sizeof(esci_serial_in_buf0)); +#else +static +SERIAL_CHANNEL(esci_serial_channel0, + esci_serial_funs, + esci_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(esci_serial_io0, + CYGDAT_IO_SERIAL_FREESCALE_ESCI_A_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + esci_serial_init, + esci_serial_lookup, + &esci_serial_channel0); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_A + +#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_B +static esci_serial_info esci_serial_info1 = { + esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_PRIORITY +}; +#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE > 0 +static unsigned char + esci_serial_out_buf1[CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE]; +static unsigned char + esci_serial_in_buf1[CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(esci_serial_channel1, + esci_serial_funs, + esci_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &esci_serial_out_buf1[0], + sizeof(esci_serial_out_buf1), + &esci_serial_in_buf1[0], + sizeof(esci_serial_in_buf1)); +#else +static +SERIAL_CHANNEL(esci_serial_channel1, + esci_serial_funs, + esci_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(esci_serial_io1, + CYGDAT_IO_SERIAL_FREESCALE_ESCI_B_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + esci_serial_init, + esci_serial_lookup, + &esci_serial_channel1); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_B + +#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_C +static esci_serial_info esci_serial_info2 = { + esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_PRIORITY +}; +#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE > 0 +static unsigned char + esci_serial_out_buf2[CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE]; +static unsigned char + esci_serial_in_buf2[CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(esci_serial_channel2, + esci_serial_funs, + esci_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &esci_serial_out_buf2[0], + sizeof(esci_serial_out_buf2), + &esci_serial_in_buf2[0], + sizeof(esci_serial_in_buf2)); +#else +static +SERIAL_CHANNEL(esci_serial_channel2, + esci_serial_funs, + esci_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(esci_serial_io2, + CYGDAT_IO_SERIAL_FREESCALE_ESCI_C_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + esci_serial_init, + esci_serial_lookup, + &esci_serial_channel2); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_C + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_D +static esci_serial_info esci_serial_info3 = { + esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_PRIORITY +}; +#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE > 0 +static unsigned char + esci_serial_out_buf3[CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE]; +static unsigned char + esci_serial_in_buf3[CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(esci_serial_channel3, + esci_serial_funs, + esci_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &esci_serial_out_buf3[0], + sizeof(esci_serial_out_buf3), + &esci_serial_in_buf3[0], + sizeof(esci_serial_in_buf3)); +#else +static +SERIAL_CHANNEL(esci_serial_channel3, + esci_serial_funs, + esci_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(esci_serial_io3, + CYGDAT_IO_SERIAL_FREESCALE_ESCI_D_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + esci_serial_init, + esci_serial_lookup, + &esci_serial_channel3); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_D + +//---------------------------------------------------------------------------- +// Internal function to actually configure the hardware to desired +// baud rate, etc. +//---------------------------------------------------------------------------- +static bool +esci_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config, + bool init) +{ + esci_serial_info * esci_chan = (esci_serial_info *)(chan->dev_priv); + cyg_addrword_t esci_base = esci_chan->esci_base; + cyg_uint16 baud_rate = ((new_config->baud >= 0) && + (new_config->baud < (sizeof(select_baud)/ + sizeof(select_baud[0])))) + ? select_baud[new_config->baud] : 0; + + cyg_uint16 esci_cr12=0, esci_cr12_old; + + HAL_WRITE_UINT8(FREESCALE_ESCI_CR3(esci_base), 0); + HAL_WRITE_UINT16(FREESCALE_ESCI_LINCTRL(esci_base), 0); + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), 0); + + if(!baud_rate) return false; // Invalid baud rate selected + + switch(new_config->word_length){ + case 8: break; + default: return false; + } + + switch(new_config->parity){ + case CYGNUM_SERIAL_PARITY_ODD: + esci_cr12 |= FREESCALE_ESCI_CR12_PT; + case CYGNUM_SERIAL_PARITY_EVEN: + esci_cr12 |= FREESCALE_ESCI_CR12_PE; + case CYGNUM_SERIAL_PARITY_NONE: + break; + default: return false; + } + + if(new_config->stop!=CYGNUM_SERIAL_STOP_1) return false; + + // Enable the device + esci_cr12 |= FREESCALE_ESCI_CR12_TE | FREESCALE_ESCI_CR12_RE; + + if(init){ // Enable the receiver interrupt + esci_cr12 |= FREESCALE_ESCI_CR12_RIE; + }else{ // Restore the old interrupt state + HAL_READ_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12_old); + esci_cr12 |= (esci_cr12_old & FREESCALE_ESCI_CR12_RIE); + } + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12); + + if(new_config != &chan->config) + chan->config = *new_config; + + return true; +} + +//-------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. +//-------------------------------------------------------------- +static bool +esci_serial_init(struct cyg_devtab_entry * tab) +{ + serial_channel * chan = (serial_channel *)tab->priv; + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + if(chan->out_cbuf.len != 0){ + cyg_drv_interrupt_create(esci_chan->interrupt_num, + esci_chan->interrupt_priority, + // Data item passed to interrupt handler + (cyg_addrword_t)chan, + esci_serial_ISR, + esci_serial_DSR, + &esci_chan->interrupt_handle, + &esci_chan->interrupt_obj); + + cyg_drv_interrupt_attach(esci_chan->interrupt_handle); + cyg_drv_interrupt_unmask(esci_chan->interrupt_num); + } + return esci_serial_config_port(chan, &chan->config, true); +} + +//---------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) +//---------------------------------------------------------------------- +static Cyg_ErrNo +esci_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, const char * name) +{ + serial_channel * chan = (serial_channel *)(*tab)->priv; + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + return ENOERR; +} + +//----------------------------------------------------------------- +// Send a character to Tx +//----------------------------------------------------------------- +static bool +esci_serial_putc(serial_channel * chan, unsigned char ch_out) +{ + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + cyg_addrword_t esci_base = esci_chan->esci_base; + cyg_uint16 esci_sr; + + HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + if(esci_sr & FREESCALE_ESCI_SR_TDRE){ + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_TDRE); + HAL_WRITE_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_out); + return true; + }else + return false; +} + +//--------------------------------------------------------------------- +// Fetch a character Rx (for polled operation only) +//--------------------------------------------------------------------- +static unsigned char +esci_serial_getc(serial_channel * chan) +{ + cyg_uint8 ch_in; + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + cyg_addrword_t esci_base = esci_chan->esci_base; + + cyg_uint16 esci_sr; + + do{ + HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + }while(esci_sr & FREESCALE_ESCI_SR_RDRF); + + HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in); + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF); + + return ch_in; +} + +//--------------------------------------------------- +// Set up the device characteristics; baud rate, etc. +//--------------------------------------------------- +static bool +esci_serial_set_config(serial_channel * chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 * len) +{ + switch(key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO:{ + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if(*len < sizeof(cyg_serial_info_t)) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if(true != esci_serial_config_port(chan, config, false)) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------- +// Enable the transmitter on the device +//------------------------------------- +static void esci_serial_start_xmit(serial_channel * chan) +{ + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + cyg_addrword_t esci_base = esci_chan->esci_base; + cyg_uint16 esci_cr12; + + HAL_READ_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12); + esci_cr12 |= FREESCALE_ESCI_CR12_TIE; + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12); +} + +//-------------------------------------- +// Disable the transmitter on the device +//-------------------------------------- +static void esci_serial_stop_xmit(serial_channel * chan) +{ + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + + cyg_addrword_t esci_base = esci_chan->esci_base; + cyg_uint16 esci_cr12; + + HAL_READ_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12); + esci_cr12 &= ~FREESCALE_ESCI_CR12_TIE; + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12); +} + +//----------------------------------------- +// The low level interrupt handler +//----------------------------------------- +static +cyg_uint32 esci_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel * chan = (serial_channel *)data; + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(esci_chan->interrupt_num); + cyg_drv_interrupt_acknowledge(esci_chan->interrupt_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + + +//------------------------------------------ +// The high level interrupt handler +//------------------------------------------ + +#define FREESCALE_ESCI_SR_ERRORS (FREESCALE_ESCI_SR_OR | \ + FREESCALE_ESCI_SR_NF | \ + FREESCALE_ESCI_SR_FE | \ + FREESCALE_ESCI_SR_PF) + +static void +esci_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel * chan = (serial_channel *)data; + esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv; + cyg_addrword_t esci_base = esci_chan->esci_base; + cyg_uint16 esci_sr; + cyg_uint8 esci_dr; + + HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + if(esci_sr & FREESCALE_ESCI_SR_RDRF){ // Receiver full + HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), esci_dr); + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF); + if(esci_sr &= (cyg_uint16)FREESCALE_ESCI_SR_ERRORS){ + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + }else{ + (chan->callbacks->rcv_char)(chan, (cyg_uint8)esci_dr); + } + }else if(esci_sr & FREESCALE_ESCI_SR_TDRE){ //Transmitter empty + (chan->callbacks->xmt_char)(chan); + } + + cyg_drv_interrupt_unmask(esci_chan->interrupt_num); +} + +#endif // CYGPKG_IO_SERIAL_FREESCALE_ESCI_[ABCD] +// EOF ser_esci.c diff --git a/ecos/packages/devs/serial/freescale/esci/hdr/current/ChangeLog b/ecos/packages/devs/serial/freescale/esci/hdr/current/ChangeLog new file mode 100644 index 0000000..e4e3253 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/esci/hdr/current/ChangeLog @@ -0,0 +1,47 @@ +2007-01-10 Ilija Koco <ilijak@siva.com.mk> + + * ser_freescale_esci_h.cdl: moved in a newly created directory for + CYGPKG_IO_SERIAL_FREESCALE_ESCI_H due ecosadmin.tcl issue + reported by John Dallaway + + +2006-08-31 Ilija Koco <ilijak@siva.com.mk> + + * ser_freescale_esci.cdl: driver now requires at least 1 selected + channel + +2006-08-08 Ilija Koco <ilijak@siva.com.mk> + + * ser_esci.h : platform dependent clock related macros + removed and placed in platform/var header + +2006-05-24 Ilija Koco <ilijak@siva.com.mk> + + * cdl/ser_freescale_esci.cdl: + * include/ser_esci.h: + * src/ser_esci.c + New package + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/freescale/esci/hdr/current/cdl/ser_freescale_esci_h.cdl b/ecos/packages/devs/serial/freescale/esci/hdr/current/cdl/ser_freescale_esci_h.cdl new file mode 100644 index 0000000..18b758c --- /dev/null +++ b/ecos/packages/devs/serial/freescale/esci/hdr/current/cdl/ser_freescale_esci_h.cdl @@ -0,0 +1,68 @@ +# ==================================================================== +# +# ser_freescale_esci_h.cdl +# +# eCos serial Freescale/esci configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Koco <ilijak@siva.com.mk> +# Original data: +# Contributors: +# Date: 2006-05-30 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_FREESCALE_ESCI_H { + display "eSCI header" + + include_dir cyg/devs + description " + This option provides header for Freescale eSCI - Enhanced + Serial Communication Interface. eSCI is on-chip serial + controller found on some Freescale micro controllers such as: + MAC7100 familly, etc. " + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_freescale_esci.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } +} + +# EOF ser_freescale_esci_h.cdl diff --git a/ecos/packages/devs/serial/freescale/esci/hdr/current/include/ser_esci.h b/ecos/packages/devs/serial/freescale/esci/hdr/current/include/ser_esci.h new file mode 100644 index 0000000..e08afb1 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/esci/hdr/current/include/ser_esci.h @@ -0,0 +1,162 @@ +#ifndef CYGONCE_DEVS_SERIAL_FREESCALE_ESCI_H +#define CYGONCE_DEVS_SERIAL_FREESCALE_ESCI_H +//========================================================================== +// +// ser_esci.h +// +// Freescale eSCI Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-04-20 +// Purpose: eSCI Serial I/O definitions. +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +// Note: Following macros are platform dependent +// and have to be defined in var_io.h or plf_io.h +// Macros referenced by serial driver: +// CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE +// CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE +// CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE +// CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE +// CYGNUM_DEV_SER_FREESCALE_ESCI_SYSTEM_CLOCK +// FREESCALE_ESCI_BAUD(baud_rate) + +// Macros not referenced by serial driver +// but by interrupt controller +// CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR +// CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR +// CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR +// CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR +// MAC7100_ESCI_A_IV +// MAC7100_ESCI_B_IV +// MAC7100_ESCI_C_IV +// MAC7100_ESCI_D_IV +// + +#define FREESCALE_ESCI_A_BASE (CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE) +#define FREESCALE_ESCI_B_BASE (CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE) +#define FREESCALE_ESCI_C_BASE (CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE) +#define FREESCALE_ESCI_D_BASE (CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE) + +#define FREESCALE_ESCI_A_I 0 +#define FREESCALE_ESCI_B_I 1 +#define FREESCALE_ESCI_C_I 2 +#define FREESCALE_ESCI_D_I 3 + +#define FREESCALE_ESCI_BD(esci_base) \ + (esci_base + FREESCALE_ESCI_BD_OFFSET) //short +#define FREESCALE_ESCI_CR12(esci_base) \ + (esci_base + FREESCALE_ESCI_CR12_OFFSET) //short +#define FREESCALE_ESCI_CR34(esci_base) \ + (esci_base + FREESCALE_ESCI_CR34_OFFSET) //short +#define FREESCALE_ESCI_CR1(esci_base) \ + (esci_base + FREESCALE_ESCI_CR1_OFFSET) //char +#define FREESCALE_ESCI_CR2(esci_base) \ + (esci_base + FREESCALE_ESCI_CR2_OFFSET) //char +#define FREESCALE_ESCI_CR3(esci_base) \ + (esci_base + FREESCALE_ESCI_CR3_OFFSET) //char +#define FREESCALE_ESCI_CR4(esci_base) \ + (esci_base + FREESCALE_ESCI_CR4_OFFSET) //short +#define FREESCALE_ESCI_LINCTRL(esci_base) \ + (esci_base + FREESCALE_ESCI_LINCTRL_OFFSET) //short +#define FREESCALE_ESCI_LINCRCP(esci_base) \ + (esci_base + FREESCALE_ESCI_LINCRCP_OFFSET) //short +#define FREESCALE_ESCI_SR(esci_base) \ + (esci_base + FREESCALE_ESCI_SR_OFFSET) //short +#define FREESCALE_ESCI_DRL(esci_base) \ + (esci_base + FREESCALE_ESCI_DRL_OFFSET) //char + +#define FREESCALE_ESCI_BD_OFFSET (0x0000) +#define FREESCALE_ESCI_CR12_OFFSET (0x0002) +#define FREESCALE_ESCI_CR34_OFFSET (0x0002) +#define FREESCALE_ESCI_CR1_OFFSET (0x0002) +#define FREESCALE_ESCI_CR2_OFFSET (0x0003) +#define FREESCALE_ESCI_CR3_OFFSET (0x0004) +#define FREESCALE_ESCI_CR4_OFFSET (0x0005) +#define FREESCALE_ESCI_DRL_OFFSET (0x0007) +#define FREESCALE_ESCI_SR_OFFSET (0x0008) +#define FREESCALE_ESCI_LINSTAT_OFFSET (0x000A) +#define FREESCALE_ESCI_LINCTRL_OFFSET (0x000C) +#define FREESCALE_ESCI_LINRX_OFFSET (0x0010) +#define FREESCALE_ESCI_LINTX_OFFSET (0x0014) +#define FREESCALE_ESCI_LINCRCP_OFFSET (0x0018) + +#define FREESCALE_ESCI_CR12_LOOPS (0x8000) +#define FREESCALE_ESCI_CR12_SCISDOZ (0x4000) +#define FREESCALE_ESCI_CR12_RSRC (0x2000) +#define FREESCALE_ESCI_CR12_M (0x1000) +#define FREESCALE_ESCI_CR12_WAKE (0x0800) +#define FREESCALE_ESCI_CR12_ILT (0x0400) +#define FREESCALE_ESCI_CR12_PE (0x0200) +#define FREESCALE_ESCI_CR12_PT (0x0100) +#define FREESCALE_ESCI_CR12_TIE (0x0080) +#define FREESCALE_ESCI_CR12_TCIE (0x0040) +#define FREESCALE_ESCI_CR12_RIE (0x0020) +#define FREESCALE_ESCI_CR12_ILIE (0x0010) +#define FREESCALE_ESCI_CR12_TE (0x0008) +#define FREESCALE_ESCI_CR12_RE (0x0004) +#define FREESCALE_ESCI_CR12_RWU (0x0002) +#define FREESCALE_ESCI_CR12_SBK (0x0001) + +#define FREESCALE_ESCI_CR3_MDIS (0x80) +#define FREESCALE_ESCI_CR3_FBR (0x40) +#define FREESCALE_ESCI_CR3_BSTP (0x20) +#define FREESCALE_ESCI_CR3_IEBERR (0x10) +#define FREESCALE_ESCI_CR3_RXDMA (0x08) +#define FREESCALE_ESCI_CR3_TXDMA (0x04) +#define FREESCALE_ESCI_CR3_BRK13 (0x02) +#define FREESCALE_ESCI_CR3_TXDIR (0x01) + +#define FREESCALE_ESCI_SR_TDRE (0x8000) +#define FREESCALE_ESCI_SR_TC (0x4000) +#define FREESCALE_ESCI_SR_RDRF (0x2000) +#define FREESCALE_ESCI_SR_IDLE (0x1000) +#define FREESCALE_ESCI_SR_OR (0x0800) +#define FREESCALE_ESCI_SR_NF (0x0400) +#define FREESCALE_ESCI_SR_FE (0x0200) +#define FREESCALE_ESCI_SR_PF (0x0100) +#define FREESCALE_ESCI_SR_BERR (0x0010) +#define FREESCALE_ESCI_SR_RAF (0x0001) + +#endif // CYGONCE_DEVS_SERIAL_FREESCALE_ESCI_H +// EOF ser_esci.h diff --git a/ecos/packages/devs/serial/freescale/uart/drv/current/ChangeLog b/ecos/packages/devs/serial/freescale/uart/drv/current/ChangeLog new file mode 100644 index 0000000..3b7ea0c --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/drv/current/ChangeLog @@ -0,0 +1,43 @@ +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * include/ser_freescale_uart_chan.inl. include/ser_freescale_uart.c: + Add clock gating enable. [ Bugzilla 1001814 ] + +2012-02-07 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_freescale_uart.cdl: + Add consolidated Interrupt Priority Scheme [Bugzilla 1001450] + +2011-03-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_freescale_uart.cdl: + * src/ser_freescale_uart.c: + * include/ser_freescale_uart_chan.inl: + * include/ser_freescale_uart_tty_add.inl: + * include/ser_freescale_uart_termiostty_add.inl: + + New package -- Freescale UART driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl b/ecos/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl new file mode 100644 index 0000000..bc29622 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl @@ -0,0 +1,269 @@ +# ==================================================================== +# +# ser_freescale_uart.cdl +# +# eCos serial Freescale UART configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Kocho <ilijak@siva.com.mk> +# Original data: +# Contributors: +# Date: 2011-02-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_FREESCALE_UART { + display "Freescale UART device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + requires CYGPKG_IO_SERIAL_FREESCALE_UART_HDR + requires CYGPKG_ERROR + + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Freescale UART, an on-chip serial controller found on some + freescale microcontrollers such as Kinetis, etc." + + compile -library=libextras.a ser_freescale_uart.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_freescale_uart.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + # Support up to 6 on-chip UART modules. The number may vary between + # processor variants so it is easy to update this here + for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { + + cdl_interface CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] { + display "Platform provides UART [set ::channel]" + flavor bool + description " + This interface will be implemented if the specific + controller being used has on-chip UART [set ::channel], and if + that UART is accessible on the target hardware." + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_UART[set ::channel] { + display "Freescale UART port [set ::channel] driver" + flavor bool + active_if CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] + default_value CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] + implements CYGINT_IO_SERIAL_TTY_TTY[set ::channel] + description " + This option includes the serial device driver for Freescale + UART port [set ::channel]." + + cdl_option CYGDAT_IO_SERIAL_FREESCALE_UART[set ::channel]_NAME { + display "Device name for Freescale UART port [set ::channel]" + flavor data + default_value [ format {"\"/dev/ser%d\""} $::channel ] + description " + This option specifies the device name for + Freescale UART port [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_BAUD { + display "Baud rate for the Freescale UART port [set ::channel] driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate for the + UART port [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_BUFSIZE { + display "Buffer size for the Freescale UART port [set ::channel] driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for Freescale UART port [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_INT_PRIORITY { + display "Freescale UART port [set ::channel] interrupt priority" + flavor data + default_value CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_INT_PRIORITY_SP + description " + This option selects the interupt priority for the + UART [set ::channel] interrupts." + } + } + } + + cdl_component CYGDAT_IO_SERIAL_TTY_ADD_INL { + display "Freescale TTY devices beyond #3" + parent CYGPKG_IO_SERIAL + active_if CYGPKG_IO_SERIAL_TTY + flavor data + calculated { "<cyg/io/ser_freescale_uart_tty_add.inl>" } + + + cdl_component CYGPKG_IO_SERIAL_TTY_TTY4 { + display "TTY mode channel #4" + flavor bool + parent CYGPKG_IO_SERIAL_TTY + active_if CYGPKG_IO_SERIAL_TTY + default_value 0 + description " + This option causes '/dev/tty4', which is provided by Freescale + UART, to be included in the standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TTY_TTY4_DEV { + display "TTY mode channel #4 device" + flavor data + default_value { "\"/dev/ser4\"" } + description " + This option selects the physical device to use for + '/dev/tty4'." + } + } + + cdl_component CYGPKG_IO_SERIAL_TTY_TTY5 { + display "TTY mode channel #5" + flavor bool + parent CYGPKG_IO_SERIAL_TTY + active_if CYGPKG_IO_SERIAL_TTY + default_value 0 + description " + This option causes '/dev/tty5', which is provided by Freescale + UART, to be included in the standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TTY_TTY5_DEV { + display "TTY mode channel #5 device" + flavor data + default_value { "\"/dev/ser5\"" } + description " + This option selects the physical device to use for + '/dev/tty5'." + } + } + } + + cdl_component CYGDAT_IO_SERIAL_TERMIOS_ADD_INL { + display "Freescale TERMIOS devices beyond #3" + parent CYGPKG_IO_SERIAL + active_if CYGPKG_IO_SERIAL_TERMIOS + flavor data + calculated { "<cyg/io/ser_freescale_uart_termiostty_add.inl>" } + + cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS4 { + display "Termios TTY channel #4" + flavor bool + default_value 0 + implements CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY + parent CYGPKG_IO_SERIAL_TERMIOS + active_if CYGPKG_IO_SERIAL_TERMIOS + description " + This option causes '/dev/termios4' to be included in the + standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS4_DEV { + display "Termios TTY channel #4 device" + flavor data + default_value {"\"/dev/ser4\""} + description " + This option selects the physical device to use for + '/dev/termios4'." + } + } + + cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS5 { + display "Termios TTY channel #5" + flavor bool + default_value 0 + implements CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY + parent CYGPKG_IO_SERIAL_TERMIOS + active_if CYGPKG_IO_SERIAL_TERMIOS + description " + This option causes '/dev/termios5' to be included in the + standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS5_DEV { + display "Termios TTY channel #5 device" + flavor data + default_value {"\"/dev/ser5\""} + description " + This option selects the physical device to use for + '/dev/termios5'." + } + } + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_UART_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_IO_SERIAL_FREESCALE_UART_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_FREESCALE_UART_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_freescale_uart.cdl diff --git a/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl b/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl new file mode 100644 index 0000000..6593ef2 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl @@ -0,0 +1,378 @@ +//========================================================================== +// +// ser_freescale_uart.inl +// +// Freescale UART Serial channel definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-10 +// Purpose: Freescale UART Serial I/O module (interrupt driven version) +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART0 +static const uart_pins_t uart0_pins = { + rx : CYGHWR_IO_FREESCALE_UART0_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART0_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART0_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART0_PIN_CTS +}; +static uart_serial_info uart_serial_info0 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY, + clock : CYGHWR_IO_FREESCALE_UART0_CLOCK, + pins_p : &uart0_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE]; +static unsigned char + uart_serial_in_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS( + uart_serial_channel0, + uart_serial_funs, + uart_serial_info0, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf0[0], + sizeof(uart_serial_out_buf0), + &uart_serial_in_buf0[0], + sizeof(uart_serial_in_buf0)); +#else +static +SERIAL_CHANNEL(uart_serial_channel0, + uart_serial_funs, + uart_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io0, + CYGDAT_IO_SERIAL_FREESCALE_UART0_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel0); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART0 + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART1 +static const uart_pins_t uart1_pins = { + rx : CYGHWR_IO_FREESCALE_UART1_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART1_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART1_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART1_PIN_CTS +}; +static uart_serial_info uart_serial_info1 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY, + clock : CYGHWR_IO_FREESCALE_UART1_CLOCK, + pins_p : &uart1_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE]; +static unsigned char + uart_serial_in_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel1, + uart_serial_funs, + uart_serial_info1, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf1[0], + sizeof(uart_serial_out_buf1), + &uart_serial_in_buf1[0], + sizeof(uart_serial_in_buf1)); +#else +static +SERIAL_CHANNEL(uart_serial_channel1, + uart_serial_funs, + uart_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io1, + CYGDAT_IO_SERIAL_FREESCALE_UART1_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel1); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART1 + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART2 +static const uart_pins_t uart2_pins = { + rx : CYGHWR_IO_FREESCALE_UART2_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART2_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART2_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART2_PIN_CTS +}; +static uart_serial_info uart_serial_info2 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY, + clock : CYGHWR_IO_FREESCALE_UART2_CLOCK, + pins_p : &uart2_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE]; +static unsigned char + uart_serial_in_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel2, + uart_serial_funs, + uart_serial_info2, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf2[0], + sizeof(uart_serial_out_buf2), + &uart_serial_in_buf2[0], + sizeof(uart_serial_in_buf2)); +#else +static +SERIAL_CHANNEL(uart_serial_channel2, + uart_serial_funs, + uart_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io2, + CYGDAT_IO_SERIAL_FREESCALE_UART2_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel2); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART2 + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART3 +static const uart_pins_t uart3_pins = { + rx : CYGHWR_IO_FREESCALE_UART3_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART3_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART3_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART3_PIN_CTS +}; +static uart_serial_info uart_serial_info3 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY, + clock : CYGHWR_IO_FREESCALE_UART3_CLOCK, + pins_p : &uart3_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE]; +static unsigned char + uart_serial_in_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel3, + uart_serial_funs, + uart_serial_info3, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf3[0], + sizeof(uart_serial_out_buf3), + &uart_serial_in_buf3[0], + sizeof(uart_serial_in_buf3)); +#else +static +SERIAL_CHANNEL(uart_serial_channel3, + uart_serial_funs, + uart_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io3, + CYGDAT_IO_SERIAL_FREESCALE_UART3_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel3); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART3 + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART4 +static const uart_pins_t uart4_pins = { + rx : CYGHWR_IO_FREESCALE_UART4_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART4_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART4_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART4_PIN_CTS +}; +static uart_serial_info uart_serial_info4 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY, + clock : CYGHWR_IO_FREESCALE_UART4_CLOCK, + pins_p : &uart4_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE]; +static unsigned char + uart_serial_in_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel4, + uart_serial_funs, + uart_serial_info4, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf4[0], + sizeof(uart_serial_out_buf4), + &uart_serial_in_buf4[0], + sizeof(uart_serial_in_buf4)); +#else +static +SERIAL_CHANNEL(uart_serial_channel4, + uart_serial_funs, + uart_serial_info4, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io4, + CYGDAT_IO_SERIAL_FREESCALE_UART4_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel4); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART4 + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART5 +static const uart_pins_t uart5_pins = { + rx : CYGHWR_IO_FREESCALE_UART5_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART5_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART5_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART5_PIN_CTS +}; +static uart_serial_info uart_serial_info5 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY, + clock : CYGHWR_IO_FREESCALE_UART5_CLOCK, + pins_p : &uart5_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE]; +static unsigned char + uart_serial_in_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel5, + uart_serial_funs, + uart_serial_info5, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf5[0], + sizeof(uart_serial_out_buf5), + &uart_serial_in_buf5[0], + sizeof(uart_serial_in_buf5)); +#else +static +SERIAL_CHANNEL(uart_serial_channel5, + uart_serial_funs, + uart_serial_info5, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io5, + CYGDAT_IO_SERIAL_FREESCALE_UART5_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel5); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART5 diff --git a/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl b/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl new file mode 100644 index 0000000..309c8f9 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl @@ -0,0 +1,79 @@ +#ifndef CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL +#define CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL +//============================================================================= +// +// ser_freescale_uart_termiostty_add.inl +// +// Termios definitions beyond #3. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-03-28 +// Purpose: Termios definitions beyond #3. +// Description: +// Usage: This file is included by pkgconf/io/serial.h +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS4 +static struct termios_private_info termios_private_info4; +DEVTAB_ENTRY(termios_io4, + "/dev/termios4", + CYGDAT_IO_SERIAL_TERMIOS_TERMIOS4_DEV, + &termios_devio, + termios_init, + termios_lookup, + &termios_private_info4); +#endif + +#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS5 +static struct termios_private_info termios_private_info5; +DEVTAB_ENTRY(termios_io5, + "/dev/termios5", + CYGDAT_IO_SERIAL_TERMIOS_TERMIOS5_DEV, + &termios_devio, + termios_init, + termios_lookup, + &termios_private_info5); +#endif +//----------------------------------------------------------------------------- +// end of ser_freescale_uart_termiostty_add.inl +#endif // CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL diff --git a/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl b/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl new file mode 100644 index 0000000..6587cc9 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl @@ -0,0 +1,79 @@ +#ifndef CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL +#define CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL +//============================================================================= +// +// ser_freescale_uart_tty_add.inl +// +// TTY definitions beyond #3. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-03-28 +// Purpose: TTY definitions beyond 3. +// Description: +// Usage: This file is included by pkgconf/io/serial.h +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +#ifdef CYGPKG_IO_SERIAL_TTY_TTY4 +static struct tty_private_info tty_private_info4; +DEVTAB_ENTRY(tty_io4, + "/dev/tty4", + CYGDAT_IO_SERIAL_TTY_TTY4_DEV, + &tty_devio, + tty_init, + tty_lookup, // Execute this when device is being looked up + &tty_private_info4); +#endif + +#ifdef CYGPKG_IO_SERIAL_TTY_TTY5 +static struct tty_private_info tty_private_info5; +DEVTAB_ENTRY(tty_io5, + "/dev/tty5", + CYGDAT_IO_SERIAL_TTY_TTY5_DEV, + &tty_devio, + tty_init, + tty_lookup, // Execute this when device is being looked up + &tty_private_info5); +#endif +//----------------------------------------------------------------------------- +// end of ser_freescale_uart_tty_add.inl +#endif // CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL diff --git a/ecos/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c b/ecos/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c new file mode 100644 index 0000000..6c89ae5 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c @@ -0,0 +1,397 @@ +//========================================================================== +// +// ser_freescale_uart.c +// +// Freescale UART Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-10 +// Purpose: Freescale UART Serial I/O module (interrupt driven version) +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arbiter.h> +#include <cyg/hal/hal_io.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> +#include <cyg/io/ser_freescale_uart.h> + +// Only build this driver for if Freescale UART is needed. +#ifdef CYGPKG_IO_SERIAL_FREESCALE_UART + +typedef struct uart_pins_s { + cyg_uint32 rx; + cyg_uint32 tx; + cyg_uint32 rts; + cyg_uint32 cts; +} uart_pins_t; + + +typedef struct uart_serial_info { + CYG_ADDRWORD uart_base; // Base address of the uart port + CYG_WORD interrupt_num; // NVIC interrupt vector + cyg_priority_t interrupt_priority; // NVIC interupt priority + const uart_pins_t *pins_p; // Rx, Tx, etc. + cyg_uint32 clock; // Clock gate + cyg_bool tx_active; + cyg_interrupt interrupt_obj; // Interrupt object + cyg_handle_t interrupt_handle; // Interrupt handle +} uart_serial_info; + +static bool uart_serial_init(struct cyg_devtab_entry * tab); +static bool uart_serial_putc(serial_channel * chan, unsigned char c); +static Cyg_ErrNo uart_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, + const char * name); +static unsigned char uart_serial_getc(serial_channel *chan); +static Cyg_ErrNo uart_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void uart_serial_start_xmit(serial_channel *chan); +static void uart_serial_stop_xmit(serial_channel *chan); + +// Interrupt servers +static cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(uart_serial_funs, + uart_serial_putc, + uart_serial_getc, + uart_serial_set_config, + uart_serial_start_xmit, + uart_serial_stop_xmit); + +// Available baud rates +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +#include <cyg/io/ser_freescale_uart_chan.inl> + +//---------------------------------------------------------------------------- +// Internal function to actually configure the hardware to desired +// baud rate, etc. +//---------------------------------------------------------------------------- +static bool +uart_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config, + bool init) +{ + cyg_uint32 regval; + uart_serial_info * uart_chan = (uart_serial_info *)(chan->dev_priv); + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 baud_rate = select_baud[new_config->baud]; + + if(!baud_rate) return false; // Invalid baud rate selected + + // Bring clock to the sevice + CYGHWR_IO_CLOCK_ENABLE(uart_chan->clock); + // Configure PORT pins + CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->rx); + CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->tx); + + CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_base, baud_rate); + + if(new_config->word_length != 8) + return false; + + switch(new_config->parity) { + case CYGNUM_SERIAL_PARITY_NONE: + regval = 0; + break; + case CYGNUM_SERIAL_PARITY_EVEN: + regval = CYGHWR_DEV_FREESCALE_UART_C1_PE; + break; + case CYGNUM_SERIAL_PARITY_ODD: + regval = CYGHWR_DEV_FREESCALE_UART_C1_PE | + CYGHWR_DEV_FREESCALE_UART_C1_PT; + break; + default: return false; + } + + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C1, regval); + + if(init) { // Enable the receiver interrupt + regval = CYGHWR_DEV_FREESCALE_UART_C2_RIE; + } else { // Restore the old interrupt state + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval); + } + + // Enable the device + regval |= CYGHWR_DEV_FREESCALE_UART_C2_TE | + CYGHWR_DEV_FREESCALE_UART_C2_RE; + + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval); + + uart_chan->tx_active = false; + + if(new_config != &chan->config) + chan->config = *new_config; + + return true; +} + +//-------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. +//-------------------------------------------------------------- +static bool +uart_serial_init(struct cyg_devtab_entry * tab) +{ + serial_channel * chan = (serial_channel *)tab->priv; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + if(chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(uart_chan->interrupt_num, + uart_chan->interrupt_priority, + // Data item passed to interrupt handler + (cyg_addrword_t)chan, + uart_serial_ISR, + uart_serial_DSR, + &uart_chan->interrupt_handle, + &uart_chan->interrupt_obj); + + cyg_drv_interrupt_attach(uart_chan->interrupt_handle); + cyg_drv_interrupt_unmask(uart_chan->interrupt_num); + } + return uart_serial_config_port(chan, &chan->config, true); +} + +//---------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) +//---------------------------------------------------------------------- +static Cyg_ErrNo +uart_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, const char * name) +{ + serial_channel * chan = (serial_channel *)(*tab)->priv; + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + return ENOERR; +} + +//----------------------------------------------------------------- +// Send a character to Tx +//----------------------------------------------------------------- +static bool +uart_serial_putc(serial_channel * chan, unsigned char ch_out) +{ + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 uart_sr; + + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr); + if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE) { + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_out); + return true; + } else { + return false; + } +} + + +//--------------------------------------------------------------------- +// Fetch a character Rx (for polled operation only) +//--------------------------------------------------------------------- +static unsigned char +uart_serial_getc(serial_channel * chan) +{ + cyg_uint8 ch_in; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + + cyg_uint32 uart_sr; + + do { + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr); + } while(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_RDRF); + + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + + return ch_in; +} + + +//--------------------------------------------------- +// Set up the device characteristics; baud rate, etc. +//--------------------------------------------------- +static bool +uart_serial_set_config(serial_channel * chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 * len) +{ + switch(key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if(*len < sizeof(cyg_serial_info_t)) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if(true != uart_serial_config_port(chan, config, false)) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------- +// Enable the transmitter on the device +//------------------------------------- +static void uart_serial_start_xmit(serial_channel * chan) +{ + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 uart_cr12; + + if(!uart_chan->tx_active) { + uart_chan->tx_active = true; + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + uart_cr12 |= CYGHWR_DEV_FREESCALE_UART_C2_TIE; + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + } +} + +//-------------------------------------- +// Disable the transmitter on the device +//-------------------------------------- +static void uart_serial_stop_xmit(serial_channel * chan) +{ + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 uart_cr12; + + if(uart_chan->tx_active) { + uart_chan->tx_active = false; + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + uart_cr12 &= ~CYGHWR_DEV_FREESCALE_UART_C2_TIE; + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + } +} + +//----------------------------------------- +// The low level interrupt handler +//----------------------------------------- +static +cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel * chan = (serial_channel *)data; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(uart_chan->interrupt_num); + cyg_drv_interrupt_acknowledge(uart_chan->interrupt_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + + +//------------------------------------------ +// The high level interrupt handler +//------------------------------------------ + +#define CYGHWR_DEV_FREESCALE_UART_S1_ERRORS \ + (CYGHWR_DEV_FREESCALE_UART_S1_OR | \ + CYGHWR_DEV_FREESCALE_UART_S1_NF | \ + CYGHWR_DEV_FREESCALE_UART_S1_FE | \ + CYGHWR_DEV_FREESCALE_UART_S1_PF) + +static void +uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel * chan = (serial_channel *)data; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + volatile cyg_uint32 uart_sr; + cyg_uint8 uart_dr; + + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr); + if(uart_sr & (CYGHWR_DEV_FREESCALE_UART_S1_RDRF | + CYGHWR_DEV_FREESCALE_UART_S1_ERRORS)) { + // Receiver full or errors + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, uart_dr); + if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_ERRORS) { + // Check for receive error + } else { // No errors, get the character + (chan->callbacks->rcv_char)(chan, (cyg_uint8)uart_dr); + } + } + + if(uart_chan->tx_active && (uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)){ + //Transmitter empty + (chan->callbacks->xmt_char)(chan); + } + + cyg_drv_interrupt_unmask(uart_chan->interrupt_num); +} + +#endif // CYGPKG_IO_SERIAL_FREESCALE_UART +// EOF ser_freescale_uart.c diff --git a/ecos/packages/devs/serial/freescale/uart/hdr/current/ChangeLog b/ecos/packages/devs/serial/freescale/uart/hdr/current/ChangeLog new file mode 100644 index 0000000..0a2d232 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/hdr/current/ChangeLog @@ -0,0 +1,34 @@ +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * include/ser_freescale_uart.h: Add clock gating comment. + [ Bugzilla 1001814 ] + +2011-03-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_freescale_uart_hdr.cdl: + * include/ser_freescale_uart.h: + New package -- Freescale UART header. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl b/ecos/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl new file mode 100644 index 0000000..e2bac47 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl @@ -0,0 +1,68 @@ +# ==================================================================== +# +# ser_freescale_uart_h.cdl +# +# eCos serial Freescale UART configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Kocho <ilijak@siva.com.mk> +# Original data: +# Contributors: +# Date: 2011-02-05 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_FREESCALE_UART_HDR { + display "Freescale UART header" + + include_dir cyg/io + description " + This pacckage provides header file with definitions and macros for + Freescale UART. Same header is used by Freescale UART serial driver + as well as by HAL. Freescale UART is on-chip serial controller found + on some Freescale micro-controllers such as Kinetis familly, etc." + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HDR_HEADER <pkgconf/io_serial_freescale_uart_hdr.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } +} + +# EOF ser_freescale_uart_h.cdl diff --git a/ecos/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h b/ecos/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h new file mode 100644 index 0000000..4bfc837 --- /dev/null +++ b/ecos/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h @@ -0,0 +1,144 @@ +#ifndef CYGONCE_DEVS_SERIAL_FREESCALE_UART_H +#define CYGONCE_DEVS_SERIAL_FREESCALE_UART_H +//========================================================================== +// +// ser_freescale_uart.h +// +// Freescale UART I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-05 +// Purpose: Freescale UART I/O definitions. +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +enum { + CYGHWR_DEV_FREESCALE_UART_BDH, // UART Baud Rate Register High + CYGHWR_DEV_FREESCALE_UART_BDL, // UART Baud Rate Register Low + CYGHWR_DEV_FREESCALE_UART_C1, // UART Control Register 1 + CYGHWR_DEV_FREESCALE_UART_C2, // UART Control Register 2 + CYGHWR_DEV_FREESCALE_UART_S1, // UART Status Register 1 + CYGHWR_DEV_FREESCALE_UART_S2, // UART Status Register 2 + CYGHWR_DEV_FREESCALE_UART_C3, // UART Control Register 3 + CYGHWR_DEV_FREESCALE_UART_D, // UART Data Register + CYGHWR_DEV_FREESCALE_UART_MA1, // UART Match Address Registers 1 + CYGHWR_DEV_FREESCALE_UART_MA2, // UART Match Address Registers 2 + CYGHWR_DEV_FREESCALE_UART_C4, // UART Control Register 4 + CYGHWR_DEV_FREESCALE_UART_C5, // UART Control Register 5 + CYGHWR_DEV_FREESCALE_UART_ED, // UART Extended Data Register + CYGHWR_DEV_FREESCALE_UART_MODEM, // UART Modem Register + CYGHWR_DEV_FREESCALE_UART_IR, // UART Infrared Register + CYGHWR_DEV_FREESCALE_UART_Res_0, + CYGHWR_DEV_FREESCALE_UART_PFIFO, // UART FIFO Parameters + CYGHWR_DEV_FREESCALE_UART_CFIFO, // UART FIFO Control Register + CYGHWR_DEV_FREESCALE_UART_SFIFO, // UART FIFO Status Register + CYGHWR_DEV_FREESCALE_UART_TWFIFO, // UART FIFO Transmit Watermark + CYGHWR_DEV_FREESCALE_UART_TCFIFO, // UART FIFO Transmit Count + CYGHWR_DEV_FREESCALE_UART_RWFIFO, // UART FIFO Receive Watermark + CYGHWR_DEV_FREESCALE_UART_RCFIFO, // UART FIFO Receive Count + CYGHWR_DEV_FREESCALE_UART_Res_1, + CYGHWR_DEV_FREESCALE_UART_C7816, // UART 7816 Control Register + CYGHWR_DEV_FREESCALE_UART_IE7816, // UART 7816 Interrupt Enable Register + CYGHWR_DEV_FREESCALE_UART_IS7816, // UART 7816 Interrupt Status Register + CYGHWR_DEV_FREESCALE_UART_WP7816_T0T1, // UART 7816 Wait Parameter Register + CYGHWR_DEV_FREESCALE_UART_WN7816, // UART 7816 Wait N Register + CYGHWR_DEV_FREESCALE_UART_WF7816, // UART 7816 Wait FD Register + CYGHWR_DEV_FREESCALE_UART_ET7816, // UART 7816 Error Threshold Register + CYGHWR_DEV_FREESCALE_UART_TL7816 // UART 7816 Transmit Length Register +}; + +// CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) should be provided by HAL. +// CYGHWR_IO_FREESCALE_UART_PIN(__pin) should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_CLOCK should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_RX should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_TX should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_RTS should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_CTS should be provided by HAL. + + +#define CYGHWR_DEV_FREESCALE_UART_C1_LOOPS (0x80) +#define CYGHWR_DEV_FREESCALE_UART_C1_UARTSWAI (0x40) +#define CYGHWR_DEV_FREESCALE_UART_C1_RSRC (0x20) +#define CYGHWR_DEV_FREESCALE_UART_C1_M (0x10) +#define CYGHWR_DEV_FREESCALE_UART_C1_WAKE (0x08) +#define CYGHWR_DEV_FREESCALE_UART_C1_ILT (0x04) +#define CYGHWR_DEV_FREESCALE_UART_C1_PE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_C1_PT (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_C2_TIE (0x80) +#define CYGHWR_DEV_FREESCALE_UART_C2_TCIE (0x40) +#define CYGHWR_DEV_FREESCALE_UART_C2_RIE (0x20) +#define CYGHWR_DEV_FREESCALE_UART_C2_ILIE (0x10) +#define CYGHWR_DEV_FREESCALE_UART_C2_TE (0x08) +#define CYGHWR_DEV_FREESCALE_UART_C2_RE (0x04) +#define CYGHWR_DEV_FREESCALE_UART_C2_RWU (0x02) +#define CYGHWR_DEV_FREESCALE_UART_C2_SBK (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_S1_TDRE (0x80) +#define CYGHWR_DEV_FREESCALE_UART_S1_TC (0x40) +#define CYGHWR_DEV_FREESCALE_UART_S1_RDRF (0x20) +#define CYGHWR_DEV_FREESCALE_UART_S1_IDLE (0x10) +#define CYGHWR_DEV_FREESCALE_UART_S1_OR (0x08) +#define CYGHWR_DEV_FREESCALE_UART_S1_NF (0x04) +#define CYGHWR_DEV_FREESCALE_UART_S1_FE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_S1_PF (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_S2_LBKDIF (0x80) +#define CYGHWR_DEV_FREESCALE_UART_S2_RXEDGIF (0x40) +#define CYGHWR_DEV_FREESCALE_UART_S2_MSBF (0x20) +#define CYGHWR_DEV_FREESCALE_UART_S2_RXINV (0x10) +#define CYGHWR_DEV_FREESCALE_UART_S2_RWUID (0x08) +#define CYGHWR_DEV_FREESCALE_UART_S2_BRK13 (0x04) +#define CYGHWR_DEV_FREESCALE_UART_S2_LBKDE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_S2_RAF (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_C3_R8 (0x80) +#define CYGHWR_DEV_FREESCALE_UART_C3_T8 (0x40) +#define CYGHWR_DEV_FREESCALE_UART_C3_TXDIR (0x20) +#define CYGHWR_DEV_FREESCALE_UART_C3_TXINV (0x10) +#define CYGHWR_DEV_FREESCALE_UART_C3_ORIE (0x08) +#define CYGHWR_DEV_FREESCALE_UART_C3_NEIE (0x04) +#define CYGHWR_DEV_FREESCALE_UART_C3_FEIE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_C3_PEIE (0x01) + + +#endif // CYGONCE_DEVS_SERIAL_FREESCALE_UART_H diff --git a/ecos/packages/devs/serial/generic/16x5x/current/ChangeLog b/ecos/packages/devs/serial/generic/16x5x/current/ChangeLog new file mode 100644 index 0000000..34e95a1 --- /dev/null +++ b/ecos/packages/devs/serial/generic/16x5x/current/ChangeLog @@ -0,0 +1,349 @@ +2012-02-07 Bernard Fouché <bernard.fouche@kuantic.com> + + * src/ser_16x5x.c (serial_config_port): Clear potential Overrun Error + condition at init by always reading RHR. + +2009-02-17 Rene Schipp von Branitz Nielsen <rbn@vitesse.com> + + * src/ser_16x5x.c: + Allow platform code to override the default implementation for + writing the LCR register and reading the ISR register by using + the SER_16X5X_WRITE_LCR() and SER_16X5X_READ_ISR() macros. + +2008-07-08 Uwe Kindler <uwe_kindler@web.de> + + * cdl/ser_generic_16x5x.cdl + (CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO): New interface + for devices that support per channel interrupt priorities. + + * src/ser_16x5x.c Added int_prio to pc_serial_info type. + serial_config_port(): uses macro + CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR() to get the baud + devisor from platform if device suppports per channel baudrate + clocks, pc_serial_init(): Use interrupt priority from int_prio + data field if device implements + CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + +2007-06-22 Alexander Aganichev <aaganichev@gmail.com> + + * cdl/ser_generic_16x5x.cdl + (CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME): New option. + + * src/ser_16x5x.c (pc_serial_start_xmit): Allow platform to define + CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME if enabling THRE + interrupt does not generate interrupt unless bytes are posted to the + FIFO. + +2006-11-27 Jonathan Larmour <jifl@eCosCentric.com> + + * src/ser_16x5x.c (serial_config_port): Add + CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK + in case devices need extra initialization. + +2006-02-07 Daniel Néri <daniel.neri@sigicom.se> + + * cdl/ser_generic_16x5x.cdl + (CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE): New option. + + * src/ser_16x5x.c (serial_config_port, pc_serial_putc, + pc_serial_DSR): At TX interrupt, write up to + CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE bytes to the transmit + FIFO. This makes better use of the FIFO, since the LSR_THE flag + resets when the FIFO is non-empty (not when it's full, as this + code previously assumed). + +2003-09-19 Gary Thomas <gary@mlbassoc.com> + + * src/ser_16x5x.c (pc_serial_init): + Allow platform to define CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR + if the baud rate clock (values) cannot be known at compile time. In + this case, the baud rate generator values are provided by platform + specific code, computed when the device is first initialized. + +2003-07-16 Jonathan Larmour <jifl@eCosCentric.com> + + * src/ser_16x5x.c (CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY): Add + so that the calling hardware-specific drivers can override priorities. + Clarify flow control comment. + +2003-03-18 Gary Thomas <gary@mlbassoc.com> + + * src/ser_16x5x.c (pc_serial_set_config): + Flag for CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE is 32 bits. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_generic_16x5x.cdl: Remove irrelevant doc link. + +2001-06-19 Jesper Skov <jskov@redhat.com> + + * cdl/ser_generic_16x5x.cdl: Only define + CYGDAT_IO_SERIAL_DEVICE_HEADER when necessary. + +2001-06-18 Jonathan Larmour <jlarmour@redhat.com> + + * src/ser_16x5x.c (pc_serial_set_config): Fix length check typo + +2001-06-18 Jesper Skov <jskov@masala.cambridge.redhat.com> + + * src/ser_16x5x.c (LCR_PE): Set correct bits (from Boris V. Guzhov) + +2001-06-08 Jonathan Larmour <jlarmour@redhat.com> + + * src/ser_16x5x.c: Support FIFOs better by detecting what we've got, + and only acting if we have a _working_ FIFO. + Assert on unhandled serial interrupt type. + +2001-03-13 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_generic_16x5x.cdl: Rename + CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_OPTIONS to + CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO and make it a boolean. Clarify + descriptions a little. + + * src/ser_16x5x.c (serial_config_port): Only program FCR if FIFO + support requested. + Don't bother with intermediate _fifo_thresh. + Detabify. + +2001-03-13 Jesper Skov <jskov@redhat.com> + + * cdl/ser_generic_16x5x.cdl: Removed the default value. + +2001-03-09 Julian Smart <julians@redhat.com> + Removed default value for flavor none in + CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_OPTIONS since it + causes an assert in libcdl + +2001-03-05 Jesper Skov <jskov@redhat.com> + 2001-02-15 Dave Airlie <airlied@parthus.com> + + * src/ser_16x5x.c (serial_config_port): Add support for setting + a FIFO RX Threshold via CDL + + * cdl/ser_generic_16x5x.cdl: Add support for setting a FIFO + RX threshold via CDL + +2001-01-24 Dave Airlie <airlied@parthus.com> + + * src/ser_16x5x.c (pc_serial_DSR): Allow RX timeouts to be interpreted + as RXs. + +2000-12-19 Dave Airlie <airlied@parthus.com> + + * src/ser_16x5x.c: Add defines for FIFO control register + (serial_config_port): Use these defines. + +2000-12-07 Jesper Skov <jskov@redhat.com> + + * src/ser_16x5x.c (ISR_LS): Corrected value. Spotted by Dave Airlie. + +2000-09-18 Jesper Skov <jskov@redhat.com> + + * src/ser_16x5x.c: Allow clients to specify register + stepping. Rename a type. Fix compile error. + +2000-09-14 Jesper Skov <jskov@redhat.com> + + * src/ser_16x5x.c: Moved ARM/PID driver to provide generic 16x5x + driver. Rewritten to use HAL IO macros. Still needs some polish + and configury to properly support all the various target + controllers that may only have a partial set of the features. + * cdl/ser_generic_16x5x.cdl: Same. + + * Removed non-PID related ChangeLog entries. + +---------------------------------------------------------------------------- +2000-08-24 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/pid_serial_with_ints.c (pid_serial_DSR): Remove accidental + OVERRUNERR check duplication + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/pid_serial_with_ints.c: Throughout, add support for line status + and modem status callbacks, hardware RTS/CTS and DSR/DTR flow control + (pid_serial_set_config): Now use keys to make + more flexible. + + * src/pid_serial.h: Add more line status, interrupt status and modem + status register definitions + + * cdl/ser_arm_pid.cdl: Implements flow control and line status + interfaces + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-06-09 Jesper Skov <jskov@redhat.com> + + * src/pid_serial_with_ints.c: + * src/pid_serial.h: + Cleaned up defines and made DSR handle all received characters. + (Dave Airlie (airlied at parthus dot com)) + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_arm_pid.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/arm/pid_serial.h: Added BE support. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv + interrupts properly (can't ignore them even with TO bit set). + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + Check for receive interrupt before reading. + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + Update CDL to follow naming conventions. + + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change + so that the physical port is not modified unless the provided + configuration is valid. + + * src/arm/pid_serial_with_ints.c: + Add configury for baud rate and buffer size. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo + in comment. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: + Update device names to match CDL. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Add 'CYGDBG_IO_INIT' for control + of init messages. + + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/generic/16x5x/current/cdl/ser_generic_16x5x.cdl b/ecos/packages/devs/serial/generic/16x5x/current/cdl/ser_generic_16x5x.cdl new file mode 100644 index 0000000..2133603 --- /dev/null +++ b/ecos/packages/devs/serial/generic/16x5x/current/cdl/ser_generic_16x5x.cdl @@ -0,0 +1,160 @@ +# ==================================================================== +# +# ser_generic_16x5x.cdl +# +# eCos serial 16x5x configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-07 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_GENERIC_16X5X { + display "16x5x generic serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + + active_if CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + 16x5x compatiple controllers." + + compile -library=libextras.a ser_16x5x.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_generic_16x5x.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG"; + } + + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO { + display "Per channel interrupt priority support" + flavor bool + description " + A platform should implement this interface if it supports + per channel interrupt priorities. If a platform implements + this interface it needs to provide an interrupt priority + value for each UART channel it supports." + } + + cdl_option CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME { + display "Transmission require priming" + flavor bool + default_value 0 + description " + This option should be switched on when enabling THRE interrupt + does not generate interrupt unless bytes are posted to the FIFO." + } + + cdl_component CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO { + display "16x5x FIFO support" + flavor bool + default_value 1 + description " + Options to configure the FIFO on a 16550 (or above) variant." + + cdl_option CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD { + display "Threshold for RX interrupt on 16550 FIFO" + flavor data + legal_values { 14 8 4 1 } + default_value 1 + description " + This options configures the threshold value at which + the RX interrupt occurs when a FIFO is used. (16550 and + above only), this may be after 1, 4, 8 or 14 characters." + } + + cdl_option CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE { + display "16x5x TX FIFO size" + flavor data + default_value 16 + description " + Configures the maximum number of bytes written to the + 16x5x UART transmit FIFO when the TX interrupt occurs." + } + } + + cdl_component CYGPKG_IO_SERIAL_GENERIC_16X5X_OPTIONS { + display "Serial device driver build options" + flavor none + + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_GENERIC_16X5X_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_GENERIC_16X5X_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_generic_16x5x.cdl diff --git a/ecos/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c b/ecos/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c new file mode 100644 index 0000000..d7cf2df --- /dev/null +++ b/ecos/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c @@ -0,0 +1,700 @@ +//========================================================================== +// +// io/serial/generic/16x5x/ser_16x5x.c +// +// Generic 16x5x serial driver +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2006, 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jlarmour, jskov +// Date: 1999-02-04 +// Purpose: 16x5x generic serial driver +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_io.h> + +// Only compile driver if an inline file with driver details was selected. +#ifdef CYGDAT_IO_SERIAL_GENERIC_16X5X_INL + +#ifndef CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP +#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 1 +#endif + +#define SER_REG(_x_) ((_x_)*CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP) + +// Receive control Registers +#define REG_rhr SER_REG(0) // Receive holding register +#define REG_isr SER_REG(2) // Interrupt status register +#define REG_lsr SER_REG(5) // Line status register +#define REG_msr SER_REG(6) // Modem status register +#define REG_scr SER_REG(7) // Scratch register + +// Transmit control Registers +#define REG_thr SER_REG(0) // Transmit holding register +#define REG_ier SER_REG(1) // Interrupt enable register +#define REG_fcr SER_REG(2) // FIFO control register +#define REG_lcr SER_REG(3) // Line control register +#define REG_mcr SER_REG(4) // Modem control register +#define REG_ldl SER_REG(0) // LSB of baud rate +#define REG_mdl SER_REG(1) // MSB of baud rate + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x18 // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_OE 0x02 +#define LSR_PE 0x04 +#define LSR_FE 0x08 +#define LSR_BI 0x10 +#define LSR_THE 0x20 +#define LSR_TEMT 0x40 +#define LSR_FIE 0x80 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts +#define MCR_LOOP 0x10 // Loopback mode + +// Interrupt status Register +#define ISR_MS 0x00 +#define ISR_nIP 0x01 +#define ISR_Tx 0x02 +#define ISR_Rx 0x04 +#define ISR_LS 0x06 +#define ISR_RxTO 0x0C +#define ISR_64BFIFO 0x20 +#define ISR_FIFOworks 0x40 +#define ISR_FIFOen 0x80 + +// Modem Status Register +#define MSR_DCTS 0x01 +#define MSR_DDSR 0x02 +#define MSR_TERI 0x04 +#define MSR_DDCD 0x08 +#define MSR_CTS 0x10 +#define MSR_DSR 0x20 +#define MSR_RI 0x40 +#define MSR_CD 0x80 + +// FIFO Control Register +#define FCR_FE 0x01 // FIFO enable +#define FCR_CRF 0x02 // Clear receive FIFO +#define FCR_CTF 0x04 // Clear transmit FIFO +#define FCR_DMA 0x08 // DMA mode select +#define FCR_F64 0x20 // Enable 64 byte fifo (16750+) +#define FCR_RT14 0xC0 // Set Rx trigger at 14 +#define FCR_RT8 0x80 // Set Rx trigger at 8 +#define FCR_RT4 0x40 // Set Rx trigger at 4 +#define FCR_RT1 0x00 // Set Rx trigger at 1 + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// selec_baud[] must be define by the client + +typedef struct pc_serial_info { + cyg_addrword_t base; + int int_num; +#ifdef CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + int int_prio; +#endif // CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO + enum { + sNone = 0, + s8250, + s16450, + s16550, + s16550a + } deviceType; + unsigned tx_fifo_size; + volatile unsigned tx_fifo_avail; +#endif +} pc_serial_info; + +static bool pc_serial_init(struct cyg_devtab_entry *tab); +static bool pc_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo pc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char pc_serial_getc(serial_channel *chan); +static Cyg_ErrNo pc_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void pc_serial_start_xmit(serial_channel *chan); +static void pc_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 pc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void pc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(pc_serial_funs, + pc_serial_putc, + pc_serial_getc, + pc_serial_set_config, + pc_serial_start_xmit, + pc_serial_stop_xmit + ); + +#include CYGDAT_IO_SERIAL_GENERIC_16X5X_INL + +#ifndef CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY +# define CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY 4 +#endif + +// Allow platform code to override the default implementation of +// a write to the LCR +#ifndef SER_16X5X_WRITE_LCR +#define SER_16X5X_WRITE_LCR(_base_, _val_) HAL_WRITE_UINT8((_base_) + REG_lcr, _val_) +#endif + +// Allow platform code to override the default implementation of +// a read of the ISR +#ifndef SER_16X5X_READ_ISR +#define SER_16X5X_READ_ISR(_base_, _val_) HAL_READ_UINT8((_base_) + REG_isr, _val_) +#endif + +// Internal function to actually configure the hardware to desired +// baud rate, etc. +static bool +serial_config_port(serial_channel *chan, + cyg_serial_info_t *new_config, bool init) +{ + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + // + // If the device supports a dynamic per channel baudrate generator + // then we call the CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR() + // macro to get the baud divisor. The macro takes the serial channel data + // pointer and the baudrate as parameters and returns the baud divisior + // +#ifdef CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR + unsigned short baud_divisor = CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(ser_chan, new_config->baud); +#else + unsigned short baud_divisor = select_baud[new_config->baud]; +#endif + unsigned char _lcr, _ier; + if (baud_divisor == 0) return false; // Invalid configuration + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(base+REG_ier, _ier); + HAL_WRITE_UINT8(base+REG_ier, 0); + + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + SER_16X5X_WRITE_LCR(base, _lcr | LCR_DL); + HAL_WRITE_UINT8(base+REG_mdl, baud_divisor >> 8); + HAL_WRITE_UINT8(base+REG_ldl, baud_divisor & 0xFF); + SER_16X5X_WRITE_LCR(base, _lcr); + if (init) { +#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO + unsigned char _fcr_thresh; + cyg_uint8 b; + + /* First, find out what kind of device it is. */ + ser_chan->deviceType = sNone; + HAL_WRITE_UINT8(base+REG_mcr, MCR_LOOP); // enable loopback mode + HAL_READ_UINT8(base+REG_msr, b); + if (0 == (b & 0xF0)) { // see if MSR had CD, RI, DSR or CTS set + HAL_WRITE_UINT8(base+REG_mcr, MCR_LOOP|MCR_DTR|MCR_RTS); + HAL_READ_UINT8(base+REG_msr, b); + if (0xF0 != (b & 0xF0)) // check that all of CD,RI,DSR and CTS set + ser_chan->deviceType = s8250; + } + HAL_WRITE_UINT8(base+REG_mcr, 0); // disable loopback mode + + if (ser_chan->deviceType == s8250) { + // Check for a scratch register; scratch register + // indicates 16450 or above. + HAL_WRITE_UINT8(base+REG_scr, 0x55); + HAL_READ_UINT8(base+REG_scr, b); + if (b == 0x55) { + HAL_WRITE_UINT8(base+REG_scr, 0xAA); + HAL_READ_UINT8(base+REG_scr, b); + if (b == 0xAA) + ser_chan->deviceType = s16450; + } + } + + if (ser_chan->deviceType == s16450) { + // Check for a FIFO + HAL_WRITE_UINT8(base+REG_fcr, FCR_FE); + HAL_READ_UINT8(base+REG_isr, b); + if (b & ISR_FIFOen) + ser_chan->deviceType = s16550; // but FIFO doesn't + // necessarily work + if (b & ISR_FIFOworks) + ser_chan->deviceType = s16550a; // 16550a FIFOs work + } + + if (ser_chan->deviceType == s16550a) { + switch(CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD) { + default: + case 1: + _fcr_thresh=FCR_RT1; break; + case 4: + _fcr_thresh=FCR_RT4; break; + case 8: + _fcr_thresh=FCR_RT8; break; + case 14: + _fcr_thresh=FCR_RT14; break; + } + _fcr_thresh|=FCR_FE|FCR_CRF|FCR_CTF; + ser_chan->tx_fifo_size = + CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE; + // Enable and clear FIFO + HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh); + // Read RHR to clear potential Overrun Error + HAL_READ_UINT8(base+REG_rhr, b); + } + else { + ser_chan->tx_fifo_size = 1; + HAL_WRITE_UINT8(base+REG_fcr, 0); // make sure it's disabled + } + + ser_chan->tx_fifo_avail = ser_chan->tx_fifo_size; +#endif + if (chan->out_cbuf.len != 0) { + _ier = IER_RCV; + } else { + _ier = 0; + } + // Master interrupt enable + HAL_WRITE_UINT8(base+REG_mcr, MCR_INT|MCR_DTR|MCR_RTS); + } +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + _ier |= (IER_LS|IER_MS); +#endif + HAL_WRITE_UINT8(base+REG_ier, _ier); + +#ifdef CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK + CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK( ser_chan, new_config ); +#endif + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +pc_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + +#ifdef CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR + // Fill in baud rate table - used for platforms where this cannot + // be determined statically + int baud_idx, baud_val; + if (select_baud[0] == 9999) { + // Table not yet initialized + // Assumes that 'select_baud' looks like this: + // static int select_baud[] = { + // 9999, -- marker + // 50, -- first baud rate + // 110, -- second baud rate + // etc. + for (baud_idx = 1; baud_idx < sizeof(select_baud)/sizeof(select_baud[0]); baud_idx++) { + baud_val = CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR(select_baud[baud_idx]); + select_baud[baud_idx] = baud_val; + } + select_baud[0] = 0; + } +#endif + +#ifdef CYGDBG_IO_INIT + diag_printf("16x5x SERIAL init - dev: %x.%d\n", + ser_chan->base, ser_chan->int_num); +#endif + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + // + // If the device supports per channel interrupt priorities then + // we take the priority from the serial channel data. If it does + // not support per channel interrupt priority we fall back to + // the old method and use CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY + // to define the priority + // +#ifdef CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + cyg_priority_t intprio = ser_chan->int_prio; +#else + cyg_priority_t intprio = CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY; +#endif // CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(ser_chan->int_num, + intprio, + (cyg_addrword_t)chan, + pc_serial_ISR, + pc_serial_DSR, + &ser_chan->serial_interrupt_handle, + &ser_chan->serial_interrupt); + cyg_drv_interrupt_attach(ser_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(ser_chan->int_num); + } + serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +pc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +pc_serial_putc(serial_channel *chan, unsigned char c) +{ +#ifndef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO + cyg_uint8 _lsr; +#endif + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + +#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO + if (ser_chan->tx_fifo_avail > 0) { + HAL_WRITE_UINT8(base+REG_thr, c); + --ser_chan->tx_fifo_avail; + return true; + } +#else + HAL_READ_UINT8(base+REG_lsr, _lsr); + if (_lsr & LSR_THE) { + // Transmit buffer is empty + HAL_WRITE_UINT8(base+REG_thr, c); + return true; + } +#endif + // No space + return false; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +pc_serial_getc(serial_channel *chan) +{ + unsigned char c; + cyg_uint8 _lsr; + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + + // Wait for char + do { + HAL_READ_UINT8(base+REG_lsr, _lsr); + } while ((_lsr & LSR_RSR) == 0); + + HAL_READ_UINT8(base+REG_rhr, c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +pc_serial_set_config(serial_channel *chan, cyg_uint32 key, const void *xbuf, + cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + cyg_uint8 _mcr; + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + cyg_uint32 *f = (cyg_uint32 *)xbuf; + unsigned char mask=0; + if ( *len < sizeof(*f) ) + return -EINVAL; + + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) + mask = MCR_RTS; + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX ) + mask |= MCR_DTR; + HAL_READ_UINT8(base+REG_mcr, _mcr); + if (*f) // we should throttle + _mcr &= ~mask; + else // we should no longer throttle + _mcr |= mask; + HAL_WRITE_UINT8(base+REG_mcr, _mcr); + } + break; + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + // Nothing to do because we do support both RTSCTS and DSRDTR flow + // control. + // Other targets would clear any unsupported flags here and + // would then return -ENOSUPP - the higher layer can then query + // what flags are set and decide what to do. This is optimised for + // the most common case - i.e. that authors know what their hardware + // is capable of. + // We just return ENOERR. + break; +#endif + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +pc_serial_start_xmit(serial_channel *chan) +{ + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(base+REG_ier, _ier); + _ier |= IER_XMT; // Enable xmit interrupt + HAL_WRITE_UINT8(base+REG_ier, _ier); +#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME + (chan->callbacks->xmt_char)(chan); +#endif +} + +// Disable the transmitter on the device +static void +pc_serial_stop_xmit(serial_channel *chan) +{ + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(base+REG_ier, _ier); + _ier &= ~IER_XMT; // Disable xmit interrupt + HAL_WRITE_UINT8(base+REG_ier, _ier); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +pc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(ser_chan->int_num); + cyg_drv_interrupt_acknowledge(ser_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +pc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->base; + cyg_uint8 _isr; + + // Check if we have an interrupt pending - note that the interrupt + // is pending of the low bit of the isr is *0*, not 1. + SER_16X5X_READ_ISR(base, _isr); + while ((_isr & ISR_nIP) == 0) { + switch (_isr&0xE) { + case ISR_Rx: + case ISR_RxTO: + { + cyg_uint8 _lsr; + unsigned char c; + HAL_READ_UINT8(base+REG_lsr, _lsr); + while(_lsr & LSR_RSR) { + HAL_READ_UINT8(base+REG_rhr, c); + (chan->callbacks->rcv_char)(chan, c); + HAL_READ_UINT8(base+REG_lsr, _lsr); + } + break; + } + case ISR_Tx: +#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO + ser_chan->tx_fifo_avail = ser_chan->tx_fifo_size; +#endif + (chan->callbacks->xmt_char)(chan); + break; + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + case ISR_LS: + { + cyg_serial_line_status_t stat; + cyg_uint8 _lsr; + HAL_READ_UINT8(base+REG_lsr, _lsr); + + // this might look expensive, but it is rarely the case that + // more than one of these is set + stat.value = 1; + if ( _lsr & LSR_OE ) { + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat ); + } + if ( _lsr & LSR_PE ) { + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat ); + } + if ( _lsr & LSR_FE ) { + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat ); + } + if ( _lsr & LSR_BI ) { + stat.which = CYGNUM_SERIAL_STATUS_BREAK; + (chan->callbacks->indicate_status)(chan, &stat ); + } + } + break; + + case ISR_MS: + { + cyg_serial_line_status_t stat; + cyg_uint8 _msr; + + HAL_READ_UINT8(base+REG_msr, _msr); +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + if ( _msr & MSR_DDSR ) + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_TX ) { + stat.which = CYGNUM_SERIAL_STATUS_FLOW; + stat.value = (0 != (_msr & MSR_DSR)); + (chan->callbacks->indicate_status)(chan, &stat ); + } + if ( _msr & MSR_DCTS ) + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX ) { + stat.which = CYGNUM_SERIAL_STATUS_FLOW; + stat.value = (0 != (_msr & MSR_CTS)); + (chan->callbacks->indicate_status)(chan, &stat ); + } +#endif + if ( _msr & MSR_DDCD ) { + stat.which = CYGNUM_SERIAL_STATUS_CARRIERDETECT; + stat.value = (0 != (_msr & MSR_CD)); + (chan->callbacks->indicate_status)(chan, &stat ); + } + if ( _msr & MSR_RI ) { + stat.which = CYGNUM_SERIAL_STATUS_RINGINDICATOR; + stat.value = 1; + (chan->callbacks->indicate_status)(chan, &stat ); + } + if ( _msr & MSR_TERI ) { + stat.which = CYGNUM_SERIAL_STATUS_RINGINDICATOR; + stat.value = 0; + (chan->callbacks->indicate_status)(chan, &stat ); + } + } + break; +#endif + default: + // Yes, this assertion may well not be visible. *But* + // if debugging, we may still successfully hit a breakpoint + // on cyg_assert_fail, which _is_ useful + CYG_FAIL("unhandled serial interrupt state"); + } + + HAL_READ_UINT8(base+REG_isr, _isr); + } // while + + cyg_drv_interrupt_unmask(ser_chan->int_num); +} +#endif + +// EOF ser_16x5x.c diff --git a/ecos/packages/devs/serial/h8300/h8300h/current/ChangeLog b/ecos/packages/devs/serial/h8300/h8300h/current/ChangeLog new file mode 100644 index 0000000..f4f5762 --- /dev/null +++ b/ecos/packages/devs/serial/h8300/h8300h/current/ChangeLog @@ -0,0 +1,31 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/serial_h8300.cdl: Remove irrelevant doc link. + +2002-04-24 Yoshinori Sato <qzb04471@nifty.ne.jp> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/h8300/h8300h/current/cdl/serial_h8300.cdl b/ecos/packages/devs/serial/h8300/h8300h/current/cdl/serial_h8300.cdl new file mode 100644 index 0000000..edda67d --- /dev/null +++ b/ecos/packages/devs/serial/h8300/h8300h/current/cdl/serial_h8300.cdl @@ -0,0 +1,112 @@ +# ==================================================================== +# +# serial_h8300.cdl +# +# eCos serial H8/300 SCI configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_H8300_SCI { + display "H8/300 SCI serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_H8300 + + active_if CYGINT_IO_SERIAL_H8300_SCI_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + SCI module in Hitachi H8/300 CPUs." + + compile -library=libextras.a h8300_sci_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_h8300_sci.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_SH_SCI_CFG"; + } + + cdl_component CYGPKG_IO_SERIAL_SH_SCI_OPTIONS { + display "SCI serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_IO_SERIAL_SH_SCI_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_SH_SCI_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF serial_h8300.cdl diff --git a/ecos/packages/devs/serial/h8300/h8300h/current/src/h8300_sci_serial.c b/ecos/packages/devs/serial/h8300/h8300h/current/src/h8300_sci_serial.c new file mode 100644 index 0000000..0380f18 --- /dev/null +++ b/ecos/packages/devs/serial/h8300/h8300h/current/src/h8300_sci_serial.c @@ -0,0 +1,575 @@ +//========================================================================== +// +// h8300_sci_serial.c +// +// H8/300 Serial SCI I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 1999-05-24 +// Purpose: H8/300 Serial I/O module (interrupt driven version) +// Description: +// +// Note: Since interrupt sources from the same SCI channel share the same +// interrupt level, there is no risk of races when altering the +// channel's control register from ISRs and DSRs. However, when +// altering the control register from user-level code, interrupts +// must be disabled while the register is being accessed. +// +// FIXME: Receiving in polled mode prevents duplex transfers from working for +// some reason. +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +// FIXME: This is necessary since the SCIF driver may be overriding +// CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two +// different drivers. +#include <pkgconf/io_serial_h8300_sci.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#ifdef CYGDAT_IO_SERIAL_H8300_SCI +// The SCI controller register layout on the SH3/7708. +#define SCI_SCSMR 0 // serial mode register +#define SCI_SCBRR 1 // bit rate register +#define SCI_SCSCR 2 // serial control register +#define SCI_SCTDR 3 // transmit data register +#define SCI_SCSSR 4 // serial status register +#define SCI_SCRDR 5 // receive data register +#define SCI_SCSPTR -4 // serial port register + +static short select_word_length[] = { + -1, + -1, + CYGARC_REG_SCSMR_CHR, // 7 bits + 0 // 8 bits +}; + +static short select_stop_bits[] = { + -1, + 0, // 1 stop bit + -1, + CYGARC_REG_SCSMR_STOP // 2 stop bits +}; + +static short select_parity[] = { + 0, // No parity + CYGARC_REG_SCSMR_PE, // Even parity + CYGARC_REG_SCSMR_PE|CYGARC_REG_SCSMR_OE, // Odd parity + -1, + -1 +}; + +static unsigned short select_baud[] = { + 0, // Unused + CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50), + CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75), + CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110), + CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134), + CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150), + CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200), + CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300), + CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600), + CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200), + CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800), + CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400), + CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600), + CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800), + CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200), + CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600), + CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400), + CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200), + CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400), + CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600), + CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200), + CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400) +}; + + +typedef struct h8300_sci_info { + CYG_ADDRWORD data; // Pointer to data register + + CYG_WORD er_int_num, // Error interrupt number + rx_int_num, // Receive interrupt number + tx_int_num; // Transmit interrupt number + + CYG_ADDRWORD ctrl_base; // Base address of SCI controller + + cyg_interrupt serial_er_interrupt, + serial_rx_interrupt, + serial_tx_interrupt; + cyg_handle_t serial_er_interrupt_handle, + serial_rx_interrupt_handle, + serial_tx_interrupt_handle; + + bool tx_enabled; +} sh_sci_info; + +static bool h8300_serial_init(struct cyg_devtab_entry *tab); +static bool h8300_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo h8300_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char h8300_serial_getc(serial_channel *chan); +static Cyg_ErrNo h8300_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void h8300_serial_start_xmit(serial_channel *chan); +static void h8300_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 h8300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void h8300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 h8300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void h8300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 h8300_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void h8300_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(h8300_serial_funs, + h8300_serial_putc, + h8300_serial_getc, + h8300_serial_set_config, + h8300_serial_start_xmit, + h8300_serial_stop_xmit + ); + + +static h8300_sci_info h8300_serial_info = +{ + NULL, + CYGNUM_HAL_INTERRUPT_ERI0, + CYGNUM_HAL_INTERRUPT_RXI0, + CYGNUM_HAL_INTERRUPT_TXI0, + CYGARC_REG_SMR0 +}; + +#if CYGNUM_IO_SERIAL_H8300_H8300H_SERIAL1_BUFSIZE > 0 +static unsigned char h8300_serial_out_buf[CYGNUM_IO_SERIAL_H8300_CQ7708_SERIAL1_BUFSIZE]; +static unsigned char h8300_serial_in_buf[CYGNUM_IO_SERIAL_H8300_CQ7708_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(h8300_serial_channel, + h8300_serial_funs, + h8300_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_H8300_H8300H_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &h8300_serial_out_buf[0], + sizeof(h8300_serial_out_buf), + &h8300_serial_in_buf[0], + sizeof(h8300_serial_in_buf) + ); +#else +static SERIAL_CHANNEL(h8300_serial_channel, + h8300_serial_funs, + h8300_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_H8300_H8300H_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(h8300_serial_io, + CYGDAT_IO_SERIAL_H8300_H8300H_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + h8300_serial_init, + h8300_serial_lookup, // Serial driver may need initializing + &h8300_serial_channel + ); + +// Internal function to actually configure the hardware to desired baud rate, +// etc. +static bool +h8300_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, + bool init) +{ + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + cyg_uint8 _scr, _smr; + + // Check configuration request + if ((-1 == select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)]) + || -1 == select_stop_bits[new_config->stop] + || -1 == select_parity[new_config->parity] + || baud_divisor == 0) + return false; + + // Disable SCI interrupts while changing hardware + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, 0); + + // Set databits, stopbits and parity. + _smr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSMR, _smr); + + // Set baud rate. + _smr &= ~CYGARC_REG_SCSMR_CKSx_MASK; + _smr |= baud_divisor >> 8; + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSMR, _smr); + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff); + + // Clear the status register. + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, 0); + + if (init) { + // Always enable transmitter and receiver. + _scr = CYGARC_REG_SCSCR_TE | CYGARC_REG_SCSCR_RE; + + if (chan->out_cbuf.len != 0) + _scr |= CYGARC_REG_SCSCR_TIE; // enable tx interrupts + + if (chan->in_cbuf.len != 0) + _scr |= CYGARC_REG_SCSCR_RIE; // enable rx interrupts + } + + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +h8300_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("SH SERIAL init - dev: %x.%d\n", + h8300_chan->data, h8300_chan->rx_int_num); +#endif + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(h8300_chan->tx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + h8300_serial_tx_ISR, + h8300_serial_tx_DSR, + &h8300_chan->serial_tx_interrupt_handle, + &h8300_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(h8300_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_unmask(h8300_chan->tx_int_num); + h8300_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + // Receive interrupt + cyg_drv_interrupt_create(h8300_chan->rx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + h8300_serial_rx_ISR, + h8300_serial_rx_DSR, + &h8300_chan->serial_rx_interrupt_handle, + &h8300_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(h8300_chan->serial_rx_interrupt_handle); + // Receive error interrupt + cyg_drv_interrupt_create(h8300_chan->er_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + h8300_serial_er_ISR, + h8300_serial_er_DSR, + &h8300_chan->serial_er_interrupt_handle, + &h8300_chan->serial_er_interrupt); + cyg_drv_interrupt_attach(h8300_chan->serial_er_interrupt_handle); + // This unmasks both interrupt sources. + cyg_drv_interrupt_unmask(h8300_chan->rx_int_num); + } + h8300_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +h8300_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +h8300_serial_putc(serial_channel *chan, unsigned char c) +{ + cyg_uint8 _ssr; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr); + if (_ssr & CYGARC_REG_SCSSR_TDRE) { +// Transmit buffer is empty + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCTDR, c); + // Clear empty flag. + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_TDRE); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +h8300_serial_getc(serial_channel *chan) +{ + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + unsigned char c; + cyg_uint8 _ssr; + + do { + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr); + } while ((_ssr & CYGARC_REG_SCSSR_RDRF) == 0); + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCRDR, c); + + // Clear buffer full flag. + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF); + + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +h8300_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != h8300_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +h8300_serial_start_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + + h8300_chan->tx_enabled = true; + + // Mask the interrupts (all sources of the unit) while changing + // the CR since a rx interrupt in the middle of this would result + // in a bad CR state. + cyg_drv_interrupt_mask(h8300_chan->rx_int_num); + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCSCR_TIE; // Enable xmit interrupt + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + + cyg_drv_interrupt_unmask(h8300_chan->rx_int_num); +} + +// Disable the transmitter on the device +static void +h8300_serial_stop_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + + h8300_chan->tx_enabled = false; + + // Mask the interrupts (all sources of the unit) while changing + // the CR since a rx interrupt in the middle of this would result + // in a bad CR state. + cyg_drv_interrupt_mask(h8300_chan->rx_int_num); + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCSCR_TIE; // Disable xmit interrupt + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + + cyg_drv_interrupt_unmask(h8300_chan->rx_int_num); +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +h8300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCSCR_TIE; // mask out tx interrupts + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +h8300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + + (chan->callbacks->xmt_char)(chan); + + if (h8300_chan->tx_enabled) { + cyg_uint8 _scr; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCSCR_TIE; // unmask tx interrupts + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + } +} + +// Serial I/O - low level RX interrupt handler (ISR) +static cyg_uint32 +h8300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +h8300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + cyg_uint8 _ssr, _scr; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr); + if (_ssr & CYGARC_REG_SCSSR_RDRF) { + cyg_uint8 _c; + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCRDR, _c); + // Clear buffer full flag. + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF); + + (chan->callbacks->rcv_char)(chan, _c); + } + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); +} + +static volatile int h8300_serial_error_orer = 0; +static volatile int h8300_serial_error_fer = 0; +static volatile int h8300_serial_error_per = 0; + +// Serial I/O - low level error interrupt handler (ISR) +static cyg_uint32 +h8300_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level error interrupt handler (DSR) +static void +h8300_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv; + cyg_uint8 _ssr, _ssr2, _scr; + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr); + _ssr2 = CYGARC_REG_SCSSR_CLEARMASK; + + if (_ssr & CYGARC_REG_SCSSR_ORER) { + _ssr2 &= ~CYGARC_REG_SCSSR_ORER; + h8300_serial_error_orer++; + } + if (_ssr & CYGARC_REG_SCSSR_FER) { + _ssr2 &= ~CYGARC_REG_SCSSR_FER; + h8300_serial_error_fer++; + } + if (_ssr & CYGARC_REG_SCSSR_PER) { + _ssr2 &= ~CYGARC_REG_SCSSR_PER; + h8300_serial_error_per++; + } + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr2); + + HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr); +} + +#endif // ifdef CYGDAT_IO_SERIAL_H8300_SCI diff --git a/ecos/packages/devs/serial/i386/pc/current/ChangeLog b/ecos/packages/devs/serial/i386/pc/current/ChangeLog new file mode 100644 index 0000000..e42ba5d --- /dev/null +++ b/ecos/packages/devs/serial/i386/pc/current/ChangeLog @@ -0,0 +1,1196 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_i386_pc.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_i386_pc.cdl: + Fix 234000->230400 typo. + +2001-06-08 Jonathan Larmour <jlarmour@redhat.com> + + * include/i386_pc_ser.inl: Use generic 16x5x driver now. + + * cdl/ser_i386_pc.cdl: Define necessary options to use generic + 16x5x driver. + Fix IRQ->INT in CDL display strings. + + * src/pc_serial.c: Removed in favour of generic driver. + * src/pc_serial.h: Ditto. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_i386_pc.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/pc_serial.c (pc_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_i386_pc.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/i386/pc/current/cdl/ser_i386_pc.cdl b/ecos/packages/devs/serial/i386/pc/current/cdl/ser_i386_pc.cdl new file mode 100644 index 0000000..94e0e3d --- /dev/null +++ b/ecos/packages/devs/serial/i386/pc/current/cdl/ser_i386_pc.cdl @@ -0,0 +1,268 @@ +# ==================================================================== +# +# ser_i386_pc.cdl +# +# eCos serial PC configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jlarmour, nickg, gthomas, pjo +# Original data: +# Contributors: jskov +# Date: 2001-06-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_I386_PC { + display "PC serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_I386_PCMB + + requires CYGPKG_ERROR + include_dir cyg/io + description " + This option enables the serial device drivers for the + PC." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/i386_pc_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_i386_pc.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_I386_PC_SERIAL0 { + display "PC serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 0 on the + PC." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_I386_PC_SERIAL0_NAME { + display "Device name for PC serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name port 0 on the PC." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BAUD { + display "Baud rate for the PC serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PC port 0." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BUFSIZE { + display "Buffer size for the PC serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the PC port 0." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL0_IOBASE { + display "I/O base address for the i386-PC serial port 0" + flavor data + legal_values 0 to 0xFF8 + default_value 0x3F8 + description " + This option specifies the I/O address of the 8250 or 16550 for serial port 0." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL0_IRQ { + display "IRQ for the i386-PC serial port 0" + flavor data + legal_values 0 to 15 + default_value 4 + description " + This option specifies the IRQ of the 8250 or 16550 for serial port 0." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL0_INT { + display "INT for the i386-PC serial port 0" + flavor data + legal_values 32 to 47 + default_value { CYGNUM_IO_SERIAL_I386_PC_SERIAL0_IRQ + 32 } + description " + This option specifies the interrupt vector of the 8250 or 16550 for serial port 0." + } +} + +cdl_component CYGPKG_IO_SERIAL_I386_PC_SERIAL1 { + display "PC serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 1 on + the PC." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_I386_PC_SERIAL1_NAME { + display "Device name for PC serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name port 1 on the PC." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BAUD { + display "Baud rate for the PC serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BUFSIZE { + display "Buffer size for the PC serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the PC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL1_IOBASE { + display "I/O base address for the i386-PC serial port 1" + flavor data + legal_values 0 to 0xFF8 + default_value 0x2F8 + description " + This option specifies the I/O address of the 8250 or 16550 for serial port 1." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL1_IRQ { + display "IRQ for the i386-PC serial port 1" + flavor data + legal_values 0 to 15 + default_value 3 + description " + This option specifies the IRQ of the 8250 or 16550 for serial port 1." + } + + cdl_option CYGNUM_IO_SERIAL_I386_PC_SERIAL1_INT { + display "INT for the i386-PC serial port 1" + flavor data + legal_values 32 to 47 + default_value { CYGNUM_IO_SERIAL_I386_PC_SERIAL1_IRQ + 32 } + description " + This option specifies the interrupt vector of the 8250 or 16550 for serial port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_I386_PC_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_I386_PC_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_I386_PC_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_I386_PC_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_I386_PC_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_I386_PC_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"i386pc\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_i386_pc.cdl diff --git a/ecos/packages/devs/serial/i386/pc/current/include/i386_pc_ser.inl b/ecos/packages/devs/serial/i386/pc/current/include/i386_pc_ser.inl new file mode 100644 index 0000000..8219cb4 --- /dev/null +++ b/ecos/packages/devs/serial/i386/pc/current/include/i386_pc_ser.inl @@ -0,0 +1,163 @@ +//========================================================================== +// +// io/serial/i386/pc/i386_pc_ser.inl +// +// i386 PC Serial I/O Interface Module (interrupt driven) +// for use with 8250s or 16550s. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2001-06-08 +// Purpose: PC Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// Baud rate specification, based on raw 24MHz clock + +static unsigned short select_baud[] = { + 0, // Unused + 2304, // 50 + 1536, // 75 + 1047, // 110 + 857, // 134.5 + 768, // 150 + 576, // 200 + 384, // 300 + 192, // 600 + 96, // 1200 + 64, // 1800 + 48, // 2400 + 32, // 3600 + 24, // 4800 + 16, // 7200 + 12, // 9600 + 8, // 14400 + 6, // 19200 + 3, // 38400 + 2, // 57600 + 1, // 115200 + 0, // 230400 +}; + +#ifdef CYGPKG_IO_SERIAL_I386_PC_SERIAL0 +static pc_serial_info pc_serial_info0 = {CYGNUM_IO_SERIAL_I386_PC_SERIAL0_IOBASE, + CYGNUM_IO_SERIAL_I386_PC_SERIAL0_INT}; +#if CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BUFSIZE > 0 +static unsigned char pc_serial_out_buf0[CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BUFSIZE]; +static unsigned char pc_serial_in_buf0[CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf0[0], sizeof(pc_serial_out_buf0), + &pc_serial_in_buf0[0], sizeof(pc_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_I386_PC_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io0, + CYGDAT_IO_SERIAL_I386_PC_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_I386_PC_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_I386_PC_SERIAL1 +static pc_serial_info pc_serial_info1 = {CYGNUM_IO_SERIAL_I386_PC_SERIAL1_IOBASE, + CYGNUM_IO_SERIAL_I386_PC_SERIAL1_INT}; +#if CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BUFSIZE > 0 +static unsigned char pc_serial_out_buf1[CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BUFSIZE]; +static unsigned char pc_serial_in_buf1[CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf1[0], sizeof(pc_serial_out_buf1), + &pc_serial_in_buf1[0], sizeof(pc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_I386_PC_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io1, + CYGDAT_IO_SERIAL_I386_PC_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_I386_PC_SERIAL1 + +// EOF i386_pc_ser.inl diff --git a/ecos/packages/devs/serial/loop/current/ChangeLog b/ecos/packages/devs/serial/loop/current/ChangeLog new file mode 100644 index 0000000..c049490 --- /dev/null +++ b/ecos/packages/devs/serial/loop/current/ChangeLog @@ -0,0 +1,53 @@ +2009-10-09 John Dallaway <john@dallaway.org.uk> + + * cdl/ser_loop.cdl: Remove irrelevant testing parameters which + prevent the loading of this package in the presence of other serial + device drivers. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_loop.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_loop.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_loop.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/loop_serial.c (loop_serial_set_config): Now use keys to make + more flexible. + +2000-06-15 Nick Garnett <nickg@cygnus.co.uk> + + * cdl/ser_loop.cdl: + * src/loop/loop_serial.c: + Added loopback serial driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/loop/current/cdl/ser_loop.cdl b/ecos/packages/devs/serial/loop/current/cdl/ser_loop.cdl new file mode 100644 index 0000000..4bed65b --- /dev/null +++ b/ecos/packages/devs/serial/loop/current/cdl/ser_loop.cdl @@ -0,0 +1,188 @@ +# ==================================================================== +# +# ser_loop.cdl +# +# eCos serial LOOP configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-07 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_LOOP { + display "Loop serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + + description " + This package contains the loop serial device driver." + + compile -library=libextras.a loop_serial.c + + # FIXME: Bad name + cdl_option CYGPKG_IO_SERIAL_LOOP_POLLED_MODE { + display "LOOP polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial loop device + drivers for the should be polled-mode instead of + interrupt driven." + } + + cdl_component CYGPKG_IO_SERIAL_LOOP_SERIAL0 { + display "LOOP serial port 0 driver" + flavor bool + default_value 0 + description " + This option includes the serial loop device driver for port 0." + + cdl_option CYGDAT_IO_SERIAL_LOOP_SERIAL0_NAME { + display "Device name for LOOP serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the first loop device name." + } + + cdl_option CYGNUM_IO_SERIAL_LOOP_SERIAL0_BAUD { + display "Baud rate for the LOOP serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 + 2400 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + LOOP port 0." + } + + cdl_option CYGNUM_IO_SERIAL_LOOP_SERIAL0_BUFSIZE { + display "Buffer size for the LOOP serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the LOOP port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_LOOP_SERIAL1 { + display "LOOP serial port 1 driver" + flavor bool + default_value 0 + description " + This option includes the serial device driver for port 1 on + the LOOP." + + cdl_option CYGDAT_IO_SERIAL_LOOP_SERIAL1_NAME { + display "Device name for LOOP serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name port 1 on the LOOP." + } + + cdl_option CYGNUM_IO_SERIAL_LOOP_SERIAL1_BAUD { + display "Baud rate for the LOOP serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 + 2400 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + LOOP port 1." + } + + cdl_option CYGNUM_IO_SERIAL_LOOP_SERIAL1_BUFSIZE { + display "Buffer size for the LOOP serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the LOOP port 1." + } + } + + cdl_component CYGPKG_IO_SERIAL_LOOP_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_LOOP_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags + are used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_LOOP_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_loop.cdl diff --git a/ecos/packages/devs/serial/loop/current/src/loop_serial.c b/ecos/packages/devs/serial/loop/current/src/loop_serial.c new file mode 100644 index 0000000..be5ea46 --- /dev/null +++ b/ecos/packages/devs/serial/loop/current/src/loop_serial.c @@ -0,0 +1,456 @@ +//========================================================================== +// +// loop_serial.c +// +// Loopback serial device driver +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-02-25 +// Purpose: Loopback serial device driver +// Description: This device driver implements a pair of serial lines that are +// connected back-to-back. Data output to one will appear as +// input on the other. This process in in part driven by an alarm +// object which provides a degree of separation between the two +// channels. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io_serial_loop.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/kernel/kapi.h> + +#ifdef CYGPKG_IO_SERIAL_LOOP + +//------------------------------------------------------------------------- + +extern void diag_printf(const char *fmt, ...); + +//------------------------------------------------------------------------- +// Forward definitions + +static bool loop_serial_init(struct cyg_devtab_entry *tab); +static bool loop_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo loop_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char loop_serial_getc(serial_channel *chan); +static Cyg_ErrNo loop_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void loop_serial_start_xmit(serial_channel *chan); +static void loop_serial_stop_xmit(serial_channel *chan); + +#ifndef CYGPKG_IO_SERIAL_LOOP_POLLED_MODE +static void alarm_handler(cyg_handle_t alarm, cyg_addrword_t data); +#endif + +//------------------------------------------------------------------------- +// Alarm object for feeding data back into serial channels + +static cyg_alarm alarm_obj; + +static cyg_handle_t alarm_handle; + +//------------------------------------------------------------------------- +// Transfer FIFOs + +#define FIFO_SIZE 16 + +struct fifo +{ + cyg_bool tx_enable; + volatile int head; + volatile int tail; + volatile int num; + volatile char buf[FIFO_SIZE+1]; +}; + +static struct fifo fifo0 = { false, 0, 0, 0 }; // from serial0 to serial1 +static struct fifo fifo1 = { false, 0, 0, 0 }; // from serial1 to serial0 + +//------------------------------------------------------------------------- + +#define BUFSIZE 128 + +//------------------------------------------------------------------------- +// Info for each serial device controlled + +typedef struct loop_serial_info { + struct fifo *write_fifo; + struct fifo *read_fifo; +} loop_serial_info; + +//------------------------------------------------------------------------- +// Callback functions exported by this driver + +static SERIAL_FUNS(loop_serial_funs, + loop_serial_putc, + loop_serial_getc, + loop_serial_set_config, + loop_serial_start_xmit, + loop_serial_stop_xmit + ); + +//------------------------------------------------------------------------- +// Hardware info for each serial line + +#ifdef CYGPKG_IO_SERIAL_LOOP_SERIAL0 +static loop_serial_info loop_serial_info0 = { + &fifo0, + &fifo1 +}; +#if CYGNUM_IO_SERIAL_LOOP_SERIAL0_BUFSIZE > 0 +static unsigned char loop_serial_out_buf0[CYGNUM_IO_SERIAL_LOOP_SERIAL0_BUFSIZE]; +static unsigned char loop_serial_in_buf0[CYGNUM_IO_SERIAL_LOOP_SERIAL0_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_LOOP_SERIAL1 +static loop_serial_info loop_serial_info1 = { + &fifo1, + &fifo0 +}; +#if CYGNUM_IO_SERIAL_LOOP_SERIAL1_BUFSIZE > 0 +static unsigned char loop_serial_out_buf1[CYGNUM_IO_SERIAL_LOOP_SERIAL1_BUFSIZE]; +static unsigned char loop_serial_in_buf1[CYGNUM_IO_SERIAL_LOOP_SERIAL1_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL1 + +//------------------------------------------------------------------------- +// Channel descriptions: + +#ifdef CYGPKG_IO_SERIAL_LOOP_POLLED_MODE +#define SIZEOF_BUF(_x_) 0 +#else +#define SIZEOF_BUF(_x_) sizeof(_x_) +#endif + +#ifdef CYGPKG_IO_SERIAL_LOOP_SERIAL0 +#if CYGNUM_IO_SERIAL_LOOP_SERIAL0_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(loop_serial_channel0, + loop_serial_funs, + loop_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_LOOP_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &loop_serial_out_buf0[0], + SIZEOF_BUF(loop_serial_out_buf0), + &loop_serial_in_buf0[0], + SIZEOF_BUF(loop_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(loop_serial_channel0, + loop_serial_funs, + loop_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_LOOP_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_LOOP_SERIAL1 +#if CYGNUM_IO_SERIAL_LOOP_SERIAL1_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(loop_serial_channel1, + loop_serial_funs, + loop_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_LOOP_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &loop_serial_out_buf1[0], + SIZEOF_BUF(loop_serial_out_buf1), + &loop_serial_in_buf1[0], + SIZEOF_BUF(loop_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(loop_serial_channel1, + loop_serial_funs, + loop_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_LOOP_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL1 + +//------------------------------------------------------------------------- +// And finally, the device table entries: + +#ifdef CYGPKG_IO_SERIAL_LOOP_SERIAL0 +DEVTAB_ENTRY(loop_serial_io0, + CYGDAT_IO_SERIAL_LOOP_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + loop_serial_init, + loop_serial_lookup, // Serial driver may need initializing + &loop_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_LOOP_SERIAL1 +DEVTAB_ENTRY(loop_serial_io1, + CYGDAT_IO_SERIAL_LOOP_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + loop_serial_init, + loop_serial_lookup, // Serial driver may need initializing + &loop_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_LOOP_SERIAL1 + +//------------------------------------------------------------------------- + +static bool +loop_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ +// loop_serial_info *loop_chan = (loop_serial_info *)chan->dev_priv; + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +//------------------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. + +bool loop_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; +// loop_serial_info *loop_chan = (loop_serial_info *)chan->dev_priv; + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + +#ifndef CYGPKG_IO_SERIAL_LOOP_POLLED_MODE + + // Set up alarm for feeding data back into channels + + cyg_alarm_create( cyg_real_time_clock(), + alarm_handler, + 0, + &alarm_handle, + &alarm_obj); + + cyg_alarm_initialize( alarm_handle, 1, 1 ); + +#endif + + loop_serial_config_port(chan, &chan->config, true); + + return true; +} + +//------------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) + +static Cyg_ErrNo +loop_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +//------------------------------------------------------------------------- +// Return 'true' if character is sent to device + +bool +loop_serial_putc(serial_channel *chan, unsigned char c) +{ + loop_serial_info *loop_chan = (loop_serial_info *)chan->dev_priv; + + struct fifo *f = loop_chan->write_fifo; + + if( f->num == FIFO_SIZE ) + return false; + + f->buf[f->tail] = c; + f->num++; + f->tail++; + if( f->tail == sizeof(f->buf) ) + f->tail = 0; + + return true; +} + +//------------------------------------------------------------------------- + +unsigned char +loop_serial_getc(serial_channel *chan) +{ + unsigned char c; + loop_serial_info *loop_chan = (loop_serial_info *)chan->dev_priv; + + struct fifo *f = loop_chan->read_fifo; + + while( f->num == 0 ) + continue; + + c = f->buf[f->head]; + f->num--; + f->head++; + if( f->head == sizeof(f->buf) ) + f->head = 0; + + return c; +} + +//------------------------------------------------------------------------- + +static Cyg_ErrNo +loop_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != loop_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------------------------------------------- +// Enable the transmitter on the device + +static void +loop_serial_start_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_LOOP_POLLED_MODE + loop_serial_info *loop_chan = (loop_serial_info *)chan->dev_priv; + + loop_chan->write_fifo->tx_enable = true; + + (chan->callbacks->xmt_char)(chan); +#endif +} + +//------------------------------------------------------------------------- +// Disable the transmitter on the device + +static void +loop_serial_stop_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_LOOP_POLLED_MODE + loop_serial_info *loop_chan = (loop_serial_info *)chan->dev_priv; + + loop_chan->write_fifo->tx_enable = false; + +#endif +} + +//------------------------------------------------------------------------- + +static void alarm_handler(cyg_handle_t alarm, cyg_addrword_t data) +{ + serial_channel *chan0 = &loop_serial_channel0; + serial_channel *chan1 = &loop_serial_channel1; + + while( fifo0.num ) + { + // Data ready for delivery to serial1 + + struct fifo *f = &fifo0; + char c; + + c = f->buf[f->head]; + f->num--; + f->head++; + if( f->head == sizeof(f->buf) ) + f->head = 0; + + (chan1->callbacks->rcv_char)(chan1, c); + if( f->tx_enable ) + (chan0->callbacks->xmt_char)(chan0); + } + + while( fifo1.num ) + { + // Data ready for delivery to serial0 + + struct fifo *f = &fifo1; + char c; + + c = f->buf[f->head]; + f->num--; + f->head++; + if( f->head == sizeof(f->buf) ) + f->head = 0; + + (chan0->callbacks->rcv_char)(chan0, c); + if( f->tx_enable ) + (chan1->callbacks->xmt_char)(chan1); + } + + + +} + + +#endif // CYGPKG_IO_SERIAL_LOOP + +//------------------------------------------------------------------------- +// EOF loop.c diff --git a/ecos/packages/devs/serial/m68k/mcf52xx/current/ChangeLog b/ecos/packages/devs/serial/m68k/mcf52xx/current/ChangeLog new file mode 100644 index 0000000..dea863b --- /dev/null +++ b/ecos/packages/devs/serial/m68k/mcf52xx/current/ChangeLog @@ -0,0 +1,115 @@ +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl, doc/mcf52xx_ser.sgml, src/ser_mcf52xx.c: + minor clean-ups. + +2008-05-26 Bart Veer <bartv@ecoscentric.com> + + * src/ser_mcf52xx.c: provide more flow control capability + information to higher levels. + +2006-09-25 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx_ser.sgml: update docs to reflect changes in the + hal/m68k hierarchy. + + * src/ser_mcf52xx.c: Motorola -> Freescale. + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * src/ser_mcf52xx.c: update to use new var_io.h definitions. + +2006-09-05 Bart Veer <bartv@ecoscentric.com> + + * src/ser_mcf52xx.c, cdl/ser_mcf52xx.cdl: + Trigger off options/components in the processor HAL rather than + on interfaces in the device driver. The latter were essentially + duplicates of the former so no longer served a purpose. + +2006-07-10 Bart Veer <bartv@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl, src/ser_mcf52xx.c: separate out RTS/CTS + handling. Cope with various changes in the mcf52xx variant HAL for + better support of the ColdFire range of processors. + +2006-03-10 John Dallaway <jld@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl: Add reference to package documentation. + +2004-08-03 John Dallaway <jld@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl: Use any port for serial testing. + +2004-08-02 Bart Veer <bartv@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl, src/ser_mcf52xx.c, doc/mcf52xx_ser.sgml: + Make it easier for platform HALs to control what functionality is + enabled, e.g. whether or not RTS/CTS are connected. + +2004-03-17 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx_ser.sgml: update following port to mcf5282 + +2004-03-08 Bart Veer <bartv@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl: look for default ISR priorities supplied by + the HAL. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * src/ser_mcf52xx.c, cdl/ser_mcf52xx.cdl: add support for an + optional third UART. + +2003-08-01 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx_ser.sgml: Document use of rx fifo + + * src/ser_mcf52xx.c: + Use rx fifo where available. Add some statistics gathering. + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx_ser.sgml: fix various typos etc. + +2003-07-18 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx_ser.sgml: Add documentation. + +2003-07-10 Bart Veer <bartv@ecoscentric.com> + + * src/ser_mcf52xx.c (mcf52xx_serial_set_config): + Reject DSR/DTR flow control more gracefully. + +2003-07-08 Bart Veer <bartv@ecoscentric.com> + + * cdl/ser_mcf52xx.cdl, src/ser_mcf52xx.c: + Add support for hardware handshaking. + Make better use of the fifos to reduce interrupts. + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/m68k/mcf52xx/current/cdl/ser_mcf52xx.cdl b/ecos/packages/devs/serial/m68k/mcf52xx/current/cdl/ser_mcf52xx.cdl new file mode 100644 index 0000000..e6db120 --- /dev/null +++ b/ecos/packages/devs/serial/m68k/mcf52xx/current/cdl/ser_mcf52xx.cdl @@ -0,0 +1,186 @@ +# ==================================================================== +# +# ser_mcfxxxx.cdl +# +# Serial driver for mcfxxxx coldfire processors +# +# ==================================================================== +# ####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later +# version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with eCos; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered by +# the GNU General Public License. However the source code for this file +# must still be made available in accordance with section (3) of the GNU +# General Public License v2. +# +# This exception does not invalidate any other reasons why a work based +# on this file might be covered by the GNU General Public License. +# ------------------------------------------- +# ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Contributors: +# Date: 2003-06-4 +# +#####DESCRIPTIONEND#### +# ==================================================================== + +cdl_package CYGPKG_DEVS_SERIAL_MCFxxxx { + display "Serial driver for the coldfire mcfxxxx family" + doc ref/devs-ser-m68k-mcfxxxx-part.html + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_M68K_MCFxxxx + + requires CYGPKG_ERROR + + description " + This package provides a serial device driver for the on-chip + UART's in MCFxxxx ColdFire processors." + compile -library=libextras.a ser_mcf52xx.c + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/devs_serial_mcfxxxx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + # Support up to three on-chip UART's. The number varies between + # processor variants, and on some platforms some of the UART's + # may not be connected to save board space or to obtain more + # GPIO lines. Also h/w handshake lines may or may not be connected. + for { set ::uart 0 } { $::uart < 3 } { incr ::uart } { + + cdl_component CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL[set ::uart] { + display "Allow access to the on-chip uart[set ::uart] via a serial driver" + flavor bool + active_if CYGHWR_HAL_M68K_MCFxxxx_UART[set ::uart] + default_value 1 + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + If the application needs to access the on-chip uart[set ::uart] + via an eCos serial driver then this option should be enabled." + + cdl_option CYGDAT_DEVS_SERIAL_MCFxxxx_SERIAL[set ::uart]_NAME { + display "Device name for uart [set ::uart]" + flavor data + default_value [format {"\"/dev/ser%d\""} $::uart] + description " + This option controls the name that an eCos application + should use to access this device via cyg_io_lookup(), + open(), or similar calls." + } + + cdl_option CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL[set ::uart]_ISR_PRIORITY { + display "Interrupt priority for this device" + flavor data + default_value is_loaded(CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_UART[set ::uart]) ? \ + CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_UART[set ::uart] : \ + CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN + legal_values CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX + description " + By default uart [set ::uart] is given an interrupt priority of 1, + in other words it will interrupt at IPL level 1. The device can + be made to interrupt at a higher priority but this is rarely + useful since nearly all processing happens at DSR level rather + than ISR level." + } + + cdl_option CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL[set ::uart]_BAUD { + display "Default baud rate for uart [set ::uart]" + flavor data + default_value 38400 + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + description "This option determines the initial baud rate for uart [set ::uart]" + } + + cdl_option CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL[set ::uart]_BUFSIZE { + display "Buffer size for the uart [set ::uart] serial driver" + flavor booldata + default_value 128 + legal_values 16 to 8192 + description " + Typically the device driver will run in interrupt mode and will + perform some buffering of both incoming and outgoing data. This + option controls the size of both input and output buffer. If + the device will be used only in polled mode then this option + can be disabled." + } + } + } + + cdl_component CYGPKG_DEVS_SERIAL_MCFxxxx_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_DEVS_SERIAL_MCFxxxx_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_DEVS_SERIAL_MCFxxxx_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } + + cdl_component CYGPKG_DEVS_SERIAL_MCFxxxx_TESTING { + display "Testing parameters" + flavor none + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"mcfxxxx\"" + } + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { "\"/dev/ser0\"" } + } + cdl_option CYGPRI_SER_TEST_TTY_DEV { + display "TTY device used for testing" + flavor data + default_value { "\"/dev/tty0\"" } + } + } +} diff --git a/ecos/packages/devs/serial/m68k/mcf52xx/current/doc/mcf52xx_ser.sgml b/ecos/packages/devs/serial/m68k/mcf52xx/current/doc/mcf52xx_ser.sgml new file mode 100644 index 0000000..62483ca --- /dev/null +++ b/ecos/packages/devs/serial/m68k/mcf52xx/current/doc/mcf52xx_ser.sgml @@ -0,0 +1,208 @@ +<!-- DOCTYPE refentry PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- mcfxxxx_ser.sgml --> +<!-- --> +<!-- mcfxxxx serial driver documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/07/15 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="devs-ser-m68k-mcfxxxx-part"><title>Freescale MCFxxxx Serial Driver</title> + +<refentry id="devs-ser-m68k-mcfxxxx"> + <refmeta> + <refentrytitle>MCFxxxx Serial Driver</refentrytitle> + </refmeta> + <refnamediv> + <refname><varname>CYGPKG_DEVS_SERIAL_MCFxxxx</varname></refname> + <refpurpose>eCos Support for the MCFxxxx On-chip Serial Devices</refpurpose> + </refnamediv> + + <refsect1 id="devs-ser-m68k-mcfxxxx-description"><title>Description</title> + <para> +All members of the Freescale MCFxxxx ColdFire family of processors +contain a number of on-chip UARTs for serial communication. They all +use very similar hardware. There are some variations such as different +fifo sizes, and some processors contain extra functionality such as +autobaud detection, but a single eCos device driver can cope with most +of these differences. The +<varname>CYGPKG_DEVS_SERIAL_MCFxxxx</varname> package provides this +driver. It will use definitions provided by the variant HAL +<varname>CYGPKG_HAL_M68K_MCFxxxx</varname>, the processor HAL and the +platform HAL. + </para> + <para> +The driver provides partial support for hardware flow control and for +serial line status. Only CTS/RTS hardware flow control is supported +since the UART does not provide DTR/DSR lines. Similarly only line +breaks, and certain communication errors are supported for line status +since the UART does not provide other lines such as DCD or RI. On some +platforms it should be possible to emulate these lines using GPIO +pins, but currently there is no support for this. + </para> + <para> +Once application code accesses a UART through the serial driver, for +example by opening a device <literal>/dev/ser0</literal>, the driver +assumes that it has sole access to the hardware. This means that the +UART should not be used for any other purpose, for example HAL +diagnostics or gdb debug traffic. Instead such traffic has to go via +another communication channel such as ethernet. + </para> + </refsect1> + + <refsect1 id="devs-ser-m68k-mcfxxxx-config"><title>Configuration Options</title> + <para> + The MCFxxxx serial driver should be loaded automatically when +selecting a platform containing a suitable processor, and it should +never be necessary to load it explicitly. The driver as a whole is +inactive unless the generic serial support, +<varname>CYGPKG_IO_SERIAL_DEVICES</varname>, is enabled. Exactly which +UART or UARTs are accessible on a given platform is determined by the +platform because even if the processor contains a UART the platform +may not provide a connector. Support for a given UART, say uart0, is +controlled by a configuration option +<varname>CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL0</varname>. The device +driver configuration option in turn depends on a HAL configuration +option <varname>CYGHWR_HAL_M68K_MCFxxxx_UART0</varname> to indicate +that the UART is actually present and connected on the target +hardware. If a given UART is of no interest to an application +developer then it is possible to save some memory by disabling this +option. + </para> + <para> +For every enabled UART there are a further four configuration options: + </para> + <variablelist> + <varlistentry> + <term><varname>CYGDAT_DEVS_SERIAL_MCFxxxx_SERIAL0_NAME</varname></term> + <listitem><para> +Each serial device should have a unique name so that application code +can open it. The default device names are <literal>/dev/ser0</literal>, +<literal>/dev/ser1</literal>, and so on. It is only necessary to change +these if the platform contains additional off-chip UARTs with clashing +names. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_ISR_PRIORITY</varname></term> + <listitem><para> +By default the driver arranges for the UARTs to interrupt at a low +interrupt priority. Usually there will be no need to change this +because the driver does not actually do very much processing at ISR +level, and anyway UARTs are not especially fast devices so do not +require immediate attention. On some Coldfires with MCF5282-compatible +interrupt controllers care has to be taken that all interrupt +priorities are unique. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BAUD</varname></term> + <listitem><para> +Each UART will be initialized to a given baud rate. The default baud +rate is 38400 because in most scenarios this is fast enough yet +does not suffer from excess data corruption. Lower baud rates can be +used if the application will operate in an electrically noisy +environment, or higher baud rates up to 230400 can be used if +38400 does not provide sufficient throughput. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BUFSIZE</varname></term> + <listitem><para> +The serial driver will maintain software buffers for incoming and +outgoing data. The former allows data to continue to arrive even if +the application is still busy processing the previous transfer, and +thus potentially improves throughput. The latter allows the +application to transmit data without immediately blocking until the +transfer is complete, often eliminating the need for a separate +thread. The size of these buffers can be controlled via this +configuration option, or alternatively these buffers can be disabled +completely to save memory. + </para></listitem> + </varlistentry> + </variablelist> + <para> +There are additional options in the generic serial I/O package +<varname>CYGPKG_IO_SERIAL</varname> which will affect this driver. For +example <varname>CYGPKG_IO_SERIAL_FLOW_CONTROL</varname> and its +sub-options determine what flow control mechanism (if any) should be +used. + </para> + <para> +This package also defines some configuration options related to +testing. Usually these options are of no interest to application +developers and can be ignored. + </para> + </refsect1> + + <refsect1 id="devs-ser-m68k-mcfxxxx-porting"><title>Porting</title> + <para> +The generic driver needs some information from other packages about +the exact hardware, for example how many UARTs are available and where +in memory they can be accessed. + </para> + <orderedlist> + <listitem><para> +Another package, usually the processor HAL, should provide one or more +options <varname>CYGHWR_HAL_M68K_MCFxxxx_UART0</varname>, +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART1</varname> or +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART2</varname>. These may be +calculated or user-configurable depending on the processor. + </para></listitem> + <listitem><para> +The device driver will also look for symbol definitions +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS</varname> and +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0_CTS</varname>, and the +equivalents for the other UARTs, to determine whether or not these +handshake lines are connected. These may be configuration options or +they may be statically defined in a HAL I/O header file. The platform +HAL should also implement the generic serial package's interface +<varname>CYGINT_IO_SERIAL_FLOW_CONTROL_HW</varname> if appropriate. + </para></listitem> + <listitem><para> +If RTS is connected then the driver will also look for a symbol +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS</varname>. This +enables partial support for RS485 communication in that the device +driver will arrange for the RTS line to be asserted during a transmit. +The driver has no support for more advanced RS485 functionality such +as multidrop. + </para></listitem> + </orderedlist> + <para> +In addition the driver assumes the standard MCFxxxx HAL macros are +defined for the UART base addresses and the registers. The driver +primarily targets MCF5282-compatible UARTs but there is also some +support for functionality available on other members of the Coldfire +range, for example the MCF5272's fractional baud rate support. + </para> + </refsect1> + +</refentry> +</part> diff --git a/ecos/packages/devs/serial/m68k/mcf52xx/current/src/ser_mcf52xx.c b/ecos/packages/devs/serial/m68k/mcf52xx/current/src/ser_mcf52xx.c new file mode 100644 index 0000000..2a0e7e3 --- /dev/null +++ b/ecos/packages/devs/serial/m68k/mcf52xx/current/src/ser_mcf52xx.c @@ -0,0 +1,850 @@ +//========================================================================== +// +// ser_mcfxxxx.c +// +// Serial driver for Freescale coldfire processors +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Contributors: bartv +// Date: 2003-06-04 +// Purpose: support coldfire on-chip uart's +// Description: The various coldfire mcfxxxx processors all use the same +// basic UART. There are some variations, e.g. different +// fifo sizes, autobaud capability, and calculating baud +// rates requires platform-specific knowledge such as the +// cpu speed. Also there is no standardization of base +// addresses or interrupt vectors. Never the less a single +// driver should be able to support most devices, with +// various processor-specific or platform-specific #define's +// and other support. +// +//####DESCRIPTIONEND#### +//========================================================================== + +// NOTE: some platforms may use GPIO pins for other modem lines such as +// ring and DSR/DTR/DCD. This code could check for #ifdef HAL_MCF52xx_UART_SET_DCD() +// and incorporate support from the platform HAL. + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include CYGBLD_HAL_VARIANT_H +#include CYGBLD_HAL_PROC_H +#include CYGBLD_HAL_PLATFORM_H +#include <pkgconf/devs_serial_mcfxxxx.h> + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_io.h> + +//#define MCFxxxx_SERIAL_STATS 1 +#undef MCFxxxx_SERIAL_STATS + +#ifdef MCFxxxx_SERIAL_STATS +# define INCR_STAT(_info_, _field_, _amount_) \ + CYG_MACRO_START \ + (_info_)->_field_ += _amount_; \ + CYG_MACRO_END +#else +# define INCR_STAT(_info_, _field_, _amount_) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// ---------------------------------------------------------------------------- +// devtab entries for the supported devices. + +static bool mcfxxxx_serial_init(struct cyg_devtab_entry*); +static Cyg_ErrNo mcfxxxx_serial_lookup(struct cyg_devtab_entry**, struct cyg_devtab_entry*, const char*); +static Cyg_ErrNo mcfxxxx_serial_set_config(serial_channel*, cyg_uint32, const void*, cyg_uint32*); +static bool mcfxxxx_serial_putc(serial_channel*, unsigned char); +static unsigned char mcfxxxx_serial_getc(serial_channel*); +static void mcfxxxx_serial_start_xmit(serial_channel*); +static void mcfxxxx_serial_stop_xmit(serial_channel*); +static cyg_uint32 mcfxxxx_serial_isr(cyg_vector_t, cyg_addrword_t); +static void mcfxxxx_serial_dsr(cyg_vector_t, cyg_ucount32, cyg_addrword_t); + +typedef struct mcfxxxx_serial_info { + cyg_uint8* base; + cyg_vector_t isr_vec; + int isr_priority; + cyg_uint8 uimr_shadow; + cyg_uint8 umr1_shadow; + cyg_uint8 umr2_shadow; + cyg_uint8 flags; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +#ifdef MCFxxxx_SERIAL_STATS + cyg_uint32 isr_count; + cyg_uint32 dsr_count; + cyg_uint32 rx_bytes; + cyg_uint32 tx_bytes; + cyg_uint32 rx_errors; +#endif +} mcfxxxx_serial_info; + +#define MCFxxxx_SERIAL_RTS (0x01 << 0) +#define MCFxxxx_SERIAL_CTS (0x01 << 1) +#define MCFxxxx_SERIAL_RS485_RTS (0x01 << 2) + +static SERIAL_FUNS(mcfxxxx_serial_funs, + mcfxxxx_serial_putc, + mcfxxxx_serial_getc, + mcfxxxx_serial_set_config, + mcfxxxx_serial_start_xmit, + mcfxxxx_serial_stop_xmit + ); + + +#ifdef CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL0 +static mcfxxxx_serial_info mcfxxxx_serial0_info = { + base: (cyg_uint8*)HAL_MCFxxxx_UART0_BASE, + isr_vec: CYGNUM_HAL_ISR_UART0, + isr_priority: CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_ISR_PRIORITY, +#ifdef MCFxxxx_SERIAL_STATS + isr_count: 0, + dsr_count: 0, + rx_bytes: 0, + tx_bytes: 0, + rx_errors: 0, +#endif + flags: +#if defined(CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS) + MCFxxxx_SERIAL_RS485_RTS | +#elif defined(CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS) + MCFxxxx_SERIAL_RTS | +#endif +#if defined(CYGHWR_HAL_M68K_MCFxxxx_UART0_CTS) + MCFxxxx_SERIAL_CTS | +#endif + 0x00 +}; + +# ifdef CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BUFSIZE +static unsigned char mcfxxxx_serial0_tx_buf[CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BUFSIZE]; +static unsigned char mcfxxxx_serial0_rx_buf[CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mcfxxxx_serial0_chan, + mcfxxxx_serial_funs, + mcfxxxx_serial0_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + mcfxxxx_serial0_tx_buf, CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BUFSIZE, + mcfxxxx_serial0_rx_buf, CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BUFSIZE + ); +#else +static SERIAL_CHANNEL(mcfxxxx_serial0_chan, + mcfxxxx_serial_funs, + mcfxxxx_serial0_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +# endif + +DEVTAB_ENTRY(mcfxxxx_serial0_devtab, + CYGDAT_DEVS_SERIAL_MCFxxxx_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mcfxxxx_serial_init, + mcfxxxx_serial_lookup, // Serial driver may need initializing + &mcfxxxx_serial0_chan + ); +#endif + +#ifdef CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL1 +static mcfxxxx_serial_info mcfxxxx_serial1_info = { + base: (cyg_uint8*)HAL_MCFxxxx_UART1_BASE, + isr_vec: CYGNUM_HAL_ISR_UART1, + isr_priority: CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_ISR_PRIORITY, +#ifdef MCFxxxx_SERIAL_STATS + isr_count: 0, + dsr_count: 0, + rx_bytes: 0, + tx_bytes: 0, + rx_errors: 0, +#endif + flags: +#if defined(CYGHWR_HAL_M68K_MCFxxxx_UART1_RS485_RTS) + MCFxxxx_SERIAL_RS485_RTS | +#elif defined(CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS) + MCFxxxx_SERIAL_RTS | +#endif +#if defined(CYGHWR_HAL_M68K_MCFxxxx_UART1_CTS) + MCFxxxx_SERIAL_CTS | +#endif + 0x00 +}; + +# ifdef CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BUFSIZE +static unsigned char mcfxxxx_serial1_tx_buf[CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BUFSIZE]; +static unsigned char mcfxxxx_serial1_rx_buf[CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mcfxxxx_serial1_chan, + mcfxxxx_serial_funs, + mcfxxxx_serial1_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + mcfxxxx_serial1_tx_buf, CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BUFSIZE, + mcfxxxx_serial1_rx_buf, CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BUFSIZE + ); +#else +static SERIAL_CHANNEL(mcfxxxx_serial1_chan, + mcfxxxx_serial_funs, + mcfxxxx_serial1_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +# endif + +DEVTAB_ENTRY(mcfxxxx_serial1_devtab, + CYGDAT_DEVS_SERIAL_MCFxxxx_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mcfxxxx_serial_init, + mcfxxxx_serial_lookup, // Serial driver may need initializing + &mcfxxxx_serial1_chan + ); +#endif + +#ifdef CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL2 +static mcfxxxx_serial_info mcfxxxx_serial2_info = { + base: (cyg_uint8*)HAL_MCFxxxx_UART2_BASE, + isr_vec: CYGNUM_HAL_ISR_UART2, + isr_priority: CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_ISR_PRIORITY, +#ifdef MCFxxxx_SERIAL_STATS + isr_count: 0, + dsr_count: 0, + rx_bytes: 0, + tx_bytes: 0, + rx_errors: 0, +#endif + flags: +#if defined(CYGHWR_HAL_M68K_MCFxxxx_UART2_RS485_RTS) + MCFxxxx_SERIAL_RS485_RTS | +#elif defined(CYGHWR_HAL_M68K_MCFxxxx_UART2_RTS) + MCFxxxx_SERIAL_RTS | +#endif +#if defined(CYGHWR_HAL_M68K_MCFxxxx_UART2_CTS) + MCFxxxx_SERIAL_CTS | +#endif + 0x00 +}; + +# ifdef CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BUFSIZE +static unsigned char mcfxxxx_serial2_tx_buf[CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BUFSIZE]; +static unsigned char mcfxxxx_serial2_rx_buf[CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mcfxxxx_serial2_chan, + mcfxxxx_serial_funs, + mcfxxxx_serial2_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + mcfxxxx_serial2_tx_buf, CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BUFSIZE, + mcfxxxx_serial2_rx_buf, CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BUFSIZE + ); +#else +static SERIAL_CHANNEL(mcfxxxx_serial2_chan, + mcfxxxx_serial_funs, + mcfxxxx_serial2_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +# endif + +DEVTAB_ENTRY(mcfxxxx_serial2_devtab, + CYGDAT_DEVS_SERIAL_MCFxxxx_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mcfxxxx_serial_init, + mcfxxxx_serial_lookup, // Serial driver may need initializing + &mcfxxxx_serial2_chan + ); +#endif + +// ---------------------------------------------------------------------------- + +static cyg_uint32 mcfxxxx_baud_rates[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 134, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400 // 230400 +}; + +static bool +mcfxxxx_serial_config(serial_channel* chan, cyg_serial_info_t* config, cyg_bool init) +{ + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + cyg_uint8* base = info->base; + + if (init) { +#if defined(CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL0) && defined(HAL_MCFxxxx_UART0_PROC_INIT) + if (info == &mcfxxxx_serial0_info) { + HAL_MCFxxxx_UART0_PROC_INIT(); + } +#endif +#if defined(CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL1) && defined(HAL_MCFxxxx_UART1_PROC_INIT) + if (info == &mcfxxxx_serial1_info) { + HAL_MCFxxxx_UART1_PROC_INIT(); + } +#endif +#if defined(CYGPKG_DEVS_SERIAL_MCFxxxx_SERIAL2) && defined(HAL_MCFxxxx_UART2_PROC_INIT) + if (info == &mcfxxxx_serial2_info) { + HAL_MCFxxxx_UART2_PROC_INIT(); + } +#endif + // Various resets to get the UART in a known good state + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCR]), HAL_MCFxxxx_UARTx_UCR_MISC_RR); + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCR]), HAL_MCFxxxx_UARTx_UCR_MISC_RT); + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCR]), HAL_MCFxxxx_UARTx_UCR_MISC_RES); + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCR]), HAL_MCFxxxx_UARTx_UCR_MISC_RBCI); + + // Initialize the interrupt mask register. We want to trigger on rxrdy() and + // optionally on breaks. Tx interrupts are not enabled by default, only + // when a transmit is in progress. + // + // Some processors may define HAL_MCFxxxx_UARTx_UIMR_RXFTO which can be + // used instead of RXRDY, getting an interrupt only when the fifo is full + // or when 64 bit times have elapsed without new data. This reduces the + // number of rx interrupts by e.g. a factor of 12. It is not without + // penalty: if higher-level code could start processing data before the + // fifo has filled up then the latency is increased significantly; even + // if a whole packet needs to be received first, unless the packet size + // maps cleanly on to fifo boundaries the latency is increased by the + // timeout; if software flow control is in use then this side may not + // respond to XON/XOFF bytes for a while. For now rx fifos are used + // by default if available, although this should probably be made configurable. + info->uimr_shadow = 0; + if (chan->out_cbuf.len != 0) { +# if defined(HAL_MCFxxxx_UARTx_UIMR_RXFIFO) && defined(HAL_MCFxxxx_UARTx_UIMR_RXFTO) && defined(HAL_MCFxxxx_UARTx_URF) + info->uimr_shadow = HAL_MCFxxxx_UARTx_UIMR_RXFTO | HAL_MCFxxxx_UARTx_UIMR_RXFIFO; +# else + info->uimr_shadow = HAL_MCFxxxx_UARTx_UIMR_RXRDY; +#endif + } +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + info->uimr_shadow |= HAL_MCFxxxx_UARTx_UIMR_DB; +#endif + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UIMR]), info->uimr_shadow); + + // If the hardware supports tx fifo control, set it up so that + // interrupts only occur when the fifo is more than 75% empty. + // That cuts down on the number of interrupts without + // affecting performance. The processor should service the interrupt + // and replenish the fifo before the remaining bytes go out. +#ifdef HAL_MCFxxxx_UARTx_UTF + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UTF]), HAL_MCFxxxx_UARTx_UTF_TXS_75); +#endif + // Ditto for rx fifo, but trigger on 50%. That is a compromise between + // latency and efficiency. +#ifdef HAL_MCFxxxx_UARTx_URF + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_URF]), HAL_MCFxxxx_UARTx_URF_RXS_50); +#endif + // Always use the internal prescaled CLKIN. + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCSR]), HAL_MCFxxxx_UARTx_UCSR_RCS_CLKIN | HAL_MCFxxxx_UARTx_UCSR_TCS_CLKIN); + + // Hardware flow control. + // + // Default: no TXRTS, no TXCTS, no RXRTS, no configurable RTS fifo level + info->umr1_shadow = 0x00; + info->umr2_shadow = 0x00; + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UACR]), 0x00); + + // CTS, used to throttle the transmitter automatically. This involves + // setting the TXCTS bit. However it is not the default, h/w flow control + // has to be explicitly enabled by a set_config() call. + + // RTS. This may not be connected at all, or it may be used + // for h/w control of an RS485 transceiver, or it may be used + // for RS232 handshaking. If the latter then the uart provides + // automatic support for throttling the other side when the + // fifo starts filling up. + if (info->flags & MCFxxxx_SERIAL_RS485_RTS) { + info->umr2_shadow = HAL_MCFxxxx_UARTx_UMR2_TXRTS; + } else if (info->flags & MCFxxxx_SERIAL_RTS) { + // RS232 h/w flow control. + // See if the processor supports configurable RTS levels. +# ifdef HAL_MCFxxxx_UARTx_UACR_RTSL_25 + // Set up RTS to change when the fifo is 25% full. This means the + // processor can accept another 18 bytes, more than the 16-byte + // transmit fifo in a typical PC uart. Increasing the RTS level to + // any more than this may cause overruns. + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UACR]), HAL_MCFxxxx_UARTx_UACR_RTSL_25); +# else + // Only RxRTS mode is supported, so use it. + info->umr1_shadow = HAL_MCFxxxx_UARTx_UMR1_RXRTS; +# endif + // If RTS is connected assert it here, allowing the other side to transmit + // data. This may be too early since the h/w is not fully set up yet, but + // we only want to do this during init. + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UOP1]), HAL_MCFxxxx_UARTx_UOP_RTS); + } else { + // RTS is not connected at all. + } + + // Enable both RX and TX + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCR]), HAL_MCFxxxx_UARTx_UCR_TC_TE | HAL_MCFxxxx_UARTx_UCR_RC_RE); + } + + info->umr1_shadow &= ~(HAL_MCFxxxx_UARTx_UMR1_BC_MASK | HAL_MCFxxxx_UARTx_UMR1_PM_MASK); + switch (config->word_length) { + case CYGNUM_SERIAL_WORD_LENGTH_5: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_BC_5; + break; + case CYGNUM_SERIAL_WORD_LENGTH_6: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_BC_6; + break; + case CYGNUM_SERIAL_WORD_LENGTH_7: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_BC_7; + break; + case CYGNUM_SERIAL_WORD_LENGTH_8: + default: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_BC_8; + break; + } + switch (config->parity) { + case CYGNUM_SERIAL_PARITY_EVEN: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_PM_WITH; + break; + case CYGNUM_SERIAL_PARITY_ODD: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_PM_WITH | HAL_MCFxxxx_UARTx_UMR1_PT; + break; + case CYGNUM_SERIAL_PARITY_MARK: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_PM_FORCE | HAL_MCFxxxx_UARTx_UMR1_PT; + break; + case CYGNUM_SERIAL_PARITY_SPACE: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_PM_FORCE; + break; + case CYGNUM_SERIAL_PARITY_NONE: + default: + info->umr1_shadow |= HAL_MCFxxxx_UARTx_UMR1_PM_NO; + break; + } + info->umr2_shadow &= ~HAL_MCFxxxx_UARTx_UMR2_SB_MASK; + switch (config->stop) { + case CYGNUM_SERIAL_STOP_2: + info->umr2_shadow |= HAL_MCFxxxx_UARTx_UMR2_SB_2; + break; + case CYGNUM_SERIAL_STOP_1_5: + info->umr2_shadow |= (CYGNUM_SERIAL_WORD_LENGTH_5 == config->word_length) ? 0x07 : 0x08; + break; + case CYGNUM_SERIAL_STOP_1: + default: + info->umr2_shadow |= (CYGNUM_SERIAL_WORD_LENGTH_5 == config->word_length) ? 0x00 : HAL_MCFxxxx_UARTx_UMR2_SB_1; + break; + } + + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UCR]), HAL_MCFxxxx_UARTx_UCR_MISC_RMRP); + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UMR]), info->umr1_shadow); + HAL_WRITE_UINT8(&(base[HAL_MCFxxxx_UARTx_UMR]), info->umr2_shadow); + + // Set the baud rate, using a processor or platform macro. That way the + // calculation can depend on the clock speed. + HAL_MCFxxxx_UARTx_SET_BAUD(base, mcfxxxx_baud_rates[config->baud]); + + if (config != &chan->config) { + chan->config = *config; + } + + return true; +} + +// ---------------------------------------------------------------------------- +static bool +mcfxxxx_serial_init(struct cyg_devtab_entry* devtab_entry) +{ + serial_channel* chan = (serial_channel*) devtab_entry->priv; + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + + mcfxxxx_serial_config(chan, &(chan->config), true); + + if (0 != chan->out_cbuf.len) { + cyg_drv_interrupt_create(info->isr_vec, + info->isr_priority, + (cyg_addrword_t) chan, + &mcfxxxx_serial_isr, + &mcfxxxx_serial_dsr, + &(info->serial_interrupt_handle), + &(info->serial_interrupt)); + cyg_drv_interrupt_attach(info->serial_interrupt_handle); + cyg_drv_interrupt_unmask(info->isr_vec); + } + return true; +} + +// ---------------------------------------------------------------------------- +static Cyg_ErrNo +mcfxxxx_serial_lookup(struct cyg_devtab_entry** tab, struct cyg_devtab_entry* sub_tab, const char* name) +{ + serial_channel* chan = (serial_channel*) (*tab)->priv; + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// ---------------------------------------------------------------------------- +static Cyg_ErrNo +mcfxxxx_serial_set_config(serial_channel* chan, cyg_uint32 key, const void* buf, cyg_uint32* len) +{ + Cyg_ErrNo result = ENOERR; + + switch(key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + cyg_serial_info_t* config = (cyg_serial_info_t*) buf; + if (*len < sizeof(cyg_serial_info_t)) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + // DSR/DTR is never supported. + if (config->flags & (CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX)) { + result = -ENOSUPP; + config->flags &= ~(CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX); + } + // RTS/CTS may be supported, if the appropriate pins are connected. + if ((config->flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX) && !(info->flags & MCFxxxx_SERIAL_RTS)) { + result = -ENOSUPP; + config->flags &= ~CYGNUM_SERIAL_FLOW_RTSCTS_RX; + } + if ((config->flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX) && !(info->flags & MCFxxxx_SERIAL_CTS)) { + result = -ENOSUPP; + config->flags &= ~CYGNUM_SERIAL_FLOW_RTSCTS_TX; + } + if (ENOERR == result) { + if (! mcfxxxx_serial_config(chan, config, false)) { + result = -EINVAL; + } + } + break; + } +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + // RX flow control involves just the RTS line. Most of the + // work is done by the hardware depending on the state of + // the fifo. This option serves mainly to drop RTS if + // higher-level code is running out of buffer space, even + // if the fifo is not yet full. + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + cyg_uint32* flag = (cyg_uint32*) buf; + if (! (info->flags & MCFxxxx_SERIAL_RTS)) { + return -ENOSUPP; + } + if (*flag) { + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UOP0, HAL_MCFxxxx_UARTx_UOP_RTS); + } else { + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UOP1, HAL_MCFxxxx_UARTx_UOP_RTS); + } + } + break; + + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + { + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + + // DSR/DTR is never supported. + if (chan->config.flags & (CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX)) { + result = -ENOSUPP; + chan->config.flags &= ~(CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX); + } + // RTS/CTS may be supported, if the appropriate pins are connected. + if ((chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX) && !(info->flags & MCFxxxx_SERIAL_RTS)) { + result = -ENOSUPP; + chan->config.flags &= ~CYGNUM_SERIAL_FLOW_RTSCTS_RX; + } + if ((chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX) && !(info->flags & MCFxxxx_SERIAL_CTS)) { + result = -ENOSUPP; + chan->config.flags &= ~CYGNUM_SERIAL_FLOW_RTSCTS_TX; + } + + // RTS flow control for RX. Either UMR1 RxRTS or a UACR RTS trigger + // level has been set during initialization. There is little point + // changing either of these. If h/w flow control is being disabled + // then the other side should start ignoring the RTS signal, even + // if this side still thinks it is a good idea to change it depending + // on the fifo level. + + // CTS flow control for TX just involves the UMR2 TxCTS bit. + if (0 != (chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX)) { + info->umr2_shadow |= HAL_MCFxxxx_UARTx_UMR2_TXCTS; + } else { + info->umr2_shadow &= ~HAL_MCFxxxx_UARTx_UMR2_TXCTS; + } + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RMRP); + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UMR, info->umr1_shadow); + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UMR, info->umr2_shadow); + } + break; +#endif + default: + return -EINVAL; + } + + return result; +} + +// ---------------------------------------------------------------------------- +// Non-blocking send, returning true if the character was consumed. This can +// be called in both interrupt and polled mode. + +static bool +mcfxxxx_serial_putc(serial_channel* chan, unsigned char ch) +{ + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + cyg_uint8 usr; + + HAL_READ_UINT8(info->base + HAL_MCFxxxx_UARTx_USR, usr); + if (usr & HAL_MCFxxxx_UARTx_USR_TXRDY) { + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UTB, ch); + INCR_STAT(info, tx_bytes, 1); + return true; + } + return false; +} + +// Blocking receive, only called in polled mode. + +static unsigned char +mcfxxxx_serial_getc(serial_channel* chan) +{ + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + cyg_uint8 usr, data; + + do { + HAL_READ_UINT8(info->base + HAL_MCFxxxx_UARTx_USR, usr); + } while (! (usr & HAL_MCFxxxx_UARTx_USR_RXRDY)); + HAL_READ_UINT8(info->base + HAL_MCFxxxx_UARTx_URB, data); + INCR_STAT(info, rx_bytes, 1); + return data; +} + +// Start transmitting, only called in interrupt mode. This just requires +// unmasking tx interrupts, with the interrupt handling code doing the +// rest. The UIMR register is write-only so this has to go via a shadow +// copy. +// +// If the processor supports interrupting on TXFIFO then that is used +// instead, raising interrupts only if the fifo >= 75% empty. +// +// In RS485 mode it is necessary to enable RTS here so that the transceiver +// is no longer tristated. RTS will be dropped automatically at the end of the +// transmit. It is assumed that the fifo will be refilled quickly enough +// that RTS does not get dropped too soon. Arguably RTS should be raised +// in the fifo fill code, but that would introduce problems if another node +// has decided a timeout has occurred and it should start transmitting now. + +static void +mcfxxxx_serial_start_xmit(serial_channel* chan) +{ + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + CYG_INTERRUPT_STATE saved_state; + + if (info->flags & MCFxxxx_SERIAL_RS485_RTS) { + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UOP1, HAL_MCFxxxx_UARTx_UOP_RTS); + } + + HAL_DISABLE_INTERRUPTS(saved_state); +#ifdef HAL_MCFxxxx_UARTx_UIMR_TXFIFO + info->uimr_shadow |= HAL_MCFxxxx_UARTx_UIMR_TXFIFO; +#else + info->uimr_shadow |= HAL_MCFxxxx_UARTx_UIMR_TXRDY; +#endif + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UIMR, info->uimr_shadow); + HAL_RESTORE_INTERRUPTS(saved_state); +} + +// Stop transmitting, only called in interrupt mode. +static void +mcfxxxx_serial_stop_xmit(serial_channel* chan) +{ + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + CYG_INTERRUPT_STATE saved_state; + + HAL_DISABLE_INTERRUPTS(saved_state); +#ifdef HAL_MCFxxxx_UARTx_UIMR_TXFIFO + info->uimr_shadow &= ~HAL_MCFxxxx_UARTx_UIMR_TXFIFO; +#else + info->uimr_shadow &= ~HAL_MCFxxxx_UARTx_UIMR_TXRDY; +#endif + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UIMR, info->uimr_shadow); + HAL_RESTORE_INTERRUPTS(saved_state); +} + +// ---------------------------------------------------------------------------- +// The main serial I/O callbacks expect to be called in DSR context, not +// ISR context, so it is not possible to do much processing in the ISR. +// Instead everything is deferred to the DSR. + +static cyg_uint32 +mcfxxxx_serial_isr(cyg_vector_t vec, cyg_addrword_t data) +{ + serial_channel* chan = (serial_channel*) data; + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UIMR, 0); + + INCR_STAT(info, isr_count, 1); + + return CYG_ISR_CALL_DSR; +} + +// ---------------------------------------------------------------------------- +static void +mcfxxxx_serial_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel* chan = (serial_channel*) data; + mcfxxxx_serial_info* info = (mcfxxxx_serial_info*) chan->dev_priv; + cyg_uint8 uisr; + + INCR_STAT(info, dsr_count, 1); + + HAL_READ_UINT8(info->base + HAL_MCFxxxx_UARTx_UISR, uisr); + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + // This is not quite right, it will report a break event instead of a delta-break, + // so higher-level code will see two breaks instead of start-break and end-break. + // In practice that should be good enough. + // + // There is also a received-break bit in the usr register, indicating that a + // break occurred in the middle of a character. + if (uisr & HAL_MCFxxxx_UARTx_UISR_DB) { + cyg_serial_line_status_t stat; + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RBCI); + stat.value = 1; + stat.which = CYGNUM_SERIAL_STATUS_BREAK; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + + // Do not report CTS changes to higher-level code. There is no point since flow + // control should be handled by the hardware. + + if (uisr & HAL_MCFxxxx_UARTx_UISR_RXRDY) { + cyg_uint8 usr, data; + while (1) { + HAL_READ_UINT8(info->base + HAL_MCFxxxx_UARTx_USR, usr); + + if (! (usr & HAL_MCFxxxx_UARTx_USR_RXRDY)) { +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + // Now check for an overrun, so that the error is + // reported in approximately the right place in the + // data stream. It is possible that an extra byte + // or so has come in after the overrun, but that + // cannot be detected. + if (usr & HAL_MCFxxxx_UARTx_USR_OE) { + cyg_serial_line_status_t stat; + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RES); + stat.value = 1; + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat); + INCR_STAT(info, rx_errors, 1); + } +#endif + // There is no more data in the fifo, so look for transmits. + break; + } + + // RXRDY is set, so we have either a valid or a corrupted byte + // in the current fifo position. First pass the byte up the stack, + // then report the error. + HAL_READ_UINT8(info->base + HAL_MCFxxxx_UARTx_URB, data); + (chan->callbacks->rcv_char)(chan, data); + INCR_STAT(info, rx_bytes, 1); +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + if (usr & HAL_MCFxxxx_UARTx_USR_FE) { + cyg_serial_line_status_t stat; + stat.value = 1; + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat); + INCR_STAT(info, rx_errors, 1); + } + if (usr & HAL_MCFxxxx_UARTx_USR_PE) { + cyg_serial_line_status_t stat; + stat.value = 1; + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat); + INCR_STAT(info, rx_errors, 1); + } +#endif + } + } + + if (uisr & HAL_MCFxxxx_UARTx_UISR_TXRDY) { + (chan->callbacks->xmt_char)(chan); + } + + // Re-enable UART interrupts + HAL_WRITE_UINT8(info->base + HAL_MCFxxxx_UARTx_UIMR, info->uimr_shadow); +} diff --git a/ecos/packages/devs/serial/mcf52xx/mcf5272/current/ChangeLog b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/ChangeLog new file mode 100644 index 0000000..a89edc0 --- /dev/null +++ b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/ChangeLog @@ -0,0 +1,27 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mcf5272_uart.cdl: Remove irrelevant doc link. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mcf52xx/mcf5272/current/cdl/ser_mcf5272_uart.cdl b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/cdl/ser_mcf5272_uart.cdl new file mode 100644 index 0000000..282bd17 --- /dev/null +++ b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/cdl/ser_mcf5272_uart.cdl @@ -0,0 +1,141 @@ +# ==================================================================== +# +# ser_MCF5272_uart.cdl +# +# eCos serial driver for MCF5272 UART +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_MCF5272_UART { + display "Serial driver for MCF5272 UART" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + requires CYGPKG_ERROR + include_dir cyg/io + description " + This option enables the serial device drivers for the + GMPU boards." + + compile -library=libextras.a ser_mcf5272_uart.c + + #define_proc { + # puts $::cdl_system_header "/***** serial driver proc output start *****/" + # puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_MCF52xx_ser_MFC5272_uart.h>" + # puts $::cdl_system_header "/***** serial driver proc output end *****/" + #} + + + cdl_component CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 { + display "MCF5272 UART serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description "This option includes the serial device driver for the MCF5272 UART port 0." + + cdl_option CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL0_NAME { + display "Device name for the MCF5272 UART serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of serial device for the + MCF5272 UART port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD { + display "Baud rate for the MCF5272 UART serial port 0 driver" + flavor data + legal_values {1200 2400 4800 9600 14400 19200 38400 115200} + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + MCF5272 UART port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE { + display "Buffer size for the MCF5272 UART serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MCF5272 UART port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 { + display "MCF5272 UART serial port 1 driver" + flavor bool + default_value 0 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description "This option includes the serial device driver for the MCF5272 UART port 1." + + cdl_option CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL1_NAME { + display "Device name for the MCF5272 UART serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + MCF5272 UART port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BAUD { + display "Baud rate for the MCF5272 UART serial port 1 driver" + flavor data + legal_values {1200 2400 4800 9600 14400 19200 38400 115200} + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + MCF5272 UART port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE { + display "Buffer size for the MCF5272 UART serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MCF5272 UART port 1." + } + } +} + diff --git a/ecos/packages/devs/serial/mcf52xx/mcf5272/current/include/ser_mcf5272_uart.h b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/include/ser_mcf5272_uart.h new file mode 100644 index 0000000..6aa055c --- /dev/null +++ b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/include/ser_mcf5272_uart.h @@ -0,0 +1,129 @@ +#ifndef _SER_MCF5272_H_ +#define _SER_MCF5272_H_ +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/io_serial_mcf5272_uart.h> + +/* Bit level definitions and macros */ +#define MCF5272_UART_UMR1_RXRTS (0x80) +#define MCF5272_UART_UMR1_RXIRQ (0x40) +#define MCF5272_UART_UMR1_ERR (0x20) +#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5272_UART_UMR1_PM_NONE (0x10) +#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5272_UART_UMR1_PM_ODD (0x04) +#define MCF5272_UART_UMR1_PM_EVEN (0x00) +#define MCF5272_UART_UMR1_BC_5 (0x00) +#define MCF5272_UART_UMR1_BC_6 (0x01) +#define MCF5272_UART_UMR1_BC_7 (0x02) +#define MCF5272_UART_UMR1_BC_8 (0x03) + +#define MCF5272_UART_UMR2_CM_NORMAL (0x00) +#define MCF5272_UART_UMR2_CM_ECHO (0x40) +#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0) +#define MCF5272_UART_UMR2_TXRTS (0x20) +#define MCF5272_UART_UMR2_TXCTS (0x10) +#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F) +#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */ + +//#define MCF5272_UART_USR_RB (0x80) +//#define MCF5272_UART_USR_FE (0x40) +//#define MCF5272_UART_USR_PE (0x20) +//#define MCF5272_UART_USR_OE (0x10) +//#define MCF5272_UART_USR_TXEMP (0x08) +//#define MCF5272_UART_USR_TXRDY (0x04) +#define MCF5272_UART_USR_FFULL (0x02) +#define MCF5272_UART_USR_RXRDY (0x01) + +#define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */ +#define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */ + + +#define MCF5272_UART_UCR_NONE (0x00) +#define MCF5272_UART_UCR_ENAB (0x80) +#define MCF5272_UART_UCR_STOP_BREAK (0x70) +#define MCF5272_UART_UCR_START_BREAK (0x60) +#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5272_UART_UCR_RESET_ERROR (0x40) +#define MCF5272_UART_UCR_RESET_TX (0x30) +#define MCF5272_UART_UCR_RESET_RX (0x20) +#define MCF5272_UART_UCR_RESET_MR (0x10) +#define MCF5272_UART_UCR_TX_DISABLED (0x08) +#define MCF5272_UART_UCR_TX_ENABLED (0x04) +#define MCF5272_UART_UCR_RX_DISABLED (0x02) +#define MCF5272_UART_UCR_RX_ENABLED (0x01) + +#define MCF5272_UART_UCCR_COS (0x10) +#define MCF5272_UART_UCCR_CTS (0x01) + +#define MCF5272_UART_UACR_BRG (0x80) +#define MCF5272_UART_UACR_CTMS_TIMER (0x60) +#define MCF5272_UART_UACR_IEC (0x01) + +#define MCF5272_UART_UISR_COS (0x80) +#define MCF5272_UART_UISR_ABC (0x40) +#define MCF5272_UART_UISR_DB (0x04) +#define MCF5272_UART_UISR_RXRDY (0x02) +#define MCF5272_UART_UISR_TXRDY (0x01) + +#define MCF5272_UART_UIMR_COS (0x80) +#define MCF5272_UART_UIMR_ABC (0x40) +#define MCF5272_UART_UIMR_DB (0x04) +#define MCF5272_UART_UIMR_FFULL (0x02) +#define MCF5272_UART_UIMR_TXRDY (0x01) + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 +unsigned long MCF5272_uart_get_channel_0_baud_rate(void); +#endif /* CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 */ + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 +unsigned long MCF5272_uart_get_channel_1_baud_rate(void); +#endif /* CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 */ + +#endif /* _SER_MCF5272_H_ */ + diff --git a/ecos/packages/devs/serial/mcf52xx/mcf5272/current/src/ser_mcf5272_uart.c b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/src/ser_mcf5272_uart.c new file mode 100644 index 0000000..4d30a87 --- /dev/null +++ b/ecos/packages/devs/serial/mcf52xx/mcf5272/current/src/ser_mcf5272_uart.c @@ -0,0 +1,945 @@ +//========================================================================== +// +// devs/serial/MCF52xx/MCF5282 +// +// MCF5272 UART Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_memmap.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/drv_api.h> +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <pkgconf/io_serial_mcf5272_uart.h> +#include <cyg/io/ser_mcf5272_uart.h> + + +/* The UART priority level */ +#define MCF5272_UART_PRIORITY_LEVEL 2 + + +/* Autobaud states */ +typedef enum autobaud_states_t +{ + AB_IDLE = 0, /* Normal state. Autobaud process hasn't been initiated yet. */ + AB_BEGIN_BREAK, /* Detected a start of the break */ + AB_BEGIN, /* Detected the end of the break and has set up the autobaud.*/ + +}autobaud_states_t; + +#define FIELD_OFFSET(type,field) (cyg_uint32)(&(((type*)0)->field)) + +typedef struct MCF5272_uart_info_t +{ + + volatile mcf5272_sim_uart_t* base; // Base address of the UART registers + uint32 uart_vector; // UART interrupt vector number + + cyg_interrupt serial_interrupt; // Interrupt context + cyg_handle_t serial_interrupt_handle; // Interrupt handle + + volatile uint8 imr_mirror; // Interrupt mask register mirror + + cyg_serial_info_t config; // The channel configuration + + autobaud_states_t autobaud_state; // The autobaud state + + +} MCF5272_uart_info_t; + +/* Function prtoftyps for the MCF5272 UART ISR and DSR. */ +static cyg_uint32 MCF5272_uart_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void MCF5272_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + + +/* Function prototypes for the serial functions. */ +static bool MCF5272_uart_init(struct cyg_devtab_entry * tab); +static Cyg_ErrNo MCF5272_uart_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static bool MCF5272_uart_putc(serial_channel *chan, unsigned char c); +static unsigned char MCF5272_uart_getc(serial_channel *chan); +Cyg_ErrNo MCF5272_uart_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void MCF5272_uart_start_xmit(serial_channel *chan); +static void MCF5272_uart_stop_xmit(serial_channel * chan); + + +/* Declare the serial functions that are called by the common serial driver layer. */ +static SERIAL_FUNS +( + MCF5272_uart_funs, + MCF5272_uart_putc, + MCF5272_uart_getc, + MCF5272_uart_set_config, + MCF5272_uart_start_xmit, + MCF5272_uart_stop_xmit +); + + +/* Definition for channel 0 UART configuration. */ +/************************************************/ +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 + +/* Data structure contains + channel informtion. + */ +static MCF5272_uart_info_t MCF5272_uart_channel_info_0; + +/* If the channel buffer size is zero, do not include interrupt UART processing */ +#if CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE > 0 + +/* Allocated receive and transmit buffer. The size of the buffer is */ +/* configured by the configtool. */ + +static unsigned char MCF5272_uart_out_buf0[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE]; +static unsigned char MCF5272_uart_in_buf0[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE]; + +/* Channel function table. We register the UART functions here so */ +/* that uppper serial drivers can call the serial driver's routines. */ + +static SERIAL_CHANNEL_USING_INTERRUPTS( + MCF5272_uart_channel_0, + MCF5272_uart_funs, + MCF5272_uart_channel_info_0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + MCF5272_uart_out_buf0, sizeof(MCF5272_uart_out_buf0), + MCF5272_uart_in_buf0, sizeof(MCF5272_uart_in_buf0) +); +#else +/* Don't use interrupt processing for the UART. */ +static SERIAL_CHANNEL( + MCF5272_uart_channel_0, + MCF5272_uart_funs, + MCF5272_uart_channel_info_0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT +); +#endif + +DEVTAB_ENTRY( + MCF5272_uart_io0, + CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, // The table of I/O functions. + MCF5272_uart_init, // UART initialization function. + MCF5272_uart_lookup, // The UART lookup function. This function typically sets + // up the device for actual use, turing on interrupts, configuring the port, etc. + &MCF5272_uart_channel_0 +); +#endif // CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0 + +/* Definition for channel 1 UART configuration. */ +/************************************************/ + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 + + +/* Data structure contains + channel informtion. + */ +static MCF5272_uart_info_t MCF5272_uart_channel_info_1; + +/* If the channel buffer size is zero, do not include interrupt UART processing */ +#if CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE > 0 + +/* Allocated receive and transmit buffer. The size of the buffer is */ +/* configured by the configtool. */ + +static unsigned char MCF5272_uart_out_buf1[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE]; +static unsigned char MCF5272_uart_in_buf1[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE]; + +/* Channel function table. We register the UART functions here so */ +/* that uppper serial drivers can call the serial driver's routines. */ + +static SERIAL_CHANNEL_USING_INTERRUPTS( + MCF5272_uart_channel_1, + MCF5272_uart_funs, + MCF5272_uart_channel_info_1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + MCF5272_uart_out_buf1, sizeof(MCF5272_uart_out_buf1), + MCF5272_uart_in_buf1, sizeof(MCF5272_uart_in_buf1) +); + +#else +static SERIAL_CHANNEL(MCF5272_uart_channel_1, + MCF5272_uart_funs, + MCF5272_uart_channel_info_1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +DEVTAB_ENTRY( + MCF5272_uart_io1, + CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, // The table of I/O functions. + MCF5272_uart_init, // UART initialization function. + MCF5272_uart_lookup, // The UART lookup function. This function typically sets + // up the device for actual use, turing on interrupts, configuring the port, etc. + &MCF5272_uart_channel_1 +); +#endif // CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1 + + + +/* Definition of macros that access the UART's SIM registers */ +/* Read from a register */ + +#define MCF5272_UART_WRITE(_addr_,_value_) \ + *((volatile CYG_BYTE*)&(_addr_)) = (CYG_BYTE)(_value_) +/* Write to a register */ +#define MCF5272_UART_READ(_addr_) \ + *(volatile CYG_BYTE*)&(_addr_) + + +/* Function Prototypes */ +/* =================== */ +/* Internal function to actually configure the hardware to desired baud rate, etc. */ +static bool MCF5272_uart_config_port(serial_channel*, cyg_serial_info_t*); +static void MCF5272_uart_start_xmit(serial_channel*); + + +/* Baudrate conversion table. */ +static unsigned long baud_rates_table[]= +{ + 0, + 50, // CYGNUM_SERIAL_BAUD_50 = 1 + 75, // CYGNUM_SERIAL_BAUD_75 + 110, // CYGNUM_SERIAL_BAUD_110 + 134, // CYGNUM_SERIAL_BAUD_134_5 + 150, // CYGNUM_SERIAL_BAUD_150 + 200, // CYGNUM_SERIAL_BAUD_200 + 300, // CYGNUM_SERIAL_BAUD_300 + 600, // CYGNUM_SERIAL_BAUD_600 + 1200, // CYGNUM_SERIAL_BAUD_1200 + 1800, // CYGNUM_SERIAL_BAUD_1800 + 2400, // CYGNUM_SERIAL_BAUD_2400 + 3600, // CYGNUM_SERIAL_BAUD_3600 + 4800, // CYGNUM_SERIAL_BAUD_4800 + 7200, // CYGNUM_SERIAL_BAUD_7200 + 9600, // CYGNUM_SERIAL_BAUD_9600 + 14400, // CYGNUM_SERIAL_BAUD_14400 + 19200, // CYGNUM_SERIAL_BAUD_19200 + 38400, // CYGNUM_SERIAL_BAUD_38400 + 57600, // CYGNUM_SERIAL_BAUD_57600 + 115200, // CYGNUM_SERIAL_BAUD_115200 + 230400 // CYGNUM_SERIAL_BAUD_230400 +}; + +/* The table contains divers to divide the clock to configre a */ +/* approppriate for the UART. */ + +static unsigned long dividers_table[]= +{ + 0, + 46080, // 50 + 30720, // 75 + 20945, // 110 + 17130, // 134_5 + 15360, // 150 + 11520, // 200 + 7680, // 300 + 3840, // 600 + 1920, // 1200 + 1280, // 1800 + 960, // 2400 + 640, // 3600 + 480, // 4800 + 320, // 7200 + 240, // 9600 + 160, // 14400 + 120, // 19200 + 60, // 38400 + 40, // 57600 + 20, // 115200 + 10 // 230400 +}; + +/******************************************************************************* + MCF5272_uart_init() - This routine is called during bootstrap to set up the + UART driver. + + INPUT: + Pointer to the the device table. + + RETURN: + Returns true if the initialization is successful. Otherwise, it retuns false +*/ +static bool MCF5272_uart_init(struct cyg_devtab_entry * tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + MCF5272_uart_info_t *MCF5272_uart_chan = (MCF5272_uart_info_t *)chan->dev_priv; + + #ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 + + /* Instantiation of the UART channel 0 data strucutre. This data */ + /* structure contains channel information. */ + + if (strcmp(tab->name, CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL0_NAME) == 0) + { + + /* Initiliaze the UART information data to all zeros. */ + + memset(MCF5272_uart_chan, sizeof(MCF5272_uart_info_t), 0); + + /* Set the base address of the UART registers to differentiate */ + /* itself from the different regusters for the other UART port. */ + + MCF5272_uart_chan->base = (mcf5272_sim_uart_t*)&MCF5272_SIM->uart[0]; + + /* Set the UART interrupt vector number. */ + + MCF5272_uart_chan->uart_vector = CYGNUM_HAL_VECTOR_UART1; + + /* Set the autobaud state to idle. */ + + MCF5272_uart_chan->autobaud_state = AB_IDLE; + + /* Initilize the UART 0 output pins */ + + MCF5272_SIM->gpio.pbcnt = MCF5272_GPIO_PBCNT_URT0_EN | + ((MCF5272_SIM->gpio.pbcnt) & ~MCF5272_GPIO_PBCNT_URT0_MSK); + } + #endif + + #ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 + + /* Instantiation of the UART channel 1 data strucutre. This data structure contains + channel information. + */ + if (strcmp(tab->name, CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL1_NAME) == 0) + { + + /* Initiliaze the UART information data to all zeros. */ + + memset(MCF5272_uart_chan, sizeof(MCF5272_uart_info_t), 0); + + /* Set the base address of the UART registers to differentiate */ + /* itself from the different regusters for the other UART port. */ + + MCF5272_uart_chan->base = (mcf5272_sim_uart_t*)&MCF5272_SIM->uart[1]; + + /* Set the UART interrupt vector number. */ + + MCF5272_uart_chan->uart_vector = CYGNUM_HAL_VECTOR_UART2; + + /* Set the autobaud state to idle. */ + + MCF5272_uart_chan->autobaud_state = AB_IDLE; + + /* Initilize the UART 1 output pins */ + + MCF5272_SIM->gpio.pdcnt = MCF5272_GPIO_PDCNT_URT1_EN | + ((MCF5272_SIM->gpio.pdcnt) & ~MCF5272_GPIO_PDCNT_URT1_MSK); + + } + #endif + + + if (chan->out_cbuf.len > 0) { + + /* If the the buffer is greater than zero, then the driver will */ + /* use interrupt driven I/O. Hence, the driver creates an */ + /* interrupt context for the UART device. */ + + cyg_drv_interrupt_create(MCF5272_uart_chan->uart_vector, + MCF5272_UART_PRIORITY_LEVEL, // Priority - Level 2 + (cyg_addrword_t)chan, // Data item passed to interrupt handler + MCF5272_uart_ISR, + MCF5272_uart_DSR, + &MCF5272_uart_chan->serial_interrupt_handle, + &MCF5272_uart_chan->serial_interrupt); + + cyg_drv_interrupt_attach(MCF5272_uart_chan->serial_interrupt_handle); + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + } + + // Configure Serial device. + return(MCF5272_uart_config_port(chan, &chan->config)); +} + +/****************************************************************************************************** + MCF5272_uart_config_port() - Configure the UART port. + + Internal function to actually configure the hardware to desired baud rate, etc. + + INPUT: + chan - The channel information + new_confg - The port configuration which include the desired baud rate, etc. + + RETURN: + Returns true if the port configuration is successful. Otherwise, it retuns false + + */ +static bool MCF5272_uart_config_port(serial_channel *chan, + cyg_serial_info_t *new_config) +{ + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + uint8 mode_reg = 0; + uint32 ubgs; + unsigned int baud_divisor; + + + /* Get the divisor from the baudrate table which will use to */ + /* configure the port's baud rate. */ + + baud_divisor = baud_rates_table[new_config->baud]; + + /* If the divisor is zeor, we dont' configure the port. */ + + if (baud_divisor == 0) return false; + + /* Save the configuration value for later use. */ + + port->config = *new_config; + + /* We first write the reset values into the device and then configure */ + /* the device the we way we want to use it. */ + + /* Reset Transmitter */ + + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_TX); + + /* Reset Receiver */ + + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_RX); + + /* Reset Mode Register */ + + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_MR); + + /* Translate the parity configuration to UART mode bits. */ + + switch(port->config.parity) + { + default: + case CYGNUM_SERIAL_PARITY_NONE: + mode_reg = 0 | MCF5272_UART_UMR1_PM_NONE; + break; + case CYGNUM_SERIAL_PARITY_EVEN: + mode_reg = 0 | MCF5272_UART_UMR1_PM_EVEN; + break; + case CYGNUM_SERIAL_PARITY_ODD: + mode_reg = 0 | MCF5272_UART_UMR1_PM_ODD; + break; + case CYGNUM_SERIAL_PARITY_MARK: + mode_reg = 0 | MCF5272_UART_UMR1_PM_FORCE_HI; + break; + case CYGNUM_SERIAL_PARITY_SPACE: + mode_reg = 0 | MCF5272_UART_UMR1_PM_FORCE_LO; + break; + } + + /* Translate the number of bits per character configuration to UART mode bits. */ + + switch(port->config.word_length) + { + + case CYGNUM_SERIAL_WORD_LENGTH_5: + mode_reg |= MCF5272_UART_UMR1_BC_5; + break; + case CYGNUM_SERIAL_WORD_LENGTH_6: + mode_reg |= MCF5272_UART_UMR1_BC_6; + break; + case CYGNUM_SERIAL_WORD_LENGTH_7: + mode_reg |= MCF5272_UART_UMR1_BC_7; + break; + default: + case CYGNUM_SERIAL_WORD_LENGTH_8: + mode_reg |= MCF5272_UART_UMR1_BC_8; + break; + } + + /* Configure the parity and the bits per character */ + + MCF5272_UART_WRITE(port->base->umr, mode_reg); + + /* Translate the stop bit length to UART mode bits. */ + + switch(port->config.stop) + { + default: + case CYGNUM_SERIAL_STOP_1: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_1; + break; + case CYGNUM_SERIAL_STOP_1_5: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_15; + break; + case CYGNUM_SERIAL_STOP_2: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_2; + break; + } + + /* No echo or loopback */ + + MCF5272_UART_WRITE(port->base->umr, 0 | MCF5272_UART_UMR2_CM_NORMAL | mode_reg); + + /* Set Rx and Tx baud by timer */ + + MCF5272_UART_WRITE(port->base->ucr, 0 | MCF5272_UART_UCSR_RCS(0xD) | + MCF5272_UART_UCSR_TCS(0xD)); + + /* Mask all USART interrupts */ + + MCF5272_UART_WRITE(port->base->uisr_uimr, 0); + + /* Calculate baud settings */ + + ubgs = (uint16)((CYGHWR_HAL_SYSTEM_CLOCK_MHZ*1000000)/ + (baud_divisor * 32)); + + /* Program the baud settings to the device. */ + + MCF5272_UART_WRITE(port->base->udu, (uint8)((ubgs & 0xFF00) >> 8)); + MCF5272_UART_WRITE(port->base->udl, (uint8)(ubgs & 0x00FF)); + + /* Enable receiver and transmitter */ + + MCF5272_UART_WRITE(port->base->ucr, 0 | MCF5272_UART_UCR_TXRXEN); + + /* Enable both transmit and receive interrupt. */ + + port->imr_mirror = MCF5272_UART_UIMR_TXRDY | MCF5272_UART_UIMR_FFULL | + MCF5272_UART_UIMR_DB; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + + return true; /* Returns true to indicate a successful configuration */ + +} + +/******************************************************************************* + MCF5272_uart_lookup() - This routine is called when the device is "looked" up + (i.e. attached) + + INPUT: + tab - pointer to a pointer of the device table + sub_tab - Pointer to the sub device table. + name - name of the device + + RETURN: + always return ENOERR + +*/ +static Cyg_ErrNo MCF5272_uart_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +/******************************************************************************* + MCF5272_uart_putc() - Send a character to the device output buffer. + + INPUT: + chan - pointer to the serial private data. + c - the character to output + + RETURN: + 'true' if character is sent to device, return 'false' when we've + ran out of buffer space in the device itself. + +*/ + +static bool MCF5272_uart_putc(serial_channel *chan, unsigned char c) +{ + CYG_INTERRUPT_STATE int_state; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *)chan->dev_priv; + + /* Make sure the transmitter is not full. If it is full, return false. */ + if (!(MCF5272_UART_READ(port->base->usr_ucsr) & MCF5272_UART_USR_TXRDY)) + return false; + + /* Enable transmit interrupt. */ + HAL_DISABLE_INTERRUPTS(int_state); + port->imr_mirror |= MCF5272_UART_UIMR_TXRDY; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + HAL_RESTORE_INTERRUPTS(int_state); + + /* Enable the UART transmit. */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_TXRXEN); + + /* Send the character */ + MCF5272_UART_WRITE(port->base->urb_utb, c); + + return true ; +} + + +/****************************************************************************************************** + MCF5272_uart_getc() - Fetch a character from the device input bufferand return it to the alling + routine. Wait until there is a character ready. + + INPUT: + chan - pointer to the serial private data. + + RETURN: + the character read from the UART. + + */ +static unsigned char MCF5272_uart_getc(serial_channel *chan) +{ + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *)chan->dev_priv; + + /* Wait until character has been received */ + + while (!(MCF5272_UART_READ(port->base->usr_ucsr) & MCF5272_UART_USR_RXRDY)) + { + diag_printf("ready poll"); + } + + /* Read the character from the FIFO queue. */ + + return MCF5272_UART_READ(port->base->urf); + +} + + +/******************************************************************************* + MCF5272_uart_set_config() - Set up the device characteristics; baud rate, etc. + + INPUT: + chan - pointer to the serial private data. + key - configuration key (command). + xbuf - pointer to the configuration buffer + len - the length of the configuration buffer + + RETURN: + NOERR - If the configuration is successful + EINVAL - If the argument is invalid + +*/ + +Cyg_ErrNo MCF5272_uart_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + /* Set serial configuration. */ + if ( *len < sizeof(cyg_serial_info_t) ) { + return EINVAL; + } + *len = sizeof(cyg_serial_info_t); + + if (!MCF5272_uart_config_port(chan, config)) + return EINVAL; + } + break; + + case CYG_IO_GET_CONFIG_SERIAL_INFO: + // Retrieve UART configuration + *config = port->config; + break; + + default: + return EINVAL; + } + return ENOERR; +} + + +/******************************************************************************* + MCF5272_uart_start_xmit() - Enable the transmitter on the device. + + INPUT: + chan - pointer to the serial private data. + +*/ +static void MCF5272_uart_start_xmit(serial_channel *chan) +{ + CYG_INTERRUPT_STATE int_state; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + /* Enable the UART transmit. */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_TXEN); + + /* Enable transmit interrupt */ + HAL_DISABLE_INTERRUPTS(int_state); + port->imr_mirror |= MCF5272_UART_UIMR_TXRDY; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + HAL_RESTORE_INTERRUPTS(int_state); + + +} + + +/****************************************************************************************************** + MCF5272_uart_stop_xmit() - Disable the transmitter on the device + + INPUT: + chan - pointer to the serial private data. + +*/ +static void MCF5272_uart_stop_xmit(serial_channel * chan) +{ + CYG_INTERRUPT_STATE int_state; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + /* Disable transmit interrupt */ + HAL_DISABLE_INTERRUPTS(int_state); + port->imr_mirror &= ~MCF5272_UART_UIMR_TXRDY; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + HAL_RESTORE_INTERRUPTS(int_state); + + /* Disable the UART transmit. + !!!!!!!!!!!!! + !!!WARNING!!! + !!!!!!!!!!!!! + If the transmit the disabe + the diag_printf routines will poll forever to transmit the + a character. Hence, don't ever disable the transmit if + we want it to work with diag_printf. + */ + //MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_TXDE); + + +} + + +/****************************************************************************************************** + MCF5272_uart_ISR() - UART I/O interrupt interrupt service routine (ISR). + + INPUT: + vector - the interrupt vector number + data - user parameter. + + + RETURN: + returns CYG_ISR_CALL_DSR to call the DSR. + + */ +static cyg_uint32 MCF5272_uart_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *) data; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + + /* Write the value in the interrupt status register back + to the mask register to disable the interrupt temporarily. + */ + + MCF5272_UART_WRITE(port->base->uisr_uimr, 0); + + return CYG_ISR_CALL_DSR; // Cause DSR to run +} + + + +/****************************************************************************************************** + MCF5272_uart_DSR() - Defered Service Routine (DSR) - This routine processes the interrupt + from the device. + + INPUT: + vector - The interrupt vector number + count - The nunber of DSR requests. + data - Device specific information + +*/ + +static void MCF5272_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *)chan->dev_priv; + volatile u8_t isr; + + + /* Retrieve the interrupt status bits. We use these status bits to figure out + what process shouled we perform: read from the UART or inform of a completion + of a data transmission. + */ + + /* Retrieve the interrupt status register so + * the DSR can look it up. + */ + + + while((isr = (MCF5272_UART_READ(port->base->uisr_uimr) & port->imr_mirror))) + { + switch (port->autobaud_state) + { + default: + case AB_IDLE: + if (isr & MCF5272_UART_UISR_DB) + { + /* Detected the begin of a break, set the state to AB_BEGIN_BREAK + */ + port->autobaud_state = AB_BEGIN_BREAK; + + /* Reset the Delta Break bit in the UISR */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_BKCHGINT); + + } + break; + case AB_BEGIN_BREAK: + if (isr & MCF5272_UART_UISR_DB) + { + /* Detected the end of a break, set the state to AB_BEGIN, and + setup autobaud detection. + */ + port->autobaud_state = AB_BEGIN; + + /* Reset the Delta Break bit in the UISR and Enable autobaud */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_BKCHGINT | + MCF5272_UART_UCR_ENAB); + + /* Enable autobaud completion interrupt */ + port->imr_mirror |= MCF5272_UART_UIMR_ABC; + /* Disable the delta break interrupt so we can't receive + anymore break interrupt. + */ + port->imr_mirror &= ~MCF5272_UART_UIMR_DB; + + } + break; + + case AB_BEGIN: + if (isr & MCF5272_UART_UISR_ABC) + { + int count; + // Retrieve the baudrate that we're using now. + u16_t divider = (port->base->uabu << 8) + port->base->uabl; + // Search in the list to find a match. + for (count = sizeof(dividers_table)/sizeof(unsigned long) - 1; + count >= 0; + count--) + { + if (divider < dividers_table[count]) break; + } + + // Set the baud. + port->config.baud = count; + + /* Autobaud completion */ + port->autobaud_state = AB_IDLE; + + /* Disable autobaud */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_NONE); + + /* Ignore autobaud completion interrupt. */ + port->imr_mirror &= ~MCF5272_UART_UIMR_ABC; + + /* Reenable begin break change and receive interrupt. */ + port->imr_mirror |= MCF5272_UART_UIMR_DB; + + } + break; + + } + + + /* Receive character interrupt */ + if ((isr & MCF5272_UART_UISR_RXRDY)) + /* Ignore all receive interrupt when we're autobauding. */ + { + // Read all the characters in the fifo. + while ((MCF5272_UART_READ(port->base->uisr_uimr) & MCF5272_UART_UISR_RXRDY)) + { + char c; + /* Read the character from the UART. */ + c = MCF5272_UART_READ(port->base->urb_utb); + /* Pass the read character to the upper layer. */ + (chan->callbacks->rcv_char)(chan, c); + } + } + + /* Transmit complete interrupt */ + + if ((isr & MCF5272_UART_UISR_TXRDY)) + { + + /* Transmit holding register is empty */ + (chan->callbacks->xmt_char)(chan); + + } + + } + + /* Unmask all the DUART interrupts that were masked in the ISR, so */ + /* that we can receive the next interrupt. */ + + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + +} + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 +unsigned long MCF5272_uart_get_channel_0_baud_rate() +{ + /* return the baud rate for the first serial port */ + + return baud_rates_table[MCF5272_uart_channel_info_0.config.baud]; +} +#endif + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 +unsigned long MCF5272_uart_get_channel_1_baud_rate() +{ + /* return the baud rate for the second serial port */ + + return baud_rates_table[MCF5272_uart_channel_info_1.config.baud]; +} +#endif + + diff --git a/ecos/packages/devs/serial/mips/atlas/current/ChangeLog b/ecos/packages/devs/serial/mips/atlas/current/ChangeLog new file mode 100644 index 0000000..7c6ef46 --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/ChangeLog @@ -0,0 +1,43 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_atlas.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_atlas.cdl: + Fix 234000->230400 typo. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/atlas_serial.c (atlas_serial_set_config): Now use keys to make + more flexible. + +2000-07-14 Drew Moseley <dmoseley@redhat.com> + + * cdl/ser_mips_atlas.cdl: New file. Implement a serial driver for the mips Atlas board + * src/atlas_serial.c: Ditto. + * src/atlas_serial.h: Ditto. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl b/ecos/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl new file mode 100644 index 0000000..68d5d0e --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl @@ -0,0 +1,157 @@ +# ==================================================================== +# +# ser_mips_atlas.cdl +# +# eCos serial MIPS/ATLAS configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): dmoseley +# Original data: gthomas +# Contributors: +# Date: 2000-06-23 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_ATLAS { + display "MIPS ATLAS serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_ATLAS + + requires CYGPKG_ERROR + include_dir cyg/io +# include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + MIPS ATLAS." + + compile -library=libextras.a atlas_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_atlas.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +# FIXME: Bad name +cdl_option CYGPKG_IO_SERIAL_MIPS_ATLAS_POLLED_MODE { + display "MIPS ATLAS polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the MIPS ATLAS should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_MIPS_ATLAS_SERIAL_A { + display "MIPS ATLAS serial port driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the 16C550C on the + MIPS ATLAS." + + cdl_option CYGDAT_IO_SERIAL_MIPS_ATLAS_SERIAL_A_NAME { + display "Device name for MIPS ATLAS serial port" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name on the MIPS ATLAS." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BAUD { + display "Baud rate for the MIPS ATLAS serial port driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MIPS ATLAS 16c550c port." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE { + display "Buffer size for the MIPS ATLAS serial port driver" + flavor data + legal_values 0 to 8192 + default_value 512 + description " + This option specifies the size of the internal buffers used + for the MIPS ATLAS 16c550c port." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_ATLAS_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_ATLAS_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_ATLAS_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_mips_atlas.cdl diff --git a/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.c b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.c new file mode 100644 index 0000000..df264ed --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.c @@ -0,0 +1,372 @@ +//========================================================================== +// +// atlas_serial.c +// +// Serial device driver for ATLAS on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dmoseley, based on POWERPC driver by jskov +// Contributors: gthomas, jskov, dmoseley +// Date: 2000-06-23 +// Purpose: ATLAS serial device driver +// Description: ATLAS serial device driver +// +// To Do: +// Put in magic to effectively use the FIFOs. Transmitter FIFO fill is a +// problem, and setting receiver FIFO interrupts to happen only after +// n chars may conflict with hal diag. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_ATLAS + +#include "atlas_serial.h" + +typedef struct atlas_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; + cyg_uint8 iir; +} atlas_serial_info; + +static bool atlas_serial_init(struct cyg_devtab_entry *tab); +static bool atlas_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo atlas_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char atlas_serial_getc(serial_channel *chan); +static Cyg_ErrNo atlas_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void atlas_serial_start_xmit(serial_channel *chan); +static void atlas_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 atlas_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void atlas_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(atlas_serial_funs, + atlas_serial_putc, + atlas_serial_getc, + atlas_serial_set_config, + atlas_serial_start_xmit, + atlas_serial_stop_xmit + ); + +static atlas_serial_info atlas_serial_info0 ={ATLAS_SER_16550_BASE_A, + CYGNUM_HAL_INTERRUPT_SER}; + +#if CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE > 0 +static unsigned char atlas_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE]; +static unsigned char atlas_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(atlas_serial_channel0, + atlas_serial_funs, + atlas_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &atlas_serial_out_buf0[0], + sizeof(atlas_serial_out_buf0), + &atlas_serial_in_buf0[0], + sizeof(atlas_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(atlas_serial_channel0, + atlas_serial_funs, + atlas_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(atlas_serial_io0, + CYGDAT_IO_SERIAL_MIPS_ATLAS_SERIAL_A_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + atlas_serial_init, + atlas_serial_lookup, // Serial driver may need initializing + &atlas_serial_channel0 + ); + + + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +atlas_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + cyg_uint8 _lcr, _ier; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + // + // We may need to increase the timeout before causing a break reset. + // According to the Atlas Users Manual (Document MD00005) The BRKRES + // register will need to be programmed with a value larger that 0xA (the default) + // if we are going to use a baud rate lower than 2400. + // + if (new_config->baud <= CYGNUM_SERIAL_BAUD_2400) + { + // For now, just disable the break reset entirely. + HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, 0); + } else { + // Put the break reset state back to the default + HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, HAL_ATLAS_BRKRES_DEFAULT_VALUE); + } + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(port+SER_16550_IER, _ier); + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set databits, stopbits and parity. + _lcr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + if (init) { + // Enable and clear FIFO + HAL_WRITE_UINT8(port+SER_16550_FCR, + (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); + + if (chan->out_cbuf.len != 0) { + HAL_WRITE_UINT8(port+SER_16550_IER, SIO_IER_ERDAI); + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + } + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +atlas_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("ATLAS SERIAL init - dev: %x.%d\n", atlas_chan->base, atlas_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(atlas_chan->int_num, + 0, // can change IRQ0 priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + atlas_serial_ISR, + atlas_serial_DSR, + &atlas_chan->serial_interrupt_handle, + &atlas_chan->serial_interrupt); + cyg_drv_interrupt_attach(atlas_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(atlas_chan->int_num); + } + atlas_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +atlas_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +atlas_serial_putc(serial_channel *chan, unsigned char c) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _lsr; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + if (_lsr & SIO_LSR_THRE) { + // Transmit buffer is empty + HAL_WRITE_UINT8(port+SER_16550_THR, c); + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +atlas_serial_getc(serial_channel *chan) +{ + unsigned char c; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _lsr; + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ((_lsr & SIO_LSR_DR) == 0); + HAL_READ_UINT8(port+SER_16550_RBR, c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +atlas_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != atlas_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +atlas_serial_start_xmit(serial_channel *chan) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier |= IER_XMT; // Enable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + + // We should not need to call this here. THRE Interrupts are enabled, and the DSR + // below calls this function. However, sometimes we get called with Master Interrupts + // disabled, and thus the DSR never runs. This is unfortunate because it means we + // will be doing multiple processing steps for the same thing. + (chan->callbacks->xmt_char)(chan); +} + +// Disable the transmitter on the device +static void +atlas_serial_stop_xmit(serial_channel *chan) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier &= ~IER_XMT; // Disable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +atlas_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(atlas_chan->int_num); + cyg_drv_interrupt_acknowledge(atlas_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +atlas_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _iir; + + HAL_READ_UINT8(port+SER_16550_IIR, _iir); + _iir &= SIO_IIR_ID_MASK; + if ( ISR_Tx_Empty == _iir ) { + (chan->callbacks->xmt_char)(chan); + } else if (( ISR_Rx_Avail == _iir ) || ( ISR_Rx_Char_Timeout == _iir )) { + cyg_uint8 _c; + HAL_READ_UINT8(port+SER_16550_RBR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + + cyg_drv_interrupt_unmask(atlas_chan->int_num); +} + +#endif + +//------------------------------------------------------------------------- +// EOF atlas_serial.c diff --git a/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.h b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.h new file mode 100644 index 0000000..1b78b9d --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.h @@ -0,0 +1,213 @@ +//========================================================================== +// +// io/serial/mips/atlas/atlas_serial.h +// +// MIPS Atlas Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dmoseley, based on PowerPC driver by jskov +// Contributors:gthomas, jskov, dmoseley +// Date: 2000-06-23 +// Purpose: Atlas Serial definitions +//####DESCRIPTIONEND#### +//========================================================================== + +// Description of serial ports on Atlas board + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_None 0x01 +#define ISR_Rx_Line_Status 0x06 +#define ISR_Rx_Avail 0x04 +#define ISR_Rx_Char_Timeout 0x0C +#define ISR_Tx_Empty 0x02 +#define IRS_Modem_Status 0x00 + +// FIFO control register +#define FCR_ENABLE 0x01 +#define FCR_CLEAR_RCVR 0x02 +#define FCR_CLEAR_XMIT 0x04 + + +//////////////////////////////////////////////////////////// +// Clean this up. + +#define ATLAS_SER_16550_BASE_A 0xBF000900 +#define SER_16550_BASE ATLAS_SER_16550_BASE_A + +//----------------------------------------------------------------------------- +// Define the serial registers. The Atlas board is equipped with a 16550C +// serial chip. +#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 +#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define SER_16550_IER 0x08 // interrupt enable register, read/write, dlab = 0 +#define SER_16550_DLM 0x08 // divisor latch (MS), read/write, dlab = 1 +#define SER_16550_IIR 0x10 // interrupt identification reg, read, dlab = 0 +#define SER_16550_FCR 0x10 // fifo control register, write, dlab = 0 +#define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1 +#define SER_16550_LCR 0x18 // line control register, read/write +#define SER_16550_MCR 0x20 // modem control register, read/write +#define SER_16550_LSR 0x28 // line status register, read +#define SER_16550_MSR 0x30 // modem status register, read +#define SER_16550_SCR 0x38 // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO +///////////////////////////////////////// + + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// FIXME: calc all properly +// The Atlas board has a 3.6864 MHz crystal +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 2094, // 110 + 0, // 134.5 + 1536, // 150 + 0, // 200 + 768, // 300 + 384, // 600 + 192, // 1200 + 0, // 1800 + 96, // 2400 + 0, // 3600 + 48, // 4800 + 32, // 7200 + 24, // 9600 + 16, // 14400 + 12, // 19200 + 6, // 38400 + 4, // 57600 + 2, // 115200 + 1, // 230400 +}; + diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/ChangeLog b/ecos/packages/devs/serial/mips/idt79s334a/current/ChangeLog new file mode 100644 index 0000000..01c0c41 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/ChangeLog @@ -0,0 +1,38 @@ +2003-03-09 Tim Michals <t.michals@attbi.com> + + * cdl/ser_mipsidt_334a.cdl: Add configuration for second serial port. + * src/mipsidt_serial.c: Updated support for dual serial ports + * src/mipsidt_serial.h: Add some helpful extra defines for debug. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mipsidt_334a.cdl: Remove irrelevant doc link. + +2003-02-13 Tim Michals <t.michals@attbi.com> +2003-02-13 Jonathan Larmour <jifl@eCosCentric.com> + + * New package - support for MIPS IDT 79s334a board. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/cdl/ser_mipsidt_334a.cdl b/ecos/packages/devs/serial/mips/idt79s334a/current/cdl/ser_mipsidt_334a.cdl new file mode 100644 index 0000000..b3748d5 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/cdl/ser_mipsidt_334a.cdl @@ -0,0 +1,196 @@ +# ==================================================================== +# +# ser_mipsidt_334a.cdl +# +# eCos serial MIPS/IDT 334a reference platform configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): tmichals +# Original data: dmoseley +# Contributors: +# Date: 2003-02-13 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_IDT79S334A { + display "MIPS IDT79RC32344 reference platform serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_IDT32334 + + requires CYGPKG_ERROR + include_dir cyg/io +# include_files ; # none _exported_ whatsoever + description " + This package contains the serial device drivers for the + MIPS IDT79RC32334 reference platform." + + compile -library=libextras.a mipsidt_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_idt79s334a.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + +cdl_option CYGPKG_IO_SERIAL_MIPS_POLLED_MODE { + display "MIPS IDT polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the MIPS should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A { + display "MIPS IDT79S334A serial port driver 0" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the 16C550 on the + MIPS IDT79S334A." + + cdl_option CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_NAME { + display "Device name for MIPS IDT79S334A serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name on the MIPS IDT79S334A." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BAUD { + display "Baud rate for the MIPS IDT79S334A serial port driver 0" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 115200 + description " + This option specifies the default baud rate (speed) for the + MIPS 16c550 port." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE { + display "Buffer size for the MIPS IDT79S334A serial port driver 0" + flavor data + legal_values 0 to 8192 + default_value 512 + description " + This option specifies the size of the internal buffers used + for the MIPS IDT79S334A 16c550c port." + } +} + +cdl_component CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B { + display "MIPS IDT79S334A serial port driver 1" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the 16C550 on the + MIPS IDT79S334A." + + cdl_option CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_NAME { + display "Device name for MIPS IDT79S334A serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name on the MIPS IDT79S334A." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BAUD { + display "Baud rate for the MIPS IDT79S334A serial port driver 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 115200 + description " + This option specifies the default baud rate (speed) for the + MIPS 16c550 port." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE { + display "Buffer size for the MIPS IDT79S334A serial port driver 1" + flavor data + legal_values 0 to 8192 + default_value 512 + description " + This option specifies the size of the internal buffers used + for the MIPS IDT79S334A 16c550c port." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_IDT79S334A_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_IDT79S334A_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_IDT79S334A_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_mipsidt_334A.cdl diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.c b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.c new file mode 100755 index 0000000..6943c64 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.c @@ -0,0 +1,409 @@ +//========================================================================== +// +// mipsidt_serial.c +// +// Serial device driver for MIPS IDT79s334a reference platform on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals based on driver by dmoseley, based on POWERPC driver by jskov +// Contributors: gthomas, jskov, dmoseley, tmichals +// Date: 2003-02-13 +// Purpose: MIPS IDT79s334a reference platform serial device driver +// Description: IDT MIPS serial device driver +// +// To Do: +// Put in magic to effectively use the FIFOs. Transmitter FIFO fill is a +// problem, and setting receiver FIFO interrupts to happen only after +// n chars may conflict with hal diag. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_IDT79S334A + +#include "mipsidt_serial.h" + +typedef struct mipsidt_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; + cyg_uint8 iir; +} mipsidt_serial_info; + +static bool mipsidt_serial_init(struct cyg_devtab_entry *tab); +static bool mipsidt_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo mipsidt_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char mipsidt_serial_getc(serial_channel *chan); +static Cyg_ErrNo mipsidt_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void mipsidt_serial_start_xmit(serial_channel *chan); +static void mipsidt_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 mipsidt_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void mipsidt_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(mipsidt_serial_funs, + mipsidt_serial_putc, + mipsidt_serial_getc, + mipsidt_serial_set_config, + mipsidt_serial_start_xmit, + mipsidt_serial_stop_xmit + ); + + +#ifdef CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A +static mipsidt_serial_info mipsidt_serial_info0 ={IDTMIPS_SER_16550_BASE_A, + CYGNUM_HAL_INTERRUPT_SIO_0}; + +#if CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE > 0 +static unsigned char mipsidt_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE]; +static unsigned char mipsidt_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mipsidt_serial_channel0, + mipsidt_serial_funs, + mipsidt_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mipsidt_serial_out_buf0[0], + sizeof(mipsidt_serial_out_buf0), + &mipsidt_serial_in_buf0[0], + sizeof(mipsidt_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(mipsidt_serial_channel0, + mipsidt_serial_funs, + mipsidt_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(mipsidt_serial_io0, + CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mipsidt_serial_init, + mipsidt_serial_lookup, // Serial driver may need initializing + &mipsidt_serial_channel0 + ); + +#endif + +#ifdef CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B +static mipsidt_serial_info mipsidt_serial_info1 ={IDTMIPS_SER_16550_BASE_B, + CYGNUM_HAL_INTERRUPT_SIO_1}; + +#if CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE > 0 +static unsigned char mipsidt_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE]; +static unsigned char mipsidt_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mipsidt_serial_channel1, + mipsidt_serial_funs, + mipsidt_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mipsidt_serial_out_buf1[0], + sizeof(mipsidt_serial_out_buf1), + &mipsidt_serial_in_buf1[0], + sizeof(mipsidt_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(mipsidt_serial_channel1, + mipsidt_serial_funs, + mipsidt_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(mipsidt_serial_io1, + CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mipsidt_serial_init, + mipsidt_serial_lookup, // Serial driver may need initializing + &mipsidt_serial_channel1 + ); + +#endif + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +mipsidt_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint32 baud_divisor = select_baud[new_config->baud]; ; + cyg_uint8 _lcr, _ier; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + baud_divisor = (CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL * 10) / (16 * select_baud[new_config->baud]); + + baud_divisor +=5; + baud_divisor = ((cyg_int32)baud_divisor) / 10; + + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(port+SER_16550_IER, _ier); + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set databits, stopbits and parity. + _lcr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + if (init) { + // Enable and clear FIFO + HAL_WRITE_UINT8(port+SER_16550_FCR, + (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); + + if (chan->out_cbuf.len != 0) { + HAL_WRITE_UINT8(port+SER_16550_IER, SIO_IER_ERDAI); + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + } + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +mipsidt_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("IDT SERIAL init - dev: %x.%d\n", mipsidt_chan->base, mipsidt_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(mipsidt_chan->int_num, + 0, // can change IRQ0 priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + mipsidt_serial_ISR, + mipsidt_serial_DSR, + &mipsidt_chan->serial_interrupt_handle, + &mipsidt_chan->serial_interrupt); + cyg_drv_interrupt_attach(mipsidt_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(mipsidt_chan->int_num); + } + mipsidt_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +mipsidt_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +mipsidt_serial_putc(serial_channel *chan, unsigned char c) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _lsr; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + if (((_lsr & (SIO_LSR_THRE | SIO_LSR_TEMT)) == 0x60)) { + // Transmit buffer is empty + HAL_WRITE_UINT8(port+SER_16550_THR, c); + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +mipsidt_serial_getc(serial_channel *chan) +{ + unsigned char c; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _lsr; + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ((_lsr & SIO_LSR_DR) == 0); + HAL_READ_UINT8(port+SER_16550_RBR, c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +mipsidt_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != mipsidt_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +mipsidt_serial_start_xmit(serial_channel *chan) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier |= IER_XMT; // Enable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + + // We should not need to call this here. THRE Interrupts are enabled, and the DSR + // below calls this function. However, sometimes we get called with Master Interrupts + // disabled, and thus the DSR never runs. This is unfortunate because it means we + // will be doing multiple processing steps for the same thing. + (chan->callbacks->xmt_char)(chan); +} + +// Disable the transmitter on the device +static void +mipsidt_serial_stop_xmit(serial_channel *chan) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier &= ~IER_XMT; // Disable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +mipsidt_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mipsidt_chan->int_num); + cyg_drv_interrupt_acknowledge(mipsidt_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +mipsidt_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _iir; + + HAL_READ_UINT8(port+SER_16550_IIR, _iir); + _iir &= SIO_IIR_ID_MASK; + if ( ISR_Tx_Empty == _iir ) { + (chan->callbacks->xmt_char)(chan); + } else if (( ISR_Rx_Avail == _iir ) || ( ISR_Rx_Char_Timeout == _iir )) { + cyg_uint8 _c; + HAL_READ_UINT8(port+SER_16550_RBR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + + cyg_drv_interrupt_unmask(mipsidt_chan->int_num); +} + +#endif + +//------------------------------------------------------------------------- +// EOF mipsidt_serial.c diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.h b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.h new file mode 100755 index 0000000..7975d78 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.h @@ -0,0 +1,218 @@ +//========================================================================== +// +// io/serial/mips/idt79s334a/mipsidt_serial.h +// +// MIPS IDT79S334A Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals based on driver by dmoseley, based on POWERPC driver by jskov +// Contributors: gthomas, jskov, dmoseley, tmichals +// Date: 2003-02-13 +// Date: 2003-02-13 +// Purpose: MIPS IDT79s334a reference platform serial device driver definitions. +// Description: IDT MIPS serial device driver definitions. +//####DESCRIPTIONEND#### +//========================================================================== + +// Description of serial ports on IDT board + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_None 0x01 +#define ISR_Rx_Line_Status 0x06 +#define ISR_Rx_Avail 0x04 +#define ISR_Rx_Char_Timeout 0x0C +#define ISR_Tx_Empty 0x02 +#define IRS_Modem_Status 0x00 + +// FIFO control register +#define FCR_ENABLE 0x01 +#define FCR_CLEAR_RCVR 0x02 +#define FCR_CLEAR_XMIT 0x04 + + +//////////////////////////////////////////////////////////// +// Clean this up. + +#define IDTMIPS_SER_16550_BASE_A 0xB8000803 +#define IDTMIPS_SER_16550_BASE_B 0xB8000823 +#define SER_16550_BASE IDTMIPS_SER_16550_BASE_A +#define INTR_COM0_REG 0xB8000554 +#define INTR_COM1_REG 0xB8000564 + +//----------------------------------------------------------------------------- +// Define the serial registers. The IDT board is equipped with a 16550C +// serial chip. +#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 +#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define SER_16550_IER 0x04 // interrupt enable register, read/write, dlab = 0 +#define SER_16550_DLM 0x04 // divisor latch (MS), read/write, dlab = 1 +#define SER_16550_IIR 0x08 // interrupt identification reg, read, dlab = 0 +#define SER_16550_FCR 0x08 // fifo control register, write, dlab = 0 +#define SER_16550_AFR 0x08 // alternate function reg, read/write, dlab = 1 +#define SER_16550_LCR 0x0c // line control register, read/write +#define SER_16550_MCR 0x10 // modem control register, read/write +#define SER_16550_LSR 0x14 // line status register, read +#define SER_16550_MSR 0x18 // modem status register, read +#define SER_16550_SCR 0x1c // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO +///////////////////////////////////////// + + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + + +static unsigned int select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 134, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +// EOF mipsidt_serial.h diff --git a/ecos/packages/devs/serial/mips/jmr3904/current/ChangeLog b/ecos/packages/devs/serial/mips/jmr3904/current/ChangeLog new file mode 100644 index 0000000..91f4a29 --- /dev/null +++ b/ecos/packages/devs/serial/mips/jmr3904/current/ChangeLog @@ -0,0 +1,1185 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_jmr3904.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/tx3904_serial.c (tx3904_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_mips_jmr3904.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl b/ecos/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl new file mode 100644 index 0000000..cf922eb --- /dev/null +++ b/ecos/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl @@ -0,0 +1,219 @@ +# ==================================================================== +# +# ser_mips_jmr3904.cdl +# +# eCos serial MIPS/JMR3904 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_TX39_JMR3904 { + display "TX39 JMR3904 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_TX39_JMR3904 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + TX39 JMR3904." + + compile -library=libextras.a tx3904_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_tx39_jmr3904.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +# FIXME: Bad name +cdl_option CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE { + display "TX39 JMR3904 polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the TX39 JMR3904 should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 { + display "TX39 JMR3904 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 0 on the + TX39 JMR3904." + + cdl_option CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL0_NAME { + display "Device name for TX39 JMR3904 serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name port 0 on the TX39 JMR3904." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BAUD { + display "Baud rate for the TX39 JMR3904 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + TX39 JMR3904 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE { + display "Buffer size for the TX39 JMR3904 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the TX39 JMR3904 port 0." + } +} +cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 { + display "TX39 JMR3904 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 1 on + the TX39 JMR3904." + + cdl_option CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL1_NAME { + display "Device name for TX39 JMR3904 serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name port 1 on the TX39 JMR3904." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD { + display "Baud rate for the TX39 JMR3904 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + TX39 JMR3904 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE { + display "Buffer size for the TX39 JMR3904 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the TX39 JMR3904 port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_TX39_JMR3904_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_TX39_JMR3904_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + implements CYGINT_IO_SERIAL_TEST_SKIP_STOP_2 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"tx39jmr\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_jmr3904.cdl diff --git a/ecos/packages/devs/serial/mips/jmr3904/current/src/tx3904_serial.c b/ecos/packages/devs/serial/mips/jmr3904/current/src/tx3904_serial.c new file mode 100644 index 0000000..0552d65 --- /dev/null +++ b/ecos/packages/devs/serial/mips/jmr3904/current/src/tx3904_serial.c @@ -0,0 +1,756 @@ +//========================================================================== +// +// tx3904_serial.c +// +// Serial device driver for TX3904 on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-03-3 +// Purpose: TX3904 serial device driver +// Description: TX3904 serial device driver +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/io_serial.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904 + +cyg_bool cyg_hal_is_break(char *buf, int size); +void cyg_hal_user_break( CYG_ADDRWORD *regs ); + +//------------------------------------------------------------------------- + +extern void diag_printf(const char *fmt, ...); + +//------------------------------------------------------------------------- +// Forward definitions + +static bool tx3904_serial_init(struct cyg_devtab_entry *tab); +static bool tx3904_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo tx3904_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char tx3904_serial_getc(serial_channel *chan); +static Cyg_ErrNo tx3904_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void tx3904_serial_start_xmit(serial_channel *chan); +static void tx3904_serial_stop_xmit(serial_channel *chan); + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE +static cyg_uint32 tx3904_serial_ISR(cyg_vector_t vector, cyg_addrword_t data, cyg_addrword_t *regs); +static void tx3904_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#endif + + +//------------------------------------------------------------------------- +// TX3904 serial line control register values: + +// Offsets to serial control registers from base +#define SERIAL_CR 0x00 +#define SERIAL_SR 0x04 +#define SERIAL_ICR 0x08 +#define SERIAL_ISR 0x0C +#define SERIAL_FCR 0x10 +#define SERIAL_BRG 0x14 +#define SERIAL_TXB 0x20 +#define SERIAL_RXB 0x30 + +// Status register bits +#define ISR_RXRDY 0x01 +#define ISR_TXRDY 0x02 +#define ISR_ERROR 0x04 + +// Control register bits +#define LCR_SB1 0x0000 +#define LCR_SB1_5 0x0000 +#define LCR_SB2 0x0004 +#define LCR_PN 0x0000 // Parity mode - none +#define LCR_PS 0x0000 // Forced "space" parity +#define LCR_PM 0x0000 // Forced "mark" parity +#define LCR_PE 0x0018 // Parity mode - even +#define LCR_PO 0x0010 // Parity mode - odd +#define LCR_WL5 0x0001 // not supported - use 7bit +#define LCR_WL6 0x0001 // not supported - use 7bit +#define LCR_WL7 0x0001 // 7 bit chars +#define LCR_WL8 0x0000 // 8 bit chars + +#define LCR_BRG 0x0020 // Select baud rate generator + +#define ICR_RXE 0x0001 // receive enable +#define ICR_TXE 0x0002 // transmit enable + +//------------------------------------------------------------------------- +// Tables to map input values to hardware settings + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// The values in this table plug straight into the BRG register +// in the serial driver hardware. They comprise a baud rate divisor +// in the bottom 8 bits and a clock selector in the top 8 bits. +// These figures all come from Toshiba. + +#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0x0300|20, // 600 + 0x0300|10, // 1200 + 0, // 1800 + 0x0300|05, // 2400 + 0, // 3600 + 0x0300|10, // 4800 + 0, // 7200 + 0x0200|05, // 9600 + 0, // 14400 + 0x0100|10, // 19200 + 0x0100|05, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0x0300|27, // 600 + 0x0200|54, // 1200 + 0, // 1800 + 0x0200|27, // 2400 + 0, // 3600 + 0x0100|54, // 4800 + 0, // 7200 + 0x0100|27, // 9600 + 0, // 14400 + 0x0000|54, // 19200 + 0x0000|27, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#else + +#error Unsupported CPU frequency + +#endif + +//------------------------------------------------------------------------- +// Info for each serial device controlled + +typedef struct tx3904_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt interrupt; + cyg_handle_t interrupt_handle; + cyg_uint8 input_char; + cyg_bool input_char_valid; + cyg_bool output_ready; + cyg_uint16 cur_baud; +} tx3904_serial_info; + +//------------------------------------------------------------------------- +// Callback functions exported by this driver + +static SERIAL_FUNS(tx3904_serial_funs, + tx3904_serial_putc, + tx3904_serial_getc, + tx3904_serial_set_config, + tx3904_serial_start_xmit, + tx3904_serial_stop_xmit + ); + +//------------------------------------------------------------------------- +// Hardware info for each serial line + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 +static tx3904_serial_info tx3904_serial_info0 = { + 0xFFFFF300, + CYGNUM_HAL_INTERRUPT_SIO_0 +}; +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE > 0 +static unsigned char tx3904_serial_out_buf0[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE]; +static unsigned char tx3904_serial_in_buf0[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 +static tx3904_serial_info tx3904_serial_info1 = { + 0xFFFFF400, + CYGNUM_HAL_INTERRUPT_SIO_1 +}; +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE > 0 +static unsigned char tx3904_serial_out_buf1[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE]; +static unsigned char tx3904_serial_in_buf1[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 + +//------------------------------------------------------------------------- +// Channel descriptions: + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE +#define SIZEOF_BUF(_x_) 0 +#else +#define SIZEOF_BUF(_x_) sizeof(_x_) +#endif + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(tx3904_serial_channel0, + tx3904_serial_funs, + tx3904_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &tx3904_serial_out_buf0[0], + SIZEOF_BUF(tx3904_serial_out_buf0), + &tx3904_serial_in_buf0[0], + SIZEOF_BUF(tx3904_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(tx3904_serial_channel0, + tx3904_serial_funs, + tx3904_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(tx3904_serial_channel1, + tx3904_serial_funs, + tx3904_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &tx3904_serial_out_buf1[0], + SIZEOF_BUF(tx3904_serial_out_buf1), + &tx3904_serial_in_buf1[0], + SIZEOF_BUF(tx3904_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(tx3904_serial_channel1, + tx3904_serial_funs, + tx3904_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 + +//------------------------------------------------------------------------- +// And finally, the device table entries: + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 +DEVTAB_ENTRY(tx3904_serial_io0, + CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + tx3904_serial_init, + tx3904_serial_lookup, // Serial driver may need initializing + &tx3904_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 +DEVTAB_ENTRY(tx3904_serial_io1, + CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + tx3904_serial_init, + tx3904_serial_lookup, // Serial driver may need initializing + &tx3904_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 + +// ------------------------------------------------------------------------ +// Delay for some number of character times. This is based on the baud +// rate currently set. We use the numbers that plug in to the BRG +// clock select and divider to control two loops. The innermost delay +// loop uses a count that is derived from dividing the CPU frequency +// by the BRG granularity (and we then add 1 to compensate for any +// rounding). This gives the number of cycles that the innermost loop +// must consume. For the sake of simplicity we assume that this loop +// will take 1 cycle per loop, which is roughly true in optimized +// code. + +void delay_char_time(tx3904_serial_info *tx3904_chan, int n) +{ + static cyg_uint16 clock_val[4] = { 4, 16, 64, 256 }; + cyg_uint16 baud_val = select_baud[tx3904_chan->cur_baud]; + cyg_count32 clock_loop = clock_val[baud_val>>8]; + cyg_count32 div_loop = baud_val & 0xFF; + cyg_count32 bit_time = ((CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL)/(2457600)) + 1; + + n *= 11; // allow for start and stop bits and 8 data bits + + while( n-- ) + { + cyg_count32 i,j,k; + + for( i = 0; i < clock_loop; i++ ) + for( j = 0; j < div_loop; j++ ) + for( k = 0; k < bit_time; k++ ) + continue; + } +} + +//------------------------------------------------------------------------- + +static bool +tx3904_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 cr = 0; + cyg_uint16 icr = 0; + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + // set up other config values: + + cr |= select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + cr |= select_stop_bits[new_config->stop]; + cr |= select_parity[new_config->parity]; + + // Source transfer clock from BRG + cr |= LCR_BRG; + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + // Enable RX interrupts only at present +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + if ((chan->out_cbuf.len != 0) || (chan == &tx3904_serial_channel0)) { +#else + if (chan->out_cbuf.len != 0) { +#endif + icr |= ICR_RXE; + } +#endif + + // Avoid any interrupts while we are fiddling with the line parameters. + cyg_drv_interrupt_mask(tx3904_chan->int_num); + + + // In theory we should wait here for the transmitter to drain the + // FIFO so we dont change the line parameters with characters + // unsent. Unfortunately the TX39 serial devices do not allow us + // to discover when the FIFO is empty. + + delay_char_time(tx3904_chan, 8); + + // Disable device entirely. +// HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_CR, 0); +// HAL_WRITE_UINT8(tx3904_chan->base+SERIAL_ICR, 0); + + // Reset the FIFOs + + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_FCR, 7); + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_FCR, 0); + + // Set up baud rate + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_BRG, baud_divisor ); + + // Write CR into hardware + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_CR, cr); + + // Write ICR into hardware + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_ICR, icr); + + // Re-enable interrupts. + cyg_drv_interrupt_unmask(tx3904_chan->int_num); + + // Save current baud rate + tx3904_chan->cur_baud = new_config->baud; + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +//------------------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. + +bool tx3904_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + + tx3904_chan->cur_baud = CYGNUM_SERIAL_BAUD_38400; + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + if (chan->out_cbuf.len != 0) { + // Install and enable the interrupt + cyg_drv_interrupt_create(tx3904_chan->int_num, + 4, // Priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + (cyg_ISR_t *)tx3904_serial_ISR, + tx3904_serial_DSR, + &tx3904_chan->interrupt_handle, + &tx3904_chan->interrupt); + cyg_drv_interrupt_attach(tx3904_chan->interrupt_handle); + cyg_drv_interrupt_unmask(tx3904_chan->int_num); + } +#endif + + tx3904_serial_config_port(chan, &chan->config, true); + + return true; +} + +//------------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) + +static Cyg_ErrNo +tx3904_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +//------------------------------------------------------------------------- +// Return 'true' if character is sent to device + +bool +tx3904_serial_putc(serial_channel *chan, unsigned char c) +{ + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 isr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + if( isr & ISR_TXRDY ) + { + HAL_WRITE_UINT8( tx3904_chan->base+SERIAL_TXB, c ); + + isr &= ~ISR_TXRDY; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + return true; + } + else return false; +} + +//------------------------------------------------------------------------- + +unsigned char +tx3904_serial_getc(serial_channel *chan) +{ + unsigned char c; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 isr; + + do + { + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + // Eliminate any RX errors + if( isr & ISR_ERROR ) + { + cyg_uint16 sr = 0; + + isr &= ISR_ERROR; + +// HAL_READ_UINT16( tx3904_chan->base+SERIAL_SR, sr ); + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_SR, sr ); + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + } + + } while( (isr & ISR_RXRDY) != ISR_RXRDY ); + + HAL_READ_UINT8( tx3904_chan->base+SERIAL_RXB, c ); + + isr &= ~ISR_RXRDY; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + return c; +} + +//------------------------------------------------------------------------- + +static Cyg_ErrNo +tx3904_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != tx3904_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------------------------------------------- +// Enable the transmitter on the device + +static void +tx3904_serial_start_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 icr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); + + icr |= ICR_TXE; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); +#endif +} + +//------------------------------------------------------------------------- +// Disable the transmitter on the device + +static void +tx3904_serial_stop_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 icr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); + + icr &= ~ICR_TXE; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); +#endif +} + +//------------------------------------------------------------------------- +// Serial I/O - low level interrupt handlers (ISR) + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + +static cyg_uint32 +tx3904_serial_ISR(cyg_vector_t vector, cyg_addrword_t data, cyg_addrword_t *regs) +{ + serial_channel *chan = (serial_channel *)data; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint8 isr; + cyg_uint32 result = 0; + + cyg_drv_interrupt_mask(tx3904_chan->int_num); + cyg_drv_interrupt_acknowledge(tx3904_chan->int_num); + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + // Eliminate any RX errors + if( isr & ISR_ERROR ) + { + cyg_uint16 sr = 0; + + isr &= ~ISR_ERROR; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_SR, sr ); + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_SR, 0 ); + } + + // Check for a TX interrupt and set the flag if so. + if( isr & ISR_TXRDY ) + { + isr &= ~ISR_TXRDY; + + tx3904_chan->output_ready = true; + + result |= CYG_ISR_CALL_DSR; // Cause DSR to be run + } + + + // Check here for an RX interrupt and fetch the character. If it + // is a ^C then call into GDB stub to handle it. + + if( isr & ISR_RXRDY ) + { + cyg_uint8 rxb; + HAL_READ_UINT8( tx3904_chan->base+SERIAL_RXB, rxb ); + + isr &= ~ISR_RXRDY; + + if( cyg_hal_is_break( &rxb , 1 ) ) + cyg_hal_user_break( regs ); + else + { + tx3904_chan->input_char = rxb; + tx3904_chan->input_char_valid = true; + result |= CYG_ISR_CALL_DSR; // Cause DSR to be run + } + + } + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + return result; +} + + +#endif + +//------------------------------------------------------------------------- +// Serial I/O - high level interrupt handler (DSR) + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + +static void +tx3904_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint8 isr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + if( tx3904_chan->input_char_valid ) + { + (chan->callbacks->rcv_char)(chan, tx3904_chan->input_char); + + tx3904_chan->input_char_valid = false; + +#if 0 + // And while we are here, pull any further characters out of the + // FIFO. This should help to reduce the interrupt rate. + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + while( isr & ISR_RXRDY ) + { + cyg_uint8 rxb; + HAL_READ_UINT8( tx3904_chan->base+SERIAL_RXB, rxb ); + + (chan->callbacks->rcv_char)(chan, rxb); + + isr &= ~ISR_RXRDY; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + } +#endif + + } + + if( tx3904_chan->output_ready ) + { + (chan->callbacks->xmt_char)(chan); + + tx3904_chan->output_ready = false; + } + + cyg_drv_interrupt_unmask(tx3904_chan->int_num); +} + +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904 + +//------------------------------------------------------------------------- +// EOF tx3904_serial.c diff --git a/ecos/packages/devs/serial/mips/ref4955/current/ChangeLog b/ecos/packages/devs/serial/mips/ref4955/current/ChangeLog new file mode 100644 index 0000000..fbaff46 --- /dev/null +++ b/ecos/packages/devs/serial/mips/ref4955/current/ChangeLog @@ -0,0 +1,60 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_ref4955.cdl: Remove irrelevant doc link. + +2000-09-18 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_ref4955.cdl: Use CDL to specify testing parameters. + + * include/mips_tx49_ref4955_ser.inl: Follow type naming changes in + generic driver. + +2000-09-14 Jesper Skov <jskov@redhat.com> + + * include/mips_tx49_ref4955_ser.inl: Use with generic 16x5x serial + driver. + * src/ref4955_serial.c: Deleted. + * src/ref4955_serial.h: Deleted. + * cdl/ser_mips_ref4955.cdl: Changed accordingly. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/ref4955_serial.c (pc_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-05-25 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_ref4955.cdl: + * src/ref4955_serial.h: + * src/ref4955_serial.c: + REF4955 serial driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl b/ecos/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl new file mode 100644 index 0000000..4570fe3 --- /dev/null +++ b/ecos/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl @@ -0,0 +1,182 @@ +# ==================================================================== +# +# ser_mips_ref4955.cdl +# +# eCos serial MIPS/REF4955 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 2000-05-24 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_REF4955 { + display "REF4955 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_TX49_REF4955 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + REF4955." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/mips_tx49_ref4955_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_mips_ref4955.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 { + display "REF4955 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the + REF4955 port 0." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED +# implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW +# implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME { + display "Device name for the REF4955 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the + REF4955 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD { + display "Baud rate for the REF4955 serial port 0 driver" + flavor data + legal_values { 1200 2400 4800 9600 14400 19200 38400 57600 115200} + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the REF4955 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE { + display "Buffer size for the REF4955 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the REF4955 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL1 { + display "REF4955 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the + REF4955 port 1." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED +# implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW +# implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL1_NAME { + display "Device name for the REF4955 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for + the REF4955 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD { + display "Baud rate for the REF4955 serial port 1 driver" + flavor data + legal_values { 1200 2400 4800 9600 14400 19200 38400 57600 115200} + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the REF4955 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE { + display "Buffer size for the REF4955 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the REF4955 port 1." + } + } + + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"ref4955\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_ref4955.cdl diff --git a/ecos/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl b/ecos/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl new file mode 100644 index 0000000..ea514f3 --- /dev/null +++ b/ecos/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl @@ -0,0 +1,176 @@ +//========================================================================== +// +// devs/serial/mips/ref4955/src/mips_tx49_ref4955_ser.inl +// +// REF4955 Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 2000-05-24 +// Purpose: REF4955 Serial definitions +//####DESCRIPTIONEND#### +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// There are two serial ports. +#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1 +#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2 + +//----------------------------------------------------------------------------- +// The REF4955 board has a 14.318 MHz crystal, but the PC87338 part +// uses a 24MHz internal clock for baud rate calculation. +#define BAUD_DIVISOR(_x_) 24000000/13/16/(_x_) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + BAUD_DIVISOR(1200), + 0, // 1800 + BAUD_DIVISOR(2400), + 0, // 3600 + BAUD_DIVISOR(4800), + 0 , // 7200 + BAUD_DIVISOR(9600), + BAUD_DIVISOR(14400), + BAUD_DIVISOR(19200), + BAUD_DIVISOR(38400), + BAUD_DIVISOR(57600), + BAUD_DIVISOR(115200), + 0, // 230400 +}; + +//----------------------------------------------------------------------------- +// Port 0 descriptors + +#ifdef CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 +static pc_serial_info pc_serial_info0 = {CYG_DEVICE_SERIAL_SCC1, + CYGNUM_HAL_INTERRUPT_DEBUG_UART}; +#if CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE > 0 +static unsigned char pc_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE]; +static unsigned char pc_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf0[0], + sizeof(pc_serial_out_buf0), + &pc_serial_in_buf0[0], + sizeof(pc_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io0, + CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel0 + ); +#endif + +//----------------------------------------------------------------------------- +// Port 1 descriptors + +#ifdef CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL1 +static pc_serial_info pc_serial_info1 = {CYG_DEVICE_SERIAL_SCC2, + CYGNUM_HAL_INTERRUPT_USER_UART}; +#if CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE > 0 +static unsigned char pc_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE]; +static unsigned char pc_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf1[0], + sizeof(pc_serial_out_buf1), + &pc_serial_in_buf1[0], + sizeof(pc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io1, + CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel1 + ); +#endif + +// EOF mips_tx49_ref4955_ser.inl diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/ChangeLog b/ecos/packages/devs/serial/mips/upd985xx/current/ChangeLog new file mode 100644 index 0000000..4b52d82 --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/ChangeLog @@ -0,0 +1,43 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_upd985xx.cdl: Remove irrelevant doc link. + +2002-02-11 Jesper Skov <jskov@redhat.com> + + * src/upd985xx_serial.c (upd985xx_serial_init): Fix compile error. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_upd985xx.cdl: + Fix 234000->230400 typo. + +2001-07-18 Hugo Tyson <hmt@redhat.com> + + * src/upd985xx_serial.c: + * src/upd985xx_serial.h: + * cdl/ser_mips_upd985xx.cdl: + New files; implement asynchronous serial device for uPD985xx. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/cdl/ser_mips_upd985xx.cdl b/ecos/packages/devs/serial/mips/upd985xx/current/cdl/ser_mips_upd985xx.cdl new file mode 100644 index 0000000..6669288 --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/cdl/ser_mips_upd985xx.cdl @@ -0,0 +1,164 @@ +# ==================================================================== +# +# ser_mips_upd985xx.cdl +# +# eCos serial MIPS/Upd985xx configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): hmt +# Contributors: gthomas +# Date: 2001-07-17 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_UPD985XX { + display "NEC uPD985xx serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_UPD985XX + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + NEC MIPS uPD985xx system-on-chip device." + + compile -library=libextras.a upd985xx_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_upd985xx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL0 { + display "MIPS UPD985XX serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the MIPS UPD985XX + serial port." + + cdl_option CYGDAT_IO_SERIAL_MIPS_UPD985XX_SERIAL0_NAME { + display "Device name for MIPS UPD985XX serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + MIPS UPD985XX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BAUD { + display "Baud rate for the MIPS UPD985XX serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MIPS UPD985XX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE { + display "Buffer size for the MIPS UPD985XX serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MIPS UPD985XX port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_UPD985XX_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_UPD985XX_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_UPD985XX_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_UPD985XX_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_UPD985XX_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"upd985xx\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_upd985xx.cdl diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.c b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.c new file mode 100644 index 0000000..402ea9c --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.c @@ -0,0 +1,312 @@ +//========================================================================== +// +// io/serial/mips/upd985xx/upd985xx_serial.c +// +// NEC MIPS uPD985xx Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: gthomas +// Date: 2001-07-17 +// Purpose: NEC MIPS uPD985xx Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#include "upd985xx_serial.h" + +typedef struct upd985xx_serial_info { +// CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} upd985xx_serial_info; + +static bool upd985xx_serial_init(struct cyg_devtab_entry *tab); +static bool upd985xx_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo upd985xx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char upd985xx_serial_getc(serial_channel *chan); +static Cyg_ErrNo upd985xx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void upd985xx_serial_start_xmit(serial_channel *chan); +static void upd985xx_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 upd985xx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void upd985xx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(upd985xx_serial_funs, + upd985xx_serial_putc, + upd985xx_serial_getc, + upd985xx_serial_set_config, + upd985xx_serial_start_xmit, + upd985xx_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL0 +static upd985xx_serial_info upd985xx_serial_info0 = { + // base: (CYG_ADDRWORD)UPD985XX_UART3_CONTROL0, + int_num: CYGNUM_HAL_INTERRUPT_UART, +}; +#if CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE > 0 +static unsigned char upd985xx_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE]; +static unsigned char upd985xx_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS( + upd985xx_serial_channel0, + upd985xx_serial_funs, + upd985xx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &upd985xx_serial_out_buf0[0], sizeof(upd985xx_serial_out_buf0), + &upd985xx_serial_in_buf0[0], sizeof(upd985xx_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL( + upd985xx_serial_channel0, + upd985xx_serial_funs, + upd985xx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(upd985xx_serial_io0, + CYGDAT_IO_SERIAL_MIPS_UPD985XX_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + upd985xx_serial_init, + upd985xx_serial_lookup, // Serial driver may need initializing + &upd985xx_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL1 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +upd985xx_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + unsigned char parity; + unsigned char word_length; + unsigned char stop_bits; + int baud; + + parity = select_parity[new_config->parity]; + word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5]; + stop_bits = select_stop_bits[new_config->stop]; + baud = select_baud[new_config->baud]; + + if ((word_length == 0xFF) || + (parity == 0xFF) || + (stop_bits == 0xFF)) { + return false; // Unsupported configuration + } + + // First ensure we are accessing the right registers. + // Clear the divisor latch access bit + *UARTLCR &=~UARTLCR_DLAB; + + // Disable Receiver and Transmitter + // No such thing in uPD985xx - but we can mask interrupts: + *UARTIER = 0; + + // Clear sticky (writable) status bits. + // Ensure it's in 16550 mode at least: + *UARTFCR = UARTFCR_16550_MODE; + + // Set parity, word length, stop bits (keep DLAB clear) + *UARTLCR = word_length | parity | stop_bits; + + // Set the desired baud rate. + *UARTLCR |= UARTLCR_DLAB; + *UARTDLM = (baud >> 8) & 0xff; + *UARTDLL = baud & 0xff; + *UARTLCR &=~UARTLCR_DLAB; + + // Enable the receiver (with interrupts) and the transmitter. + *UARTIER = UARTIER_ERBFI; + + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +upd985xx_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + upd985xx_serial_info *upd985xx_chan = (upd985xx_serial_info *)chan->dev_priv; + int res; +#ifdef CYGDBG_IO_INIT + diag_printf("UPD985XX SERIAL init - dev: %x.%d\n", 0 /* upd985xx_chan->base */, + upd985xx_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(upd985xx_chan->int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + upd985xx_serial_ISR, + upd985xx_serial_DSR, + &upd985xx_chan->serial_interrupt_handle, + &upd985xx_chan->serial_interrupt); + cyg_drv_interrupt_attach(upd985xx_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(upd985xx_chan->int_num); + } + res = upd985xx_serial_config_port(chan, &chan->config, true); + return res; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +upd985xx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +upd985xx_serial_putc(serial_channel *chan, unsigned char c) +{ + if ( 0 == (UARTLSR_THRE & *UARTLSR) ) + return false; + *UARTTHR = (unsigned int)c; + return true; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +upd985xx_serial_getc(serial_channel *chan) +{ + while ( 0 == (UARTLSR_DR & *UARTLSR) ) + /* do nothing */ ; + + return (char)*UARTRBR; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +upd985xx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != upd985xx_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +upd985xx_serial_start_xmit(serial_channel *chan) +{ + (chan->callbacks->xmt_char)(chan); // Kick transmitter (if necessary) + *UARTIER |= UARTIER_ERBEI; // enable interrupts +} + +// Disable the transmitter on the device +static void +upd985xx_serial_stop_xmit(serial_channel *chan) +{ + *UARTIER &=~UARTIER_ERBEI; // disable interrupts +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +upd985xx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(vector); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +upd985xx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + + int stat = *UARTIIR; + + stat &= UARTIIR_UIID_MASK; + + if (stat == UARTIIR_TX_EMPTY) { + (chan->callbacks->xmt_char)(chan); + } + if (stat == UARTIIR_RXD_AVAIL) { + while (0 != (UARTLSR_DR & *UARTLSR)) { + (chan->callbacks->rcv_char)(chan, (char)*UARTRBR); + } + } + cyg_drv_interrupt_acknowledge(vector); + cyg_drv_interrupt_unmask(vector); +} + +// ------------------------------------------------------------------------ +// EOF upd985xx_serial.c diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.h b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.h new file mode 100644 index 0000000..ad9f96c --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_MIPS_UPD985XX_SERIAL_H +#define CYGONCE_MIPS_UPD985XX_SERIAL_H +// ==================================================================== +// +// upd985xx_serial.h +// +// Device I/O - Description of NEC MIPS uPD985xx serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: gthomas +// Date: 2001-07-17 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on NEC MIPS uPD985xx + +#include <cyg/hal/hal_arch.h> // Register definitions + +static unsigned char select_word_length[] = { + 0xFF, // 5 bits / word (char) + 0xFF, // 6 + UARTLCR_7, // 7 + UARTLCR_8 // 8 +}; + +static unsigned char select_stop_bits[] = { + 0xFF, // N/A + UARTLCR_STB1, // 1 stop bit + 0xFF, // 1.5 stop bit + UARTLCR_STB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + UARTLCR_NOP, // No parity + UARTLCR_EP, // Even parity + UARTLCR_OP, // Odd parity + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + UARTDLL_VAL( 50 ), // 50 + UARTDLL_VAL( 75 ), // 75 + UARTDLL_VAL( 110 ), // 110 + 0, // 134.5 + UARTDLL_VAL( 150 ), // 150 + UARTDLL_VAL( 200 ), // 200 + UARTDLL_VAL( 300 ), // 300 + UARTDLL_VAL( 600 ), // 600 + UARTDLL_VAL( 1200 ), // 1200 + UARTDLL_VAL( 1800 ), // 1800 + UARTDLL_VAL( 2400 ), // 2400 + UARTDLL_VAL( 3600 ), // 3600 + UARTDLL_VAL( 4800 ), // 4800 + UARTDLL_VAL( 7200 ), // 7200 + UARTDLL_VAL( 9600 ), // 9600 + UARTDLL_VAL( 14400 ), // 14400 + UARTDLL_VAL( 19200 ), // 19200 + UARTDLL_VAL( 38400 ), // 38400 + UARTDLL_VAL( 57600 ), // 57600 + UARTDLL_VAL( 115200 ), // 115200 + UARTDLL_VAL( 230400 ), // 230400 +}; + +#endif // CYGONCE_MIPS_UPD985XX_SERIAL_H + +// ------------------------------------------------------------------------ +// EOF upd985xx_serial.h diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/ChangeLog b/ecos/packages/devs/serial/mips/vrc437x/current/ChangeLog new file mode 100644 index 0000000..88678cc --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/ChangeLog @@ -0,0 +1,1206 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_vrc437x.cdl: Remove irrelevant doc link. + +2001-09-18 Nick Garnett <nickg@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + * src/vrc437x_serial.h: + * src/vrc437x_serial.c: + Fixed VRC4373 -> VRC437X conversions that were missed. + Also made default baud rates 38400 rather than 9600. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + Fix 234000->230400 typo. + +2001-09-07 Nick Garnett <nickg@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + * src/vrc437x_serial.h: + * src/vrc437x_serial.c: + Moved this entire tree over to vrc437x from vrc4373 to make it + generic to both kinds of board. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_vrc4373.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/vrc4373_serial.c (vrc4373_serial_set_config): Now use keys + to make more flexible. + +2000-07-22 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/vrc4373_serial.c (vrc4373_serial_init): Add comment about broken + interrupt handling + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_mips_vrc4373.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl b/ecos/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl new file mode 100644 index 0000000..fb459a0 --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl @@ -0,0 +1,202 @@ +# ==================================================================== +# +# ser_mips_vrc437x.cdl +# +# eCos serial MIPS/VRC437X configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_VRC437X { + display "VRC437X serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_VR4300_VRC437X + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + VRC437X." + + compile -library=libextras.a vrc437x_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_vrc437x.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 { + display "VRC437X serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the VRC437X port 0." + + cdl_option CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME { + display "Device name for the VRC437X serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the VRC437X + port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD { + display "Baud rate for the VRC437X serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + VRC437X port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE { + display "Buffer size for the VRC437X serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the VRC437X port 0." + } +} +cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 { + display "VRC437X serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the VRC437X port 1." + + cdl_option CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL1_NAME { + display "Device name for the VRC437X serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + VRC437X port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD { + display "Baud rate for the VRC437X serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + VRC437X port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE { + display "Buffer size for the VRC437X serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the VRC437X port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_VRC437X_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_VRC437X_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"vrc437X\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_vrc437x.cdl diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c new file mode 100644 index 0000000..96dc6d3 --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c @@ -0,0 +1,493 @@ +//========================================================================== +// +// io/serial/mips/vrc437x_serial.c +// +// Mips VRC437X Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-15 +// Purpose: VRC437X Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X + +#include "vrc437x_serial.h" + +#if defined(CYGPKG_HAL_MIPS_LSBFIRST) +#define VRC437X_SCC_BASE 0xC1000000 +#elif defined(CYGPKG_HAL_MIPS_MSBFIRST) +#define VRC437X_SCC_BASE 0xC1000003 +#else +#error MIPS endianness not defined by configuration +#endif + +#define VRC437X_SCC_INT CYGNUM_HAL_INTERRUPT_DUART +#define SCC_CHANNEL_A 4 +#define SCC_CHANNEL_B 0 + +extern void diag_printf(const char *fmt, ...); + +typedef struct vrc437x_serial_info { + CYG_ADDRWORD base; + unsigned char regs[16]; // Known register state (since hardware is write-only!) +} vrc437x_serial_info; + +static bool vrc437x_serial_init(struct cyg_devtab_entry *tab); +static bool vrc437x_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo vrc437x_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char vrc437x_serial_getc(serial_channel *chan); +static Cyg_ErrNo vrc437x_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void vrc437x_serial_start_xmit(serial_channel *chan); +static void vrc437x_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void vrc437x_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(vrc437x_serial_funs, + vrc437x_serial_putc, + vrc437x_serial_getc, + vrc437x_serial_set_config, + vrc437x_serial_start_xmit, + vrc437x_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 +static vrc437x_serial_info vrc437x_serial_info0 = {VRC437X_SCC_BASE+SCC_CHANNEL_A}; +#if CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE > 0 +static unsigned char vrc437x_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE]; +static unsigned char vrc437x_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(vrc437x_serial_channel0, + vrc437x_serial_funs, + vrc437x_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &vrc437x_serial_out_buf0[0], sizeof(vrc437x_serial_out_buf0), + &vrc437x_serial_in_buf0[0], sizeof(vrc437x_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(vrc437x_serial_channel0, + vrc437x_serial_funs, + vrc437x_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(vrc437x_serial_io0, + CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + vrc437x_serial_init, + vrc437x_serial_lookup, // Serial driver may need initializing + &vrc437x_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 +static vrc437x_serial_info vrc437x_serial_info1 = {VRC437X_SCC_BASE+SCC_CHANNEL_B}; +#if CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE > 0 +static unsigned char vrc437x_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE]; +static unsigned char vrc437x_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(vrc437x_serial_channel1, + vrc437x_serial_funs, + vrc437x_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &vrc437x_serial_out_buf1[0], sizeof(vrc437x_serial_out_buf1), + &vrc437x_serial_in_buf1[0], sizeof(vrc437x_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(vrc437x_serial_channel1, + vrc437x_serial_funs, + vrc437x_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(vrc437x_serial_io1, + CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + vrc437x_serial_init, + vrc437x_serial_lookup, // Serial driver may need initializing + &vrc437x_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 + +static cyg_interrupt vrc437x_serial_interrupt; +static cyg_handle_t vrc437x_serial_interrupt_handle; + +// Table which maps hardware channels (A,B) to software ones +struct serial_channel *vrc437x_chans[] = { +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 // Hardware channel A + &vrc437x_serial_channel0, +#else + 0, +#endif +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 // Hardware channel B + &vrc437x_serial_channel1, +#else + 0, +#endif +}; + +// Support functions which access the serial device. Note that this chip requires +// a substantial delay after each access. + +#define SCC_DELAY 100 +inline static void +scc_delay(void) +{ + int i; + for (i = 0; i < SCC_DELAY; i++) ; +} + +inline static void +scc_write_reg(volatile unsigned char *reg, unsigned char val) +{ + scc_delay(); + *reg = val; +} + +inline static unsigned char +scc_read_reg(volatile unsigned char *reg) +{ + unsigned char val; + scc_delay(); + val = *reg; + return (val); +} + +inline static unsigned char +scc_read_ctl(volatile struct serial_port *port, int reg) +{ + if (reg != 0) { + scc_write_reg(&port->scc_ctl, reg); + } + return (scc_read_reg(&port->scc_ctl)); +} + +inline static void +scc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val) +{ + if (reg != 0) { + scc_write_reg(&port->scc_ctl, reg); + } + scc_write_reg(&port->scc_ctl, val); +} + +inline static unsigned char +scc_read_dat(volatile struct serial_port *port) +{ + return (scc_read_reg(&port->scc_dat)); +} + +inline static void +scc_write_dat(volatile struct serial_port *port, unsigned char val) +{ + scc_write_reg(&port->scc_dat, val); +} + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +vrc437x_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + cyg_int32 baud_rate = select_baud[new_config->baud]; + cyg_int32 baud_divisor; + unsigned char *regs = &vrc437x_chan->regs[0]; + if (baud_rate == 0) return false; + // Compute state of registers. The register/control state needs to be kept in + // the shadow variable 'regs' because the hardware registers can only be written, + // not read (in general). + if (init) { + // Insert appropriate resets? + if (chan->out_cbuf.len != 0) { + regs[R1] = WR1_IntAllRx; + regs[R9] = WR9_MIE | WR9_NoVector; + } else { + regs[R1] = 0; + regs[R9] = 0; + } + // Clocks are from the baud rate generator + regs[R11] = WR11_TRxCBR | WR11_TRxCOI | WR11_TxCBR | WR11_RxCBR; + regs[R14] = WR14_BRenable | WR14_BRSRC; + regs[R10] = 0; // Unused in this [async] mode + regs[R15] = 0; + } + regs[R3] = WR3_RxEnable | select_word_length_WR3[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + regs[R4] = WR4_X16CLK | select_stop_bits[new_config->stop] | select_parity[new_config->parity]; + regs[R5] = WR5_TxEnable | select_word_length_WR5[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + baud_divisor = BRTC(baud_rate); + regs[R12] = baud_divisor & 0xFF; + regs[R13] = baud_divisor >> 8; + // Now load the registers + scc_write_ctl(port, R4, regs[R4]); + scc_write_ctl(port, R10, regs[R10]); + scc_write_ctl(port, R3, regs[R3] & ~WR3_RxEnable); + scc_write_ctl(port, R5, regs[R5] & ~WR5_TxEnable); + scc_write_ctl(port, R1, regs[R1]); + scc_write_ctl(port, R9, regs[R9]); + scc_write_ctl(port, R11, regs[R11]); + scc_write_ctl(port, R12, regs[R12]); + scc_write_ctl(port, R13, regs[R13]); + scc_write_ctl(port, R14, regs[R14]); + scc_write_ctl(port, R15, regs[R15]); + scc_write_ctl(port, R3, regs[R3]); + scc_write_ctl(port, R5, regs[R5]); + // Update configuration + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +vrc437x_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + static bool init = false; +#ifdef CYGDBG_IO_INIT + diag_printf("VRC437X SERIAL init '%s' - dev: %x\n", tab->name, vrc437x_chan->base); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (!init && chan->out_cbuf.len != 0) { + init = true; +// Note that the hardware is rather broken. The interrupt status needs to +// be read using only channel A + cyg_drv_interrupt_create(VRC437X_SCC_INT, + 99, + (cyg_addrword_t)VRC437X_SCC_BASE+SCC_CHANNEL_A, + vrc437x_serial_ISR, + vrc437x_serial_DSR, + &vrc437x_serial_interrupt_handle, + &vrc437x_serial_interrupt); + cyg_drv_interrupt_attach(vrc437x_serial_interrupt_handle); + cyg_drv_interrupt_unmask(VRC437X_SCC_INT); + } + vrc437x_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +vrc437x_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +vrc437x_serial_putc(serial_channel *chan, unsigned char c) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + if (scc_read_ctl(port, R0) & RR0_TxEmpty) { +// Transmit buffer is empty + scc_write_dat(port, c); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +vrc437x_serial_getc(serial_channel *chan) +{ + unsigned char c; + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + while ((scc_read_ctl(port, R0) & RR0_RxAvail) == 0) ; // Wait for char + c = scc_read_dat(port); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +vrc437x_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != vrc437x_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +vrc437x_serial_start_xmit(serial_channel *chan) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + if ((vrc437x_chan->regs[R1] & WR1_TxIntEnab) == 0) { + CYG_INTERRUPT_STATE old; + HAL_DISABLE_INTERRUPTS(old); + vrc437x_chan->regs[R1] |= WR1_TxIntEnab; // Enable Tx interrupt + scc_write_ctl(port, R1, vrc437x_chan->regs[R1]); + (chan->callbacks->xmt_char)(chan); // Send first character to start xmitter + HAL_RESTORE_INTERRUPTS(old); + } +} + +// Disable the transmitter on the device +static void +vrc437x_serial_stop_xmit(serial_channel *chan) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + if ((vrc437x_chan->regs[R1] & WR1_TxIntEnab) != 0) { + CYG_INTERRUPT_STATE old; + HAL_DISABLE_INTERRUPTS(old); + vrc437x_chan->regs[R1] &= ~WR1_TxIntEnab; // Disable Tx interrupt + scc_write_ctl(port, R1, vrc437x_chan->regs[R1]); + HAL_RESTORE_INTERRUPTS(old); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(VRC437X_SCC_INT); + cyg_drv_interrupt_acknowledge(VRC437X_SCC_INT); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +inline static void +vrc437x_int(serial_channel *chan, unsigned char stat) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + // Note: 'stat' value is interrupt status register, shifted into "B" position + if (stat & RR3_BRxIP) { + // Receive interrupt + unsigned char c; + c = scc_read_dat(port); + (chan->callbacks->rcv_char)(chan, c); + } + if (stat & RR3_BTxIP) { + // Transmit interrupt + (chan->callbacks->xmt_char)(chan); + } + if (stat & RR3_BExt) { + // Status interrupt (parity error, framing error, etc) + } +} + +// Serial I/O - high level interrupt handler (DSR) +// Note: This device presents a single interrupt for both channels. Thus the +// interrupt handler has to query the device and decide which channel needs service. +// Additionally, more than one interrupt condition may be present so this needs to +// be done in a loop until all interrupt requests have been handled. +// Also note that the hardware is rather broken. The interrupt status needs to +// be read using only channel A (pointed to by 'data') +static void +vrc437x_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan; + volatile struct serial_port *port = (volatile struct serial_port *)data; + unsigned char stat; + while (true) { + stat = scc_read_ctl(port, R3); + if (stat & (RR3_AExt | RR3_ATxIP | RR3_ARxIP)) { + chan = vrc437x_chans[0]; // Hardware channel A + vrc437x_int(chan, stat>>3); // Handle interrupt + } else if (stat & (RR3_BExt | RR3_BTxIP | RR3_BRxIP)) { + chan = vrc437x_chans[1]; // Hardware channel B + vrc437x_int(chan, stat); // Handle interrupt + } else { + // No more interrupts, all done + break; + } + } + cyg_drv_interrupt_unmask(VRC437X_SCC_INT); +} +#endif diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h new file mode 100644 index 0000000..23e4127 --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h @@ -0,0 +1,343 @@ +#ifndef CYGONCE_MIPS_VRC437X_SERIAL_H +#define CYGONCE_MIPS_VRC437X_SERIAL_H + +// ==================================================================== +// +// vrc437x_serial.h +// +// Device I/O - Description of Mips VRC437X serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-15 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Mips VRC437X +// Based on Zilog 85C30 SCC + +struct serial_port { + unsigned char _byte[16]; +}; + +#define scc_ctl _byte[0] +#define scc_dat _byte[8] + +#define R0 0 /* Register selects */ +#define R1 1 +#define R2 2 +#define R3 3 +#define R4 4 +#define R5 5 +#define R6 6 +#define R7 7 +#define R8 8 +#define R9 9 +#define R10 10 +#define R11 11 +#define R12 12 +#define R13 13 +#define R14 14 +#define R15 15 + +/* Write Register 0 */ +#define WR0_NullCode 0x00 /* Null Code */ +#define WR0_PointHigh 0x08 /* Select upper half of registers */ +#define WR0_ResExtInt 0x10 /* Reset Ext. Status Interrupts */ +#define WR0_SendAbort 0x18 /* HDLC Abort */ +#define WR0_ResRxIntFC 0x20 /* Reset RxINT on First Character */ +#define WR0_ResTxP 0x28 /* Reset TxINT Pending */ +#define WR0_ErrReset 0x30 /* Error Reset */ +#define WR0_ResHiIUS 0x38 /* Reset highest IUS */ + +#define WR0_ResRxCRC 0x40 /* Reset Rx CRC Checker */ +#define WR0_ResTxCRC 0x80 /* Reset Tx CRC Checker */ +#define WR0_ResEOMlatch 0xC0 /* Reset EOM latch */ + +/* Write Register 1 */ + +#define WR1_ExtIntEnab 0x01 /* Ext Int Enable */ +#define WR1_TxIntEnab 0x02 /* Tx Int Enable */ +#define WR1_ParSpec 0x04 /* Parity is special condition */ + +#define WR1_RxIntDisab 0x00 /* Rx Int Disable */ +#define WR1_RxIntFCE 0x08 /* Rx Int on First Character Only or Error */ +#define WR1_IntAllRx 0x10 /* Int on all Rx Characters or error */ +#define WR1_IntErrRx 0x18 /* Int on error only */ + +#define WR1_WtRdyRT 0x20 /* Wait/Ready on R/T */ +#define WR1_WtFnRdyFn 0x40 /* Wait/FN/Ready FN */ +#define WR1_WtRdyEnab 0x80 /* Wait/Ready Enable */ + +/* Write Register #2 (Interrupt Vector) */ + +/* Write Register 3 */ + +#define WR3_RxEnable 0x01 /* Rx Enable */ +#define WR3_SyncInhibit 0x02 /* Sync Character Load Inhibit */ +#define WR3_AddrSearch 0x04 /* Address Search Mode (SDLC) */ +#define WR3_RxCRC_ENAB 0x08 /* Rx CRC Enable */ +#define WR3_EntHuntMode 0x10 /* Enter Hunt Mode */ +#define WR3_AutoEnab 0x20 /* Auto Enables */ +#define WR3_Rx5 0x00 /* Rx 5 Bits/Character */ +#define WR3_Rx7 0x40 /* Rx 7 Bits/Character */ +#define WR3_Rx6 0x80 /* Rx 6 Bits/Character */ +#define WR3_Rx8 0xc0 /* Rx 8 Bits/Character */ +#define WR3_RxNbitsMask 0xc0 + +/* Write Register 4 */ + +#define WR4_ParityEn 0x01 /* Parity Enable */ +#define WR4_ParityEven 0x02 /* Parity Even/Odd* */ + +#define WR4_SyncEnable 0x00 /* Sync Modes Enable */ +#define WR4_SB1 0x04 /* 1 stop bit/char */ +#define WR4_SB15 0x08 /* 1.5 stop bits/char */ +#define WR4_SB2 0x0c /* 2 stop bits/char */ +#define WR4_SB_MASK 0x0c + +#define WR4_Monsync 0x00 /* 8 Bit Sync character */ +#define WR4_Bisync 0x10 /* 16 bit sync character */ +#define WR4_SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ +#define WR4_EXtSync 0x30 /* External Sync Mode */ + +#define WR4_X1CLK 0x00 /* x1 clock mode */ +#define WR4_X16CLK 0x40 /* x16 clock mode */ +#define WR4_X32CLK 0x80 /* x32 clock mode */ +#define WR4_X64CLK 0xC0 /* x64 clock mode */ +#define WR4_XCLK_MASK 0xC0 + +/* Write Register 5 */ + +#define WR5_TxCRCEnab 0x01 /* Tx CRC Enable */ +#define WR5_RTS 0x02 /* RTS */ +#define WR5_SDLC_CRC 0x04 /* SDLC/CRC-16 */ +#define WR5_TxEnable 0x08 /* Tx Enable */ +#define WR5_SendBreak 0x10 /* Send Break */ +#define WR5_Tx5 0x00 /* Tx 5 bits (or less)/character */ +#define WR5_Tx7 0x20 /* Tx 7 bits/character */ +#define WR5_Tx6 0x40 /* Tx 6 bits/character */ +#define WR5_Tx8 0x60 /* Tx 8 bits/character */ +#define WR5_TxNbitsMask 0x60 +#define WR5_DTR 0x80 /* DTR */ + +/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ + +/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ + +/* Write Register 8 (transmit buffer) */ + +/* Write Register 9 (Master interrupt control) */ +#define WR9_VIS 0x01 /* Vector Includes Status */ +#define WR9_NoVector 0x02 /* No Vector */ +#define WR9_DLC 0x04 /* Disable Lower Chain */ +#define WR9_MIE 0x08 /* Master Interrupt Enable */ +#define WR9_StatHi 0x10 /* Status high */ +#define WR9_NoReset 0x00 /* No reset on write to R9 */ +#define WR9_ResetB 0x40 /* Reset channel B */ +#define WR9_ResetA 0x80 /* Reset channel A */ +#define WR9_HwReset 0xc0 /* Force hardware reset */ + +/* Write Register 10 (misc control bits) */ +#define WR10_Bit6 0x01 /* 6 bit/8bit sync */ +#define WR10_LoopMode 0x02 /* SDLC Loop mode */ +#define WR10_AbrtUnder 0x04 /* Abort/flag on SDLC xmit underrun */ +#define WR10_MarkIdle 0x08 /* Mark/flag on idle */ +#define WR10_GAOP 0x10 /* Go active on poll */ +#define WR10_NRZ 0x00 /* NRZ mode */ +#define WR10_NRZI 0x20 /* NRZI mode */ +#define WR10_FM1 0x40 /* FM1 (transition = 1) */ +#define WR10_FM0 0x60 /* FM0 (transition = 0) */ +#define WR10_CRCPS 0x80 /* CRC Preset I/O */ + +/* Write Register 11 (Clock Mode control) */ +#define WR11_TRxCXT 0x00 /* TRxC = Xtal output */ +#define WR11_TRxCTC 0x01 /* TRxC = Transmit clock */ +#define WR11_TRxCBR 0x02 /* TRxC = BR Generator Output */ +#define WR11_TRxCDP 0x03 /* TRxC = DPLL output */ +#define WR11_TRxCOI 0x04 /* TRxC O/I */ +#define WR11_TxCRTxCP 0x00 /* Transmit clock = RTxC pin */ +#define WR11_TxCTRxCP 0x08 /* Transmit clock = TRxC pin */ +#define WR11_TxCBR 0x10 /* Transmit clock = BR Generator output */ +#define WR11_TxCDPLL 0x18 /* Transmit clock = DPLL output */ +#define WR11_RxCRTxCP 0x00 /* Receive clock = RTxC pin */ +#define WR11_RxCTRxCP 0x20 /* Receive clock = TRxC pin */ +#define WR11_RxCBR 0x40 /* Receive clock = BR Generator output */ +#define WR11_RxCDPLL 0x60 /* Receive clock = DPLL output */ +#define WR11_RTxCX 0x80 /* RTxC Xtal/No Xtal */ + +/* Write Register 12 (lower byte of baud rate generator time constant) */ + +/* Write Register 13 (upper byte of baud rate generator time constant) */ + +/* Write Register 14 (Misc control bits) */ +#define WR14_BRenable 0x01 /* Baud rate generator enable */ +#define WR14_BRSRC 0x02 /* Baud rate generator source */ +#define WR14_DTRreq 0x04 /* DTR/Request function */ +#define WR14_AutoEcho 0x08 /* Auto Echo */ +#define WR14_LoopBack 0x10 /* Local loopback */ +#define WR14_Search 0x20 /* Enter search mode */ +#define WR14_RMC 0x40 /* Reset missing clock */ +#define WR14_NoDPLL 0x60 /* Disable DPLL */ +#define WR14_SSBR 0x80 /* Set DPLL source = BR generator */ +#define WR14_SSRTxC 0xa0 /* Set DPLL source = RTxC */ +#define WR14_SFMM 0xc0 /* Set FM mode */ +#define WR14_SNRZI 0xe0 /* Set NRZI mode */ + +/* Write Register 15 (external/status interrupt control) */ +#define WR15_ZCIE 0x02 /* Zero count IE */ +#define WR15_DCDIE 0x08 /* DCD IE */ +#define WR15_SYNCIE 0x10 /* Sync/hunt IE */ +#define WR15_CTSIE 0x20 /* CTS IE */ +#define WR15_TxUIE 0x40 /* Tx Underrun/EOM IE */ +#define WR15_BRKIE 0x80 /* Break/Abort IE */ + +/* Read Register 0 */ +#define RR0_RxAvail 0x01 /* Rx Character Available */ +#define RR0_Zcount 0x02 /* Zero count */ +#define RR0_TxEmpty 0x04 /* Tx Buffer empty */ +#define RR0_DCD 0x08 /* DCD */ +#define RR0_SyncHunt 0x10 /* Sync/hunt */ +#define RR0_CTS 0x20 /* CTS */ +#define RR0_TxEOM 0x40 /* Tx underrun */ +#define RR0_BrkAbort 0x80 /* Break/Abort */ + +/* Read Register 1 */ +#define RR1_AllSent 0x01 /* All sent */ +/* Residue Data for 8 Rx bits/char programmed */ +#define RR1_RES3 0x08 /* 0/3 */ +#define RR1_RES4 0x04 /* 0/4 */ +#define RR1_RES5 0x0c /* 0/5 */ +#define RR1_RES6 0x02 /* 0/6 */ +#define RR1_RES7 0x0a /* 0/7 */ +#define RR1_RES8 0x06 /* 0/8 */ +#define RR1_RES18 0x0e /* 1/8 */ +#define RR1_RES28 0x00 /* 2/8 */ +/* Special Rx Condition Interrupts */ +#define RR1_PariryError 0x10 /* Parity error */ +#define RR1_RxOverrun 0x20 /* Rx Overrun Error */ +#define RR1_FrameError 0x40 /* CRC/Framing Error */ +#define RR1_EndOfFrame 0x80 /* End of Frame (SDLC) */ + +/* Read Register 2 (channel b only) - Interrupt vector */ + +/* Read Register 3 (interrupt pending register) ch a only */ +#define RR3_BExt 0x01 /* Channel B Ext/Stat IP */ +#define RR3_BTxIP 0x02 /* Channel B Tx IP */ +#define RR3_BRxIP 0x04 /* Channel B Rx IP */ +#define RR3_AExt 0x08 /* Channel A Ext/Stat IP */ +#define RR3_ATxIP 0x10 /* Channel A Tx IP */ +#define RR3_ARxIP 0x20 /* Channel A Rx IP */ + +/* Read Register 8 (receive data register) */ + +/* Read Register 10 (misc status bits) */ +#define RR10_OnLoop 0x02 /* On loop */ +#define RR10_LoopSend 0x10 /* Loop sending */ +#define RR10_Clk2Mis 0x40 /* Two clocks missing */ +#define RR10_Clk1Mis 0x80 /* One clock missing */ + +/* Read Register 12 (lower byte of baud rate generator constant) */ + +/* Read Register 13 (upper byte of baud rate generator constant) */ + +/* Read Register 15 (value of WR 15) */ + +#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) +#define DUART_CLOCK 4915200 /* Z8530 duart */ +#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ + +static unsigned char select_word_length_WR3[] = { + WR3_Rx5, // 5 bits / word (char) + WR3_Rx6, + WR3_Rx7, + WR3_Rx8 +}; + +static unsigned char select_word_length_WR5[] = { + WR5_Tx5, // 5 bits / word (char) + WR5_Tx6, + WR5_Tx7, + WR5_Tx8 +}; + +static unsigned char select_stop_bits[] = { + 0, + WR4_SB1, // 1 stop bit + WR4_SB15, // 1.5 stop bit + WR4_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + 0, // No parity + WR4_ParityEn | WR4_ParityEven, // Even parity + WR4_ParityEn, // Odd parity + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_MIPS_VRC437X_SERIAL_H diff --git a/ecos/packages/devs/serial/mn10300/mn10300/current/ChangeLog b/ecos/packages/devs/serial/mn10300/mn10300/current/ChangeLog new file mode 100644 index 0000000..7414cf2 --- /dev/null +++ b/ecos/packages/devs/serial/mn10300/mn10300/current/ChangeLog @@ -0,0 +1,1181 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mn10300.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mn10300.cdl: + Fix 234000->230400 typo. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300_serial.c (mn10300_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_mn10300.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mn10300/mn10300/current/cdl/ser_mn10300.cdl b/ecos/packages/devs/serial/mn10300/mn10300/current/cdl/ser_mn10300.cdl new file mode 100644 index 0000000..6d2f192 --- /dev/null +++ b/ecos/packages/devs/serial/mn10300/mn10300/current/cdl/ser_mn10300.cdl @@ -0,0 +1,237 @@ +# ==================================================================== +# +# ser_mn10300.cdl +# +# eCos serial MN10300 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-07 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MN10300 { + display "MN10300 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MN10300 + + # Note: this is not currently tied to a specific board since the + # ports are "on chip" + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + MN10300." + + compile -library=libextras.a mn10300_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mn10300.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +# FIXME: Bad name +cdl_option CYGPKG_IO_SERIAL_MN10300_POLLED_MODE { + display "MN10300 polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the MN10300 should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_MN10300_SERIAL0 { + display "MN10300 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 0 on the + MN10300." + + cdl_option CYGDAT_IO_SERIAL_MN10300_SERIAL0_NAME { + display "Device name for MN10300 serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name port 0 on the MN10300." + } + + cdl_option CYGNUM_IO_SERIAL_MN10300_SERIAL0_BAUD { + display "Baud rate for the MN10300 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MN10300 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MN10300_SERIAL0_BUFSIZE { + display "Buffer size for the MN10300 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MN10300 port 0." + } +} + +cdl_component CYGPKG_IO_SERIAL_MN10300_SERIAL1 { + display "MN10300 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 1 on + the MN10300." + + cdl_option CYGDAT_IO_SERIAL_MN10300_SERIAL1_NAME { + display "Device name for MN10300 serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name port 1 on the MN10300." + } + + cdl_option CYGNUM_IO_SERIAL_MN10300_SERIAL1_BAUD { + display "Baud rate for the MN10300 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MN10300 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MN10300_SERIAL1_BUFSIZE { + display "Buffer size for the MN10300 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MN10300 port 1." + } +} +cdl_component CYGPKG_IO_SERIAL_MN10300_SERIAL2 { + display "MN10300 serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 2 on the + MN10300." + + cdl_option CYGDAT_IO_SERIAL_MN10300_SERIAL2_NAME { + display "Device name for MN10300 serial port 2" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name port 2 on the MN10300." + } + + cdl_option CYGNUM_IO_SERIAL_MN10300_SERIAL2_BAUD { + display "Baud rate for the MN10300 serial port 2 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MN10300 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_MN10300_SERIAL2_BUFSIZE { + display "Buffer size for the MN10300 serial port 2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MN10300 port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_MN10300_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MN10300_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MN10300_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_mn10300.cdl diff --git a/ecos/packages/devs/serial/mn10300/mn10300/current/src/mn10300_serial.c b/ecos/packages/devs/serial/mn10300/mn10300/current/src/mn10300_serial.c new file mode 100644 index 0000000..0a81cbd --- /dev/null +++ b/ecos/packages/devs/serial/mn10300/mn10300/current/src/mn10300_serial.c @@ -0,0 +1,1035 @@ +//========================================================================== +// +// mn10300_serial.c +// +// Serial device driver for mn10300 on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-02-25 +// Purpose: MN10300 serial device driver +// Description: MN10300 serial device driver +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/io_serial.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/hal/hal_intr.h> + +#ifdef CYGPKG_IO_SERIAL_MN10300 + +#define CYG_HAL_MN10300_SERIAL_RX_FIFO + +//------------------------------------------------------------------------- + +extern void diag_printf(const char *fmt, ...); + +//------------------------------------------------------------------------- +// Forward definitions + +static bool mn10300_serial_init(struct cyg_devtab_entry *tab); +static bool mn10300_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo mn10300_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char mn10300_serial_getc(serial_channel *chan); +static Cyg_ErrNo mn10300_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void mn10300_serial_start_xmit(serial_channel *chan); +static void mn10300_serial_stop_xmit(serial_channel *chan); + +#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE +static cyg_uint32 mn10300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static cyg_uint32 mn10300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void mn10300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static void mn10300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#endif + +//------------------------------------------------------------------------- + +#define BUFSIZE 128 + +//------------------------------------------------------------------------- +// MN10300 serial line control register values: + +// Offsets to serial control registers from base +#define SERIAL_CTR 0x0 +#define SERIAL_ICR 0x4 +#define SERIAL_TXB 0x8 +#define SERIAL_RXB 0x9 +#define SERIAL_STR 0xc +#define SERIAL_TIM 0xd + +// Status register bits +#define SR_RBF 0x10 +#define SR_TBF 0x20 +#define SR_RXF 0x40 +#define SR_TXF 0x80 + +// Control register bits +#define LCR_SB1 0x00 +#define LCR_SB1_5 0x00 +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PS 0x40 // Forced "space" parity +#define LCR_PM 0x50 // Forced "mark" parity +#define LCR_PE 0x60 // Parity mode - even +#define LCR_PO 0x70 // Parity mode - odd +#define LCR_WL5 0x00 // not supported - use 7bit +#define LCR_WL6 0x00 // not supported - use 7bit +#define LCR_WL7 0x00 // 7 bit chars +#define LCR_WL8 0x80 // 8 bit chars +#define LCR_RXE 0x4000 // receive enable +#define LCR_TXE 0x8000 // transmit enable + +#if defined(CYGPKG_HAL_MN10300_AM31) +#define LCR_TWE 0x0100 // interrupt enable (only on serial2/AM31) +#else +#define LCR_TWE 0x0000 // Bit does not exist in other variants +#endif + +//------------------------------------------------------------------------- +// MN10300 timer registers: + +#undef TIMER_BR +#undef TIMER_MD +#define TIMER_MD 0x00 +#define TIMER_BR 0x10 + +//------------------------------------------------------------------------- +// Serial and timer base registers: + +#if defined(CYGPKG_HAL_MN10300_AM31) + +#define SERIAL0_BASE 0x34000800 +#define SERIAL1_BASE 0x34000810 +#define SERIAL2_BASE 0x34000820 + +#define TIMER0_BASE 0x34001000 +#define TIMER1_BASE 0x34001001 +#define TIMER2_BASE 0x34001002 + +#define SERIAL0_TIMER_SELECT 0x0004 // timer 0 +#define SERIAL1_TIMER_SELECT 0x0004 // timer 1 +#define SERIAL2_TIMER_SELECT 0x0001 // timer 2 + +#ifdef CYGPKG_HAL_MN10300_AM31_STDEVAL1 +// The use of PORT3 to provide CTS/CTR is specific to +// the STDEVAL1 board only. +#define PORT3_MD 0x36008025 +#endif + +#define ENABLE_TRANSMIT_INTERRUPT(mn10300_chan) \ +CYG_MACRO_START \ + if( mn10300_chan->is_serial2 ) \ + cr |= LCR_TWE; \ + else \ + cr |= LCR_TXE; \ +CYG_MACRO_END + +#define DISABLE_TRANSMIT_INTERRUPT(mn10300_chan) \ +CYG_MACRO_START \ + if( mn10300_chan->is_serial2 ) \ + cr &= ~LCR_TWE; \ + else \ + cr &= ~LCR_TXE; \ +CYG_MACRO_END + +#elif defined(CYGPKG_HAL_MN10300_AM33) + +#define SERIAL0_BASE 0xd4002000 +#define SERIAL1_BASE 0xd4002010 +#define SERIAL2_BASE 0xd4002020 + +#define TIMER0_BASE 0xd4003002 +#define TIMER1_BASE 0xd4003001 +#define TIMER2_BASE 0xd4003003 + +#define SERIAL0_TIMER_SELECT 0x0005 // timer 2 +#define SERIAL1_TIMER_SELECT 0x0004 // timer 1 +#define SERIAL2_TIMER_SELECT 0x0003 // timer 3 + +#define HW_TIMER0 0xd4003000 + +#define ENABLE_TRANSMIT_INTERRUPT(mn10300_chan) + +#define DISABLE_TRANSMIT_INTERRUPT(mn10300_chan) + +#else + +#error Unsupported MN10300 variant + +#endif + +//------------------------------------------------------------------------- +// Tables to map input values to hardware settings + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +#if defined(CYGPKG_HAL_MN10300_AM31) + +static unsigned short select_baud_01[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + 0, // 1200 + 0, // 1800 + 0, // 2400 + 0, // 3600 + 0, // 4800 + 0, // 7200 + 195, // 9600 + 130, // 14400 + 98, // 19200 + 48, // 38400 + 32, // 57600 + 16, // 115200 + 8, // 230400 +}; + +// Serial 2 has its own timer register in addition to using timer 2 to +// supply the baud rate generator. Both of these must be proframmed to +// get the right baud rate. The following values come from Matsushita +// with some modifications from Cygmon. +static struct +{ + cyg_uint8 serial2_val; + cyg_uint8 timer2_val; +} select_baud_2[] = { + { 0, 0 }, // Unused + { 0, 0 }, // 50 + { 0, 0 }, // 75 + { 0, 0 }, // 110 + { 0, 0 }, // 134.5 + { 0, 0 }, // 150 + { 0, 0 }, // 200 + { 0, 0 }, // 300 + { 126, 196 }, // 600 + { 125, 98 }, // 1200 + { 0, 0 }, // 1800 + { 124, 49 }, // 2400 + { 0, 0 }, // 3600 + { 124, 24 }, // 4800 + { 0, 0 }, // 7200 + { 70, 21 }, // 9600 + { 0, 0 }, // 14400 + { 70, 10 }, // 19200 + { 22, 16 }, // 38400 + { 88, 2 }, // 57600 + { 64, 1 }, // 115200 + { 62, 0 }, // 230400 +}; + +#elif defined(CYGPKG_HAL_MN10300_AM33) + +// The AM33 runs at a different clock rate and therefore has a +// different set of dividers for the baud rate. + +static unsigned short select_baud_01[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + 3168, // 1200 + 0, // 1800 + 1584, // 2400 + 0, // 3600 + 792, // 4800 + 0, // 7200 + 396, // 9600 + 0, // 14400 + 198, // 19200 + 99, // 38400 + 0, // 57600 + 33, // 115200 + 16, // 230400 +}; + +// Serial 2 has its own timer register in addition to using timer 2 to +// supply the baud rate generator. Both of these must be proframmed to +// get the right baud rate. The following values come from Matsushita +// with some modifications from Cygmon. + +// The values in the following table differ significantly from those +// given in the Matsushita documentation. These have been determined +// by (somewhat exhaustive) experiment, the values in the documentation +// do not appear to work at all. + +static struct +{ + cyg_uint8 serial2_val; + cyg_uint8 timer2_val; +} select_baud_2[] = { + { 0, 0 }, // Unused + { 0, 0 }, // 50 + { 0, 0 }, // 75 + { 0, 0 }, // 110 + { 0, 0 }, // 134.5 + { 0, 0 }, // 150 + { 0, 0 }, // 200 + { 0, 0 }, // 300 + { 0, 0 }, // 600 + { 0, 0 }, // 1200 + { 0, 0 }, // 1800 + { 0, 0 }, // 2400 + { 0, 0 }, // 3600 + { 110, 56 }, // 4800 + { 0, 0 }, // 7200 + { 110, 28 }, // 9600 + { 0, 0 }, // 14400 + { 71, 21 }, // 19200 + { 102, 7 }, // 38400 + { 0, 0 }, // 57600 + { 9, 26 }, // 115200 + { 0, 0 }, // 230400 +}; + +#else + +#error Unsupported MN10300 variant + +#endif + +//------------------------------------------------------------------------- +// Info for each serial device controlled + +typedef struct mn10300_serial_info { + CYG_ADDRWORD base; + CYG_ADDRWORD timer_base; + CYG_WORD timer_select; + CYG_WORD rx_int; + CYG_WORD tx_int; + cyg_bool is_serial2; + cyg_interrupt rx_interrupt; + cyg_interrupt tx_interrupt; + cyg_handle_t rx_interrupt_handle; + cyg_handle_t tx_interrupt_handle; +#ifdef CYG_HAL_MN10300_SERIAL_RX_FIFO + volatile cyg_int32 fifo_head; + volatile cyg_int32 fifo_tail; + volatile cyg_uint8 fifo[16]; +#endif +} mn10300_serial_info; + +//------------------------------------------------------------------------- +// Callback functions exported by this driver + +static SERIAL_FUNS(mn10300_serial_funs, + mn10300_serial_putc, + mn10300_serial_getc, + mn10300_serial_set_config, + mn10300_serial_start_xmit, + mn10300_serial_stop_xmit + ); + +//------------------------------------------------------------------------- +// Hardware info for each serial line + +#ifndef CYGPKG_HAL_MN10300_AM31_STDEVAL1 +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 +static mn10300_serial_info mn10300_serial_info0 = { + SERIAL0_BASE, + TIMER0_BASE, + SERIAL0_TIMER_SELECT, + CYGNUM_HAL_INTERRUPT_SERIAL_0_RX, + CYGNUM_HAL_INTERRUPT_SERIAL_0_TX, + false +}; +#if CYGNUM_IO_SERIAL_MN10300_SERIAL0_BUFSIZE > 0 +static unsigned char mn10300_serial_out_buf0[CYGNUM_IO_SERIAL_MN10300_SERIAL0_BUFSIZE]; +static unsigned char mn10300_serial_in_buf0[CYGNUM_IO_SERIAL_MN10300_SERIAL0_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL0 +#endif + +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL1 +static mn10300_serial_info mn10300_serial_info1 = { + SERIAL1_BASE, + TIMER1_BASE, + SERIAL1_TIMER_SELECT, + CYGNUM_HAL_INTERRUPT_SERIAL_1_RX, + CYGNUM_HAL_INTERRUPT_SERIAL_1_TX, + false +}; +#if CYGNUM_IO_SERIAL_MN10300_SERIAL1_BUFSIZE > 0 +static unsigned char mn10300_serial_out_buf1[CYGNUM_IO_SERIAL_MN10300_SERIAL1_BUFSIZE]; +static unsigned char mn10300_serial_in_buf1[CYGNUM_IO_SERIAL_MN10300_SERIAL1_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL1 + +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL2 +static mn10300_serial_info mn10300_serial_info2 = { + SERIAL2_BASE, + TIMER2_BASE, + SERIAL2_TIMER_SELECT, + CYGNUM_HAL_INTERRUPT_SERIAL_2_RX, + CYGNUM_HAL_INTERRUPT_SERIAL_2_TX, + true +}; +#if CYGNUM_IO_SERIAL_MN10300_SERIAL2_BUFSIZE > 0 +static unsigned char mn10300_serial_out_buf2[CYGNUM_IO_SERIAL_MN10300_SERIAL2_BUFSIZE]; +static unsigned char mn10300_serial_in_buf2[CYGNUM_IO_SERIAL_MN10300_SERIAL2_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL2 + + +//------------------------------------------------------------------------- +// Channel descriptions: + +#ifdef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE +#define SIZEOF_BUF(_x_) 0 +#else +#define SIZEOF_BUF(_x_) sizeof(_x_) +#endif + +#ifndef CYGPKG_HAL_MN10300_AM31_STDEVAL1 +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 +#if CYGNUM_IO_SERIAL_MN10300_SERIAL0_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(mn10300_serial_channel0, + mn10300_serial_funs, + mn10300_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MN10300_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mn10300_serial_out_buf0[0], + SIZEOF_BUF(mn10300_serial_out_buf0), + &mn10300_serial_in_buf0[0], + SIZEOF_BUF(mn10300_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(mn10300_serial_channel0, + mn10300_serial_funs, + mn10300_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MN10300_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL0 +#endif + +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL1 +#if CYGNUM_IO_SERIAL_MN10300_SERIAL1_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(mn10300_serial_channel1, + mn10300_serial_funs, + mn10300_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MN10300_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mn10300_serial_out_buf1[0], + SIZEOF_BUF(mn10300_serial_out_buf1), + &mn10300_serial_in_buf1[0], + SIZEOF_BUF(mn10300_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(mn10300_serial_channel1, + mn10300_serial_funs, + mn10300_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MN10300_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL1 + +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL2 +#if CYGNUM_IO_SERIAL_MN10300_SERIAL2_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(mn10300_serial_channel2, + mn10300_serial_funs, + mn10300_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MN10300_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mn10300_serial_out_buf2[0], + SIZEOF_BUF(mn10300_serial_out_buf2), + &mn10300_serial_in_buf2[0], + SIZEOF_BUF(mn10300_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(mn10300_serial_channel2, + mn10300_serial_funs, + mn10300_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MN10300_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL2 + +//------------------------------------------------------------------------- +// And finally, the device table entries: + +#ifndef CYGPKG_HAL_MN10300_AM31_STDEVAL1 +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 +// On the standard eval board serial0 is not connected. If enabled, it +// generates continuous frame error and overrun interrupts. Hence we do +// not touch it. +DEVTAB_ENTRY(mn10300_serial_io0, + CYGDAT_IO_SERIAL_MN10300_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mn10300_serial_init, + mn10300_serial_lookup, // Serial driver may need initializing + &mn10300_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL0 +#endif + +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL1 +DEVTAB_ENTRY(mn10300_serial_io1, + CYGDAT_IO_SERIAL_MN10300_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mn10300_serial_init, + mn10300_serial_lookup, // Serial driver may need initializing + &mn10300_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL1 + +#ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL2 +DEVTAB_ENTRY(mn10300_serial_io2, + CYGDAT_IO_SERIAL_MN10300_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mn10300_serial_init, + mn10300_serial_lookup, // Serial driver may need initializing + &mn10300_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_MN10300_SERIAL2 + +//------------------------------------------------------------------------- +// Read the serial line's status register. Serial 2 has an 8 bit status +// register while serials 0 and 1 have 16 bit registers. This function +// uses the correct size access, but passes back a 16 bit quantity for +// both. + +static cyg_uint16 mn10300_read_sr( mn10300_serial_info *mn10300_chan ) +{ + cyg_uint16 sr = 0; + if( mn10300_chan->is_serial2 ) + { + cyg_uint8 sr8; + HAL_READ_UINT8(mn10300_chan->base+SERIAL_STR, sr8); + sr = sr8; + } + else + { + HAL_READ_UINT16(mn10300_chan->base+SERIAL_STR, sr); + } + + return sr; +} + +//------------------------------------------------------------------------- + +static bool +mn10300_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint16 cr = 0; + cyg_uint16 sr; + + // wait for the device to become quiescent. This could take some time + // if the device had been transmitting at a low baud rate. + do { + sr = mn10300_read_sr(mn10300_chan); + } while (sr & (SR_RXF|SR_TXF)); + + // Disable device entirely. + HAL_WRITE_UINT16(mn10300_chan->base+SERIAL_CTR, 0); + + // Set up the Interrupt Mode Register + HAL_WRITE_UINT8(mn10300_chan->base+SERIAL_ICR, 0); + + // Set up baud rate + if( mn10300_chan->is_serial2 ) + { + // Serial 2 is a bit different from 0 and 1 in the way that the + // baud rate is controlled. + + cyg_uint8 baud_divisor = select_baud_2[new_config->baud].timer2_val; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_BR, baud_divisor); + + HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_MD, 0x80 ); + + baud_divisor = select_baud_2[new_config->baud].serial2_val; + + HAL_WRITE_UINT8(mn10300_chan->base+SERIAL_TIM, baud_divisor); + + cr |= mn10300_chan->timer_select; + } + else + { + cyg_uint16 baud_divisor = select_baud_01[new_config->baud]; + cyg_uint8 timer_mode = 0x80; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + +#if defined(CYGPKG_HAL_MN10300_AM33) + if( baud_divisor > 255 ) + { + // The AM33 runs at a higher clock rate than the AM31 and + // needs a bigger divisor for low baud rates. We do this by + // using timer 0 as a prescaler. We set it to 198 so we can then + // use it to prescale for both serial0 and serial1 if they need + // it. + static int timer0_initialized = 0; + baud_divisor /= 198; + baud_divisor--; + timer_mode = 0x84; + if( !timer0_initialized ) + { + timer0_initialized = 1; + HAL_WRITE_UINT8(HW_TIMER0+TIMER_BR, 198 ); + HAL_WRITE_UINT8(HW_TIMER0+TIMER_MD, 0x80 ); + } + } +#endif + + HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_BR, baud_divisor); + + HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_MD, timer_mode ); + + cr |= mn10300_chan->timer_select; + } + +#ifdef PORT3_MD + HAL_WRITE_UINT8( PORT3_MD, 0x01 ); +#endif + + // set up other config values: + + cr |= select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + cr |= select_stop_bits[new_config->stop]; + cr |= select_parity[new_config->parity]; + + cr |= LCR_RXE | LCR_TXE; // enable Rx and Tx + +#ifdef CYGPKG_HAL_MN10300_AM31 + if( mn10300_chan->is_serial2 ) + { + // AM31 has an extra TX interrupt enable bit for serial 2. + DISABLE_TRANSMIT_INTERRUPT(mn10300_chan); + } +#endif + + // Write CR into hardware + HAL_WRITE_UINT16(mn10300_chan->base+SERIAL_CTR, cr); + + sr = mn10300_read_sr(mn10300_chan); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +//------------------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. + +bool mn10300_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + +#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE + if (chan->out_cbuf.len != 0) { + // Install and enable the receive interrupt + cyg_drv_interrupt_create(mn10300_chan->rx_int, + 4, // Priority - what goes here? + (cyg_addrword_t)chan, // Data item passed to interrupt handler + mn10300_serial_rx_ISR, + mn10300_serial_rx_DSR, + &mn10300_chan->rx_interrupt_handle, + &mn10300_chan->rx_interrupt); + cyg_drv_interrupt_attach(mn10300_chan->rx_interrupt_handle); + cyg_drv_interrupt_unmask(mn10300_chan->rx_int); + + // Install and enable the transmit interrupt + cyg_drv_interrupt_create(mn10300_chan->tx_int, + 4, // Priority - what goes here? + (cyg_addrword_t)chan, // Data item passed to interrupt handler + mn10300_serial_tx_ISR, + mn10300_serial_tx_DSR, + &mn10300_chan->tx_interrupt_handle, + &mn10300_chan->tx_interrupt); + cyg_drv_interrupt_attach(mn10300_chan->tx_interrupt_handle); + cyg_drv_interrupt_mask(mn10300_chan->tx_int); + } +#endif + + mn10300_serial_config_port(chan, &chan->config, true); + + return true; +} + +//------------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) + +static Cyg_ErrNo +mn10300_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +//------------------------------------------------------------------------- +// Return 'true' if character is sent to device + +bool +mn10300_serial_putc(serial_channel *chan, unsigned char c) +{ + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint8 sr = mn10300_read_sr( mn10300_chan); + + if( (sr & SR_TBF) == 0 ) + { + HAL_WRITE_UINT8( mn10300_chan->base+SERIAL_TXB, c ); + + return true; + } + else return false; +} + +//------------------------------------------------------------------------- + +unsigned char +mn10300_serial_getc(serial_channel *chan) +{ + unsigned char c; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + do + { + cyg_uint8 sr = mn10300_read_sr( mn10300_chan ); + + if( (sr & SR_RBF) != 0 ) + { + HAL_READ_UINT8( mn10300_chan->base+SERIAL_RXB, c ); + + break; + } + + } while(1); + + return c; +} + +//------------------------------------------------------------------------- + +static Cyg_ErrNo +mn10300_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != mn10300_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------------------------------------------- +// Enable the transmitter on the device + +static void +mn10300_serial_start_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint16 cr; + + HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); + + ENABLE_TRANSMIT_INTERRUPT(mn10300_chan); + + HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); + + cyg_drv_interrupt_unmask(mn10300_chan->tx_int); + + (chan->callbacks->xmt_char)(chan); +#endif +} + +//------------------------------------------------------------------------- +// Disable the transmitter on the device + +static void +mn10300_serial_stop_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint16 cr; + cyg_uint16 sr; + + // Wait until the transmitter has actually stopped before turning it off. + + do + { + sr = mn10300_read_sr( mn10300_chan ); + + } while( sr & SR_TXF ); + + HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); + + DISABLE_TRANSMIT_INTERRUPT(mn10300_chan); + + HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); + + cyg_drv_interrupt_mask(mn10300_chan->tx_int); + +#endif +} + +//------------------------------------------------------------------------- +// Serial I/O - low level interrupt handlers (ISR) + +#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE + +#ifdef CYG_HAL_MN10300_SERIAL_RX_FIFO + +// This version of the RX ISR implements a simple receive FIFO. The +// MN10300 serial devices do not have hardware FIFOs (as found in +// 16550s for example), and it can be difficult at times to keep up +// with higher baud rates without overrunning. This ISR implements a +// software equivalent of the hardware FIFO, placing recieved +// characters into the FIFO as soon as they arrive. Whenever the DSR +// is run, it collects all the pending characters from the FIFO for +// delivery to the application. Neither the ISR or DSR disable +// interrupts, instead we rely on being able to write the head and +// tail pointers atomically, to implement lock-free synchronization. + +static cyg_uint32 +mn10300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint8 sr = mn10300_read_sr( mn10300_chan); + + while( (sr & SR_RBF) != 0 ) + { + register cyg_int32 head = mn10300_chan->fifo_head; + cyg_uint8 c; + int i; + HAL_READ_UINT8( mn10300_chan->base+SERIAL_RXB, c ); + + mn10300_chan->fifo[head++] = c; + + if( head >= sizeof(mn10300_chan->fifo) ) + head = 0; + + mn10300_chan->fifo_head = head; + + sr = mn10300_read_sr( mn10300_chan); + + } + + cyg_drv_interrupt_acknowledge(mn10300_chan->rx_int); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +#else + +static cyg_uint32 +mn10300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mn10300_chan->rx_int); + cyg_drv_interrupt_acknowledge(mn10300_chan->rx_int); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +#endif + +static cyg_uint32 +mn10300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mn10300_chan->tx_int); + cyg_drv_interrupt_acknowledge(mn10300_chan->tx_int); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +#endif + +//------------------------------------------------------------------------- +// Serial I/O - high level interrupt handler (DSR) + +#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE + +#ifdef CYG_HAL_MN10300_SERIAL_RX_FIFO + +static void +mn10300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + register cyg_int32 head = mn10300_chan->fifo_head; + register cyg_int32 tail = mn10300_chan->fifo_tail; + + while( head != tail ) + { + cyg_uint8 c = mn10300_chan->fifo[tail++]; + + if( tail >= sizeof(mn10300_chan->fifo) ) tail = 0; + + (chan->callbacks->rcv_char)(chan, c); + } + + mn10300_chan->fifo_tail = tail; +} + +#else + +static void +mn10300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint8 sr = mn10300_read_sr( mn10300_chan); + + if( (sr & SR_RBF) != 0 ) + { + cyg_uint8 rxb; + HAL_READ_UINT8( mn10300_chan->base+SERIAL_RXB, rxb ); + + (chan->callbacks->rcv_char)(chan, rxb); + } + + cyg_drv_interrupt_unmask(mn10300_chan->rx_int); +} + +#endif + +static void +mn10300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint8 sr = mn10300_read_sr( mn10300_chan); + + if( (sr & SR_TBF) == 0 ) + { + (chan->callbacks->xmt_char)(chan); + } + + cyg_drv_interrupt_unmask(mn10300_chan->tx_int); +} + +#endif + +#endif // CYGPKG_IO_SERIAL_MN10300 + +//------------------------------------------------------------------------- +// EOF mn10300.c diff --git a/ecos/packages/devs/serial/powerpc/cogent/current/ChangeLog b/ecos/packages/devs/serial/powerpc/cogent/current/ChangeLog new file mode 100644 index 0000000..b47655e --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/cogent/current/ChangeLog @@ -0,0 +1,1185 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_powerpc_cogent.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_powerpc_cogent.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_powerpc_cogent.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/cogent_serial_with_ints.c (cogent_serial_set_config): Now use + keys to make more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/powerpc/cogent/current/cdl/ser_powerpc_cogent.cdl b/ecos/packages/devs/serial/powerpc/cogent/current/cdl/ser_powerpc_cogent.cdl new file mode 100644 index 0000000..8659afa --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/cogent/current/cdl/ser_powerpc_cogent.cdl @@ -0,0 +1,206 @@ +# ==================================================================== +# +# ser_powerpc_cogent.cdl +# +# eCos serial PowerPC/Cogent configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_POWERPC_COGENT { + display "Cogent PowerPC serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_POWERPC_COGENT + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + Cogent PowerPC." + + compile -library=libextras.a cogent_serial_with_ints.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_cogent.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_A { + display "Cogent PowerPC serial port A driver" + flavor bool + default_value 0 + requires (CYGIMP_KERNEL_INTERRUPTS_CHAIN || \ + !CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_B) + description " + This option includes the serial device driver for the Cogent + PowerPC port A. If both drivers need to be enabled, interrupt + chaining must be enabled in the kernel configuration." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_COGENT_SERIAL_A_NAME { + display "Device name for Cogent PowerPC serial port A" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the Cogent PowerPC + port A." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BAUD { + display "Baud rate for the Cogent PowerPC serial port A driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Cogent PowerPC port A." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BUFSIZE { + display "Buffer size for the Cogent PowerPC serial port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the Cogent PowerPC port A." + } +} +cdl_component CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_B { + display "Cogent PowerPC serial port B driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the Cogent + PowerPC port B." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_COGENT_SERIAL_B_NAME { + display "Device name for Cogent PowerPC serial port B" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the Cogent PowerPC + port B." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BAUD { + display "Baud rate for the Cogent PowerPC serial port B driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + Cogent PowerPC port B." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BUFSIZE { + display "Buffer size for the Cogent PowerPC serial port B driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the Cogent PowerPC port B." + } +} + + cdl_component CYGPKG_IO_SERIAL_POWERPC_COGENT_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_POWERPC_COGENT_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_POWERPC_COGENT_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_COGENT_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_B + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_POWERPC_COGENT_SERIAL_B_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"ppccog\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty2\"" + } + } +} + +# EOF ser_powerpc_cogent.cdl diff --git a/ecos/packages/devs/serial/powerpc/cogent/current/src/cogent_serial.h b/ecos/packages/devs/serial/powerpc/cogent/current/src/cogent_serial.h new file mode 100644 index 0000000..40a39cd --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/cogent/current/src/cogent_serial.h @@ -0,0 +1,212 @@ +//========================================================================== +// +// io/serial/powerpc/cogent_serial.h +// +// PowerPC Cogent Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, based on ARM driver by gthomas +// Contributors:gthomas, jskov +// Date: 1999-03-02 +// Purpose: Cogent Serial definitions +//####DESCRIPTIONEND#### +//========================================================================== + +// Description of serial ports on Cogent board + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_Tx 0x02 +#define ISR_Rx 0x04 + +// FIFO control register +#define FCR_ENABLE 0x01 +#define FCR_CLEAR_RCVR 0x02 +#define FCR_CLEAR_XMIT 0x04 + + +//////////////////////////////////////////////////////////// +// Clean this up. + +//----------------------------------------------------------------------------- +// There are two serial ports. +#define CMA_SER_16550_BASE_A 0xe900047 // port A +#define CMA_SER_16550_BASE_B 0xe900007 // port B +#define SER_16550_BASE CMA_SER_16550_BASE_B + +//----------------------------------------------------------------------------- +// Define the serial registers. The Cogent board is equipped with a 16552 +// serial chip. +#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 +#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define SER_16550_IER 0x08 // interrupt enable register, read/write, dlab = 0 +#define SER_16550_DLM 0x08 // divisor latch (MS), read/write, dlab = 1 +#define SER_16550_IIR 0x10 // interrupt identification reg, read, dlab = 0 +#define SER_16550_FCR 0x10 // fifo control register, write, dlab = 0 +#define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1 +#define SER_16550_LCR 0x18 // line control register, read/write +#define SER_16550_MCR 0x20 // modem control register, read/write +#define SER_16550_LSR 0x28 // line status register, read +#define SER_16550_MSR 0x30 // modem status register, read +#define SER_16550_SCR 0x38 // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO +///////////////////////////////////////// + + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// FIXME: calc all properly +// The Cogent board has a 3.6864 MHz crystal +static unsigned short select_baud[] = { + 0, // Unused + 4608, // 50 + 0, // 75 + 2094, // 110 + 0, // 134.5 + 1536, // 150 + 0, // 200 + 768, // 300 + 384, // 600 + 182, // 1200 + 0, // 1800 + 96, // 2400 + 0, // 3600 + 48, // 4800 + 32, // 7200 + 24, // 9600 + 16, // 14400 + 12, // 19200 + 6, // 38400 + 4, // 57600 + 2, // 115200 + 0, // 230400 +}; + diff --git a/ecos/packages/devs/serial/powerpc/cogent/current/src/cogent_serial_with_ints.c b/ecos/packages/devs/serial/powerpc/cogent/current/src/cogent_serial_with_ints.c new file mode 100644 index 0000000..30d7376 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/cogent/current/src/cogent_serial_with_ints.c @@ -0,0 +1,412 @@ +//========================================================================== +// +// io/serial/powerpc/cogent_serial_with_ints.c +// +// PowerPC Cogent Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, based on ARM driver by gthomas +// Contributors:gthomas, jskov +// Date: 1999-03-02 +// Purpose: Cogent Serial I/O module (interrupt driven version) +// Description: +// +// To Do: +// Put in magic to effectively use the FIFOs. Transmitter FIFO fill is a +// problem, and setting receiver FIFO interrupts to happen only after +// n chars may conflict with hal diag. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_POWERPC_COGENT + +#include "cogent_serial.h" + +// Make sure the configuration is sane. +#if defined(CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_A) && \ + defined(CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_B) && \ + !defined(CYGIMP_KERNEL_INTERRUPTS_CHAIN) +#error "Need CYGIMP_KERNEL_INTERRUPTS_CHAIN to support both ports" +#endif + + +#define BUFSIZE 128 + +typedef struct cogent_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} cogent_serial_info; + +static bool cogent_serial_init(struct cyg_devtab_entry *tab); +static bool cogent_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo cogent_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char cogent_serial_getc(serial_channel *chan); +static Cyg_ErrNo cogent_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void cogent_serial_start_xmit(serial_channel *chan); +static void cogent_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 cogent_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void cogent_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(cogent_serial_funs, + cogent_serial_putc, + cogent_serial_getc, + cogent_serial_set_config, + cogent_serial_start_xmit, + cogent_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_A +static cogent_serial_info cogent_serial_info0 ={CMA_SER_16550_BASE_A, + CYGNUM_HAL_INTERRUPT_SIU_IRQ1}; +#if CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BUFSIZE > 0 +static unsigned char cogent_serial_out_buf0[CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BUFSIZE]; +static unsigned char cogent_serial_in_buf0[CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cogent_serial_channel0, + cogent_serial_funs, + cogent_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cogent_serial_out_buf0[0], + sizeof(cogent_serial_out_buf0), + &cogent_serial_in_buf0[0], + sizeof(cogent_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(cogent_serial_channel0, + cogent_serial_funs, + cogent_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cogent_serial_io0, + CYGDAT_IO_SERIAL_POWERPC_COGENT_SERIAL_A_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + cogent_serial_init, + cogent_serial_lookup, // Serial driver may need initializing + &cogent_serial_channel0 + ); +#endif + +#ifdef CYGPKG_IO_SERIAL_POWERPC_COGENT_SERIAL_B +static cogent_serial_info cogent_serial_info1 ={CMA_SER_16550_BASE_B, + CYGNUM_HAL_INTERRUPT_SIU_IRQ1}; +#if CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BUFSIZE > 0 +static unsigned char cogent_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BUFSIZE]; +static unsigned char cogent_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cogent_serial_channel1, + cogent_serial_funs, + cogent_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cogent_serial_out_buf1[0], + sizeof(cogent_serial_out_buf1), + &cogent_serial_in_buf1[0], + sizeof(cogent_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(cogent_serial_channel1, + cogent_serial_funs, + cogent_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cogent_serial_io1, + CYGDAT_IO_SERIAL_POWERPC_COGENT_SERIAL_B_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + cogent_serial_init, + cogent_serial_lookup, // Serial driver may need initializing + &cogent_serial_channel1 + ); +#endif + + + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +cogent_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_addrword_t port = cogent_chan->base; + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + cyg_uint8 _lcr, _ier; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(port+SER_16550_IER, _ier); + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set databits, stopbits and parity. + _lcr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + if (init) { + // Enable and clear FIFO + HAL_WRITE_UINT8(port+SER_16550_FCR, + (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); + + if (chan->out_cbuf.len != 0) { + HAL_WRITE_UINT8(port+SER_16550_IER, SIO_IER_ERDAI); + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + } + + { + // Special initialization for ST16C552 on CMA102 + cyg_uint8 mcr; + + HAL_READ_UINT8(CMA_SER_16550_BASE_A+SER_16550_MCR, mcr); + mcr |= 8; + HAL_WRITE_UINT8(CMA_SER_16550_BASE_A+SER_16550_MCR, mcr); + + HAL_READ_UINT8(CMA_SER_16550_BASE_B+SER_16550_MCR, mcr); + mcr |= 8; + HAL_WRITE_UINT8(CMA_SER_16550_BASE_B+SER_16550_MCR, mcr); + } + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +cogent_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("COGENT SERIAL init - dev: %x.%d\n", cogent_chan->base, cogent_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(cogent_chan->int_num, + 0, // can change IRQ0 priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + cogent_serial_ISR, + cogent_serial_DSR, + &cogent_chan->serial_interrupt_handle, + &cogent_chan->serial_interrupt); + cyg_drv_interrupt_attach(cogent_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(cogent_chan->int_num); + } + cogent_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +cogent_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +cogent_serial_putc(serial_channel *chan, unsigned char c) +{ + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_addrword_t port = cogent_chan->base; + cyg_uint8 _lsr; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + if (_lsr & SIO_LSR_THRE) { +// Transmit buffer is empty + HAL_WRITE_UINT8(port+SER_16550_THR, c); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +cogent_serial_getc(serial_channel *chan) +{ + unsigned char c; + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_addrword_t port = cogent_chan->base; + cyg_uint8 _lsr; + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ((_lsr & SIO_LSR_DR) == 0); + + HAL_READ_UINT8(port+SER_16550_RBR, c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +cogent_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != cogent_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +cogent_serial_start_xmit(serial_channel *chan) +{ + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_addrword_t port = cogent_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier |= IER_XMT; // Enable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + + (chan->callbacks->xmt_char)(chan); +} + +// Disable the transmitter on the device +static void +cogent_serial_stop_xmit(serial_channel *chan) +{ + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_addrword_t port = cogent_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier &= ~IER_XMT; // Disable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +cogent_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(cogent_chan->int_num); + cyg_drv_interrupt_acknowledge(cogent_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +cogent_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cogent_serial_info *cogent_chan = (cogent_serial_info *)chan->dev_priv; + cyg_addrword_t port = cogent_chan->base; + cyg_uint8 _iir; + + HAL_READ_UINT8(port+SER_16550_IIR, _iir); + _iir &= SIO_IIR_ID_MASK; + if ( ISR_Tx == _iir ) { + (chan->callbacks->xmt_char)(chan); + } else if ( ISR_Rx == _iir ) { + cyg_uint8 _c; + HAL_READ_UINT8(port+SER_16550_RBR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + cyg_drv_interrupt_unmask(cogent_chan->int_num); +} +#endif diff --git a/ecos/packages/devs/serial/powerpc/mpc555/current/ChangeLog b/ecos/packages/devs/serial/powerpc/mpc555/current/ChangeLog new file mode 100644 index 0000000..750cd75 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc555/current/ChangeLog @@ -0,0 +1,59 @@ +2008-12-23 Steven Clugston <steven.clugston@ncl.ac.uk> + + * cdl/ser_powerpc_mpc555.cdl: Add HW queue option + * src/mpc555_serial_with_ints.c: + To help resolve an issue of characters being lost a software buffer + has been added between the Rx ISR and DSR when no hardware queue is + being used. + A cdl option to enable support the hardware queue on the first serial + port has been added. This enables 16 character hardware Tx and Rx + buffers to be used which allows continuous transmission and reception + of serial data and significantly improves performance. + +2008-05-13 Steven Clugston <steven.clugston@ncl.ac.uk> + + * cdl/ser_powerpc_mpc555.cdl: Add line status + * src/mpc555_serial_with_ints.c: + Fixed exception caused by attempt to clear scsr bits. + Add line status callbacks + +2008-04-06 Steven Clugston <steven.clugston@ncl.ac.uk> + + * Refactored package to more generic mpc555 + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_powerpc_cme555.cdl: Remove irrelevant doc link. + +2002-11-11 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be> + + * src/cme555_serial_with_ints.c: + interrupt arbiter slightly modified to make GDB CTRL-C work + +2002-04-24 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/powerpc/mpc555/current/cdl/ser_powerpc_mpc555.cdl b/ecos/packages/devs/serial/powerpc/mpc555/current/cdl/ser_powerpc_mpc555.cdl new file mode 100644 index 0000000..f25a447 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc555/current/cdl/ser_powerpc_mpc555.cdl @@ -0,0 +1,196 @@ +# ==================================================================== +# +# ser_powerpc_mpc555.cdl +# +# eCos serial PowerPC/mpc555 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Bob Koninckx +# Original data: +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_POWERPC_MPC555 { + display "mpc555 PowerPC serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_POWERPC_MPC555 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + mpc555 mpc555 development board." + + compile -library=libextras.a mpc555_serial_with_ints.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_mpc555.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A { + display "mpc555 PowerPC serial port A driver" + flavor bool + default_value 0 + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + implements CYGINT_IO_SERIAL_BLOCK_TRANSFER + description " + This option includes the serial device driver for the mpc555 + PowerPC port A." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_NAME { + display "Device name for mpc555 PowerPC serial port A" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the mpc555 PowerPC + port A." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BAUD { + display "Baud rate for the mpc555 PowerPC serial port A driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + mpc555 PowerPC port A." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BUFSIZE { + display "Buffer size for the mpc555 PowerPC serial port A driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the mpc555 PowerPC port A." + } + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE { + display "Use hardware queue for mpc555 PowerPC serial port A" + flavor bool + default_value 1 + description " + This option specifies if the QSCI 16-byte hardware queue + is used for the mpc555 PowerPC port A. Using the queue + makes block transfers possible. Select this option + if you need to support continuous transmission and reception + without buffer overruns occurring." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_B { + display "mpc555 PowerPC serial port B driver" + flavor bool + default_value 1 + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + description " + This option includes the serial device driver for the mpc555 + PowerPC port B." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_B_NAME { + display "Device name for mpc555 PowerPC serial port B" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the mpc555 PowerPC + port B." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BAUD { + display "Baud rate for the mpc555 PowerPC serial port B driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + mpc555 PowerPC port B." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BUFSIZE { + display "Buffer size for the mpc555 PowerPC serial port B driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the mpc555 PowerPC port B." + } +} + + cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC555_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_POWERPC_MPC555_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_POWERPC_MPC555_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_powerpc_mpc555.cdl diff --git a/ecos/packages/devs/serial/powerpc/mpc555/current/src/mpc555_serial.h b/ecos/packages/devs/serial/powerpc/mpc555/current/src/mpc555_serial.h new file mode 100644 index 0000000..8c0044b --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc555/current/src/mpc555_serial.h @@ -0,0 +1,156 @@ +#ifndef CYGONCE_DEVS_SERIAL_POWERPC_MPC555_SERIAL_H +#define CYGONCE_DEVS_SERIAL_POWERPC_MPC555_SERIAL_H +//========================================================================== +// +// mpc555_serial.h +// +// PowerPC 5xx MPC555 Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Bob Koninckx +// Contributors: +// Date: 2002-04-25 +// Purpose: MPC555 Serial I/O definitions. +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +//---------------------------------- +// Includes and forward declarations +//---------------------------------- + +//---------------------- +// Constants definitions +//---------------------- +// Base addresses for the two serial ports +#define MPC555_SERIAL_BASE_A 0x305008 +#define MPC555_SERIAL_BASE_B 0x305020 + +// The offset from the base for all serial registers +#define MPC555_SERIAL_SCCxR0 0 +#define MPC555_SERIAL_SCCxR1 2 +#define MPC555_SERIAL_SCxSR 4 +#define MPC555_SERIAL_SCxDR 6 + +// The bits in the serial registers +#define MPC555_SERIAL_SCCxR0_OTHR 0x8000 +#define MPC555_SERIAL_SCCxR0_LINKBD 0x4000 +#define MPC555_SERIAL_SCCxR0_SCxBR 0x1fff + +#define MPC555_SERIAL_SCCxR1_LOOPS 0x4000 +#define MPC555_SERIAL_SCCxR1_WOMS 0x2000 +#define MPC555_SERIAL_SCCxR1_ILT 0x1000 +#define MPC555_SERIAL_SCCxR1_PT 0x0800 +#define MPC555_SERIAL_SCCxR1_PE 0x0400 +#define MPC555_SERIAL_SCCxR1_M 0x0200 +#define MPC555_SERIAL_SCCxR1_WAKE 0x0100 +#define MPC555_SERIAL_SCCxR1_TIE 0x0080 +#define MPC555_SERIAL_SCCxR1_TCIE 0x0040 +#define MPC555_SERIAL_SCCxR1_RIE 0x0020 +#define MPC555_SERIAL_SCCxR1_ILIE 0x0010 +#define MPC555_SERIAL_SCCxR1_TE 0x0008 +#define MPC555_SERIAL_SCCxR1_RE 0x0004 +#define MPC555_SERIAL_SCCxR1_RWU 0x0002 +#define MPC555_SERIAL_SCCxR1_SBK 0x0001 + +#define MPC555_SERIAL_SCxSR_TDRE 0x0100 +#define MPC555_SERIAL_SCxSR_TC 0x0080 +#define MPC555_SERIAL_SCxSR_RDRF 0x0040 +#define MPC555_SERIAL_SCxSR_RAF 0x0020 +#define MPC555_SERIAL_SCxSR_IDLE 0x0010 +#define MPC555_SERIAL_SCxSR_OR 0x0008 +#define MPC555_SERIAL_SCxSR_NF 0x0004 +#define MPC555_SERIAL_SCxSR_FE 0x0002 +#define MPC555_SERIAL_SCxSR_PF 0x0001 + +// The available baud rates +// These are calculated for a busclock of 40 MHz +// It is not necessary to let the compiler calculate these +// values, we did not provide clockfrequency as a configuarion +// option anyway. +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 bps unsupported + 0, // 75 bps unsupported + 0, // 110 bps unsupported + 0, // 134_5 bps unsupported + 0, // 150 bps unsupported + 0, // 200 bps unsupported + 4167, // 300 bps + 2083, // 600 bps + 1042, // 1200 bps + 0, // 1800 bps unsupported + 521, // 2400 bps + 0, // 3600 bps unsupported + 260, // 4800 bps + 0, // 7200 bps unsupported + 130, // 9600 bps + 87, // 14400 bps + 65, // 19200 bps + 33, // 38400 bps + 22, // 57600 bps + 11, // 115200 bps + 0 // 230400 bps unsupported +}; + +static unsigned char select_word_length[] = { + 0, // 5 bits / word (char) not supported + 0, // 6 bits / word (char) not supported + 7, // 7 bits / word (char) ->> 7 bits per frame + 8 // 8 bits / word (char) ->> 8 bits per frame +}; + +static unsigned char select_stop_bits[] = { + 0, + 1, // 1 stop bit ->> 1 bit per frame + 0, // 1.5 stop bit not supported + 2 // 2 stop bits ->> 2 bits per frame +}; + +static unsigned char select_parity[] = { + 0, // No parity ->> 0 bits per frame + 1, // Even parity ->> 1 bit per frame + 1, // Odd parityv ->> 1 bit per frame + 0, // Mark parity not supported + 0, // Space parity not supported +}; + +#endif // CYGONCE_DEVS_SERIAL_POWERPC_MPC555_SERIAL_H + +// EOF mpc555_serial.h diff --git a/ecos/packages/devs/serial/powerpc/mpc555/current/src/mpc555_serial_with_ints.c b/ecos/packages/devs/serial/powerpc/mpc555/current/src/mpc555_serial_with_ints.c new file mode 100644 index 0000000..6571356 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc555/current/src/mpc555_serial_with_ints.c @@ -0,0 +1,1290 @@ +//========================================================================== +// +// mpc555_serial_with_ints.c +// +// PowerPC 5xx MPC555 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Bob Koninckx +// Contributors: +// Date: 2002-04-25 +// Purpose: MPC555 Serial I/O module (interrupt driven version) +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== +//---------------------------------- +// Includes and forward declarations +//---------------------------------- +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arbiter.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +// Only build this driver for the MPC555 based boards +#if defined (CYGPKG_IO_SERIAL_POWERPC_MPC555) && \ + (defined (CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A) || \ + defined (CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_B)) + +#include "mpc555_serial.h" + +//--------------------------------------------------------------------------- +// Type definitions +//--------------------------------------------------------------------------- +#define MPC555_SCI_RX_BUFF_SIZE 256 +typedef struct st_sci_circbuf { + cyg_uint8 buf[MPC555_SCI_RX_BUFF_SIZE]; + cyg_uint16 scsr[MPC555_SCI_RX_BUFF_SIZE]; + cyg_uint8 fill_pos; + cyg_uint8 read_pos; +} mpc555_sci_circbuf_t; + +typedef struct mpc555_serial_info { + CYG_ADDRWORD base; // The base address of the serial port + CYG_WORD tx_interrupt_num; // trivial + CYG_WORD rx_interrupt_num; // trivial + cyg_priority_t tx_interrupt_priority;// trivial + cyg_priority_t rx_interrupt_priority;// trivial + bool tx_interrupt_enable; // can the tx interrupt be re-enabled? + mpc555_sci_circbuf_t* rx_circbuf; // rx buff for ISR to DSR data exchange + bool use_queue; // Use the queue when available? + CYG_WORD rx_last_queue_pointer;// Keep track where queue read is upto + CYG_WORD rx_interrupt_idle_line_num; // trivial + CYG_WORD tx_interrupt_queue_top_empty_num; // trivial + CYG_WORD tx_interrupt_queue_bot_empty_num; // trivial + CYG_WORD rx_interrupt_queue_top_full_num; // trivial + CYG_WORD rx_interrupt_queue_bot_full_num; // trivial + cyg_priority_t rx_interrupt_idle_line_priority; // trivial + cyg_priority_t tx_interrupt_queue_top_empty_priority; // trivial + cyg_priority_t tx_interrupt_queue_bot_empty_priority; // trivial + cyg_priority_t rx_interrupt_queue_top_full_priority; // trivial + cyg_priority_t rx_interrupt_queue_bot_full_priority; // trivial + cyg_interrupt tx_interrupt; // the tx interrupt object + cyg_handle_t tx_interrupt_handle; // the tx interrupt handle + cyg_interrupt rx_interrupt; // the rx interrupt object + cyg_handle_t rx_interrupt_handle; // the rx interrupt handle + cyg_interrupt rx_idle_interrupt; // the rx idle line isr object + cyg_handle_t rx_idle_interrupt_handle; // the rx idle line isr handle + cyg_interrupt tx_queue_top_interrupt; // the tx interrupt object + cyg_handle_t tx_queue_top_interrupt_handle;// the tx interrupt handle + cyg_interrupt tx_queue_bot_interrupt; // the tx interrupt object + cyg_handle_t tx_queue_bot_interrupt_handle;// the tx interrupt handle + cyg_interrupt rx_queue_top_interrupt; // the tx interrupt object + cyg_handle_t rx_queue_top_interrupt_handle;// the tx interrupt handle + cyg_interrupt rx_queue_bot_interrupt; // the tx interrupt object + cyg_handle_t rx_queue_bot_interrupt_handle;// the tx interrupt handle +} mpc555_serial_info; + +//-------------------- +// Function prototypes +//-------------------- +static bool mpc555_serial_putc(serial_channel * chan, unsigned char c); +static unsigned char mpc555_serial_getc(serial_channel *chan); +static Cyg_ErrNo mpc555_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void mpc555_serial_start_xmit(serial_channel *chan); +static void mpc555_serial_stop_xmit(serial_channel *chan); +static Cyg_ErrNo mpc555_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, + const char * name); +static bool mpc555_serial_init(struct cyg_devtab_entry * tab); + +// The interrupt servers +static cyg_uint32 mpc555_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void mpc555_serial_tx_DSR(cyg_vector_t vector, + cyg_ucount32 count, + cyg_addrword_t data); +static void mpc555_serial_rx_DSR(cyg_vector_t vector, + cyg_ucount32 count, + cyg_addrword_t data); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A +static cyg_uint32 mpc555_serial_tx_queue_top_ISR(cyg_vector_t vector, + cyg_addrword_t data); +static cyg_uint32 mpc555_serial_tx_queue_bot_ISR(cyg_vector_t vector, + cyg_addrword_t data); +static cyg_uint32 mpc555_serial_rx_queue_top_ISR(cyg_vector_t vector, + cyg_addrword_t data); +static cyg_uint32 mpc555_serial_rx_queue_bot_ISR(cyg_vector_t vector, + cyg_addrword_t data); +static cyg_uint32 mpc555_serial_rx_idle_line_ISR(cyg_vector_t vector, + cyg_addrword_t data); + +static void mpc555_serial_tx_queue_DSR(cyg_vector_t vector, + cyg_ucount32 count, + cyg_addrword_t data); +static void mpc555_serial_rx_queue_DSR(cyg_vector_t vector, + cyg_ucount32 count, + cyg_addrword_t data); + +static int mpc555_serial_read_queue(serial_channel* chan, int start, int end); +#endif + +//------------------------------------------------------------------------------ +// Register the device driver with the kernel +//------------------------------------------------------------------------------ +static SERIAL_FUNS(mpc555_serial_funs, + mpc555_serial_putc, + mpc555_serial_getc, + mpc555_serial_set_config, + mpc555_serial_start_xmit, + mpc555_serial_stop_xmit); + +//------------------------------------------------------------------------------ +// Device driver data +//------------------------------------------------------------------------------ +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A +#ifdef CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE +//static mpc555_sci_circbuf_t mpc555_serial_isr_to_dsr_buf0; + +static mpc555_serial_info mpc555_serial_info0 = { + MPC555_SERIAL_BASE_A, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY, + false, + NULL, // Don't need software buffer + true, // Use queue + 0, // init queue pointer + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF_PRIORITY}; + +static unsigned char mpc555_serial_out_buf0[CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BUFSIZE]; +static unsigned char mpc555_serial_in_buf0[CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS( + mpc555_serial_channel0, + mpc555_serial_funs, + mpc555_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc555_serial_out_buf0[0], + sizeof(mpc555_serial_out_buf0), + &mpc555_serial_in_buf0[0], + sizeof(mpc555_serial_in_buf0)); + +#elif CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BUFSIZE > 0 +static mpc555_sci_circbuf_t mpc555_serial_isr_to_dsr_buf0; + +static mpc555_serial_info mpc555_serial_info0 = { + MPC555_SERIAL_BASE_A, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY, + false, + &mpc555_serial_isr_to_dsr_buf0, + false}; + +static unsigned char mpc555_serial_out_buf0[CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BUFSIZE]; +static unsigned char mpc555_serial_in_buf0[CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS( + mpc555_serial_channel0, + mpc555_serial_funs, + mpc555_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc555_serial_out_buf0[0], + sizeof(mpc555_serial_out_buf0), + &mpc555_serial_in_buf0[0], + sizeof(mpc555_serial_in_buf0)); +#else +static mpc555_serial_info mpc555_serial_info0 = { + MPC555_SERIAL_BASE_A, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY, + false, + NULL, + false}; + +static SERIAL_CHANNEL( + mpc555_serial_channel0, + mpc555_serial_funs, + mpc555_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(mpc555_serial_io0, + CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + mpc555_serial_init, + mpc555_serial_lookup, + &mpc555_serial_channel0); +#endif // ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_B + +#if CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BUFSIZE > 0 +static mpc555_sci_circbuf_t mpc555_serial_isr_to_dsr_buf1; + +static mpc555_serial_info mpc555_serial_info1 = { + MPC555_SERIAL_BASE_B, + CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX_PRIORITY, + false, + &mpc555_serial_isr_to_dsr_buf1, + false}; + +static unsigned char mpc555_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BUFSIZE]; +static unsigned char mpc555_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS( + mpc555_serial_channel1, + mpc555_serial_funs, + mpc555_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc555_serial_out_buf1[0], + sizeof(mpc555_serial_out_buf1), + &mpc555_serial_in_buf1[0], + sizeof(mpc555_serial_in_buf1)); +#else +static mpc555_serial_info mpc555_serial_info1 = { + MPC555_SERIAL_BASE_B, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY, + false, + NULL, + false}; +static SERIAL_CHANNEL( + mpc555_serial_channel1, + mpc555_serial_funs, + mpc555_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC555_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(mpc555_serial_io1, + CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_B_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + mpc555_serial_init, + mpc555_serial_lookup, + &mpc555_serial_channel1); +#endif // ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_B + +//------------------------------------------------------------------------------ +// Device driver implementation +//------------------------------------------------------------------------------ + +// The arbitration isr. +// I think this is the best place to implement it. +// The device driver is the only place in the code where the knowledge is +// present about how the hardware is used. +// +// Always check receive interrupts. +// Some rom monitor might be waiting for CTRL-C +static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, + CYG_ADDRWORD a_data) +{ + cyg_uint16 status; + cyg_uint16 control; + + HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status); + HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control); + if((status & CYGARC_REG_IMM_SCxSR_RDRF) && + (control & CYGARC_REG_IMM_SCCxR1_RIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); +// Do not waist time on unused hardware +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A +#ifdef CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE + // Only one port supports queue mode + if((status & CYGARC_REG_IMM_SCxSR_IDLE) && + (control & CYGARC_REG_IMM_SCCxR1_ILIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE); + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, status); + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, control); + if((status & CYGARC_REG_IMM_QSCI1SR_QTHF) && + (control & CYGARC_REG_IMM_QSCI1CR_QTHFI)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF); + if((status & CYGARC_REG_IMM_QSCI1SR_QBHF) && + (control & CYGARC_REG_IMM_QSCI1CR_QBHFI)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF); + if((status & CYGARC_REG_IMM_QSCI1SR_QTHE) && + (control & CYGARC_REG_IMM_QSCI1CR_QTHEI)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE); + if((status & CYGARC_REG_IMM_QSCI1SR_QBHE) && + (control & CYGARC_REG_IMM_QSCI1CR_QBHEI)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE); +// Only for SPI, leave fo future reference +#if 0 + HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, status); + HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, control); + if((status & CYGARC_REG_IMM_SPSR_SPIF) && + (control & CYGARC_REG_IMM_SPCR2_SPIFIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI); + + HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, control); + if((status & CYGARC_REG_IMM_SPSR_MODF) && + (control & CYGARC_REG_IMM_SPCR3_HMIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF); + + if((status & CYGARC_REG_IMM_SPSR_HALTA) && + (control & CYGARC_REG_IMM_SPCR3_HMIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA); +#endif +#else //No HW Queue + if((status & CYGARC_REG_IMM_SCxSR_TDRE) && + (control & CYGARC_REG_IMM_SCCxR1_TIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX); +// Don't waist time on unused interrupts +// Transmit complete interrupt enabled (not used) +// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) +// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC); +// Don't waist time on unused interrupts +// Idle-line interrupt enabled (not used) +// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) +// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE); +#endif // HW_QUEUE +#endif // SERIAL_A + + HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status); + HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control); + if((status & CYGARC_REG_IMM_SCxSR_RDRF) && + (control & CYGARC_REG_IMM_SCCxR1_RIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX); +// Do not waist time on unused hardware +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_B + if((status & CYGARC_REG_IMM_SCxSR_TDRE) && + (control & CYGARC_REG_IMM_SCCxR1_TIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX); +// Don't waist time on unused interrupts +// Transmit complete interrupt enabled (not used) +// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) +// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC); +// Don't waist time on unused interrupts +// Idle-line interrupt enabled (not used) +// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) +// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE); +#endif + + return 0; +} + +//------------------------------------------------------------------------------ +// Internal function to configure the hardware to desired baud rate, etc. +//------------------------------------------------------------------------------ +static bool mpc555_serial_config_port(serial_channel * chan, + cyg_serial_info_t * new_config, + bool init) +{ + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)(chan->dev_priv); + + cyg_addrword_t port = mpc555_chan->base; + cyg_uint16 baud_rate = select_baud[new_config->baud]; + unsigned char frame_length = 1; // The start bit + + cyg_uint16 old_isrstate; + cyg_uint16 sccxr; + + if(!baud_rate) + return false; // Invalid baud rate selected + + if((new_config->word_length != CYGNUM_SERIAL_WORD_LENGTH_7) && + (new_config->word_length != CYGNUM_SERIAL_WORD_LENGTH_8)) + return false; // Invalid word length selected + + if((new_config->parity != CYGNUM_SERIAL_PARITY_NONE) && + (new_config->parity != CYGNUM_SERIAL_PARITY_EVEN) && + (new_config->parity != CYGNUM_SERIAL_PARITY_ODD)) + return false; // Invalid parity selected + + if((new_config->stop != CYGNUM_SERIAL_STOP_1) && + (new_config->stop != CYGNUM_SERIAL_STOP_2)) + return false; // Invalid stop bits selected + + frame_length += select_word_length[new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5]; + frame_length += select_stop_bits[new_config->stop]; + frame_length += select_parity[new_config->parity]; + + if((frame_length != 10) && (frame_length != 11)) + return false; // Invalid frame format selected + + // Disable port interrupts while changing hardware + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + old_isrstate = sccxr; + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_LOOPS); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_WOMS); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_ILT); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PT); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PE); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_M); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_WAKE); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TE); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RE); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RWU); + old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_SBK); + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TIE); + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TCIE); + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RIE); + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_ILIE); + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + +#ifdef CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE + cyg_uint16 qsci1cr = 0; + if(mpc555_chan->use_queue){ + HAL_READ_UINT16( CYGARC_REG_IMM_QSCI1SR, qsci1cr); + // disable queue + qsci1cr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QTE); + qsci1cr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QRE); + // disable queue interrupts + qsci1cr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QTHFI); + qsci1cr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QBHFI); + qsci1cr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QTHEI); + qsci1cr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QBHEI); + HAL_WRITE_UINT16( CYGARC_REG_IMM_QSCI1SR, qsci1cr); + } +#endif + // Set databits, stopbits and parity. + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + + if(frame_length == 11) + sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_M; + else + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_M); + + switch(new_config->parity){ + case CYGNUM_SERIAL_PARITY_NONE: + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PE); + break; + case CYGNUM_SERIAL_PARITY_EVEN: + sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PE; + sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PT); + break; + case CYGNUM_SERIAL_PARITY_ODD: + sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PE; + sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PT; + break; + default: + break; + } + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + + // Set baud rate. + baud_rate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR0_OTHR); + baud_rate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR0_LINKBD); + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR0, sccxr); + sccxr &= ~(MPC555_SERIAL_SCCxR0_SCxBR); + sccxr |= baud_rate; + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR0, sccxr); + + // Enable the device + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + sccxr |= MPC555_SERIAL_SCCxR1_TE; + sccxr |= MPC555_SERIAL_SCCxR1_RE; + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + + if(init){ +#ifdef CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + if(mpc555_chan->use_queue){ + cyg_uint16 qsci1sr; + // enable read queue + qsci1cr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QRE); + // enable receive queue interrupts + qsci1cr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QTHFI); + qsci1cr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QBHFI); + HAL_WRITE_UINT16( CYGARC_REG_IMM_QSCI1CR, qsci1cr); + // also enable idle line detect interrupt + sccxr |= MPC555_SERIAL_SCxSR_IDLE; + HAL_READ_UINT16( CYGARC_REG_IMM_QSCI1SR, qsci1sr); + qsci1sr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1SR_QBHF); + qsci1sr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1SR_QTHF); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr); + } + else { + // enable the receiver interrupt + sccxr |= MPC555_SERIAL_SCCxR1_RIE; + } + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); +#else + // enable the receiver interrupt + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + sccxr |= MPC555_SERIAL_SCCxR1_RIE; + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); +#endif + } + else {// Restore the old interrupt state + + HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + sccxr |= old_isrstate; + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); + } + + if(new_config != &chan->config) + chan->config = *new_config; + + return true; +} + +//------------------------------------------------------------------------------ +// Function to initialize the device. Called at bootstrap time. +//------------------------------------------------------------------------------ +static hal_mpc5xx_arbitration_data arbiter; +static bool mpc555_serial_init(struct cyg_devtab_entry * tab){ + serial_channel * chan = (serial_channel *)tab->priv; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + if(!mpc555_serial_config_port(chan, &chan->config, true)) + return false; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + if(chan->out_cbuf.len != 0){ + arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI; + arbiter.data = 0; + arbiter.arbiter = hal_arbitration_isr_qsci; + + // Install the arbitration isr, Make sure that is is not installed twice + hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); + hal_mpc5xx_install_arbitration_isr(&arbiter); + + // if !(Chan_B && using queue) + if(!mpc555_chan->use_queue){ + mpc555_chan->rx_circbuf->fill_pos = 0; + mpc555_chan->rx_circbuf->read_pos = 0; + + // Create the Tx interrupt, do not enable it yet + cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_num, + mpc555_chan->tx_interrupt_priority, + (cyg_addrword_t)chan,//Data item passed to isr + mpc555_serial_tx_ISR, + mpc555_serial_tx_DSR, + &mpc555_chan->tx_interrupt_handle, + &mpc555_chan->tx_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->tx_interrupt_handle); + + // Create the Rx interrupt, this can be safely unmasked now + cyg_drv_interrupt_create(mpc555_chan->rx_interrupt_num, + mpc555_chan->rx_interrupt_priority, + (cyg_addrword_t)chan, + mpc555_serial_rx_ISR, + mpc555_serial_rx_DSR, + &mpc555_chan->rx_interrupt_handle, + &mpc555_chan->rx_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->rx_interrupt_handle); + cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_num); + } +#ifdef CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE + else {// Use HW queue + // Create the Tx interrupt, do not enable it yet + cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_queue_top_empty_num, + mpc555_chan->tx_interrupt_queue_top_empty_priority, + (cyg_addrword_t)chan,//Data item passed to isr + mpc555_serial_tx_queue_top_ISR, + mpc555_serial_tx_queue_DSR, + &mpc555_chan->tx_queue_top_interrupt_handle, + &mpc555_chan->tx_queue_top_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->tx_queue_top_interrupt_handle); + + + cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_queue_bot_empty_num, + mpc555_chan->tx_interrupt_queue_bot_empty_priority, + (cyg_addrword_t)chan,//Data passed to isr + mpc555_serial_tx_queue_bot_ISR, + mpc555_serial_tx_queue_DSR, + &mpc555_chan->tx_queue_bot_interrupt_handle, + &mpc555_chan->tx_queue_bot_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->tx_queue_bot_interrupt_handle); + + // Rx queue interrupts + cyg_drv_interrupt_create(mpc555_chan->rx_interrupt_queue_top_full_num, + mpc555_chan->rx_interrupt_queue_top_full_priority, + (cyg_addrword_t)chan,//Data item passed to isr + mpc555_serial_rx_queue_top_ISR, + mpc555_serial_rx_queue_DSR, + &mpc555_chan->rx_queue_top_interrupt_handle, + &mpc555_chan->rx_queue_top_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->rx_queue_top_interrupt_handle); + + cyg_drv_interrupt_create(mpc555_chan->rx_interrupt_queue_bot_full_num, + mpc555_chan->rx_interrupt_queue_bot_full_priority, + (cyg_addrword_t)chan,//Data item passed to isr + mpc555_serial_rx_queue_bot_ISR, + mpc555_serial_rx_queue_DSR, + &mpc555_chan->rx_queue_bot_interrupt_handle, + &mpc555_chan->rx_queue_bot_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->rx_queue_bot_interrupt_handle); + + cyg_drv_interrupt_create(mpc555_chan->rx_interrupt_idle_line_num, + mpc555_chan->rx_interrupt_idle_line_priority, + (cyg_addrword_t)chan,//Data item passed to isr + mpc555_serial_rx_idle_line_ISR, + mpc555_serial_rx_queue_DSR, + &mpc555_chan->rx_idle_interrupt_handle, + &mpc555_chan->rx_idle_interrupt); + cyg_drv_interrupt_attach(mpc555_chan->rx_idle_interrupt_handle); + } +#endif // use queue + } + return true; +} + +//---------------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) +//---------------------------------------------------------------------------- +static Cyg_ErrNo mpc555_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, + const char * name) +{ + serial_channel * chan = (serial_channel *)(*tab)->priv; + //Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + return ENOERR; +} + +//---------------------------------------------------------------------------- +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +//---------------------------------------------------------------------------- +static bool mpc555_serial_putc(serial_channel * chan, unsigned char c){ + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + cyg_addrword_t port = mpc555_chan->base; + + cyg_uint16 scsr; + cyg_uint16 scdr; + + HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); + if(scsr & MPC555_SERIAL_SCxSR_TDRE){ + // Ok, we have space, write the character and return success + scdr = (cyg_uint16)c; + HAL_WRITE_UINT16(port + MPC555_SERIAL_SCxDR, scdr); + return true; + } + else + // We cannot write to the transmitter, return failure + return false; +} + +//---------------------------------------------------------------------------- +// Fetch a character from the device input buffer, waiting if necessary +//---------------------------------------------------------------------------- +static unsigned char mpc555_serial_getc(serial_channel * chan){ + unsigned char c; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + cyg_addrword_t port = mpc555_chan->base; + + cyg_uint16 scsr; + cyg_uint16 scdr; + + do { + HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); + } while(!(scsr & MPC555_SERIAL_SCxSR_RDRF)); + + // Ok, data is received, read it out and return + HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); + c = (unsigned char)scdr; + + return c; +} + +//---------------------------------------------------------------------------- +// Set up the device characteristics; baud rate, etc. +//---------------------------------------------------------------------------- +static bool mpc555_serial_set_config(serial_channel * chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 * len) +{ + switch(key){ + case CYG_IO_SET_CONFIG_SERIAL_INFO:{ + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if(*len < sizeof(cyg_serial_info_t)){ + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if(true != mpc555_serial_config_port(chan, config, false)) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------------------------------------------------ +// Enable the transmitter on the device +//------------------------------------------------------------------------------ +static void mpc555_serial_start_xmit(serial_channel * chan) +{ + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; +#ifdef CYGDAT_IO_SERIAL_POWERPC_MPC555_SERIAL_A_USE_HWARE_QUEUE + cyg_addrword_t port = mpc555_chan->base; + if(mpc555_chan->use_queue){ + cyg_uint16 qscicr; + cyg_uint16 qscisr; + cyg_uint16 scsr; + + int chars_avail; + unsigned char* chars; + int block_index = 0; + cyg_addrword_t i; + cyg_uint16 queue_transfer; + + if(!(mpc555_chan->tx_interrupt_enable) && + (chan->callbacks->data_xmt_req)(chan, 32, &chars_avail, &chars) + == CYG_XMT_OK){ + queue_transfer = (chars_avail > 16) ? 16 : chars_avail; + + HAL_READ_UINT16( CYGARC_REG_IMM_QSCI1CR, qscicr); + // Write QTSZ for first pass through the queue + qscicr &= ~(CYGARC_REG_IMM_QSCI1CR_QTSZ); + qscicr |= (CYGARC_REG_IMM_QSCI1CR_QTSZ & (queue_transfer - 1)); + HAL_WRITE_UINT16( CYGARC_REG_IMM_QSCI1CR, qscicr); + // Read SC1SR to clear TC bit when followed by a write of sctq + HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); + + for(i=0; i < queue_transfer; i++){ + HAL_WRITE_UINT16(CYGARC_REG_IMM_SCTQ + (i * 2), chars[block_index]); + ++block_index; + } + chan->callbacks->data_xmt_done(chan, queue_transfer); + + // clear QTHE and QBHE + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + + qscisr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + if(queue_transfer > 8){ + qscisr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + } + + mpc555_chan->tx_interrupt_enable = true; + + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_queue_top_empty_num); + if(queue_transfer > 8){ + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_queue_bot_empty_num); + } + + HAL_READ_UINT16( CYGARC_REG_IMM_QSCI1CR, qscicr); + qscicr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QTE); + HAL_WRITE_UINT16( CYGARC_REG_IMM_QSCI1CR, qscicr); + } + } + else { // no queue + mpc555_chan->tx_interrupt_enable = true; + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); +// No need to call xmt_char, this will generate an interrupt immediately. + } +#else // No queue + mpc555_chan->tx_interrupt_enable = true; + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); +// No need to call xmt_char, this will generate an interrupt immediately. +#endif +} + +//---------------------------------------------------------------------------- +// Disable the transmitter on the device +//---------------------------------------------------------------------------- +static void mpc555_serial_stop_xmit(serial_channel * chan){ + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + if(!mpc555_chan->use_queue){ + cyg_drv_dsr_lock(); + mpc555_chan->tx_interrupt_enable = false; + cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); + cyg_drv_dsr_unlock(); + } +} + +//---------------------------------------------------------------------------- +// The low level transmit interrupt handler +//---------------------------------------------------------------------------- +static cyg_uint32 mpc555_serial_tx_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->tx_interrupt_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + +//---------------------------------------------------------------------------- +// The low level receive interrupt handler +//---------------------------------------------------------------------------- +static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_num); + + cyg_addrword_t port = mpc555_chan->base; + cyg_uint16 scdr; + cyg_uint16 scsr; + + HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); + // Always read out the received character, in order to clear receiver flags + HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); + + mpc555_chan->rx_circbuf->scsr[mpc555_chan->rx_circbuf->fill_pos] = scsr; + mpc555_chan->rx_circbuf->buf[mpc555_chan->rx_circbuf->fill_pos] = (cyg_uint8)scdr; + + if(mpc555_chan->rx_circbuf->fill_pos < MPC555_SCI_RX_BUFF_SIZE - 1){ + mpc555_chan->rx_circbuf->fill_pos = mpc555_chan->rx_circbuf->fill_pos + 1; + } + else { + mpc555_chan->rx_circbuf->fill_pos = 0; + } + cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_num); + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A +//---------------------------------------------------------------------------- +// The low level queued receive interrupt handlers +//---------------------------------------------------------------------------- +static cyg_uint32 mpc555_serial_rx_queue_top_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_queue_top_full_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_queue_top_full_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + +static cyg_uint32 mpc555_serial_rx_queue_bot_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel* chan = (serial_channel *)data; + mpc555_serial_info* mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_queue_bot_full_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_queue_bot_full_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + +// This is used to flush the queue when the line falls idle +static cyg_uint32 mpc555_serial_rx_idle_line_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel* chan = (serial_channel *)data; + mpc555_serial_info* mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_idle_line_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_idle_line_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + +//---------------------------------------------------------------------------- +// The low level queued transmit interrupt handlers +//---------------------------------------------------------------------------- +static cyg_uint32 mpc555_serial_tx_queue_top_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_queue_top_empty_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->tx_interrupt_queue_top_empty_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + +static cyg_uint32 mpc555_serial_tx_queue_bot_ISR(cyg_vector_t vector, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_queue_bot_empty_num); + cyg_drv_interrupt_acknowledge(mpc555_chan->tx_interrupt_queue_bot_empty_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} +#endif // SERIAL_A + +//---------------------------------------------------------------------------- +// The high level transmit interrupt handler +//---------------------------------------------------------------------------- +static void mpc555_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + + (chan->callbacks->xmt_char)(chan); + if(mpc555_chan->tx_interrupt_enable) + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); +} + +//---------------------------------------------------------------------------- +// The high level receive interrupt handler +//---------------------------------------------------------------------------- +#define MPC555_SERIAL_SCxSR_ERRORS (MPC555_SERIAL_SCxSR_OR | \ + MPC555_SERIAL_SCxSR_NF | \ + MPC555_SERIAL_SCxSR_FE | \ + MPC555_SERIAL_SCxSR_PF) + +static void mpc555_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; +// cyg_addrword_t port = mpc555_chan->base; +// cyg_uint16 scdr; + cyg_uint16 scsr; + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + cyg_serial_line_status_t stat; +#endif + + + int i = mpc555_chan->rx_circbuf->read_pos; + while (i < mpc555_chan->rx_circbuf->fill_pos){ + scsr = mpc555_chan->rx_circbuf->scsr[i]; + if(scsr & (cyg_uint16)MPC555_SERIAL_SCxSR_ERRORS){ +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + if(scsr & MPC555_SERIAL_SCxSR_OR){ + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat); + // The current byte is still valid when OR is set + (chan->callbacks->rcv_char)(chan, mpc555_chan->rx_circbuf->buf[i]); + } + else { // OR is never set with any other error bits + if(scsr & MPC555_SERIAL_SCxSR_NF){ + stat.which = CYGNUM_SERIAL_STATUS_NOISEERR; + (chan->callbacks->indicate_status)(chan, &stat); + } + if(scsr & MPC555_SERIAL_SCxSR_FE){ + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat); + } + if(scsr & MPC555_SERIAL_SCxSR_PF){ + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat); + } + } +#endif + } + else { + (chan->callbacks->rcv_char)(chan, mpc555_chan->rx_circbuf->buf[i]); + } + ++i; + } + + cyg_drv_isr_lock(); + mpc555_chan->rx_circbuf->fill_pos = 0; + mpc555_chan->rx_circbuf->read_pos = 0; + cyg_drv_isr_unlock(); +} + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC555_SERIAL_A +//---------------------------------------------------------------------------- +// The high level queued transmit interrupt handler +//---------------------------------------------------------------------------- +static void mpc555_serial_tx_queue_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + bool QTHE = false; + bool QBHE = false; + cyg_uint16 qscisr; + cyg_uint16 qscicr; + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + QTHE = (qscisr & CYGARC_REG_IMM_QSCI1SR_QTHE) ? true : false; + QBHE = (qscisr & CYGARC_REG_IMM_QSCI1SR_QBHE) ? true : false; + + CYG_ASSERT(QTHE || QBHE,"In tx queue DSR for no reason"); + + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + int chars_avail; + unsigned char* chars; + int block_index = 0; + cyg_addrword_t i; + cyg_uint16 queue_transfer; + xmt_req_reply_t result = (chan->callbacks->data_xmt_req)(chan, 24, &chars_avail, &chars); + if(CYG_XMT_OK == result){ + queue_transfer = (chars_avail > 8) ? 8 : chars_avail; + if(QTHE){ + for(i=0; i < queue_transfer; i++){ + HAL_WRITE_UINT16(CYGARC_REG_IMM_SCTQ + (i * 2), chars[block_index]); + ++block_index; + } + chan->callbacks->data_xmt_done(chan, queue_transfer); + // Clear QTHE + qscisr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + + // Re-enable wrap QTWE + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + qscicr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QTWE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + // load QTSZ with how many chars *after* the next wrap + cyg_uint16 next_time = (chars_avail) > 16 ? 15 : chars_avail -1; + qscicr &= ~(CYGARC_REG_IMM_QSCI1CR_QTSZ); + qscicr |= (CYGARC_REG_IMM_QSCI1CR_QTSZ & next_time); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_queue_top_empty_num); + } + else if(QBHE){ + for(i=8; i < queue_transfer + 8; i++){ + HAL_WRITE_UINT16(CYGARC_REG_IMM_SCTQ + (i * 2), chars[block_index]); + ++block_index; + } + chan->callbacks->data_xmt_done(chan, queue_transfer); + // Clear QBHE + qscisr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_queue_bot_empty_num); + } + + } + else if(CYG_XMT_EMPTY== result){ + // No more data + cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_queue_top_empty_num); + cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_queue_bot_empty_num); + mpc555_chan->tx_interrupt_enable = false; + + // Clear QTHE + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + qscisr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + } +} + +//---------------------------------------------------------------------------- +// The high level queued receive interrupt handler +//---------------------------------------------------------------------------- +static void mpc555_serial_rx_queue_DSR(cyg_vector_t vector, + cyg_ucount32 count, cyg_addrword_t data){ + serial_channel * chan = (serial_channel *)data; + mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; + cyg_addrword_t port = mpc555_chan->base; + cyg_uint16 scrq; + cyg_uint16 qscisr; + cyg_uint16 scsr; + cyg_uint16 scdr; + bool QTHF = false; + bool QBHF = false; + bool idle = false; + // Read status reg before reading any data otherwise NE flag will be lost + HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + QTHF = (qscisr & CYGARC_REG_IMM_QSCI1SR_QTHF) ? true : false; + QBHF = (qscisr & CYGARC_REG_IMM_QSCI1SR_QBHF) ? true : false; + idle = (scsr & CYGARC_REG_IMM_SCxSR_IDLE)? true : false; + // The queue pointer is the next place to be filled by incomming data + cyg_uint16 queue_pointer = (qscisr & CYGARC_REG_IMM_QSCI1SR_QRPNT) >> 4; + + int start; + int space_req = 0; + // Idle needs to be handled first as the IDLE bit will be cleared by a read of + // scsr followed by a read of scrq[0:16] + + if(queue_pointer > mpc555_chan->rx_last_queue_pointer){ + start = mpc555_chan->rx_last_queue_pointer; + space_req = mpc555_serial_read_queue(chan, start, queue_pointer - 1); + } + else {// Its wrapped around + if(mpc555_chan->rx_last_queue_pointer > queue_pointer){ + space_req = mpc555_serial_read_queue(chan, mpc555_chan->rx_last_queue_pointer,15); + if(queue_pointer != 0){ + mpc555_serial_read_queue(chan, 0,queue_pointer -1); + } + } + else // No new data to read, do nothing here + { + } + } + + mpc555_chan->rx_last_queue_pointer = queue_pointer; + + if(CYGARC_REG_IMM_QSCI1SR_QOR & qscisr){ + // Need to re-enable the queue + cyg_uint16 qscicr; + HAL_READ_UINT16( CYGARC_REG_IMM_QSCI1CR, qscicr); + qscicr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QRE); + HAL_WRITE_UINT16( CYGARC_REG_IMM_QSCI1CR, qscicr); + // Queue has overrun but data might not have been lost yet + if(scsr & MPC555_SERIAL_SCxSR_OR){ +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + cyg_serial_line_status_t stat; + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat); +#endif + } + } + + if(scsr & (cyg_uint16)MPC555_SERIAL_SCxSR_ERRORS){ + // Special case for queue overrun handled above. + // Only data without FE or PF is allowed into the queue. + // Data with NE is allowed into the queue. + // If FE or PF have occured then the queue is disabled + // until they are cleared (by reading scsr then scdr). + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + cyg_serial_line_status_t stat; + if(scsr & MPC555_SERIAL_SCxSR_NF){ + // Note if there is more than one frame in the queue + // it is not possible to tell which frame + // in the queue caused the noise error. + // The error has already been cleared by reading + // srsr then scrq[n], so no action is required here. + stat.which = CYGNUM_SERIAL_STATUS_NOISEERR; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + if(scsr & (MPC555_SERIAL_SCxSR_FE | MPC555_SERIAL_SCxSR_PF)){ + // This action needs to be taken clear the status bits so that + // the queue can be re-enabled. + HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); + // Need to re-enable the queue + cyg_uint16 qscicr; + HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + qscicr |= ((cyg_uint16)CYGARC_REG_IMM_QSCI1CR_QRE); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qscicr); + +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + if(scsr & MPC555_SERIAL_SCxSR_FE){ + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat); + } + if(scsr & MPC555_SERIAL_SCxSR_PF){ + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + } + } + if(QTHF){ + qscisr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1SR_QTHF); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + //cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_queue_top_full_num); + } + if(QBHF){ + qscisr &= ~((cyg_uint16)CYGARC_REG_IMM_QSCI1SR_QBHF); + HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qscisr); + //cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_queue_bot_full_num); + } + if(idle){ + if(idle && !space_req){ + // The IDLE flag can be set sometimes when RE is set + // so a read of scrq is needed to clear it. + // If this occurs there should be no new data yet otherwise the + // condition is impossible to detect + HAL_READ_UINT16(CYGARC_REG_IMM_SCRQ, scrq); + } + HAL_READ_UINT16(CYGARC_REG_IMM_SCRQ, scrq); + //cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_idle_line_num); + } + // A bit lasy, but we don't know or care what the original ISR source + // was so to cover all bases re-enble them all + cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_queue_top_full_num); + cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_queue_bot_full_num); + cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_idle_line_num); +} + +static int mpc555_serial_read_queue(serial_channel* chan, int start, int end) +{ + int block_index = 0; + cyg_uint16 scrq; + cyg_addrword_t i; + unsigned char* space; + int space_avail = 0; + int space_req = end - start + 1; + if((space_req > 0) && + ((chan->callbacks->data_rcv_req) + (chan, space_req, &space_avail, &space) == CYG_RCV_OK)) { + CYG_ASSERT((start >= 0) && (start < 16),"rx queue read start point out of range"); + CYG_ASSERT(start <= end,"rx queue read start and end points reversed"); + for(i=start ;i < (start + space_avail); i++){ + CYG_ASSERT((i >= 0) && (i < 16),"rx queue read out of range"); + HAL_READ_UINT16(CYGARC_REG_IMM_SCRQ + (i * 2), scrq); + space[block_index] = scrq; + ++block_index; + } + (chan->callbacks->data_rcv_done)(chan,space_avail); +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS +// If there's not enough room data will be lost. +// There's no point calling rcv_char because the reader is blocked by this DSR. + if(space_avail < space_req){ + cyg_serial_line_status_t stat; + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat); + } +#endif + } + return space_req; +} +#endif // SERIAL_A +#endif // CYGPKG_IO_SERIAL_POWERPC_MPC555 + +// EOF mpc555_serial_with_ints.c + diff --git a/ecos/packages/devs/serial/powerpc/mpc8xxx/current/ChangeLog b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/ChangeLog new file mode 100644 index 0000000..c4c0aec --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/ChangeLog @@ -0,0 +1,29 @@ +2003-11-09 Gary Thomas <gary@mlbassoc.com> + + * src/mpc8xxx_serial.h: + * src/mpc8xxx_serial.c: + * cdl/ser_mpc8xxx.cdl: New package - serial I/O for MPC8xxx + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/powerpc/mpc8xxx/current/cdl/ser_mpc8xxx.cdl b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/cdl/ser_mpc8xxx.cdl new file mode 100644 index 0000000..93d0520 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/cdl/ser_mpc8xxx.cdl @@ -0,0 +1,511 @@ +# ==================================================================== +# +# ser_mpc8xxx.cdl +# +# eCos serial PowerPC MPC8XXX (QUICC-II) configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_POWERPC_MPC8XXX { + display "PowerPC MPC8XXX (QUICC-II) serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_POWERPC_MPC8XXX + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + PowerPC MPC8XXX (QUICC-II) SMC/SCC." + + compile -library=libextras.a mpc8xxx_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_mpc8xxx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC1 { + display "PowerPC MPC8XXX/SMC serial port 1 driver" + flavor bool + active_if CYGNUM_HAL_MPC8XXX_SMC1 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + MPC8XXX/SMC port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SMC1_NAME { + display "Device name for PowerPC MPC8XXX/SMC serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the PowerPC + MPC8XXX/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BAUD { + display "Baud rate for the PowerPC MPC8XXX/SMC serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC MPC8XXX/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BUFSIZE { + display "Buffer size for the PowerPC MPC8XXX/SMC serial port 1" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC MPC8XXX/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxSIZE { + display "Output buffer size for the PowerPC MPC8XXX/SMC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC MPC8XXX/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxNUM { + display "Number of output buffers for the PowerPC MPC8XXX/SMC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC MPC8XXX/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxSIZE { + display "Input buffer size for the PowerPC MPC8XXX/SMC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC MPC8XXX/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxNUM { + display "Number of input buffers for the PowerPC MPC8XXX/SMC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC MPC8XXX/SMC port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC2 { + display "PowerPC MPC8XXX/SMC serial port 2 driver" + flavor bool + active_if CYGNUM_HAL_MPC8XXX_SMC2 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + MPC8XXX/SMC port 2." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SMC2_NAME { + display "Device name for PowerPC MPC8XXX/SMC serial port 2" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the PowerPC + MPC8XXX/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BAUD { + display "Baud rate for the PowerPC MPC8XXX/SMC serial port 2" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC MPC8XXX/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BUFSIZE { + display "Buffer size for the PowerPC MPC8XXX/SMC serial port 2" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC MPC8XXX/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxSIZE { + display "Output buffer size for the PowerPC MPC8XXX/SMC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC MPC8XXX/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxNUM { + display "Number of output buffers for the PowerPC MPC8XXX/SMC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC MPC8XXX/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxSIZE { + display "Input buffer size for the PowerPC MPC8XXX/SMC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC MPC8XXX/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxNUM { + display "Number of output buffers for the PowerPC MPC8XXX/SMC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC MPC8XXX/SMC port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC1 { + display "PowerPC MPC8XXX/SCC serial port 1 driver" + flavor bool + active_if CYGNUM_HAL_MPC8XXX_SCC1 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + MPC8XXX/SCC port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SCC1_NAME { + display "Device name for PowerPC MPC8XXX/SCC serial port 1" + flavor data + default_value {"\"/dev/scc1\""} + description " + This option specifies the device name for the PowerPC + MPC8XXX/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BAUD { + display "Baud rate for the PowerPC MPC8XXX/SCC serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC MPC8XXX/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BUFSIZE { + display "Buffer size for the PowerPC MPC8XXX/SCC serial port 1" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC MPC8XXX/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxSIZE { + display "Output buffer size for the PowerPC MPC8XXX/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC MPC8XXX/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxNUM { + display "Number of output buffers for the PowerPC MPC8XXX/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC MPC8XXX/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxSIZE { + display "Input buffer size for the PowerPC MPC8XXX/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC MPC8XXX/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxNUM { + display "Number of input buffers for the PowerPC MPC8XXX/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC MPC8XXX/SCC port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC2 { + display "PowerPC MPC8XXX/SCC serial port 2 driver" + flavor bool + active_if CYGNUM_HAL_MPC8XXX_SCC2 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + MPC8XXX/SCC port 2." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SCC2_NAME { + display "Device name for PowerPC MPC8XXX/SCC serial port 2" + flavor data + default_value {"\"/dev/scc2\""} + description " + This option specifies the device name for the PowerPC + MPC8XXX/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BAUD { + display "Baud rate for the PowerPC MPC8XXX/SCC serial port 2" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC MPC8XXX/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BUFSIZE { + display "Buffer size for the PowerPC MPC8XXX/SCC serial port 2" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC MPC8XXX/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxSIZE { + display "Output buffer size for the PowerPC MPC8XXX/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC MPC8XXX/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxNUM { + display "Number of output buffers for the PowerPC MPC8XXX/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC MPC8XXX/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxSIZE { + display "Input buffer size for the PowerPC MPC8XXX/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC MPC8XXX/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxNUM { + display "Number of input buffers for the PowerPC MPC8XXX/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC MPC8XXX/SCC port 2." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC3 { + display "PowerPC MPC8XXX/SCC serial port 3 driver" + flavor bool + active_if CYGNUM_HAL_MPC8XXX_SCC3 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + MPC8XXX/SCC port 3." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SCC3_NAME { + display "Device name for PowerPC MPC8XXX/SCC serial port 3" + flavor data + default_value {"\"/dev/scc3\""} + description " + This option specifies the device name for the PowerPC + MPC8XXX/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BAUD { + display "Baud rate for the PowerPC MPC8XXX/SCC serial port 3" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC MPC8XXX/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BUFSIZE { + display "Buffer size for the PowerPC MPC8XXX/SCC serial port 3" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC MPC8XXX/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxSIZE { + display "Output buffer size for the PowerPC MPC8XXX/SCC serial port 3" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC MPC8XXX/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxNUM { + display "Number of output buffers for the PowerPC MPC8XXX/SCC serial port 3" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC MPC8XXX/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxSIZE { + display "Input buffer size for the PowerPC MPC8XXX/SCC serial port 3" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC MPC8XXX/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxNUM { + display "Number of input buffers for the PowerPC MPC8XXX/SCC serial port 3" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC MPC8XXX/SCC port 3." + } +} + +# EOF ser_mpc8xxx_smc.cdl diff --git a/ecos/packages/devs/serial/powerpc/mpc8xxx/current/src/mpc8xxx_serial.c b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/src/mpc8xxx_serial.c new file mode 100644 index 0000000..2c5eb7d --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/src/mpc8xxx_serial.c @@ -0,0 +1,1014 @@ +//========================================================================== +// +// io/serial/powerpc/mpc8xxx_serial.c +// +// PowerPC MPC8XXX (QUICC-II) (SMC/SCC) Serial I/O Interface Module +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-20 +// Purpose: MPC8XXX Serial I/O module +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/mpc8xxx.h> +#include CYGBLD_HAL_PLATFORM_H + +#include "mpc8xxx_serial.h" + +typedef struct mpc8xxx_sxx_serial_info { + CYG_ADDRWORD channel; // Which channel SMCx/SCCx + short int_num; // Interrupt number + short type; // Channel type - SCC or SMC + unsigned long *brg; // Which baud rate generator + void *pram; // Parameter RAM pointer + void *ctl; // SMC/SCC control registers + volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use + struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor + int txsize, rxsize; // Length of individual buffers + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} mpc8xxx_sxx_serial_info; + +static bool mpc8xxx_sxx_serial_init(struct cyg_devtab_entry *tab); +static bool mpc8xxx_sxx_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo mpc8xxx_sxx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char mpc8xxx_sxx_serial_getc(serial_channel *chan); +static Cyg_ErrNo mpc8xxx_sxx_serial_set_config(serial_channel *chan, + cyg_uint32 key, const void *xbuf, + cyg_uint32 *len); +static void mpc8xxx_sxx_serial_start_xmit(serial_channel *chan); +static void mpc8xxx_sxx_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 mpc8xxx_sxx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void mpc8xxx_sxx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_putc, + mpc8xxx_sxx_serial_getc, + mpc8xxx_sxx_serial_set_config, + mpc8xxx_sxx_serial_start_xmit, + mpc8xxx_sxx_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC1 +static mpc8xxx_sxx_serial_info mpc8xxx_sxx_serial_info_smc1 = { + SMC1_PAGE_SUBBLOCK, // Channel indicator + CYGNUM_HAL_INTERRUPT_SMC1, // interrupt + _SMC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BUFSIZE > 0 +static unsigned char mpc8xxx_smc_serial_out_buf_smc1[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BUFSIZE]; +static unsigned char mpc8xxx_smc_serial_in_buf_smc1[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mpc8xxx_sxx_serial_channel_smc1, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_smc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc8xxx_smc_serial_out_buf_smc1[0], sizeof(mpc8xxx_smc_serial_out_buf_smc1), + &mpc8xxx_smc_serial_in_buf_smc1[0], sizeof(mpc8xxx_smc_serial_in_buf_smc1) + ); +#else +static SERIAL_CHANNEL(mpc8xxx_sxx_serial_channel_smc1, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_smc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +static unsigned char mpc8xxx_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char mpc8xxx_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(mpc8xxx_smc_serial_io_smc1, + CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SMC1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mpc8xxx_sxx_serial_init, + mpc8xxx_sxx_serial_lookup, // Serial driver may need initializing + &mpc8xxx_sxx_serial_channel_smc1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC2 +static mpc8xxx_sxx_serial_info mpc8xxx_sxx_serial_info_smc2 = { + SMC2_PAGE_SUBBLOCK, // Channel indicator + CYGNUM_HAL_INTERRUPT_SMC2, // interrupt + _SMC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BUFSIZE > 0 +static unsigned char mpc8xxx_smc_serial_out_buf_smc2[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BUFSIZE]; +static unsigned char mpc8xxx_smc_serial_in_buf_smc2[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mpc8xxx_sxx_serial_channel_smc2, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_smc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc8xxx_smc_serial_out_buf_smc2[0], sizeof(mpc8xxx_smc_serial_out_buf_smc2), + &mpc8xxx_smc_serial_in_buf_smc2[0], sizeof(mpc8xxx_smc_serial_in_buf_smc2) + ); +#else +static SERIAL_CHANNEL(mpc8xxx_sxx_serial_channel_smc2, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_smc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char mpc8xxx_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char mpc8xxx_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(mpc8xxx_smc_serial_io_smc2, + CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SMC2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mpc8xxx_sxx_serial_init, + mpc8xxx_sxx_serial_lookup, // Serial driver may need initializing + &mpc8xxx_sxx_serial_channel_smc2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC2 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC1 +static mpc8xxx_sxx_serial_info mpc8xxx_sxx_serial_info_scc1 = { + SCC1_PAGE_SUBBLOCK, // Channel indicator + CYGNUM_HAL_INTERRUPT_SCC1, // interrupt + _SCC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BUFSIZE > 0 +static unsigned char mpc8xxx_smc_serial_out_buf_scc1[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BUFSIZE]; +static unsigned char mpc8xxx_smc_serial_in_buf_scc1[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mpc8xxx_sxx_serial_channel_scc1, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_scc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc8xxx_smc_serial_out_buf_scc1[0], sizeof(mpc8xxx_smc_serial_out_buf_scc1), + &mpc8xxx_smc_serial_in_buf_scc1[0], sizeof(mpc8xxx_smc_serial_in_buf_scc1) + ); +#else +static SERIAL_CHANNEL(mpc8xxx_sxx_serial_channel_scc1, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_scc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char mpc8xxx_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char mpc8xxx_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(mpc8xxx_smc_serial_io_scc1, + CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SCC1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mpc8xxx_sxx_serial_init, + mpc8xxx_sxx_serial_lookup, // Serial driver may need initializing + &mpc8xxx_sxx_serial_channel_scc1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC2 +static mpc8xxx_sxx_serial_info mpc8xxx_sxx_serial_info_scc2 = { + SCC2_PAGE_SUBBLOCK, // Channel indicator + CYGNUM_HAL_INTERRUPT_SCC2, // interrupt + _SCC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BUFSIZE > 0 +static unsigned char mpc8xxx_smc_serial_out_buf_scc2[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BUFSIZE]; +static unsigned char mpc8xxx_smc_serial_in_buf_scc2[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mpc8xxx_sxx_serial_channel_scc2, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_scc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc8xxx_smc_serial_out_buf_scc2[0], sizeof(mpc8xxx_smc_serial_out_buf_scc2), + &mpc8xxx_smc_serial_in_buf_scc2[0], sizeof(mpc8xxx_smc_serial_in_buf_scc2) + ); +#else +static SERIAL_CHANNEL(mpc8xxx_sxx_serial_channel_scc2, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_scc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char mpc8xxx_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char mpc8xxx_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(mpc8xxx_smc_serial_io_scc2, + CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SCC2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mpc8xxx_sxx_serial_init, + mpc8xxx_sxx_serial_lookup, // Serial driver may need initializing + &mpc8xxx_sxx_serial_channel_scc2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC2 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC3 +static mpc8xxx_sxx_serial_info mpc8xxx_sxx_serial_info_scc3 = { + SCC3_PAGE_SUBBLOCK, // Channel indicator + CYGNUM_HAL_INTERRUPT_SCC3, // interrupt + _SCC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BUFSIZE > 0 +static unsigned char mpc8xxx_smc_serial_out_buf_scc3[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BUFSIZE]; +static unsigned char mpc8xxx_smc_serial_in_buf_scc3[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mpc8xxx_sxx_serial_channel_scc3, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_scc3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mpc8xxx_smc_serial_out_buf_scc3[0], sizeof(mpc8xxx_smc_serial_out_buf_scc3), + &mpc8xxx_smc_serial_in_buf_scc3[0], sizeof(mpc8xxx_smc_serial_in_buf_scc3) + ); +#else +static SERIAL_CHANNEL(mpc8xxx_sxx_serial_channel_scc3, + mpc8xxx_sxx_serial_funs, + mpc8xxx_sxx_serial_info_scc3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char mpc8xxx_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char mpc8xxx_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(mpc8xxx_smc_serial_io_scc3, + CYGDAT_IO_SERIAL_POWERPC_MPC8XXX_SCC3_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mpc8xxx_sxx_serial_init, + mpc8xxx_sxx_serial_lookup, // Serial driver may need initializing + &mpc8xxx_sxx_serial_channel_scc3 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC3 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +mpc8xxx_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + unsigned int baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr; + volatile struct smc_regs_8260 *ctl = (volatile struct smc_regs_8260*)smc_chan->ctl; + + if (baud_divisor == 0) return false; + // Disable channel during setup + ctl->smc_smcmr = MPC8XXX_SMCMR_UART; // Disabled, UART mode + HAL_IO_BARRIER(); // Inforce I/O ordering + // Disable port interrupts while changing hardware + _lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + smc_select_stop_bits[new_config->stop] | + smc_select_parity[new_config->parity]; + // Stop transmitter while changing baud rate + IMM->cpm_cpcr = smc_chan->channel | CPCR_STOP_TX | CPCR_FLG; + HAL_IO_BARRIER(); // Inforce I/O ordering + // Set baud rate generator + *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); + + // Enable channel with new configuration + ctl->smc_smcmr = MPC8XXX_SMCMR_UART|MPC8XXX_SMCMR_TEN|MPC8XXX_SMCMR_REN|_lcr; + HAL_IO_BARRIER(); // Inforce I/O ordering + IMM->cpm_cpcr = smc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +mpc8xxx_smc_serial_init_info(mpc8xxx_sxx_serial_info *smc_chan, + t_Smc_Pram *uart_pram, + volatile struct smc_regs_8260 *ctl, + unsigned long *brg, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF) +{ + struct cp_bufdesc *txbd, *rxbd; + int i; + + smc_chan->pram = (void *)uart_pram; + smc_chan->ctl = (void *)ctl; + + // Set up baud rate generator + smc_chan->brg = (void *)brg; + + // Disable channel during setup + ctl->smc_smcmr = MPC8XXX_SMCMR_UART; // Disabled, UART mode + + // Rx, Tx function codes (used for access) + uart_pram->rfcr = 0x18; + uart_pram->tfcr = 0x18; + + // Pointers to Rx & Tx buffer descriptor rings + uart_pram->rbase = RxBD; + uart_pram->tbase = TxBD; + + /* tx and rx buffer descriptors */ + txbd = (struct cp_bufdesc *)((char *)IMM + TxBD); + rxbd = (struct cp_bufdesc *)((char *)IMM + RxBD); + smc_chan->txbd = txbd; + smc_chan->tbase = txbd; + smc_chan->txsize = TxSIZE; + smc_chan->rxbd = rxbd; + smc_chan->rbase = rxbd; + smc_chan->rxsize = RxSIZE; + + /* set max_idle feature - generate interrupt after 4 chars idle period */ + uart_pram->max_idl = 4; + + /* no last brk char received */ + uart_pram->brkln = 0; + + /* no break condition occurred */ + uart_pram->brkec = 0; + + /* 1 break char sent on top XMIT */ + uart_pram->brkcr = 1; + + /* setup RX buffer descriptors */ + for (i = 0; i < RxNUM; i++) { + rxbd->length = 0; + rxbd->buffer = RxBUF; + rxbd->ctrl = _BD_CTL_Ready | _BD_CTL_Int; + if (i == (RxNUM-1)) rxbd->ctrl |= _BD_CTL_Wrap; // Last buffer + RxBUF += RxSIZE; + rxbd++; + } + /* setup TX buffer descriptors */ + for (i = 0; i < TxNUM; i++) { + txbd->length = 0; + txbd->buffer = TxBUF; + txbd->ctrl = 0; + if (i == (TxNUM-1)) txbd->ctrl |= _BD_CTL_Wrap; // Last buffer + TxBUF += TxSIZE; + txbd++; + } + /* + * Reset Rx & Tx params + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + IMM->cpm_cpcr = smc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG; + HAL_IO_BARRIER(); // Inforce I/O ordering + /* + * Clear any previous events. Enable interrupts. + * (Section 16.15.7.14 and 16.15.7.15) + */ + ctl->smc_smce = 0xFF; + ctl->smc_smcm = SMCE_Bsy|SMCE_Tx|SMCE_Rx; +} + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +mpc8xxx_scc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + mpc8xxx_sxx_serial_info *scc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + unsigned int baud_divisor = select_baud[new_config->baud]; + volatile struct scc_regs_8260 *regs = (volatile struct scc_regs_8260*)scc_chan->ctl; + + if (baud_divisor == 0) return false; + // Set baud rate generator + *scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); + // Disable channel during setup + HAL_IO_BARRIER(); // Inforce I/O ordering + regs->gsmr_l = 0; + regs->psmr = MPC8XXX_SCC_PSMR_ASYNC | + scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + scc_select_stop_bits[new_config->stop] | + scc_select_parity[new_config->parity]; + + // Enable channel with new configuration + regs->gsmr_h = 0x20; // 8bit FIFO + regs->gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART + + /* + * Init Rx & Tx params for SCCX + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS | scc_chan->channel | CPCR_FLG; + + HAL_IO_BARRIER(); // Inforce I/O ordering + regs->gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR; // Enable Rx, Tx + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +mpc8xxx_scc_serial_init_info(mpc8xxx_sxx_serial_info *scc_chan, + volatile t_Scc_Pram *uart_pram, + volatile struct scc_regs_8260 *ctl, + unsigned long *brg, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF) +{ + struct cp_bufdesc *txbd, *rxbd; + int i; + + // Disable channel during setup + ctl->gsmr_l = 0; + scc_chan->pram = (void *)uart_pram; + scc_chan->ctl = (void *)ctl; + + // Set up baud rate generator + scc_chan->brg = brg; + + /* + * Set Rx and Tx function code + * (Section 16.15.4.2) + */ + uart_pram->rfcr = 0x18; + uart_pram->tfcr = 0x18; + /* + * Set pointers to buffer descriptors. + * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) + */ + uart_pram->rbase = RxBD; + uart_pram->tbase = TxBD; + /* tx and rx buffer descriptors */ + txbd = (struct cp_bufdesc *)((char *)IMM + TxBD); + rxbd = (struct cp_bufdesc *)((char *)IMM + RxBD); + scc_chan->txbd = txbd; + scc_chan->tbase = txbd; + scc_chan->txsize = TxSIZE; + scc_chan->rxbd = rxbd; + scc_chan->rbase = rxbd; + scc_chan->rxsize = RxSIZE; + /* max receive buffer length */ + uart_pram->mrblr = RxSIZE; + /* set max_idle feature - generate interrupt after 4 chars idle period */ + uart_pram->SpecificProtocol.u.max_idl = 4; + /* no last brk char received */ + uart_pram->SpecificProtocol.u.brkln = 0; + /* no break condition occurred */ + uart_pram->SpecificProtocol.u.brkec = 0; + /* 1 break char sent on top XMIT */ + uart_pram->SpecificProtocol.u.brkcr = 1; + /* character mask */ + uart_pram->SpecificProtocol.u.rccm = 0xC0FF; + /* control characters */ + for (i = 0; i < 8; i++) { + uart_pram->SpecificProtocol.u.cc[i] = 0x8000; // Mark unused + } + /* setup RX buffer descriptors */ + for (i = 0; i < RxNUM; i++) { + rxbd->length = 0; + rxbd->buffer = RxBUF; + rxbd->ctrl = _BD_CTL_Ready | _BD_CTL_Int; + if (i == (RxNUM-1)) rxbd->ctrl |= _BD_CTL_Wrap; // Last buffer + RxBUF += RxSIZE; + rxbd++; + } + /* setup TX buffer descriptors */ + for (i = 0; i < TxNUM; i++) { + txbd->length = 0; + txbd->buffer = TxBUF; + txbd->ctrl = 0; + if (i == (TxNUM-1)) txbd->ctrl |= _BD_CTL_Wrap; // Last buffer + TxBUF += TxSIZE; + txbd++; + } + /* + * Reset Rx & Tx params + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + IMM->cpm_cpcr = scc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG; + /* + * Clear any previous events. Enable interrupts. + * (Section 16.15.7.14 and 16.15.7.15) + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + ctl->scce = 0xFFFF; + ctl->sccm = (SCCE_Bsy | SCCE_Tx | SCCE_Rx); +} + +// Function to initialize the device. Called at bootstrap time. +static bool +mpc8xxx_sxx_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + int TxBD, RxBD; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); +#ifdef CYGDBG_IO_INIT + diag_printf("MPC8XXX_SMC SERIAL init - dev: %x.%d = %s\n", smc_chan->channel, smc_chan->int_num, tab->name); +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC1 + if (chan == &mpc8xxx_sxx_serial_channel_smc1) { + TxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxNUM); + RxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxNUM); + mpc8xxx_smc_serial_init_info(&mpc8xxx_sxx_serial_info_smc1, + (t_Smc_Pram *)((char *)IMM + DPRAM_SMC1_OFFSET), + &IMM->smc_regs[SMC1], + (unsigned long *)&IMM->brgs_brgc7, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_TxSIZE, + &mpc8xxx_smc1_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC1_RxSIZE, + &mpc8xxx_smc1_rxbuf[0] + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SMC2 +#warning "Serial driver on SMC2 is unverified" + if (chan == &mpc8xxx_sxx_serial_channel_smc2) { + TxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxNUM); + RxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxNUM); + mpc8xxx_smc_serial_init_info(&mpc8xxx_sxx_serial_info_smc2, + &IMM->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM + &IMM->smc_regs[1], // Control registers + &IMM->brgs_brgc7, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_TxSIZE, + &mpc8xxx_smc2_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SMC2_RxSIZE, + &mpc8xxx_smc2_rxbuf[0] + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC1 + if (chan == &mpc8xxx_sxx_serial_channel_scc1) { + TxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxNUM); + RxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxNUM); + mpc8xxx_scc_serial_init_info(&mpc8xxx_sxx_serial_info_scc1, + &IMM->pram.serials.scc_pram[SCC1], + &IMM->scc_regs[SCC1], + (unsigned long *)&IMM->brgs_brgc1, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_TxSIZE, + &mpc8xxx_scc1_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC1_RxSIZE, + &mpc8xxx_scc1_rxbuf[0] + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC2 +#warning "Serial driver on SCC2 is unverified" + if (chan == &mpc8xxx_sxx_serial_channel_scc2) { + TxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxNUM); + RxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxNUM); + mpc8xxx_scc_serial_init_info(&mpc8xxx_sxx_serial_info_scc2, + &IMM->pram[1].scc.pscc.u, // PRAM + &IMM->scc_regs[1], // Control registers + &IMM->brgs_brgc2, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_TxSIZE, + &mpc8xxx_scc2_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC2_RxSIZE, + &mpc8xxx_scc2_rxbuf[0] + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_MPC8XXX_SCC3 +#warning "Serial driver on SCC3 is unverified" + if (chan == &mpc8xxx_sxx_serial_channel_scc3) { + TxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxNUM); + RxBD = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxNUM); + mpc8xxx_scc_serial_init_info(&mpc8xxx_sxx_serial_info_scc3, + &IMM->pram[2].scc.pscc.u, // PRAM + &IMM->scc_regs[2], // Control registersn + &IMM->brgs_brgc3, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_TxSIZE, + &mpc8xxx_scc3_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_MPC8XXX_SCC3_RxSIZE, + &mpc8xxx_scc3_rxbuf[0] + ); + } +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(smc_chan->int_num, + 0, // Priority - unused (but asserted) + (cyg_addrword_t)chan, // Data item passed to interrupt handler + mpc8xxx_sxx_serial_ISR, + mpc8xxx_sxx_serial_DSR, + &smc_chan->serial_interrupt_handle, + &smc_chan->serial_interrupt); + cyg_drv_interrupt_attach(smc_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(smc_chan->int_num); + } + if (smc_chan->type == _SMC_CHAN) { + mpc8xxx_smc_serial_config_port(chan, &chan->config, true); + } else { + mpc8xxx_scc_serial_config_port(chan, &chan->config, true); + } + if (cache_state) + HAL_DCACHE_ENABLE(); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +mpc8xxx_sxx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Force the current transmit buffer to be sent +static void +mpc8xxx_sxx_serial_flush(mpc8xxx_sxx_serial_info *smc_chan) +{ + volatile struct cp_bufdesc *txbd = smc_chan->txbd; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_FLUSH(txbd->buffer, smc_chan->txsize); + } + if ((txbd->length > 0) && + ((txbd->ctrl & (_BD_CTL_Ready|_BD_CTL_Int)) == 0)) { + txbd->ctrl |= _BD_CTL_Ready|_BD_CTL_Int; // Signal buffer ready + if (txbd->ctrl & _BD_CTL_Wrap) { + txbd = smc_chan->tbase; + } else { + txbd++; + } + smc_chan->txbd = txbd; + } +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +mpc8xxx_sxx_serial_putc(serial_channel *chan, unsigned char c) +{ + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + volatile struct cp_bufdesc *txbd, *txfirst; + volatile t_Smc_Pram *pram = (volatile t_Smc_Pram *)smc_chan->pram; + bool res; + + cyg_drv_dsr_lock(); // Avoid race condition testing pointers + txbd = (struct cp_bufdesc *)((char *)IMM + pram->tbptr); + txfirst = txbd; + // Scan for a non-busy buffer + while (txbd->ctrl & _BD_CTL_Ready) { + // This buffer is busy, move to next one + if (txbd->ctrl & _BD_CTL_Wrap) { + txbd = smc_chan->tbase; + } else { + txbd++; + } + if (txbd == txfirst) break; // Went all the way around + } + smc_chan->txbd = txbd; + if ((txbd->ctrl & (_BD_CTL_Ready|_BD_CTL_Int)) == 0) { + // Transmit buffer is not full/busy + txbd->buffer[txbd->length++] = c; + if (txbd->length == smc_chan->txsize) { + // This buffer is now full, tell SMC to start processing it + mpc8xxx_sxx_serial_flush(smc_chan); + } + res = true; + } else { + // No space + res = false; + } + cyg_drv_dsr_unlock(); + return res; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +mpc8xxx_sxx_serial_getc(serial_channel *chan) +{ + unsigned char c; + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + + while ((rxbd->ctrl & _BD_CTL_Ready) != 0) ; + c = rxbd->buffer[0]; + rxbd->length = smc_chan->rxsize; + rxbd->ctrl |= _BD_CTL_Ready; + if (rxbd->ctrl & _BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +mpc8xxx_sxx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + int res; + + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + // FIXME - The documentation says that you can't change the baud rate + // again until at least two BRG input clocks have occurred. + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if (smc_chan->type == _SMC_CHAN) { + res = mpc8xxx_smc_serial_config_port(chan, config, true); + } else { + res = mpc8xxx_scc_serial_config_port(chan, config, true); + } + if ( true != res ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +mpc8xxx_sxx_serial_start_xmit(serial_channel *chan) +{ + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + cyg_drv_dsr_lock(); + if (smc_chan->txbd->length == 0) { + // See if there is anything to put in this buffer, just to get it going + (chan->callbacks->xmt_char)(chan); + } + if (smc_chan->txbd->length != 0) { + // Make sure it gets started + mpc8xxx_sxx_serial_flush(smc_chan); + } + cyg_drv_dsr_unlock(); +} + +// Disable the transmitter on the device +static void +mpc8xxx_sxx_serial_stop_xmit(serial_channel *chan) +{ + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + // If anything is in the last buffer, need to get it started + if (smc_chan->txbd->length != 0) { + mpc8xxx_sxx_serial_flush(smc_chan); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +mpc8xxx_sxx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(smc_chan->int_num); + return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +mpc8xxx_smc_serial_DSR(serial_channel *chan) +{ + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + volatile struct smc_regs_8260 *ctl = (volatile struct smc_regs_8260 *)smc_chan->ctl; + volatile struct cp_bufdesc *txbd; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + volatile t_Smc_Pram *pram = (volatile t_Smc_Pram *)smc_chan->pram; + struct cp_bufdesc *rxlast; + int i, cache_state; + + if (ctl->smc_smce & SMCE_Tx) { + // Transmit interrupt + ctl->smc_smce = SMCE_Tx; // Reset interrupt state; + txbd = smc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (_BD_CTL_Ready|_BD_CTL_Int)) == _BD_CTL_Int) { + txbd->length = 0; + txbd->ctrl &= ~_BD_CTL_Int; // Reset interrupt bit + } + if (txbd->ctrl & _BD_CTL_Wrap) { + txbd = smc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + while (ctl->smc_smce & SMCE_Rx) { + // Receive interrupt + ctl->smc_smce = SMCE_Rx; // Reset interrupt state; + rxlast = (struct cp_bufdesc *) ( + (char *)IMM + pram->rbptr ); + while (rxbd != rxlast) { + if ((rxbd->ctrl & _BD_CTL_Ready) == 0) { + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data + } + rxbd->length = 0; + rxbd->ctrl |= _BD_CTL_Ready; + } + if (rxbd->ctrl & _BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + } + if (ctl->smc_smce & SMCE_Bsy) { + ctl->smc_smce = SMCE_Bsy; // Reset interrupt state; + } + cyg_drv_interrupt_acknowledge(smc_chan->int_num); + cyg_drv_interrupt_unmask(smc_chan->int_num); +} + +static void +mpc8xxx_scc_serial_DSR(serial_channel *chan) +{ + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + volatile struct scc_regs_8260 *ctl = (volatile struct scc_regs_8260 *)smc_chan->ctl; + volatile struct cp_bufdesc *txbd; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + volatile t_Smc_Pram *pram = (volatile t_Smc_Pram *)smc_chan->pram; + struct cp_bufdesc *rxlast; + int i, cache_state; + + if (ctl->scce & SCCE_Tx) { + // Transmit interrupt + ctl->scce = SCCE_Tx; // Reset interrupt state; + txbd = smc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (_BD_CTL_Ready|_BD_CTL_Int)) == _BD_CTL_Int) { + txbd->length = 0; + txbd->ctrl &= ~_BD_CTL_Int; // Reset interrupt bit + } + if (txbd->ctrl & _BD_CTL_Wrap) { + txbd = smc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + while (ctl->scce & SCCE_Rx) { + // Receive interrupt + ctl->scce = SCCE_Rx; // Reset interrupt state; + rxlast = (struct cp_bufdesc *) ((char *)IMM + pram->rbptr); + while (rxbd != rxlast) { + if ((rxbd->ctrl & _BD_CTL_Ready) == 0) { + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data + } + rxbd->length = 0; + rxbd->ctrl |= _BD_CTL_Ready; + } + if (rxbd->ctrl & _BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + } + if (ctl->scce & SCCE_Bsy) { + ctl->scce = SCCE_Bsy; // Reset interrupt state; + } + cyg_drv_interrupt_acknowledge(smc_chan->int_num); + cyg_drv_interrupt_unmask(smc_chan->int_num); +} + +static void +mpc8xxx_sxx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; + + if (smc_chan->type == _SMC_CHAN) { + mpc8xxx_smc_serial_DSR(chan); + } else { + mpc8xxx_scc_serial_DSR(chan); + } +} + +// ------------------------------------------------------------------------ +// EOF powerpc/mpc8xxx_smc_serial.c diff --git a/ecos/packages/devs/serial/powerpc/mpc8xxx/current/src/mpc8xxx_serial.h b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/src/mpc8xxx_serial.h new file mode 100644 index 0000000..b0ebd71 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/mpc8xxx/current/src/mpc8xxx_serial.h @@ -0,0 +1,153 @@ +#ifndef CYGONCE_POWERPC_MPC8XXX_SERIAL_H +#define CYGONCE_POWERPC_MPC8XXX_SERIAL_H + +// ==================================================================== +// +// mpc8xxx_serial.h +// +// Device I/O - Description of PowerPC MPC8XXX (QUICC-II) serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-21 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports using MPC8XXX (QUICC-II) + +// SMC Mode Register +#define MPC8XXX_SMCMR_CLEN(n) ((n+1)<<11) // Character length +#define MPC8XXX_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2) +#define MPC8XXX_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable) +#define MPC8XXX_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even) +#define MPC8XXX_SMCMR_UART (2<<4) // UART mode +#define MPC8XXX_SMCMR_TEN (1<<1) // Enable transmitter +#define MPC8XXX_SMCMR_REN (1<<0) // Enable receiver + +static unsigned int smc_select_word_length[] = { + MPC8XXX_SMCMR_CLEN(5), // 5 bits / word (char) + MPC8XXX_SMCMR_CLEN(6), + MPC8XXX_SMCMR_CLEN(7), + MPC8XXX_SMCMR_CLEN(8) +}; + +static unsigned int smc_select_stop_bits[] = { + 0, + MPC8XXX_SMCMR_SB(1), // 1 stop bit + MPC8XXX_SMCMR_SB(1), // 1.5 stop bit + MPC8XXX_SMCMR_SB(2) // 2 stop bits +}; + +static unsigned int smc_select_parity[] = { + MPC8XXX_SMCMR_PE(0), // No parity + MPC8XXX_SMCMR_PE(1)|MPC8XXX_SMCMR_PM(1), // Even parity + MPC8XXX_SMCMR_PE(1)|MPC8XXX_SMCMR_PM(0), // Odd parity + 0, // Mark parity + 0, // Space parity +}; + +// SCC PSMR masks .... +#define MPC8XXX_SCC_PSMR_ASYNC 0x8000 +#define MPC8XXX_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb) +#define MPC8XXX_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8) +#define MPC8XXX_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled) +#define MPC8XXX_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high) +#define MPC8XXX_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high) + +static unsigned int scc_select_word_length[] = { + MPC8XXX_SCC_PSMR_CLEN(5), // 5 bits / word (char) + MPC8XXX_SCC_PSMR_CLEN(6), + MPC8XXX_SCC_PSMR_CLEN(7), + MPC8XXX_SCC_PSMR_CLEN(8) +}; + +static unsigned int scc_select_stop_bits[] = { + MPC8XXX_SCC_PSMR_SB(1), // 0.5 stop bit ?? + MPC8XXX_SCC_PSMR_SB(1), // 1 stop bit + MPC8XXX_SCC_PSMR_SB(2), // 1.5 stop bit + MPC8XXX_SCC_PSMR_SB(2) // 2 stop bits +}; + + +static unsigned int scc_select_parity[] = { + MPC8XXX_SCC_PSMR_PE(0), // No parity + MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(2)|MPC8XXX_SCC_PSMR_RPM(2), // Even parity + MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(0)|MPC8XXX_SCC_PSMR_RPM(0), // Odd parity + MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(3)|MPC8XXX_SCC_PSMR_RPM(3), // High (mark) parity + MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(1)|MPC8XXX_SCC_PSMR_RPM(1), // Low (space) parity +}; + +// Baud rate values, based on board clock + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 0, // 230400 +}; + +#define UART_BITRATE(n) \ + ((((int)(((CYGHWR_HAL_POWERPC_CPM_SPEED*2)*1000000)/16))/(n * 16))-1) + +// Channel type select +#define _SCC_CHAN 0 +#define _SMC_CHAN 1 + +#endif // CYGONCE_POWERPC_MPC8XXX_SERIAL_H diff --git a/ecos/packages/devs/serial/powerpc/ppc405/current/ChangeLog b/ecos/packages/devs/serial/powerpc/ppc405/current/ChangeLog new file mode 100644 index 0000000..268d814 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/ppc405/current/ChangeLog @@ -0,0 +1,33 @@ +2005-08-25 Markus Schade <marks@peppercon.de> + + * enabled build for PowerPC 405EP + +2003-09-19 Gary Thomas <gary@mlbassoc.com> + + * include/powerpc_ppc405_ser.inl: + * cdl/ser_powerpc_ppc405.cdl: New package - support for PowerPC 405GP, + based on generic 165x5 uart. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/powerpc/ppc405/current/cdl/ser_powerpc_ppc405.cdl b/ecos/packages/devs/serial/powerpc/ppc405/current/cdl/ser_powerpc_ppc405.cdl new file mode 100644 index 0000000..9fbf9fd --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/ppc405/current/cdl/ser_powerpc_ppc405.cdl @@ -0,0 +1,195 @@ +# ==================================================================== +# +# ser_powerpc_ppc405.cdl +# +# eCos serial configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Original data: +# Contributors: +# Date: 2003-09-16 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_POWERPC_PPC405 { + display "PowerPC PPC405 (16x5x) serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_POWERPC_PPC40x +# Only the 405GP has these ports + active_if { CYGHWR_HAL_POWERPC_PPC4XX == "405GP" || CYGHWR_HAL_POWERPC_PPC4XX == "405EP" } + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial 16x5x device drivers for the + PowerPC PPC405GP/EP based platforms." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 1" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/powerpc_ppc405_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_powerpc_ppc405.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL0 { + display "PowerPC PPC405GP/EP serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + PowerPC PPC405GP port 0." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_PPC405_SERIAL0_NAME { + display "Device name for PowerPC PPC405GP/EP serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device + for the PowerPC PPC405GP port 0." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BAUD { + display "Baud rate for the PowerPC PPC405GP serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 115200 + description " + This option specifies the default baud rate (speed) + for the PowerPC PPC405GP port 0." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BUFSIZE { + display "Buffer size for the PowerPC PPC405GP serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal + buffers used for the PowerPC PPC405GP port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL1 { + display "PowerPC PPC405GP serial port 1 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description " + This option includes the serial device driver for the + PowerPC PPC405GP port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_PPC405_SERIAL1_NAME { + display "Device name for PowerPC PPC405GP serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of the serial device + for the PowerPC PPC405GP port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BAUD { + display "Baud rate for the PowerPC PPC405GP serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 + 3600 4800 7200 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 115200 + description " + This option specifies the default baud rate (speed) + for the PowerPC PPC405GP port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BUFSIZE { + display "Buffer size for the PowerPC PPC405GP serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal + buffers used for the PowerPC PPC405GP/EP port 1." + } + } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_PPC405_TESTING { + display "Testing parameters" + flavor bool + default_value 1 + no_define + active_if { CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL1 } + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_POWERPC_PPC405_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"PPC405GP\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } + +} + +# EOF ser_powerpc_ppc405.cdl diff --git a/ecos/packages/devs/serial/powerpc/ppc405/current/include/powerpc_ppc405_ser.inl b/ecos/packages/devs/serial/powerpc/ppc405/current/include/powerpc_ppc405_ser.inl new file mode 100644 index 0000000..b89898b --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/ppc405/current/include/powerpc_ppc405_ser.inl @@ -0,0 +1,175 @@ +//========================================================================== +// +// io/serial/powerpc/powerpc_ppc405_ser.inl +// +// PPC405GP/EP Serial I/O definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: +// Date: 2003-09-16 +// Purpose: PowerPC PPC405GP/EP serial drivers +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_intr.h> +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/ppc_regs.h> + +//----------------------------------------------------------------------------- +// Baud rate specification + +static unsigned int select_baud[] = { + 9999, // Unused -- marker + 50, + 75, + 110, + 134, + 150, + 200, + 300, + 600, + 1200, + 1800, + 2400, + 3600, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400 +}; + +externC int cyg_var_baud_generator(int baud); +#define CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR cyg_var_baud_generator + +#ifdef CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL0 +#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP) +static pc_serial_info ppc405_serial_info0 = {_PPC405GP_UART0, CYGNUM_HAL_INTERRUPT_UART0}; +#endif +#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405EP) +static pc_serial_info ppc405_serial_info0 = {_PPC405EP_UART0, CYGNUM_HAL_INTERRUPT_UART0}; +#endif +#if CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BUFSIZE > 0 +static unsigned char ppc405_serial_out_buf0[CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BUFSIZE]; +static unsigned char ppc405_serial_in_buf0[CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(ppc405_serial_channel0, + pc_serial_funs, + ppc405_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &ppc405_serial_out_buf0[0], sizeof(ppc405_serial_out_buf0), + &ppc405_serial_in_buf0[0], sizeof(ppc405_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(ppc405_serial_channel0, + pc_serial_funs, + ppc405_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(ppc405_serial_io0, + CYGDAT_IO_SERIAL_POWERPC_PPC405_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &ppc405_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL1 +#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP) +static pc_serial_info ppc405_serial_info1 = {_PPC405GP_UART1, CYGNUM_HAL_INTERRUPT_UART1}; +#endif +#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405EP) +static pc_serial_info ppc405_serial_info1 = {_PPC405EP_UART1, CYGNUM_HAL_INTERRUPT_UART1}; +#endif +#if CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BUFSIZE > 0 +static unsigned char ppc405_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BUFSIZE]; +static unsigned char ppc405_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(ppc405_serial_channel1, + pc_serial_funs, + ppc405_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &ppc405_serial_out_buf1[0], sizeof(ppc405_serial_out_buf1), + &ppc405_serial_in_buf1[0], sizeof(ppc405_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(ppc405_serial_channel1, + pc_serial_funs, + ppc405_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_PPC405_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(ppc405_serial_io1, + CYGDAT_IO_SERIAL_POWERPC_PPC405_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &ppc405_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_PPC405_SERIAL1 + +// EOF powerpc_ppc405_ser.inl diff --git a/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog b/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog new file mode 100644 index 0000000..fea1a1a --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog @@ -0,0 +1,1285 @@ +2010-12-06 Mark Retallack <mark.retallack@siemens.com> + + * src/quicc_smc_serial.c: Wait for CPM Busy Flag to clear on write to + CP Command Register + +2006-01-27 Will Wagner <willw@carallon.com> + + * src/quicc_smc_serial.h: Removed unused structure + * src/quicc_smc_serial.c(quicc_smc_serial_config_port): Corrected CLEN in SMCMR + * src/quicc_smc_serial.c(quicc_smc_serial_DSR & quicc_scc_serial_DSR): Better handling of frame and parity errors + +2004-05-10 Robert Chenault <robertchenault@yahoo.com> + + * src/quicc_smc_serial.h: Added two casts of (int) on + calculations involving CYGHWR_HAL_POWERPC_BOARD_SPEED. + +2004-01-24 Philip Soeberg <ecos@soeberg.net> + + * src/quicc_smc_serial.c(quicc_sxx_serial_init): SCC3 support + for MPC8XX_823. + +2003-10-13 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.c: Add some I/O barriers to make sure that + operations happen in the correct order. Fixes BUG #90391 + +2003-10-08 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.c: Fix compile error for Adder-II (852T) + +2003-09-08 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.h: Fix baud rate clock setup - was off by 1. + Reported by Tord Andersson <Tord.Andersson@combitechsystems.com> + +2003-03-31 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.c (quicc_sxx_serial_init): Handle SCC3 on + various processors (signal routing differs). + +2003-03-28 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.c: Change how buffers are allocated & aligned + to a cache line - previous attempt wasted a huge amount of space. + +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.h: Move common definitions to common + include file (in HAL). + + * src/quicc_smc_serial.c: + * cdl/ser_quicc_smc.cdl: Remove options for baud rate generator + assignment - use more generic [automatic] support. + +2003-03-17 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.h: + * src/quicc_smc_serial.c: + * cdl/ser_quicc_smc.cdl: Add support for SCC1/SCC2/SCC3. Inspired + by Paul Randall <prandall@delta-info.com> + +2003-03-05 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc_serial.c: Use common routines to manage CPM/DPRAM + pointers - much nicer in a multi-driver environment. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_quicc_smc.cdl: Remove irrelevant doc link. + +2002-12-10 Gary Thomas <gthomas@ecoscentric.com> + + * cdl/ser_quicc_smc.cdl: Only enable devices which exist - as described + by the HAL/CDL interfaces. + +2001-11-30 Jonathan Larmour <jlarmour@redhat.com> +2001-11-29 Christoph Csebits <christoph.csebits@frequentis.com> + + * src/quicc_smc_serial.c: + aligning buffer to cache lines, + flushing buffer in cache before flushing the device. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_quicc_smc.cdl: + Fix 234000->230400 typo. + +2000-12-22 Björn Stenberg <bjorn@haxx.se> + + * src/quicc_smc_serial.c (quicc_smc_serial_init_info): + Set quicc going only after most of the other initialization is + complete - otherwise initializing too early causes some of the + parameters not to be initialized properly. + +2000-12-13 Daniel Lind <daniel.lind@sth.frontec.se> + + * src/quicc_smc_serial.c (quicc_smc_serial_flush): + Don't mark a buffer ready unless it has been fully serviced - in + particular, the interrupt bit must be clear. + [2000-12-13] committed by Gary Thomas <gthomas@redhat.com> + +2000-12-06 Jonathan Larmour <jlarmour@redhat.com> + + * src/quicc_smc_serial.c: Remove unread tx_enabled variable from + quicc_smc_serial_info + Ensure quicc serial interrupt is unmasked in general so that rx works! + (quicc_smc_serial_start_xmit): Protect better from DSR interruption + +2000-10-24 Jonathan Larmour <jlarmour@redhat.com> + + * src/quicc_smc_serial.c (quicc_smc_serial_ISR): Return with + CYG_ISR_HANDLED (reported by Daniel Lind) + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/quicc_smc_serial.c (quicc_smc_serial_set_config): Now use keys + to make more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_quicc_smc.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl b/ecos/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl new file mode 100644 index 0000000..61867cc --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl @@ -0,0 +1,512 @@ +# ==================================================================== +# +# ser_quicc_smc.cdl +# +# eCos serial PowerPC/QUICC SMC/SCC configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC { + display "PowerPC QUICC/SMC serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_QUICC + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + PowerPC QUICC/SMC/SCC." + + compile -library=libextras.a quicc_smc_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_quicc_smc.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 { + display "PowerPC QUICC/SMC serial port 1 driver" + flavor bool + active_if CYGNUM_HAL_QUICC_SMC1 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC/SMC port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME { + display "Device name for PowerPC QUICC/SMC serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the PowerPC + QUICC/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD { + display "Baud rate for the PowerPC QUICC/SMC serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SMC serial port 1" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SMC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SMC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SMC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SMC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM { + display "Number of input buffers for the PowerPC QUICC/SMC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SMC port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 { + display "PowerPC QUICC/SMC serial port 2 driver" + flavor bool + active_if CYGNUM_HAL_QUICC_SMC2 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC/SMC port 2." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME { + display "Device name for PowerPC QUICC/SMC serial port 2" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the PowerPC + QUICC/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD { + display "Baud rate for the PowerPC QUICC/SMC serial port 2" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SMC serial port 2" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SMC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SMC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SMC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SMC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM { + display "Number of output buffers for the PowerPC QUICC/SMC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SMC port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1 { + display "PowerPC QUICC/SCC serial port 1 driver" + flavor bool + active_if CYGNUM_HAL_QUICC_SCC1 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC/SCC port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_NAME { + display "Device name for PowerPC QUICC/SCC serial port 1" + flavor data + default_value {"\"/dev/scc1\""} + description " + This option specifies the device name for the PowerPC + QUICC/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BAUD { + display "Baud rate for the PowerPC QUICC/SCC serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SCC serial port 1" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM { + display "Number of input buffers for the PowerPC QUICC/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SCC port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC2 { + display "PowerPC QUICC/SCC serial port 2 driver" + flavor bool + active_if CYGNUM_HAL_QUICC_SCC2 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC/SCC port 2." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_NAME { + display "Device name for PowerPC QUICC/SCC serial port 2" + flavor data + default_value {"\"/dev/scc2\""} + description " + This option specifies the device name for the PowerPC + QUICC/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BAUD { + display "Baud rate for the PowerPC QUICC/SCC serial port 2" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SCC serial port 2" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM { + display "Number of input buffers for the PowerPC QUICC/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SCC port 2." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC3 { + display "PowerPC QUICC/SCC serial port 3 driver" + flavor bool + active_if CYGNUM_HAL_QUICC_SCC3 + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC/SCC port 3." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME { + display "Device name for PowerPC QUICC/SCC serial port 3" + flavor data + default_value {"\"/dev/scc3\""} + description " + This option specifies the device name for the PowerPC + QUICC/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BAUD { + display "Baud rate for the PowerPC QUICC/SCC serial port 3" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SCC serial port 3" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SCC serial port 3" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SCC serial port 3" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SCC serial port 3" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SCC port 3." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM { + display "Number of input buffers for the PowerPC QUICC/SCC serial port 3" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SCC port 3." + } +} + +# EOF ser_quicc_smc.cdl diff --git a/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c b/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c new file mode 100644 index 0000000..c327849 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c @@ -0,0 +1,1122 @@ +//========================================================================== +// +// io/serial/powerpc/quicc_smc_serial.c +// +// PowerPC QUICC (SMC/SCC) Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-20 +// Purpose: QUICC SMC Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/quicc/ppc8xx.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC + +#include "quicc_smc_serial.h" + +typedef struct quicc_sxx_serial_info { + CYG_ADDRWORD channel; // Which channel SMCx/SCCx + short int_num; // Interrupt number + short type; // Channel type - SCC or SMC + unsigned long *brg; // Which baud rate generator + void *pram; // Parameter RAM pointer + void *ctl; // SMC/SCC control registers + volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use + struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor + int txsize, rxsize; // Length of individual buffers + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} quicc_sxx_serial_info; + +static bool quicc_sxx_serial_init(struct cyg_devtab_entry *tab); +static bool quicc_sxx_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo quicc_sxx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char quicc_sxx_serial_getc(serial_channel *chan); +static Cyg_ErrNo quicc_sxx_serial_set_config(serial_channel *chan, + cyg_uint32 key, const void *xbuf, + cyg_uint32 *len); +static void quicc_sxx_serial_start_xmit(serial_channel *chan); +static void quicc_sxx_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 quicc_sxx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void quicc_sxx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(quicc_sxx_serial_funs, + quicc_sxx_serial_putc, + quicc_sxx_serial_getc, + quicc_sxx_serial_set_config, + quicc_sxx_serial_start_xmit, + quicc_sxx_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 +static quicc_sxx_serial_info quicc_sxx_serial_info_smc1 = { + QUICC_CPM_SMC1, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SMC1, // interrupt + _SMC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf_smc1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf_smc1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_sxx_serial_channel_smc1, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_smc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf_smc1[0], sizeof(quicc_smc_serial_out_buf_smc1), + &quicc_smc_serial_in_buf_smc1[0], sizeof(quicc_smc_serial_in_buf_smc1) + ); +#else +static SERIAL_CHANNEL(quicc_sxx_serial_channel_smc1, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_smc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(quicc_smc_serial_io_smc1, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc_sxx_serial_init, + quicc_sxx_serial_lookup, // Serial driver may need initializing + &quicc_sxx_serial_channel_smc1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 +static quicc_sxx_serial_info quicc_sxx_serial_info_smc2 = { + QUICC_CPM_SMC2, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP, // interrupt + _SMC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf_smc2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf_smc2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_sxx_serial_channel_smc2, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_smc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf_smc2[0], sizeof(quicc_smc_serial_out_buf_smc2), + &quicc_smc_serial_in_buf_smc2[0], sizeof(quicc_smc_serial_in_buf_smc2) + ); +#else +static SERIAL_CHANNEL(quicc_sxx_serial_channel_smc2, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_smc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(quicc_smc_serial_io_smc2, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc_sxx_serial_init, + quicc_sxx_serial_lookup, // Serial driver may need initializing + &quicc_sxx_serial_channel_smc2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1 +static quicc_sxx_serial_info quicc_sxx_serial_info_scc1 = { + QUICC_CPM_SCC1, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SCC1, // interrupt + _SCC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf_scc1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf_scc1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_sxx_serial_channel_scc1, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_scc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf_scc1[0], sizeof(quicc_smc_serial_out_buf_scc1), + &quicc_smc_serial_in_buf_scc1[0], sizeof(quicc_smc_serial_in_buf_scc1) + ); +#else +static SERIAL_CHANNEL(quicc_sxx_serial_channel_scc1, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_scc1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(quicc_smc_serial_io_scc1, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc_sxx_serial_init, + quicc_sxx_serial_lookup, // Serial driver may need initializing + &quicc_sxx_serial_channel_scc1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC2 +static quicc_sxx_serial_info quicc_sxx_serial_info_scc2 = { + QUICC_CPM_SCC2, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SCC2, // interrupt + _SCC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf_scc2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf_scc2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_sxx_serial_channel_scc2, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_scc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf_scc2[0], sizeof(quicc_smc_serial_out_buf_scc2), + &quicc_smc_serial_in_buf_scc2[0], sizeof(quicc_smc_serial_in_buf_scc2) + ); +#else +static SERIAL_CHANNEL(quicc_sxx_serial_channel_scc2, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_scc2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(quicc_smc_serial_io_scc2, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc_sxx_serial_init, + quicc_sxx_serial_lookup, // Serial driver may need initializing + &quicc_sxx_serial_channel_scc2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC2 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC3 +static quicc_sxx_serial_info quicc_sxx_serial_info_scc3 = { + QUICC_CPM_SCC3, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SCC3, // interrupt + _SCC_CHAN +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf_scc3[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf_scc3[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_sxx_serial_channel_scc3, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_scc3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf_scc3[0], sizeof(quicc_smc_serial_out_buf_scc3), + &quicc_smc_serial_in_buf_scc3[0], sizeof(quicc_smc_serial_in_buf_scc3) + ); +#else +static SERIAL_CHANNEL(quicc_sxx_serial_channel_scc3, + quicc_sxx_serial_funs, + quicc_sxx_serial_info_scc3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); + +DEVTAB_ENTRY(quicc_smc_serial_io_scc3, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc_sxx_serial_init, + quicc_sxx_serial_lookup, // Serial driver may need initializing + &quicc_sxx_serial_channel_scc3 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC3 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +quicc_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + unsigned int baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr; + EPPC *eppc = eppc_base(); + volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl; + + if (baud_divisor == 0) return false; + // Stop transmitter while changing baud rate + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; + HAL_IO_BARRIER(); // Inforce I/O ordering + // Disable channel during setup + ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode + HAL_IO_BARRIER(); // Inforce I/O ordering + // Disable port interrupts while changing hardware + _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) | + smc_select_stop_bits[new_config->stop] | + smc_select_parity[new_config->parity]; + HAL_IO_BARRIER(); // Inforce I/O ordering + // Set baud rate generator + *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); + + // Enable channel with new configuration + ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr; + HAL_IO_BARRIER(); // Inforce I/O ordering + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +quicc_smc_serial_init_info(quicc_sxx_serial_info *smc_chan, + volatile struct smc_uart_pram *uart_pram, + volatile struct smc_regs *ctl, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF, + int portBmask, + int port) +{ + EPPC *eppc = eppc_base(); + struct cp_bufdesc *txbd, *rxbd; + int i; + + smc_chan->pram = (void *)uart_pram; + smc_chan->ctl = (void *)ctl; + + // Set up baud rate generator + smc_chan->brg = _mpc8xx_allocate_brg(port); + + // Disable channel during setup + ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode + + /* + * Set up the PortB pins for UART operation. + * Set PAR and DIR to allow SMCTXDx and SMRXDx + * (Table 16-39) + */ + eppc->pip_pbpar |= portBmask; + eppc->pip_pbdir &= ~portBmask; + /* + * SDMA & LCD bus request level 5 + * (Section 16.10.2.1) + */ + eppc->dma_sdcr = 1; + /* + * Set Rx and Tx function code + * (Section 16.15.4.2) + */ + uart_pram->rfcr = 0x18; + uart_pram->tfcr = 0x18; + /* + * Set pointers to buffer descriptors. + * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) + */ + uart_pram->rbase = RxBD; + uart_pram->tbase = TxBD; + /* tx and rx buffer descriptors */ + txbd = (struct cp_bufdesc *)((char *)eppc + TxBD); + rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD); + smc_chan->txbd = txbd; + smc_chan->tbase = txbd; + smc_chan->txsize = TxSIZE; + smc_chan->rxbd = rxbd; + smc_chan->rbase = rxbd; + smc_chan->rxsize = RxSIZE; + /* max receive buffer length */ + uart_pram->mrblr = RxSIZE; + /* set max_idle feature - generate interrupt after 4 chars idle period */ + uart_pram->max_idl = 4; + /* no last brk char received */ + uart_pram->brkln = 0; + /* no break condition occurred */ + uart_pram->brkec = 0; + /* 1 break char sent on top XMIT */ + uart_pram->brkcr = 1; + /* setup RX buffer descriptors */ + for (i = 0; i < RxNUM; i++) { + rxbd->length = 0; + rxbd->buffer = RxBUF; + rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int; + if (i == (RxNUM-1)) rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer + RxBUF += RxSIZE; + rxbd++; + } + /* setup TX buffer descriptors */ + for (i = 0; i < TxNUM; i++) { + txbd->length = 0; + txbd->buffer = TxBUF; + txbd->ctrl = 0; + if (i == (TxNUM-1)) txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer + TxBUF += TxSIZE; + txbd++; + } + /* + * Reset Rx & Tx params + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; + HAL_IO_BARRIER(); // Inforce I/O ordering + /* + * Clear any previous events. Enable interrupts. + * (Section 16.15.7.14 and 16.15.7.15) + */ + ctl->smc_smce = 0xFF; + ctl->smc_smcm = QUICC_SMCE_BSY|QUICC_SMCE_TX|QUICC_SMCE_RX; +} + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +quicc_scc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + quicc_sxx_serial_info *scc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + unsigned int baud_divisor = select_baud[new_config->baud]; + EPPC *eppc = eppc_base(); + volatile struct scc_regs *regs = (volatile struct scc_regs *)scc_chan->ctl; + + if (baud_divisor == 0) return false; + // Set baud rate generator + *scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); + // Disable channel during setup + HAL_IO_BARRIER(); // Inforce I/O ordering + regs->scc_gsmr_l = 0; + regs->scc_psmr = QUICC_SCC_PSMR_ASYNC | + scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + scc_select_stop_bits[new_config->stop] | + scc_select_parity[new_config->parity]; + + // Enable channel with new configuration + regs->scc_gsmr_h = 0x20; // 8bit FIFO + regs->scc_gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART + + /* + * Init Rx & Tx params for SCCX + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY; + while (eppc->cp_cr & QUICC_CPM_CR_BUSY ) + continue; + HAL_IO_BARRIER(); // Inforce I/O ordering + regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +quicc_scc_serial_init_info(quicc_sxx_serial_info *scc_chan, + volatile struct uart_pram *uart_pram, + volatile struct scc_regs *ctl, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF, + int portAmask, int portBmask, int portCmask, + int port) +{ + EPPC *eppc = eppc_base(); + struct cp_bufdesc *txbd, *rxbd; + int i; + + // Disable channel during setup + ctl->scc_gsmr_l = 0; + scc_chan->pram = (void *)uart_pram; + scc_chan->ctl = (void *)ctl; + + // Set up baud rate generator + scc_chan->brg = _mpc8xx_allocate_brg(port); + + /* + * Set up the PortA/B/C pins for UART operation. + */ + eppc->pio_papar |= portAmask; + eppc->pio_padir &= ~portAmask; + eppc->pio_paodr &= ~portAmask; + + eppc->pio_pcdir &= portCmask; + eppc->pio_pcpar &= portCmask; + eppc->pio_pcso |= portCmask; + + eppc->pip_pbpar |= portBmask; + eppc->pip_pbdir |= portBmask; + + /* + * SDMA & LCD bus request level 5 + * (Section 16.10.2.1) + */ + eppc->dma_sdcr = 1; + /* + * Set Rx and Tx function code + * (Section 16.15.4.2) + */ + uart_pram->rfcr = 0x18; + uart_pram->tfcr = 0x18; + /* + * Set pointers to buffer descriptors. + * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) + */ + uart_pram->rbase = RxBD; + uart_pram->tbase = TxBD; + /* tx and rx buffer descriptors */ + txbd = (struct cp_bufdesc *)((char *)eppc + TxBD); + rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD); + scc_chan->txbd = txbd; + scc_chan->tbase = txbd; + scc_chan->txsize = TxSIZE; + scc_chan->rxbd = rxbd; + scc_chan->rbase = rxbd; + scc_chan->rxsize = RxSIZE; + /* max receive buffer length */ + uart_pram->mrblr = RxSIZE; + /* set max_idle feature - generate interrupt after 4 chars idle period */ + uart_pram->max_idl = 4; + /* no last brk char received */ + uart_pram->brkln = 0; + /* no break condition occurred */ + uart_pram->brkec = 0; + /* 1 break char sent on top XMIT */ + uart_pram->brkcr = 1; + /* character mask */ + uart_pram->rccm = 0xC0FF; + /* control characters */ + for (i = 0; i < 8; i++) { + uart_pram->cc[i] = 0x8000; // Mark unused + } + /* setup RX buffer descriptors */ + for (i = 0; i < RxNUM; i++) { + rxbd->length = 0; + rxbd->buffer = RxBUF; + rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int; + if (i == (RxNUM-1)) rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer + RxBUF += RxSIZE; + rxbd++; + } + /* setup TX buffer descriptors */ + for (i = 0; i < TxNUM; i++) { + txbd->length = 0; + txbd->buffer = TxBUF; + txbd->ctrl = 0; + if (i == (TxNUM-1)) txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer + TxBUF += TxSIZE; + txbd++; + } + /* + * Reset Rx & Tx params + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; + /* + * Clear any previous events. Enable interrupts. + * (Section 16.15.7.14 and 16.15.7.15) + */ + HAL_IO_BARRIER(); // Inforce I/O ordering + ctl->scc_scce = 0xFFFF; + ctl->scc_sccm = (QUICC_SCCE_BSY | QUICC_SCCE_TX | QUICC_SCCE_RX); +} + +// Function to initialize the device. Called at bootstrap time. +static bool +quicc_sxx_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + volatile EPPC *eppc = (volatile EPPC *)eppc_base(); + int TxBD, RxBD; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); +#ifdef CYGDBG_IO_INIT + diag_printf("QUICC_SMC SERIAL init - dev: %x.%d = %s\n", smc_chan->channel, smc_chan->int_num, tab->name); +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + if (chan == &quicc_sxx_serial_channel_smc1) { + TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM); + RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM); + quicc_smc_serial_init_info(&quicc_sxx_serial_info_smc1, + &eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM + &eppc->smc_regs[0], // Control registers + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE, + &quicc_smc1_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE, + &quicc_smc1_rxbuf[0], + 0xC0, // PortB mask + QUICC_CPM_SMC1 + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + if (chan == &quicc_sxx_serial_channel_smc2) { + TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM); + RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM); + quicc_smc_serial_init_info(&quicc_sxx_serial_info_smc2, + &eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM + &eppc->smc_regs[1], // Control registers + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE, + &quicc_smc2_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE, + &quicc_smc2_rxbuf[0], + 0xC00, // PortB mask + QUICC_CPM_SMC2 + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1 + if (chan == &quicc_sxx_serial_channel_scc1) { + TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM); + RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM); + quicc_scc_serial_init_info(&quicc_sxx_serial_info_scc1, + &eppc->pram[0].scc.pscc.u, // PRAM + &eppc->scc_regs[0], // Control registersn + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE, + &quicc_scc1_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE, + &quicc_scc1_rxbuf[0], + 0x0003, // PortA mask + 0x1000, // PortB mask + 0x0800, // PortC mask + QUICC_CPM_SCC1 + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC2 + if (chan == &quicc_sxx_serial_channel_scc2) { + TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM); + RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM); + quicc_scc_serial_init_info(&quicc_sxx_serial_info_scc2, + &eppc->pram[1].scc.pscc.u, // PRAM + &eppc->scc_regs[1], // Control registersn + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE, + &quicc_scc2_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE, + &quicc_scc2_rxbuf[0], + 0x000C, // PortA mask + 0x2000, // PortB mask + 0x0C00, // PortC mask + QUICC_CPM_SCC2 + ); + } +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC3 + if (chan == &quicc_sxx_serial_channel_scc3) { + TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM); + RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM); + quicc_scc_serial_init_info(&quicc_sxx_serial_info_scc3, + &eppc->pram[2].scc.pscc.u, // PRAM + &eppc->scc_regs[2], // Control registersn + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE, + &quicc_scc3_txbuf[0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE, + &quicc_scc3_rxbuf[0], +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_850) + 0x0000, // PortA mask + 0x00C0, // PortB mask + 0x0000, // PortC mask +#elif defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) + 0x0030, // PortA mask + 0x0000, // PortB mask + 0x0000, // PortC mask +#elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) + 0x0000, // PortA mask + 0x00C0, // PortB mask + 0x0000, // PortC mask +#else +#error "Cannot route SCC3" +#endif + QUICC_CPM_SCC3 + ); + } +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(smc_chan->int_num, + CYGARC_SIU_PRIORITY_HIGH, // Priority - unused (but asserted) + (cyg_addrword_t)chan, // Data item passed to interrupt handler + quicc_sxx_serial_ISR, + quicc_sxx_serial_DSR, + &smc_chan->serial_interrupt_handle, + &smc_chan->serial_interrupt); + cyg_drv_interrupt_attach(smc_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(smc_chan->int_num); + } + if (smc_chan->type == _SMC_CHAN) { + quicc_smc_serial_config_port(chan, &chan->config, true); + } else { + quicc_scc_serial_config_port(chan, &chan->config, true); + } + if (cache_state) + HAL_DCACHE_ENABLE(); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +quicc_sxx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Force the current transmit buffer to be sent +static void +quicc_sxx_serial_flush(quicc_sxx_serial_info *smc_chan) +{ + volatile struct cp_bufdesc *txbd = smc_chan->txbd; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_FLUSH(txbd->buffer, smc_chan->txsize); + } + if ((txbd->length > 0) && + ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0)) { + txbd->ctrl |= QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int; // Signal buffer ready + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + } else { + txbd++; + } + smc_chan->txbd = txbd; + } +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +quicc_sxx_serial_putc(serial_channel *chan, unsigned char c) +{ + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + volatile struct cp_bufdesc *txbd, *txfirst; + volatile struct smc_uart_pram *pram = (volatile struct smc_uart_pram *)smc_chan->pram; + EPPC *eppc = eppc_base(); + bool res; + + cyg_drv_dsr_lock(); // Avoid race condition testing pointers + txbd = (struct cp_bufdesc *)((char *)eppc + pram->tbptr); + txfirst = txbd; + // Scan for a non-busy buffer + while (txbd->ctrl & QUICC_BD_CTL_Ready) { + // This buffer is busy, move to next one + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + } else { + txbd++; + } + if (txbd == txfirst) break; // Went all the way around + } + smc_chan->txbd = txbd; + if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0) { + // Transmit buffer is not full/busy + txbd->buffer[txbd->length++] = c; + if (txbd->length == smc_chan->txsize) { + // This buffer is now full, tell SMC to start processing it + quicc_sxx_serial_flush(smc_chan); + } + res = true; + } else { + // No space + res = false; + } + cyg_drv_dsr_unlock(); + return res; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +quicc_sxx_serial_getc(serial_channel *chan) +{ + unsigned char c; + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + + while ((rxbd->ctrl & QUICC_BD_CTL_Ready) != 0) ; + c = rxbd->buffer[0]; + rxbd->length = smc_chan->rxsize; + rxbd->ctrl |= QUICC_BD_CTL_Ready; + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +quicc_sxx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + int res; + + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + // FIXME - The documentation says that you can't change the baud rate + // again until at least two BRG input clocks have occurred. + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if (smc_chan->type == _SMC_CHAN) { + res = quicc_smc_serial_config_port(chan, config, true); + } else { + res = quicc_scc_serial_config_port(chan, config, true); + } + if ( true != res ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +quicc_sxx_serial_start_xmit(serial_channel *chan) +{ + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + cyg_drv_dsr_lock(); + if (smc_chan->txbd->length == 0) { + // See if there is anything to put in this buffer, just to get it going + (chan->callbacks->xmt_char)(chan); + } + if (smc_chan->txbd->length != 0) { + // Make sure it gets started + quicc_sxx_serial_flush(smc_chan); + } + cyg_drv_dsr_unlock(); +} + +// Disable the transmitter on the device +static void +quicc_sxx_serial_stop_xmit(serial_channel *chan) +{ + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + // If anything is in the last buffer, need to get it started + if (smc_chan->txbd->length != 0) { + quicc_sxx_serial_flush(smc_chan); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +quicc_sxx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(smc_chan->int_num); + return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +quicc_smc_serial_DSR(serial_channel *chan) +{ + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl; + volatile struct cp_bufdesc *txbd; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + volatile struct smc_uart_pram *pram = (volatile struct smc_uart_pram *)smc_chan->pram; + struct cp_bufdesc *rxlast; + int i, cache_state; + + if (ctl->smc_smce & QUICC_SMCE_TX) { + // Transmit interrupt + ctl->smc_smce = QUICC_SMCE_TX; // Reset interrupt state; + txbd = smc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) { + txbd->length = 0; + txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset interrupt bit + } + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + while (ctl->smc_smce & QUICC_SMCE_RX) { + // Receive interrupt + ctl->smc_smce = QUICC_SMCE_RX; // Reset interrupt state; + rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr); + while (rxbd != rxlast) { + if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) { + if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) { + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + } else { + // is this necessary? + rxbd->ctrl &= QUICC_BD_CTL_MASK; + // should we report the error? + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data + } + rxbd->length = 0; + rxbd->ctrl |= QUICC_BD_CTL_Ready; + } + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + } + if (ctl->smc_smce & QUICC_SMCE_BSY) { + ctl->smc_smce = QUICC_SMCE_BSY; // Reset interrupt state; + } + cyg_drv_interrupt_acknowledge(smc_chan->int_num); + cyg_drv_interrupt_unmask(smc_chan->int_num); +} + +static void +quicc_scc_serial_DSR(serial_channel *chan) +{ + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + volatile struct scc_regs *ctl = (volatile struct scc_regs *)smc_chan->ctl; + volatile struct cp_bufdesc *txbd; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + volatile struct uart_pram *pram = (volatile struct uart_pram *)smc_chan->pram; + struct cp_bufdesc *rxlast; + int i, cache_state; + + if (ctl->scc_scce & QUICC_SCCE_TX) { + // Transmit interrupt + ctl->scc_scce = QUICC_SCCE_TX; // Reset interrupt state; + txbd = smc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) { + txbd->length = 0; + txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset interrupt bit + } + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + while (ctl->scc_scce & QUICC_SCCE_RX) { + // Receive interrupt + ctl->scc_scce = QUICC_SCCE_RX; // Reset interrupt state; + rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr); + while (rxbd != rxlast) { + if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) { + if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) { + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + } else { + // is this necessary? + rxbd->ctrl &= QUICC_BD_CTL_MASK; + // should we report the error? + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data + } + rxbd->length = 0; + rxbd->ctrl |= QUICC_BD_CTL_Ready; + } + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + } + if (ctl->scc_scce & QUICC_SCCE_BSY) { + ctl->scc_scce = QUICC_SCCE_BSY; // Reset interrupt state; + } + cyg_drv_interrupt_acknowledge(smc_chan->int_num); + cyg_drv_interrupt_unmask(smc_chan->int_num); +} + +static void +quicc_sxx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + + if (smc_chan->type == _SMC_CHAN) { + quicc_smc_serial_DSR(chan); + } else { + quicc_scc_serial_DSR(chan); + } +} + +void +show_rxbd(int dump_all) +{ +#ifdef CYGDBG_DIAG_BUF + EPPC *eppc = eppc_base(); + struct smc_uart_pram *pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u; + struct cp_bufdesc *rxbd = (struct cp_bufdesc *)((char *)eppc+pram->rbase); + int _enable = enable_diag_uart; + enable_diag_uart = 0; +#if 1 + diag_printf("SMC Mask: %x, Events: %x, Rbase: %x, Rbptr: %x\n", + eppc->smc_regs[0].smc_smcm, eppc->smc_regs[0].smc_smce, + pram->rbase, pram->rbptr); + while (true) { + diag_printf("Rx BD: %x, ctl: %x, length: %d\n", rxbd, rxbd->ctrl, rxbd->length); + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) break; + rxbd++; + } +#endif + enable_diag_uart = _enable; + if (dump_all) dump_diag_buf(); +#endif // CYGDBG_DIAG_BUF +} +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC + +// ------------------------------------------------------------------------ +// EOF powerpc/quicc_smc_serial.c diff --git a/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h b/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h new file mode 100644 index 0000000..63b0d52 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h @@ -0,0 +1,131 @@ +#ifndef CYGONCE_POWERPC_QUICC_SMC_SERIAL_H +#define CYGONCE_POWERPC_QUICC_SMC_SERIAL_H + +// ==================================================================== +// +// quicc_smc_serial.h +// +// Device I/O - Description of PowerPC QUICC/SMC serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-21 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports using QUICC/SMC + +#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions + +static unsigned int smc_select_stop_bits[] = { + 0, + QUICC_SMCMR_SB(1), // 1 stop bit + QUICC_SMCMR_SB(1), // 1.5 stop bit + QUICC_SMCMR_SB(2) // 2 stop bits +}; + +static unsigned int smc_select_parity[] = { + QUICC_SMCMR_PE(0), // No parity + QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(1), // Even parity + QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(0), // Odd parity + 0, // Mark parity + 0, // Space parity +}; + +static unsigned int scc_select_word_length[] = { + QUICC_SCC_PSMR_CLEN(5), // 5 bits / word (char) + QUICC_SCC_PSMR_CLEN(6), + QUICC_SCC_PSMR_CLEN(7), + QUICC_SCC_PSMR_CLEN(8) +}; + +static unsigned int scc_select_stop_bits[] = { + QUICC_SCC_PSMR_SB(1), // 0.5 stop bit ?? + QUICC_SCC_PSMR_SB(1), // 1 stop bit + QUICC_SCC_PSMR_SB(2), // 1.5 stop bit + QUICC_SCC_PSMR_SB(2) // 2 stop bits +}; + + +static unsigned int scc_select_parity[] = { + QUICC_SCC_PSMR_PE(0), // No parity + QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(2)|QUICC_SCC_PSMR_RPM(2), // Even parity + QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(0)|QUICC_SCC_PSMR_RPM(0), // Odd parity + QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(3)|QUICC_SCC_PSMR_RPM(3), // High (mark) parity + QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(1)|QUICC_SCC_PSMR_RPM(1), // Low (space) parity +}; + +// Baud rate values, based on board clock + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 0, // 230400 +}; + +#define UART_BITRATE(n) ((((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n)-1) +#define UART_SLOW_BITRATE(n) ((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/n)) + +// Channel type select +#define _SCC_CHAN 0 +#define _SMC_CHAN 1 + +#endif // CYGONCE_POWERPC_QUICC_SMC_SERIAL_H diff --git a/ecos/packages/devs/serial/powerpc/quicc2/current/ChangeLog b/ecos/packages/devs/serial/powerpc/quicc2/current/ChangeLog new file mode 100644 index 0000000..6aeb529 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc2/current/ChangeLog @@ -0,0 +1,45 @@ +2003-09-08 Gary Thomas <gary@mlbassoc.com> + + * src/quicc2_scc_serial.h: Fix baud rate clock setup - was off by 1. + Reported by Tord Andersson <Tord.Andersson@combitechsystems.com> + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_quicc2_scc.cdl: Remove irrelevant doc link. + +2003-01-24 Gary Thomas <gary@mlbassoc.com> (inspired by) +2003-01-24 Christoph Csebits <christoph.csebits@frequentis.com> + + * src/quicc2_scc_serial.h: Remove invalid ";" from #defines + +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/quicc2_scc_serial.h: + * src/quicc2_scc_serial.c: + * cdl/ser_quicc2_scc.cdl: New package - serial I/O suport on + PowerPC/QUICC2 based systems (like MPC8260). + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl b/ecos/packages/devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl new file mode 100644 index 0000000..a7d7ac1 --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl @@ -0,0 +1,287 @@ +# ==================================================================== +# +# ser_quicc2_scc.cdl +# +# eCos serial PowerPC/QUICC2 SCC configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): mtek +# Original data: gthomas +# Contributors: +# Date: 2002-02-27 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC { + display "PowerPC QUICC2/SCC serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_POWERPC_MPC8260 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + PowerPC QUICC2/SCC." + + compile -library=libextras.a quicc2_scc_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_quicc2_scc.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 { + display "PowerPC QUICC2/SCC serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC2/SCC port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME { + display "Device name for PowerPC QUICC2/SCC serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the PowerPC + QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD { + display "Baud rate for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE { + display "Buffer size for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BRG { + display "Which baud rate generator to use for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 1 to 4 + default_value 1 + description " + This option specifies which of the four baud rate generators + to use for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE { + display "Output buffer size for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM { + display "Number of output buffers for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE { + display "Input buffer size for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM { + display "Number of input buffers for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC2/SCC port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 { + display "PowerPC QUICC2/SCC serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC2/SCC port 2." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME { + display "Device name for PowerPC QUICC2/SCC serial port 2" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the PowerPC + QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD { + display "Baud rate for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE { + display "Buffer size for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BRG { + display "Which baud rate generator to use for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 1 to 4 + default_value 2 + description " + This option specifies which of the four baud rate generators + to use for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE { + display "Output buffer size for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM { + display "Number of output buffers for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE { + display "Input buffer size for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM { + display "Number of output buffers for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC2/SCC port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_quicc_smc.cdl diff --git a/ecos/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c b/ecos/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c new file mode 100644 index 0000000..8343d2c --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c @@ -0,0 +1,849 @@ +//========================================================================== +// +// io/serial/powerpc/quicc2_scc_serial.c +// +// PowerPC QUICC2 (SCC) Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek +// Contributors: gthomas +// Date: 1999-06-20 +// Purpose: QUICC2 SCC Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/var_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/mpc8260.h> +#include CYGBLD_HAL_PLATFORM_H + +#include "quicc2_scc_serial.h" +#define QUICC2_VADS_IMM_BASE 0x04700000 +#define QUICC2_VADS_BCSR_BASE 0x04500000 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + +static bool +quicc2_scc_serial_init(struct cyg_devtab_entry *tab); +static bool +quicc2_scc_serial_putc(serial_channel *chan, + unsigned char c); +static Cyg_ErrNo +quicc2_scc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char +quicc2_scc_serial_getc(serial_channel *chan); +static Cyg_ErrNo +quicc2_scc_serial_set_config(serial_channel *chan, + cyg_uint32 key, const void *xbuf, + cyg_uint32 *len); +static void +quicc2_scc_serial_start_xmit(serial_channel *chan); +static void +quicc2_scc_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 +quicc2_scc_serial_ISR(cyg_vector_t vector, + cyg_addrword_t data); +static void +quicc2_scc_serial_DSR(cyg_vector_t vector, + cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(quicc2_scc_serial_funs, + quicc2_scc_serial_putc, + quicc2_scc_serial_getc, + quicc2_scc_serial_set_config, + quicc2_scc_serial_start_xmit, + quicc2_scc_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 +static quicc2_scc_serial_info quicc2_scc_serial_info1; + +#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE > 0 +static unsigned char quicc2_scc_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE]; +static unsigned char quicc2_scc_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel1, + quicc2_scc_serial_funs, + quicc2_scc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc2_scc_serial_out_buf1[0], sizeof(quicc2_scc_serial_out_buf1), + &quicc2_scc_serial_in_buf1[0], sizeof(quicc2_scc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(quicc2_scc_serial_channel1, + quicc2_scc_serial_funs, + quicc2_scc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +static unsigned char quicc2_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE + HAL_DCACHE_LINE_SIZE-1]; +static unsigned char quicc2_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE + HAL_DCACHE_LINE_SIZE-1]; + +DEVTAB_ENTRY(quicc2_scc_serial_io1, + CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc2_scc_serial_init, + quicc2_scc_serial_lookup, // Serial driver may need initializing + &quicc2_scc_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 +static quicc2_scc_serial_info quicc2_scc_serial_info2; + +#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE > 0 +static unsigned char quicc2_scc_serial_out_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE]; +static unsigned char quicc2_scc_serial_in_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel2, + quicc2_scc_serial_funs, + quicc2_scc_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc2_scc_serial_out_buf2[0], sizeof(quicc2_scc_serial_out_buf2), + &quicc2_scc_serial_in_buf2[0], sizeof(quicc2_scc_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(quicc2_scc_serial_channel2, + quicc2_scc_serial_funs, + quicc2_scc_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc2_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE + HAL_DCACHE_LINE_SIZE-1]; +static unsigned char quicc2_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE + HAL_DCACHE_LINE_SIZE-1]; + +DEVTAB_ENTRY(quicc2_scc_serial_io2, + CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc2_scc_serial_init, + quicc2_scc_serial_lookup, // Serial driver may need initializing + &quicc2_scc_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + +#ifdef CYGDBG_DIAG_BUF +extern int enable_diag_uart; +#endif // CYGDBG_DIAG_BUF + +// Internal function to actually configure the hardware to +// desired baud rate, stop bits and parity ... +static bool +quicc2_scc_serial_config_port(serial_channel *chan, + cyg_serial_info_t *new_config, + bool init) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; + + unsigned long b_rate = select_baud[new_config->baud]; + + if (b_rate == 0) return false; + + // Stop the transmitter while changing baud rate + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_STOP_TX | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + // Disable Tx, RX and put them in a reset state + scc_chan->scc_regs->gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR); + + // Set the baud rate + *(scc_chan->brg) = (UART_BIT_RATE(b_rate) << 1) | QUICC2_BRG_EN; + + // Set stop bits, word length and parity + scc_chan->scc_regs->psmr = QUICC2_SCC_PSMR_ASYNC | + select_stop_bits[new_config->stop] | + select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_parity[new_config->parity]; + + // Support fractional stop bits + scc_chan->scc_regs->dsr = (new_config->stop & 1) ? QUICC2_SCC_DSR_FULL : QUICC2_SCC_DSR_HALF; + + // Initialize the parameters + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_INIT_TX_RX | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + // Enable Tx and Rx + scc_chan->scc_regs->gsmr_l |= (QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +quicc2_scc_serial_init_info(quicc2_scc_serial_info *scc_chan, + int SCC_index, + int BRG_index, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF) +{ + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; +#ifdef CYGPKG_HAL_POWERPC_VADS + volatile t_BCSR *bcsr = (volatile t_BCSR *) QUICC2_VADS_BCSR_BASE; +#endif + t_UartScc_Pram *uart_pram; + scc_bd *txbd, *rxbd; + int i; + + // Disable the channel, just in case + IMM->scc_regs[SCC_index-1].gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR); + + switch (SCC_index) { + + case 1: + // Put the data into the info structure + scc_chan->scc_cpcr = QUICC2_CPCR_SCC1; + scc_chan->scc_regs = &(IMM->scc_regs[0]); + scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[0]); + scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC1; + + // Set-up the PORT D pins + IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC1_PORTD_PPAR; + IMM->io_regs[PORT_D].psor |= QUICC2_SCC1_PORTD_PDIR; + IMM->io_regs[PORT_D].ppar |= QUICC2_SCC1_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC1_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir |= QUICC2_SCC1_PORTD_PDIR; + IMM->io_regs[PORT_D].podr &= ~QUICC2_SCC1_PORTD_PPAR; + + // Set-up the PORT C pins + IMM->io_regs[PORT_C].psor &= ~QUICC2_SCC1_PORTC_PPAR; + IMM->io_regs[PORT_C].ppar |= QUICC2_SCC1_PORTC_PPAR; + IMM->io_regs[PORT_C].pdir &= ~QUICC2_SCC1_PORTC_PPAR; + IMM->io_regs[PORT_C].podr &= ~QUICC2_SCC1_PORTC_PPAR; + + // Select the baud rate generator and connect it + IMM->cpm_mux_cmxscr &= QUICC2_CMX_SCC1_CLR; + + switch (BRG_index) { + case 1: + scc_chan->brg = &(IMM->brgs_brgc1); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG1; + break; + case 2: + scc_chan->brg = &(IMM->brgs_brgc2); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG2; + break; + case 3: + scc_chan->brg = &(IMM->brgs_brgc3); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG3; + break; + case 4: + scc_chan->brg = &(IMM->brgs_brgc4); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG4; + break; + } +#ifdef CYGPKG_HAL_POWERPC_VADS + // Enable the transciever + bcsr->bcsr1 &= ~(QUICC2_BCSR_EN_SCC1); +#endif + break; + + case 2: + // Put the data into the info structure + scc_chan->scc_cpcr = QUICC2_CPCR_SCC2; + scc_chan->scc_regs = &(IMM->scc_regs[1]); + scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[1]); + scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC2; + + // Set-up the PORT D pins + IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC2_PORTD_PPAR; + IMM->io_regs[PORT_D].ppar |= QUICC2_SCC2_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC2_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir |= QUICC2_SCC2_PORTD_PDIR; + IMM->io_regs[PORT_D].podr &= ~QUICC2_SCC2_PORTD_PPAR; + + // Set-up the PORT C pins + IMM->io_regs[PORT_C].psor &= ~QUICC2_SCC2_PORTC_PPAR; + IMM->io_regs[PORT_C].ppar |= QUICC2_SCC2_PORTC_PPAR; + IMM->io_regs[PORT_C].pdir &= ~QUICC2_SCC2_PORTC_PPAR; + IMM->io_regs[PORT_C].podr &= ~QUICC2_SCC2_PORTC_PPAR; + + // Select the baud rate generator and connect it + IMM->cpm_mux_cmxscr &= QUICC2_CMX_SCC2_CLR; + + switch (BRG_index) { + case 1: + scc_chan->brg = &(IMM->brgs_brgc1); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG1; + break; + case 2: + scc_chan->brg = &(IMM->brgs_brgc2); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG2; + break; + case 3: + scc_chan->brg = &(IMM->brgs_brgc3); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG3; + break; + case 4: + scc_chan->brg = &(IMM->brgs_brgc4); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG4; + break; + } +#ifdef CYGPKG_HAL_POWERPC_VADS + // Enable the transciever + bcsr->bcsr1 &= ~(QUICC2_BCSR_EN_SCC2); +#endif + break; + + default: + diag_printf("Incorrect SCC index in quicc2_scc_serial_init_info \n"); + break; + } + + // Initialize common SCC PRAM + scc_chan->tbase = (scc_bd *) (QUICC2_VADS_IMM_BASE + TxBD); + scc_chan->rbase = (scc_bd *) (QUICC2_VADS_IMM_BASE + RxBD); + scc_chan->txbd = (scc_bd *) (QUICC2_VADS_IMM_BASE + TxBD); + scc_chan->rxbd = (scc_bd *) (QUICC2_VADS_IMM_BASE + RxBD); + scc_chan->txsize = TxSIZE; + scc_chan->rxsize = RxSIZE; + + scc_chan->scc_pram->rbase = RxBD; + scc_chan->scc_pram->tbase = TxBD; + scc_chan->scc_pram->rfcr = 0x10; + scc_chan->scc_pram->tfcr = 0x10; + scc_chan->scc_pram->mrblr = RxSIZE; + + // Initialize UART PRAM + uart_pram = &(scc_chan->scc_pram->SpecificProtocol.u); + + uart_pram->max_idl = 4; + uart_pram->brkcr = 1; + uart_pram->brkln = 0; + uart_pram->parec = 0; + uart_pram->frmec = 0; + uart_pram->nosec = 0; + uart_pram->brkec = 0; + uart_pram->uaddr1 = 0; + uart_pram->uaddr2 = 0; + uart_pram->toseq = 0; + uart_pram->cc[0] = 0x8000; + uart_pram->cc[1] = 0x8000; + uart_pram->cc[2] = 0x8000; + uart_pram->cc[3] = 0x8000; + uart_pram->cc[4] = 0x8000; + uart_pram->cc[5] = 0x8000; + uart_pram->cc[6] = 0x8000; + uart_pram->cc[7] = 0x8000; + uart_pram->rccm = 0xC0FF; + + // Initialize registers + scc_chan->scc_regs->gsmr_l = QUICC2_SCC_GSMR_L_INIT; + scc_chan->scc_regs->gsmr_h = QUICC2_SCC_GSMR_H_INIT; + // scc_chan->scc_regs->psmr = 0x8000; // Set by config + scc_chan->scc_regs->todr = 0; + // scc_chan->scc_regs->dsr = 0x7e7e; // Set by config + scc_chan->scc_regs->scce = 0xffff; + scc_chan->scc_regs->sccm = (QUICC2_SCCE_BSY | QUICC2_SCCE_TX | QUICC2_SCCE_RX); + + /* setup RX buffer descriptors */ + rxbd = (struct scc_bd *)((char *) QUICC2_VADS_IMM_BASE + RxBD); + + for (i = 0; i < RxNUM; i++) { + rxbd->ctrl = QUICC2_BD_CTL_Ready | QUICC2_BD_CTL_Int; + rxbd->length = 0; + rxbd->buffer = RxBUF; + + RxBUF += RxSIZE; + rxbd++; + } + + rxbd--; + rxbd->ctrl |= QUICC2_BD_CTL_Wrap; // Last buffer + + /* setup TX buffer descriptors */ + txbd = (struct scc_bd *)((char *) QUICC2_VADS_IMM_BASE + TxBD); + + for (i = 0; i < TxNUM; i++) { + txbd->ctrl = 0; + txbd->length = 0; + txbd->buffer = TxBUF; + TxBUF += TxSIZE; + txbd++; + } + + txbd--; + txbd->ctrl |= QUICC2_BD_CTL_Wrap; // Last buffer + + // Issue Init RX & TX Parameters Command + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_INIT_TX_RX | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + return; + +} + +// Function to initialize the device. Called at bootstrap time. +static bool +quicc2_scc_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; + int TxBD, RxBD; + static int first_init = 1; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + +#ifdef CYGDBG_IO_INIT + diag_printf("QUICC2_SCC SERIAL init - dev: %x\n", + scc_chan->channel); +#endif + if (first_init) { + // Set up tables since many fields are dynamic [computed at runtime] + first_init = 0; +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 + + // Totally reset the CP + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = QUICC2_CPCR_RESET | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + TxBD = 0x2800; // Note: this should be configurable + RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM*8; + quicc2_scc_serial_init_info(&quicc2_scc_serial_info1, + 1, // indicates SCC1 + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BRG, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc1_txbuf[0][0]), + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc1_rxbuf[0][0]) + ); +#else +#ifdef CYGPKG_HAL_POWERPC_MPC8260 + // Ensure that SCC1 side is initialized first + diag_init(); // (pull in constructor that inits diag channel) + TxBD = 0x2900; // Note : this should be inferred from the + // chip state +#else + // there is no diag device wanting to use the QUICC, so prepare it + // for SCC2 use only. + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); // Totally reset the CP + IMM->cpm_cpcr = QUICC2_CPCR_RESET | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + TxBD = 0x2800; // Note: this should be configurable +#endif +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 + + RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM*8; + quicc2_scc_serial_init_info(&quicc2_scc_serial_info2, + 2, // indicates SCC2 + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BRG, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc2_txbuf[0][0]), + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc2_rxbuf[0][0]) + ); +#endif + } + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(scc_chan->int_vector, + 0, // CYGARC_SIU_PRIORITY_HIGH, - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + quicc2_scc_serial_ISR, + quicc2_scc_serial_DSR, + &scc_chan->serial_interrupt_handle, + &scc_chan->serial_interrupt); + cyg_drv_interrupt_attach(scc_chan->serial_interrupt_handle); + cyg_drv_interrupt_acknowledge(scc_chan->int_vector); + cyg_drv_interrupt_unmask(scc_chan->int_vector); + } + quicc2_scc_serial_config_port(chan, &chan->config, true); + if (cache_state) + HAL_DCACHE_ENABLE(); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +quicc2_scc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Force the current transmit buffer to be sent +static void +quicc2_scc_serial_flush(quicc2_scc_serial_info *scc_chan) +{ + volatile struct scc_bd *txbd = scc_chan->txbd; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_FLUSH(txbd->buffer, scc_chan->txsize); + } + + if ((txbd->length > 0) && + ((txbd->ctrl & (QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int)) == 0)) { + txbd->ctrl |= QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int; // Signal buffer ready + if (txbd->ctrl & QUICC2_BD_CTL_Wrap) { + txbd = scc_chan->tbase; + } else { + txbd++; + } + scc_chan->txbd = (scc_bd *) txbd; + } +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +quicc2_scc_serial_putc(serial_channel *chan, unsigned char c) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile struct scc_bd *txbd, *txfirst; + bool res; + + cyg_drv_dsr_lock(); // Avoid race condition testing pointers + + txbd = (scc_bd *)(QUICC2_VADS_IMM_BASE + ((int) scc_chan->scc_pram->tbptr)); + txfirst = txbd; + + // Scan for a non-busy buffer + while (txbd->ctrl & QUICC2_BD_CTL_Ready) { + // This buffer is busy, move to next one + if (txbd->ctrl & QUICC2_BD_CTL_Wrap) { + txbd = scc_chan->tbase; + } else { + txbd++; + } + if (txbd == txfirst) break; // Went all the way around + } + + scc_chan->txbd = (scc_bd *) txbd; + if ((txbd->ctrl & (QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int)) == 0) { + // Transmit buffer is not full/busy + txbd->buffer[txbd->length++] = c; + if (txbd->length == scc_chan->txsize) { + // This buffer is now full, tell SCC to start processing it + quicc2_scc_serial_flush(scc_chan); + } + res = true; + } else { + // No space + res = false; + } + + cyg_drv_dsr_unlock(); + return res; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +quicc2_scc_serial_getc(serial_channel *chan) +{ + unsigned char c; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile scc_bd *rxbd = scc_chan->rxbd; + + while ((rxbd->ctrl & QUICC2_BD_CTL_Ready) != 0) ; // WAIT ... + + c = rxbd->buffer[0]; + rxbd->length = scc_chan->rxsize; + rxbd->ctrl |= QUICC2_BD_CTL_Ready; + if (rxbd->ctrl & QUICC2_BD_CTL_Wrap) { + rxbd = scc_chan->rbase; + } else { + rxbd++; + } + scc_chan->rxbd = (scc_bd *) rxbd; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +quicc2_scc_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + // FIXME - The documentation says that you can't change the baud rate + // again until at least two BRG input clocks have occurred. + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != quicc2_scc_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +quicc2_scc_serial_start_xmit(serial_channel *chan) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + + cyg_drv_dsr_lock(); + + if (scc_chan->txbd->length == 0) { + // See if there is anything to put in this buffer, just to get it going + (chan->callbacks->xmt_char)(chan); + } + if (scc_chan->txbd->length != 0) { + // Make sure it gets started + quicc2_scc_serial_flush(scc_chan); + } + + cyg_drv_dsr_unlock(); +} + +// Disable the transmitter on the device +static void +quicc2_scc_serial_stop_xmit(serial_channel *chan) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + // If anything is in the last buffer, need to get it started + if (scc_chan->txbd->length != 0) { + quicc2_scc_serial_flush(scc_chan); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +quicc2_scc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(scc_chan->int_vector); + return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +quicc2_scc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile struct scc_regs_8260 *regs = scc_chan->scc_regs; + volatile scc_bd *txbd; + volatile scc_bd *rxbd = scc_chan->rxbd; + scc_bd *rxlast; + int i, cache_state; + +#ifdef CYGDBG_DIAG_BUF + int _time, _stime; + externC cyg_tick_count_t cyg_current_time(void); + cyg_drv_isr_lock(); + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("DSR start - CE: %x, time: %x.%x\n", + regs->scce, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + + if (regs->scce & QUICC2_SCCE_TX) { // Tx Event + +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + txbd = scc_chan->tbase; + for (i = 0; i < CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM; i++, txbd++) { + diag_printf("Tx BD: %x, length: %d, ctl: %x\n", txbd, txbd->length, txbd->ctrl); + } + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + + regs->scce = QUICC2_SCCE_TX; // Reset Tx Event + txbd = scc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int)) == QUICC2_BD_CTL_Int) { +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("TX Done - Tx: %x, length: %d, time: %x.%x\n", + txbd, txbd->length, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + txbd->length = 0; + txbd->ctrl &= ~QUICC2_BD_CTL_Int; // Reset interrupt bit + } + + if (txbd->ctrl & QUICC2_BD_CTL_Wrap) { + txbd = scc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + + while (regs->scce & QUICC2_SCCE_RX) { // Rx Event + + regs->scce = QUICC2_SCCE_RX; // Reset interrupt state; + rxlast = (scc_bd *) ((char *)QUICC2_VADS_IMM_BASE + scc_chan->scc_pram->rbptr ); + +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("Scan RX - rxbd: %x, rbptr: %x, time: %x.%x\n", + rxbd, rxlast, _stime, _time); +#endif // CYGDBG_DIAG_BUF + while (rxbd != rxlast) { + if ((rxbd->ctrl & QUICC2_BD_CTL_Ready) == 0) { +#ifdef CYGDBG_DIAG_BUF + diag_printf("rxbuf: %x, flags: %x, length: %d\n", + rxbd, rxbd->ctrl, rxbd->length); + diag_dump_buf(rxbd->buffer, rxbd->length); +#endif // CYGDBG_DIAG_BUF + + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, scc_chan->rxsize); // Make sure no stale data + } + + rxbd->length = 0; + rxbd->ctrl |= QUICC2_BD_CTL_Ready; + } + + if (rxbd->ctrl & QUICC2_BD_CTL_Wrap) { + rxbd = scc_chan->rbase; + } else { + rxbd++; + } + } +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + scc_chan->rxbd = (scc_bd *) rxbd; + } + + if (regs->scce & QUICC2_SCCE_BSY) { +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + diag_printf("RX BUSY interrupt\n"); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + regs->scce = QUICC2_SCCE_BSY; // Reset interrupt state; + } +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("DSR done - CE: %x, time: %x.%x\n", + regs->scce, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + cyg_drv_interrupt_acknowledge(scc_chan->int_vector); + cyg_drv_interrupt_unmask(scc_chan->int_vector); +#ifdef CYGDBG_DIAG_BUF + cyg_drv_isr_unlock(); +#endif // CYGDBG_DIAG_BUF +} + +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + +// ------------------------------------------------------------------------ +// EOF powerpc/quicc2_scc_serial.c diff --git a/ecos/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.h b/ecos/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.h new file mode 100644 index 0000000..d90162c --- /dev/null +++ b/ecos/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.h @@ -0,0 +1,207 @@ +#ifndef CYGONCE_POWERPC_QUICC2_SCC_SERIAL_H +#define CYGONCE_POWERPC_QUICC2_SCC_SERIAL_H + +// ==================================================================== +// +// quicc2_scc_serial.h +// +// Device I/O - Description of PowerPC QUICC2/SCC serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek +// Contributors: gthomas +// Date: 2002-2-27 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports using QUICC2/SCC + +// macro for aligning buffers to cache lines +#define ALIGN_TO_CACHELINES(b) ((cyg_uint8 *)(((CYG_ADDRESS)(b) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1))) + +#define UART_BIT_RATE(n) \ + ((((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000))/(n * 64))-1) + +// SCC PSMR masks .... +#define QUICC2_SCC_PSMR_ASYNC 0x8000 +#define QUICC2_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb) +#define QUICC2_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8) +#define QUICC2_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled) +#define QUICC2_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high) +#define QUICC2_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high) + +// SCC DSR masks +#define QUICC2_SCC_DSR_FULL 0x7e7e +#define QUICC2_SCC_DSR_HALF 0x467e + +// SCC GSMR masks ... +#define QUICC2_SCC_GSMR_H_INIT 0x00000060 +#define QUICC2_SCC_GSMR_L_INIT 0x00028004 +#define QUICC2_SCC_GSMR_L_ENT 0x00000010 +#define QUICC2_SCC_GSMR_L_ENR 0x00000020 + +// SCC Events (interrupts) +#define QUICC2_SCCE_BRK 0x0040 +#define QUICC2_SCCE_BSY 0x0004 +#define QUICC2_SCCE_TX 0x0002 +#define QUICC2_SCCE_RX 0x0001 + +// CP commands for SCC1 and SCC2 +#define QUICC2_CPCR_SCC1 0x00800000 +#define QUICC2_CPCR_SCC2 0x04A00000 +#define QUICC2_CPCR_READY 0x00010000 +#define QUICC2_CPCR_INIT_TX_RX 0x0 +#define QUICC2_CPCR_INIT_RX 0x1 +#define QUICC2_CPCR_INIT_TX 0x2 +#define QUICC2_CPCR_STOP_TX 0x4 +#define QUICC2_CPCR_RESTART_TX 0x6 +#define QUICC2_CPCR_RESET 0x80000000 + +// SCC Buffer descriptor control bits +#define QUICC2_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx) +#define QUICC2_BD_CTL_Wrap 0x2000 // Last buffer in list +#define QUICC2_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx) + +// PORT configuration masks for SCC1 and SCC2 +#define QUICC2_SCC1_PORTC_PPAR (0x00020000) +#define QUICC2_SCC1_PORTD_PPAR (0x00000003) +#define QUICC2_SCC1_PORTD_PDIR (0x00000002) + +#define QUICC2_SCC2_PORTC_PPAR (0x00080000) +#define QUICC2_SCC2_PORTD_PPAR (0x00000018) +#define QUICC2_SCC2_PORTD_PDIR (0x00000010) + +// SCC clock Route register constants +#define QUICC2_CMX_SCC1_CLR 0x00ffffff +#define QUICC2_CMX_SCC1_BRG1 0x00000000 +#define QUICC2_CMX_SCC1_BRG2 0x09000000 +#define QUICC2_CMX_SCC1_BRG3 0x12000000 +#define QUICC2_CMX_SCC1_BRG4 0x1b000000 + +#define QUICC2_CMX_SCC2_CLR 0xff00ffff +#define QUICC2_CMX_SCC2_BRG1 0x00000000 +#define QUICC2_CMX_SCC2_BRG2 0x00090000 +#define QUICC2_CMX_SCC2_BRG3 0x00120000 +#define QUICC2_CMX_SCC2_BRG4 0x001b0000 + +static unsigned int select_word_length[] = { + QUICC2_SCC_PSMR_CLEN(5), // 5 bits / word (char) + QUICC2_SCC_PSMR_CLEN(6), + QUICC2_SCC_PSMR_CLEN(7), + QUICC2_SCC_PSMR_CLEN(8) +}; + +static unsigned int select_stop_bits[] = { + QUICC2_SCC_PSMR_SB(1), // 0.5 stop bit ?? + QUICC2_SCC_PSMR_SB(1), // 1 stop bit + QUICC2_SCC_PSMR_SB(2), // 1.5 stop bit + QUICC2_SCC_PSMR_SB(2) // 2 stop bits +}; + + +static unsigned int select_parity[] = { + QUICC2_SCC_PSMR_PE(0), // No parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(2)|QUICC2_SCC_PSMR_RPM(2), // Even parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(0)|QUICC2_SCC_PSMR_RPM(0), // Odd parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(3)|QUICC2_SCC_PSMR_RPM(3), // High (mark) parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(1)|QUICC2_SCC_PSMR_RPM(1), // Low (space) parity +}; + + +// Baud rate values, will be used by the macro ... +#define QUICC2_BRG_EN 0x00010000 +static unsigned long select_baud[] = { + 0, // unused + 50, + 75, + 110, + 134, + 150, + 200, + 300, + 600, + 1200, + 1800, + 2400, + 3600, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400 +}; + +// Board control and status registers +#define QUICC2_BCSR_EN_SCC1 0x02000000 +#define QUICC2_BCSR_EN_SCC2 0x01000000 + +typedef struct bcsr { + volatile unsigned long bcsr0; + volatile unsigned long bcsr1; + volatile unsigned long bcsr2; + volatile unsigned long bcsr3; +} t_BCSR; + + +typedef struct scc_bd{ + cyg_int16 ctrl; + cyg_int16 length; + cyg_int8 *buffer; +} scc_bd; + +typedef struct quicc2_scc_serial_info { + unsigned long scc_cpcr; // Selects scc for cpcr + volatile struct scc_regs_8260 *scc_regs; // Ptr to scc registers + volatile t_Scc_Pram *scc_pram; // Ptr to scc pram + volatile int *brg; // Ptr to baud rate generator + struct scc_bd *txbd, *rxbd; // Next Tx, Rx descriptor to use + struct scc_bd *tbase, *rbase; // First Tx, Rx descriptor + int txsize, rxsize; // Length of individual buffers + unsigned int int_vector; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} quicc2_scc_serial_info; + +#endif // CYGONCE_POWERPC_QUICC_SMC_SERIAL_H diff --git a/ecos/packages/devs/serial/sh/cq7708/current/ChangeLog b/ecos/packages/devs/serial/sh/cq7708/current/ChangeLog new file mode 100644 index 0000000..e32de66 --- /dev/null +++ b/ecos/packages/devs/serial/sh/cq7708/current/ChangeLog @@ -0,0 +1,62 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_cq7708.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_cq7708_sci.inl: Serial register renaming. + +2002-04-23 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_cq7708_sci.inl (sh_serial_info): Use variant + register definition for base. + +2000-10-03 Jesper Skov <jskov@redhat.co.uk> + + * cdl/ser_sh_cq7708.cdl: Added testing parameters. + + * include/sh_sh3_cq7708_sci.inl: Use named elements in structure + initializer. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Moved to SCI package. + * scr/sh_sci_cq7708.inl: moved... + * include/sh_sh3_cq7708_sci.inl: ... to here. + * cdl/ser_sh_cq7708.cdl: Matching changes. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh_sci_serial.c (sh_serial_set_config): Now use keys to make + more flexible. + +2000-06-23 Jesper Skov <jskov@redhat.com> + + + * Imported sources contributed by Haruki Kashiwaya + (kashiwaya at redhat dot com). Still need to fix this to properly + share the driver with the EDK (and any other platform using SCI). + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/cq7708/current/cdl/ser_sh_cq7708.cdl b/ecos/packages/devs/serial/sh/cq7708/current/cdl/ser_sh_cq7708.cdl new file mode 100644 index 0000000..01aa6fd --- /dev/null +++ b/ecos/packages/devs/serial/sh/cq7708/current/cdl/ser_sh_cq7708.cdl @@ -0,0 +1,130 @@ +# ==================================================================== +# +# ser_sh_cq7708.cdl +# +# eCos serial SH/CQ7708 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_CQ7708 { + display "SH3 cq7708 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_SH7708_CQ7708 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + CQ SH3 cq7708 board, based on the generic SH SCI driver." + + # FIXME: This really belongs in the SH_SCI package + cdl_interface CYGINT_IO_SERIAL_SH_SCI_REQUIRED { + display "SH SCI driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_INL <cyg/io/sh_sh3_cq7708_sci.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_CFG <pkgconf/io_serial_sh_cq7708.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_SH_CQ7708_SERIAL1 { + display "SH3 CQ7708 serial 1 device driver (SCI)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SCI + port." + + implements CYGINT_IO_SERIAL_SH_SCI_REQUIRED + + cdl_option CYGDAT_IO_SERIAL_SH_CQ7708_SERIAL1_NAME { + display "Device name for SH3 CQ7708 SCI" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BAUD { + display "Baud rate for the SH SCI driver" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE { + display "Buffer size for the SH SCI driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the SCI port." + } + } + + cdl_component CYGPKG_IO_SERIAL_SH_CQ7708_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_CQ7708_SERIAL1 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-cq7708\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_CQ7708_SERIAL1_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} +# EOF ser_sh_cq7708.cdl diff --git a/ecos/packages/devs/serial/sh/cq7708/current/include/sh_sh3_cq7708_sci.inl b/ecos/packages/devs/serial/sh/cq7708/current/include/sh_sh3_cq7708_sci.inl new file mode 100644 index 0000000..fcf6210 --- /dev/null +++ b/ecos/packages/devs/serial/sh/cq7708/current/include/sh_sh3_cq7708_sci.inl @@ -0,0 +1,104 @@ +#ifndef CYGONCE_DEVS_SH_CQ7708_SCI_H +#define CYGONCE_DEVS_SH_CQ7708_SCI_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_cq7708_sci.inl +// +// Serial I/O Interface Module definitions for SH3/CQ7708 +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-06-16 +// Purpose: Defines SCI serial resources for SH3/CQ7708. +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + + +#include <pkgconf/io_serial_sh_cq7708.h> + +static sh_sci_info sh_serial_info = +{ + data : CYGARC_REG_SCI_SCSPTR, + er_int_num : CYGNUM_HAL_INTERRUPT_SCI_ERI, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCI_RXI, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCI_TXI, + ctrl_base : CYGARC_REG_SCI_SCSMR +}; + +#if CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE > 0 +static unsigned char sh_serial_out_buf[CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE]; +static unsigned char sh_serial_in_buf[CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sh_serial_out_buf[0], + sizeof(sh_serial_out_buf), + &sh_serial_in_buf[0], + sizeof(sh_serial_in_buf) + ); +#else +static SERIAL_CHANNEL(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io, + CYGDAT_IO_SERIAL_SH_CQ7708_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_serial_init, + sh_serial_lookup, // Serial driver may need initializing + &sh_serial_channel + ); + +#endif // CYGONCE_DEVS_SH_CQ7708_SCI_H diff --git a/ecos/packages/devs/serial/sh/edk7708/current/ChangeLog b/ecos/packages/devs/serial/sh/edk7708/current/ChangeLog new file mode 100644 index 0000000..6d6ee70 --- /dev/null +++ b/ecos/packages/devs/serial/sh/edk7708/current/ChangeLog @@ -0,0 +1,1204 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_edk7708.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_edk7708_sci.inl: Serial register renaming. + +2002-04-23 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_edk7708_sci.inl (sh_serial_info): Use variant + register definition for base. + +2000-10-03 Jesper Skov <jskov@redhat.co.uk> + + * cdl/ser_sh_edk7708.cdl: Added testing parameters. + + * include/sh_sh3_edk7708_sci.inl: Use named elements in structure + initializer. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Moved to SCI package. + * src/sh_sci_7708.inl: Moved ... + * include/sh_sh3_edk7708_sci.inl: ... to here. + * cdl/ser_sh_edk7708.cdl: Matching changes. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh_sci_serial.c (sh_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sh_edk7708.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-11 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Move compile statement into a + sub-component. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/edk7708/current/cdl/ser_sh_edk7708.cdl b/ecos/packages/devs/serial/sh/edk7708/current/cdl/ser_sh_edk7708.cdl new file mode 100644 index 0000000..e71d578 --- /dev/null +++ b/ecos/packages/devs/serial/sh/edk7708/current/cdl/ser_sh_edk7708.cdl @@ -0,0 +1,130 @@ +# ==================================================================== +# +# ser_sh_edk7708.cdl +# +# eCos serial SH/EDK7708 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_EDK7708 { + display "SH3 EDK7708 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_EDK7708 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Hitachi SH3 EDK7708 board, based on the generic SH SCI driver." + + # FIXME: This really belongs in the SH_SCI package + cdl_interface CYGINT_IO_SERIAL_SH_SCI_REQUIRED { + display "SH SCI driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_INL <cyg/io/sh_sh3_edk7708_sci.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_CFG <pkgconf/io_serial_sh_edk7708.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_SH_EDK7708_SERIAL1 { + display "SH EDK7708 serial 1 driver (SCI)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SCI + port." + + implements CYGINT_IO_SERIAL_SH_SCI_REQUIRED + + cdl_option CYGDAT_IO_SERIAL_SH_EDK7708_SERIAL1_NAME { + display "Device name for SH3 EDK7708 SCI" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BAUD { + display "Baud rate for the SH SCI driver" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE { + display "Buffer size for the SH SCI driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the SCI port." + } + } + + cdl_component CYGPKG_IO_SERIAL_SH_EDK7708_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_EDK7708_SERIAL1 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-edk7708\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_EDK7708_SERIAL1_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} +# EOF ser_sh_edk7708.cdl diff --git a/ecos/packages/devs/serial/sh/edk7708/current/include/sh_sh3_edk7708_sci.inl b/ecos/packages/devs/serial/sh/edk7708/current/include/sh_sh3_edk7708_sci.inl new file mode 100644 index 0000000..12a1b67 --- /dev/null +++ b/ecos/packages/devs/serial/sh/edk7708/current/include/sh_sh3_edk7708_sci.inl @@ -0,0 +1,104 @@ +#ifndef CYGONCE_DEVS_SH_EDK7708_SCI_H +#define CYGONCE_DEVS_SH_EDK7708_SCI_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_edk7708_sci.inl +// +// Serial I/O specification for Hitachi EDK7708 platform. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-06-16 +// Purpose: Defines SCI serial resources for SH3/7708. +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + + +#include <pkgconf/io_serial_sh_edk7708.h> + +static sh_sci_info sh_serial_info = +{ + data : CYGARC_REG_SCI_SCSPTR, + er_int_num : CYGNUM_HAL_INTERRUPT_SCI_ERI, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCI_RXI, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCI_TXI, + ctrl_base : CYGARC_REG_SCI_SCSMR +}; + +#if CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE > 0 +static unsigned char sh_serial_out_buf[CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE]; +static unsigned char sh_serial_in_buf[CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sh_serial_out_buf[0], + sizeof(sh_serial_out_buf), + &sh_serial_in_buf[0], + sizeof(sh_serial_in_buf) + ); +#else +static SERIAL_CHANNEL(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io, + CYGDAT_IO_SERIAL_SH_EDK7708_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_serial_init, + sh_serial_lookup, // Serial driver may need initializing + &sh_serial_channel + ); + +#endif // CYGONCE_DEVS_SH_EDK7708_SCI_H diff --git a/ecos/packages/devs/serial/sh/sci/current/ChangeLog b/ecos/packages/devs/serial/sh/sci/current/ChangeLog new file mode 100644 index 0000000..34de3a0 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sci/current/ChangeLog @@ -0,0 +1,156 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_sci.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Register renaming. + +2002-04-23 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Compute register offsets from register + definitions. Don't define SCI base. + +2001-02-26 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c (sh_serial_er_DSR): Enable interrupts on + exit. + +2000-09-26 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_sci.cdl: Minor hack to allow both SCI and SCIF + packages to be used at the same time. + * src/sh_sci_serial.c: Same. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Moved to generic SH SCI package. + * ChangeLog: Removed all non-SCI related references. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh_sci_serial.c (sh_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sh_edk7708.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-11 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Move compile statement into a + sub-component. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + serial_devio => cyg_io_serial_devio + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/sci/current/cdl/ser_sh_sci.cdl b/ecos/packages/devs/serial/sh/sci/current/cdl/ser_sh_sci.cdl new file mode 100644 index 0000000..de85cc4 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sci/current/cdl/ser_sh_sci.cdl @@ -0,0 +1,112 @@ +# ==================================================================== +# +# ser_sh_sci.cdl +# +# eCos serial SH/SCI configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SCI { + display "SH SCI serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH + + active_if CYGINT_IO_SERIAL_SH_SCI_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + SCI module in Hitachi SH CPUs." + + compile -library=libextras.a sh_sci_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_sh_sci.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_SH_SCI_CFG"; + } + + cdl_component CYGPKG_IO_SERIAL_SH_SCI_OPTIONS { + display "SCI serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_IO_SERIAL_SH_SCI_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_SH_SCI_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_sh_sci.cdl diff --git a/ecos/packages/devs/serial/sh/sci/current/src/sh_sci_serial.c b/ecos/packages/devs/serial/sh/sci/current/src/sh_sci_serial.c new file mode 100644 index 0000000..79d7c73 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sci/current/src/sh_sci_serial.c @@ -0,0 +1,545 @@ +//========================================================================== +// +// io/serial/sh/sh_sci_serial.c +// +// SH Serial SCI I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 1999-05-24 +// Purpose: SH Serial I/O module (interrupt driven version) +// Description: +// +// Note: Since interrupt sources from the same SCI channel share the same +// interrupt level, there is no risk of races when altering the +// channel's control register from ISRs and DSRs. However, when +// altering the control register from user-level code, interrupts +// must be disabled while the register is being accessed. +// +// FIXME: Receiving in polled mode prevents duplex transfers from working for +// some reason. +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +// FIXME: This is necessary since the SCIF driver may be overriding +// CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two +// different drivers. +#include <pkgconf/io_serial_sh_sci.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#include <cyg/hal/sh_regs.h> + +// Only compile driver if an inline file with driver details was selected. +#ifdef CYGDAT_IO_SERIAL_SH_SCI_INL + +// Find the SCI controller register layout from the SCI0 definitions +#if defined(CYGARC_REG_SCI_SCSMR0) +# define SCI_SCSMR (CYGARC_REG_SCI_SCSMR0-CYGARC_REG_SCI_SCSMR0) // serial mode register +# define SCI_SCBRR (CYGARC_REG_SCI_SCBRR0-CYGARC_REG_SCI_SCSMR0) // bit rate register +# define SCI_SCSCR (CYGARC_REG_SCI_SCSCR0-CYGARC_REG_SCI_SCSMR0) // serial control register +# define SCI_SCTDR (CYGARC_REG_SCI_SCTDR0-CYGARC_REG_SCI_SCSMR0) // transmit data register +# define SCI_SCSSR (CYGARC_REG_SCI_SCSSR0-CYGARC_REG_SCI_SCSMR0) // serial status register +# define SCI_SCRDR (CYGARC_REG_SCI_SCRDR0-CYGARC_REG_SCI_SCSMR0) // receive data register +# define SCI_SCSPTR (CYGARC_REG_SCI_SCSPTR0-CYGARC_REG_SCI_SCSMR0)// serial port register +#elif defined(CYGARC_REG_SCI_SCSMR) +# define SCI_SCSMR (CYGARC_REG_SCI_SCSMR-CYGARC_REG_SCI_SCSMR) // serial mode register +# define SCI_SCBRR (CYGARC_REG_SCI_SCBRR-CYGARC_REG_SCI_SCSMR) // bit rate register +# define SCI_SCSCR (CYGARC_REG_SCI_SCSCR-CYGARC_REG_SCI_SCSMR) // serial control register +# define SCI_SCTDR (CYGARC_REG_SCI_SCTDR-CYGARC_REG_SCI_SCSMR) // transmit data register +# define SCI_SCSSR (CYGARC_REG_SCI_SCSSR-CYGARC_REG_SCI_SCSMR) // serial status register +# define SCI_SCRDR (CYGARC_REG_SCI_SCRDR-CYGARC_REG_SCI_SCSMR) // receive data register +# define SCI_SCSPTR (CYGARC_REG_SCI_SCSPTR-CYGARC_REG_SCI_SCSMR) // serial port register +#else +# error "Missing register offsets" +#endif + +static short select_word_length[] = { + -1, + -1, + CYGARC_REG_SCI_SCSMR_CHR, // 7 bits + 0 // 8 bits +}; + +static short select_stop_bits[] = { + -1, + 0, // 1 stop bit + -1, + CYGARC_REG_SCI_SCSMR_STOP // 2 stop bits +}; + +static short select_parity[] = { + 0, // No parity + CYGARC_REG_SCI_SCSMR_PE, // Even parity + CYGARC_REG_SCI_SCSMR_PE|CYGARC_REG_SCI_SCSMR_OE, // Odd parity + -1, + -1 +}; + +static unsigned short select_baud[] = { + 0, // Unused + CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50), + CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75), + CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110), + CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134), + CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150), + CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200), + CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300), + CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600), + CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200), + CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800), + CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400), + CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600), + CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800), + CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200), + CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600), + CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400), + CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200), + CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400), + CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600), + CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200), + CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400) +}; + + +typedef struct sh_sci_info { + CYG_ADDRWORD data; // Pointer to data register + + CYG_WORD er_int_num, // Error interrupt number + rx_int_num, // Receive interrupt number + tx_int_num; // Transmit interrupt number + + CYG_ADDRWORD ctrl_base; // Base address of SCI controller + + cyg_interrupt serial_er_interrupt, + serial_rx_interrupt, + serial_tx_interrupt; + cyg_handle_t serial_er_interrupt_handle, + serial_rx_interrupt_handle, + serial_tx_interrupt_handle; + + bool tx_enabled; +} sh_sci_info; + +static bool sh_serial_init(struct cyg_devtab_entry *tab); +static bool sh_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo sh_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char sh_serial_getc(serial_channel *chan); +static Cyg_ErrNo sh_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void sh_serial_start_xmit(serial_channel *chan); +static void sh_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(sh_serial_funs, + sh_serial_putc, + sh_serial_getc, + sh_serial_set_config, + sh_serial_start_xmit, + sh_serial_stop_xmit + ); + +#include CYGDAT_IO_SERIAL_SH_SCI_INL + +// Internal function to actually configure the hardware to desired baud rate, +// etc. +static bool +sh_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, + bool init) +{ + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr, _smr; + + // Check configuration request + if ((-1 == select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)]) + || -1 == select_stop_bits[new_config->stop] + || -1 == select_parity[new_config->parity] + || baud_divisor == 0) + return false; + + // Disable SCI interrupts while changing hardware + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, 0); + + // Set databits, stopbits and parity. + _smr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr); + + // Set baud rate. + _smr &= ~CYGARC_REG_SCI_SCSMR_CKSx_MASK; + _smr |= baud_divisor >> 8; + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr); + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff); + + // Clear the status register. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, 0); + + if (init) { + // Always enable transmitter and receiver. + _scr = CYGARC_REG_SCI_SCSCR_TE | CYGARC_REG_SCI_SCSCR_RE; + + if (chan->out_cbuf.len != 0) + _scr |= CYGARC_REG_SCI_SCSCR_TIE; // enable tx interrupts + + if (chan->in_cbuf.len != 0) + _scr |= CYGARC_REG_SCI_SCSCR_RIE; // enable rx interrupts + } + + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +sh_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("SH SERIAL init - dev: %x.%d\n", + sh_chan->data, sh_chan->rx_int_num); +#endif + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(sh_chan->tx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_serial_tx_ISR, + sh_serial_tx_DSR, + &sh_chan->serial_tx_interrupt_handle, + &sh_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_unmask(sh_chan->tx_int_num); + sh_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + // Receive interrupt + cyg_drv_interrupt_create(sh_chan->rx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_serial_rx_ISR, + sh_serial_rx_DSR, + &sh_chan->serial_rx_interrupt_handle, + &sh_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle); + // Receive error interrupt + cyg_drv_interrupt_create(sh_chan->er_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_serial_er_ISR, + sh_serial_er_DSR, + &sh_chan->serial_er_interrupt_handle, + &sh_chan->serial_er_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle); + // This unmasks both interrupt sources. + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); + } + sh_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +sh_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +sh_serial_putc(serial_channel *chan, unsigned char c) +{ + cyg_uint8 _ssr; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + if (_ssr & CYGARC_REG_SCI_SCSSR_TDRE) { +// Transmit buffer is empty + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCTDR, c); + // Clear empty flag. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_TDRE); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +sh_serial_getc(serial_channel *chan) +{ + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + unsigned char c; + cyg_uint8 _ssr; + + do { + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + } while ((_ssr & CYGARC_REG_SCI_SCSSR_RDRF) == 0); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, c); + + // Clear buffer full flag. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF); + + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +sh_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != sh_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +sh_serial_start_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + sh_chan->tx_enabled = true; + + // Mask the interrupts (all sources of the unit) while changing + // the CR since a rx interrupt in the middle of this would result + // in a bad CR state. + cyg_drv_interrupt_mask(sh_chan->rx_int_num); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_TIE; // Enable xmit interrupt + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); +} + +// Disable the transmitter on the device +static void +sh_serial_stop_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + sh_chan->tx_enabled = false; + + // Mask the interrupts (all sources of the unit) while changing + // the CR since a rx interrupt in the middle of this would result + // in a bad CR state. + cyg_drv_interrupt_mask(sh_chan->rx_int_num); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_TIE; // Disable xmit interrupt + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_TIE; // mask out tx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + (chan->callbacks->xmt_char)(chan); + + if (sh_chan->tx_enabled) { + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_TIE; // unmask tx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + } +} + +// Serial I/O - low level RX interrupt handler (ISR) +static cyg_uint32 +sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_RIE; // mask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _ssr, _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + if (_ssr & CYGARC_REG_SCI_SCSSR_RDRF) { + cyg_uint8 _c; + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, _c); + // Clear buffer full flag. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF); + + (chan->callbacks->rcv_char)(chan, _c); + } + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); +} + +static volatile int sh_serial_error_orer = 0; +static volatile int sh_serial_error_fer = 0; +static volatile int sh_serial_error_per = 0; + +// Serial I/O - low level error interrupt handler (ISR) +static cyg_uint32 +sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_RIE; // mask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level error interrupt handler (DSR) +static void +sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _ssr, _ssr2, _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + _ssr2 = CYGARC_REG_SCI_SCSSR_CLEARMASK; + + if (_ssr & CYGARC_REG_SCI_SCSSR_ORER) { + _ssr2 &= ~CYGARC_REG_SCI_SCSSR_ORER; + sh_serial_error_orer++; + } + if (_ssr & CYGARC_REG_SCI_SCSSR_FER) { + _ssr2 &= ~CYGARC_REG_SCI_SCSSR_FER; + sh_serial_error_fer++; + } + if (_ssr & CYGARC_REG_SCI_SCSSR_PER) { + _ssr2 &= ~CYGARC_REG_SCI_SCSSR_PER; + sh_serial_error_per++; + } + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr2); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); +} + +#endif // ifdef CYGDAT_IO_SERIAL_SH_SCI_INL diff --git a/ecos/packages/devs/serial/sh/scif/current/ChangeLog b/ecos/packages/devs/serial/sh/scif/current/ChangeLog new file mode 100644 index 0000000..1184485 --- /dev/null +++ b/ecos/packages/devs/serial/sh/scif/current/ChangeLog @@ -0,0 +1,188 @@ +2005-08-04 Andrew Lunn <andrew.lunn@ascom.ch> +2005-05-02 Hajime Ishitani <pigmon@mail.snd.co.jp> + + * src/sh_scif_serial.c: support SH4 register access + +2003-03-18 Gary Thomas <gary@mlbassoc.com> + + * src/sh_scif_serial.c (sh_scif_set_config): + Flag for CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE is 32 bits. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_scif.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Added SH2 support. Added break interrupt + support. Added IrDA support. Added async RX/TX support. Added + support for platforms to add config keys and handle flow + control. Register renaming. + + * cdl/ser_sh_scif.cdl: Added async RX/TX and IRDA support. Also + added interface for support of break interrupts. + +2002-01-30 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_tx_DSR): Stop single-character + transmit if transmitter gets disabled. This does not change the + (output) semantics of the code, but does prevent it from looping + over the full size of the FIFO calling the (inactive) xmt_char + callback. + +2001-02-27 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_er_DSR): Clear break flag. + +2001-02-26 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_er_DSR): Enable interrupts on + exit. Clear ER flag. + +2000-10-23 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Include cyg_ass.h + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_set_config): Changes to the flow + control handling. Renamed DMA variables. + +2000-10-12 Jonathan Larmour <jlarmour@redhat.com> + + * src/sh_scif_serial.c: return -EINVAL when unsupported flow control + mode requested. + +2000-10-06 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Change to new block call syntax. + Clean up start_xmit code. Do block transfers in serial DSRs. + +2000-10-03 Jesper Skov <jskov@redhat.co.uk> + + * src/sh_scif_serial.c: Fixed receive FIFO problem. Added Line + Status handling. Don't enable TX interrupts in initialization. + * src/sh_scif_serial.c: Added DMA support. Added RTS/CTS control. + * cdl/ser_sh_scif.cdl: Added DMA interface. + +2000-09-26 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_scif.cdl: Minor hack to allow both SCI and SCIF + packages to be used at the same time. + * src/sh_scif_serial.c: Same. + +2000-09-25 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Use the SCI macros for baud rate + calculation. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Moved to separate SCIF package. + * ChangeLog: Cleaned out all non-SCIF related entries. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh3_scif_serial.c (sh3_scif_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sh_scif.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-11 Jesper Skov <jskov@redhat.com> + + * src/sh3_scif_serial.c: Can't get input FIFO to work properly. + Disabled for now. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-10 Jesper Skov <jskov@redhat.com> + + * src/sh/sh3_scif_serial.c: + Working, but FIFO isn't enabled due to an interrupt problem. + +2000-04-04 Jesper Skov <jskov@redhat.com> + + * src/sh/sh3_scif_serial.c: FIFO related changes. + +2000-04-03 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_scif.cdl: + * src/sh/sh_scif_serial.c: + Added SCIF driver, based on SCI driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/scif/current/cdl/ser_sh_scif.cdl b/ecos/packages/devs/serial/sh/scif/current/cdl/ser_sh_scif.cdl new file mode 100644 index 0000000..49793f2 --- /dev/null +++ b/ecos/packages/devs/serial/sh/scif/current/cdl/ser_sh_scif.cdl @@ -0,0 +1,176 @@ +# ==================================================================== +# +# ser_sh_scif.cdl +# +# eCos serial SH/SCIF configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 2000-04-04 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SCIF { + display "SH SCIF serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH + + active_if CYGINT_IO_SERIAL_SH_SCIF_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + SCIF module in Hitachi SH CPUs." + + compile -library=libextras.a sh_scif_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_sh_scif.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_SH_SCIF_CFG"; + } + + # The driver tries to be effective with FIFO transfers + implements CYGINT_IO_SERIAL_BLOCK_TRANSFER + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_DMA { + display "SCIF serial driver DMA support" + flavor booldata + description " + The serial driver can use DMA to move data from the + transmit buffer to the serial controller if the CPU + supports it." + } + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX { + display "SCIF async RX/TX support" + flavor booldata + description " + By enabling this option, the SCIF driver will + be able to support controllers with transceivers + that are asynchronous (RS4xx). This will cause + RX to be disabled before TX is enabled, and vice + versa." + } + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_IRDA { + display "SCIF IrDA support" + flavor booldata + description " + By enabling this option, the SCIF driver will + be able to support controllers in IrDA mode." + } + + cdl_option CYGHWR_IO_SERIAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION { + display "SCIF IrDA TX/RX switch compensation" + default_value 1 + active_if CYGINT_IO_SERIAL_SH_SCIF_IRDA + description " + When switching from TX mode to RX mode, the controller causes + a spurious 0xff character to be received at speeds up to + 57600 baud. At higher baud rates, more spurious characters + may be received. Enabling this option tries to remove the + spurious characters, but since there are no errors reported + from the controller, it is impossible to do so with any kind + of precision. + Having this option enabled allows some eCos serial tests to + run. There is a matching option in the SH2 HAL controlling a + similar kludge for the polled driver, making RedBoot usable. + It is an incomplete kludge however, and for any real use of + the IrDA mode for data transmission, the option should be + disabled, and a protocol capable of handling the spurious + receive characters must be used on top of the driver. + Note that the problem is exaggerated when the baud rate is + changed." + } + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT { + display "Controller uses BR interrupts" + flavor booldata + description " + Some controllers route BREAK interrupts to the + error interrupt vector. Others have a separate + vector. When this interface is implemented, the + driver will handle the separate BR vector." + } + + cdl_component CYGPKG_IO_SERIAL_SH_SCIF_OPTIONS { + display "SCIF serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_SH_SCIF_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_SH_SCIF_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} +# EOF ser_sh_scif.cdl diff --git a/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c b/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c new file mode 100644 index 0000000..1eb28a4 --- /dev/null +++ b/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c @@ -0,0 +1,1095 @@ +//========================================================================== +// +// io/serial/sh/scif/sh_scif_serial.c +// +// SH Serial IRDA/SCIF I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 2000-04-04 +// Purpose: SH Serial IRDA/SCIF I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +// FIXME: This is necessary since the SCI driver may be overriding +// CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two +// different drivers. +#include <pkgconf/io_serial_sh_scif.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/io/serial.h> + +#include <cyg/hal/sh_regs.h> +#include <cyg/hal/hal_cache.h> + +// Only compile driver if an inline file with driver details was selected. +#ifdef CYGDAT_IO_SERIAL_SH_SCIF_INL + +#if defined(CYGPKG_HAL_SH_SH2) +// The SCIF controller register layout on the SH2 +// The controller base is defined in the board specification file. +# define SCIF_SCSMR 0x00 // serial mode register +# define SCIF_SCBRR 0x02 // bit rate register +# define SCIF_SCSCR 0x04 // serial control register +# define SCIF_SCFTDR 0x06 // transmit data register +# define SCIF_SC1SSR 0x08 // serial status register 1 +# define SCIF_SCSSR SCIF_SC1SSR +# define SCIF_SC2SSR 0x0a // serial status register 2 +# define SCIF_SCFRDR 0x0c // receive data register +# define SCIF_SCFCR 0x0e // FIFO control +# define SCIF_SCFDR 0x10 // FIFO data count register +# define SCIF_SCFER 0x12 // FIFO error register +# define SCIF_SCIMR 0x14 // IrDA mode register +# define HAL_READ(x,y) HAL_READ_UINT8(x,y) +# define HAL_WRITE(x,y) HAL_WRITE_UINT8(x,y) + +#elif defined(CYGPKG_HAL_SH_SH3) +// The SCIF controller register layout on the SH3 +// The controller base is defined in the board specification file. +# define SCIF_SCSMR 0x00 // serial mode register +# define SCIF_SCBRR 0x02 // bit rate register +# define SCIF_SCSCR 0x04 // serial control register +# define SCIF_SCFTDR 0x06 // transmit data register +# define SCIF_SCSSR 0x08 // serial status register +# define SCIF_SCFRDR 0x0a // receive data register +# define SCIF_SCFCR 0x0c // FIFO control +# define SCIF_SCFDR 0x0e // FIFO data count register +# define HAL_READ(x,y) HAL_READ_UINT8(x,y) +# define HAL_WRITE(x,y) HAL_WRITE_UINT8(x,y) +#elif defined(CYGPKG_HAL_SH_SH4) +// The SCIF controller register layout on the SH4 +// The controller base is defined in the board specification file. +# define SCIF_SCSMR 0x00 // serial mode register +# define SCIF_SCBRR 0x04 // bit rate register +# define SCIF_SCSCR 0x08 // serial control register +# define SCIF_SCFTDR 0x0C // transmit data register +# define SCIF_SCSSR 0x10 // serial status register +# define SCIF_SCFRDR 0x14 // receive data register +# define SCIF_SCFCR 0x18 // FIFO control +# define SCIF_SCFDR 0x1C // FIFO data count register +# define HAL_READ(x,y) HAL_READ_UINT16(x,y) +# define HAL_WRITE(x,y) HAL_WRITE_UINT16(x,y) +#else +# error "Unsupported variant" +#endif + +static short select_word_length[] = { + -1, + -1, + CYGARC_REG_SCIF_SCSMR_CHR, // 7 bits + 0 // 8 bits +}; + +static short select_stop_bits[] = { + -1, + 0, // 1 stop bit + -1, + CYGARC_REG_SCIF_SCSMR_STOP // 2 stop bits +}; + +static short select_parity[] = { + 0, // No parity + CYGARC_REG_SCIF_SCSMR_PE, // Even parity + CYGARC_REG_SCIF_SCSMR_PE|CYGARC_REG_SCIF_SCSMR_OE, // Odd parity + -1, + -1 +}; + +static unsigned short select_baud[] = { + 0, // Unused + CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50), + CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75), + CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110), + CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134), + CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150), + CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200), + CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300), + CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600), + CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200), + CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800), + CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400), + CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600), + CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800), + CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200), + CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600), + CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400), + CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200), + CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400), + CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600), + CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200), + CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400) +}; + +typedef struct sh_scif_info { + CYG_WORD er_int_num, // Error interrupt number +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + br_int_num, // Break interrupt number +#endif + rx_int_num, // Receive interrupt number + tx_int_num; // Transmit interrupt number + + CYG_ADDRWORD ctrl_base; // Base address of SCI controller + + cyg_interrupt serial_er_interrupt, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + serial_br_interrupt, +#endif + serial_rx_interrupt, + serial_tx_interrupt; + cyg_handle_t serial_er_interrupt_handle, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + serial_br_interrupt_handle, +#endif + serial_rx_interrupt_handle, + serial_tx_interrupt_handle; + + volatile bool tx_enabled; // expect tx _serial_ interrupts +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + bool irda_mode; +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + bool async_rxtx_mode; +#endif + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + cyg_bool dma_enable; // Set if DMA mode + cyg_uint32 dma_xmt_cr_flags; // CR flags for DMA mode + CYG_WORD dma_xmt_int_num; // DMA xmt completion interrupt + CYG_ADDRWORD dma_xmt_base; // Base address of DMA channel + int dma_xmt_len; // length transferred by DMA + cyg_interrupt dma_xmt_interrupt; + cyg_handle_t dma_xmt_interrupt_handle; + volatile cyg_bool dma_xmt_running; // expect tx _dma_ interrupts +#endif +} sh_scif_info; + +static bool sh_scif_init(struct cyg_devtab_entry *tab); +static bool sh_scif_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo sh_scif_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char sh_scif_getc(serial_channel *chan); +static Cyg_ErrNo sh_scif_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void sh_scif_start_xmit(serial_channel *chan); +static void sh_scif_stop_xmit(serial_channel *chan); + +static cyg_uint32 sh_scif_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_scif_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_scif_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_scif_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_scif_er_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_scif_er_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA +static cyg_uint32 sh_dma_xmt_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_dma_xmt_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +#endif + +static SERIAL_FUNS(sh_scif_funs, + sh_scif_putc, + sh_scif_getc, + sh_scif_set_config, + sh_scif_start_xmit, + sh_scif_stop_xmit + ); + +// Get the board specification +#include CYGDAT_IO_SERIAL_SH_SCIF_INL + +// Allow platform to define handling of additional config keys +#ifndef CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF +# define CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF +#endif + +// Internal function to actually configure the hardware to desired baud rate, +// etc. +static bool +sh_scif_config_port(serial_channel *chan, cyg_serial_info_t *new_config, + bool init) +{ + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr, _smr; + cyg_uint16 _sr; + CYG_ADDRWORD base = sh_chan->ctrl_base; + + // Check configuration request + if ((-1 == select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)]) + || -1 == select_stop_bits[new_config->stop] + || -1 == select_parity[new_config->parity] + || baud_divisor == 0) + return false; + + // Disable SCI interrupts while changing hardware + HAL_READ(base+SCIF_SCSCR, _scr); + HAL_WRITE(base+SCIF_SCSCR, 0); + + // Reset FIFO. + HAL_WRITE(base+SCIF_SCFCR, + CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST); + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + sh_chan->async_rxtx_mode = false; +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) { + // In IrDA mode, the configuration is hardwired and the mode + // bits should not be set +#ifdef CYGARC_REG_SCIF_SCSMR_IRMOD + _smr = CYGARC_REG_SCIF_SCSMR_IRMOD; +#elif defined(SCIF_SCIMR) + _smr = 0; + HAL_WRITE_UINT8(base+SCIF_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD); +#endif + } else +#endif + { + // Set databits, stopbits and parity. + _smr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA +#ifdef SCIF_SCIMR + // Disable IrDA mode + HAL_WRITE(base+SCIF_SCIMR, 0); +#endif +#endif + } + HAL_WRITE(base+SCIF_SCSMR, _smr); + + // Set baud rate. + _smr &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK; + _smr |= baud_divisor >> 8; + HAL_WRITE(base+SCIF_SCSMR, _smr); + HAL_WRITE_UINT8(base+SCIF_SCBRR, baud_divisor & 0xff); + + // FIXME: Should delay 1/<baud> second here. + + // Clear the status register (read first). + HAL_READ_UINT16(base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(base+SCIF_SCSSR, 0); + + // Bring FIFO out of reset and set FIFO trigger marks + // + // Note that the RX FIFO size must be smaller when flow control is + // enabled. This due to observations made by running the flow2 + // serial test. The automatic RTS de-assertion happens + // (apparently) when the FIFO fills past the trigger count - + // causing the sender to stop transmission. But there's a lag + // before transmission is stopped, and if the FIFO fills in that + // time, data will be lost. Thus, seeing as HW flow control is + // presumed used for prevention of data loss, set the trigger + // level so the sender has time to stop transmission before the + // FIFO fills up. + // + // The trigger setting of 8 allows test flow2 to complete without + // problems. It tests duplex data transmission at 115200 + // baud. Depending on the lag time between the de-assertion of RTS + // and actual transmission stop, it may be necessary to reduce the + // trigger level further. +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + HAL_WRITE(base+SCIF_SCFCR, + CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8); +#else + HAL_WRITE(base+SCIF_SCFCR, + CYGARC_REG_SCIF_SCFCR_RTRG_14|CYGARC_REG_SCIF_SCFCR_TTRG_8); +#endif + + if (init) { + // Always enable received and (for normal mode) transmitter + _scr = CYGARC_REG_SCIF_SCSCR_TE | CYGARC_REG_SCIF_SCSCR_RE; +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + if (sh_chan->async_rxtx_mode) + _scr = CYGARC_REG_SCIF_SCSCR_RE; +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) + _scr = CYGARC_REG_SCIF_SCSCR_RE; +#endif + + if (chan->in_cbuf.len != 0) + _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // enable rx interrupts + } + + HAL_WRITE(base+SCIF_SCSCR, _scr); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +sh_scif_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("SH SERIAL init - dev: %x.%d\n", + sh_chan->ctrl_base, sh_chan->rx_int_num); +#endif + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(sh_chan->tx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_tx_ISR, + sh_scif_tx_DSR, + &sh_chan->serial_tx_interrupt_handle, + &sh_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_unmask(sh_chan->tx_int_num); + sh_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + // Receive interrupt + cyg_drv_interrupt_create(sh_chan->rx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_rx_ISR, + sh_scif_rx_DSR, + &sh_chan->serial_rx_interrupt_handle, + &sh_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle); + // Receive error interrupt + cyg_drv_interrupt_create(sh_chan->er_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_er_ISR, + sh_scif_er_DSR, + &sh_chan->serial_er_interrupt_handle, + &sh_chan->serial_er_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle); +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + // Break error interrupt + cyg_drv_interrupt_create(sh_chan->br_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_er_ISR, + sh_scif_er_DSR, + &sh_chan->serial_br_interrupt_handle, + &sh_chan->serial_br_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_br_interrupt_handle); +#endif + // This unmasks all interrupt sources. + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); + } + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + // Assign DMA channel and interrupt if requested + if (sh_chan->dma_enable) { + // FIXME: Need a cleaner way to assign DMA channels + static int dma_channel = 0; +#if defined(CYGPKG_HAL_SH_SH2) + sh_chan->dma_xmt_int_num = dma_channel+CYGNUM_HAL_INTERRUPT_DMAC0_TE; +#elif defined(CYGPKG_HAL_SH_SH3) + sh_chan->dma_xmt_int_num = dma_channel+CYGNUM_HAL_INTERRUPT_DMAC_DEI0; +#else +# error "No interrupt defined for variant" +#endif + sh_chan->dma_xmt_base = (dma_channel*0x10)+CYGARC_REG_SAR0; + dma_channel++; + + // Enable the DMA engines. + HAL_WRITE_UINT16(CYGARC_REG_DMAOR, CYGARC_REG_DMAOR_DME); + + cyg_drv_interrupt_create(sh_chan->dma_xmt_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_dma_xmt_ISR, + sh_dma_xmt_DSR, + &sh_chan->dma_xmt_interrupt_handle, + &sh_chan->dma_xmt_interrupt); + cyg_drv_interrupt_attach(sh_chan->dma_xmt_interrupt_handle); + cyg_drv_interrupt_unmask(sh_chan->dma_xmt_int_num); + } + sh_chan->dma_xmt_running = false; +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + + sh_scif_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +sh_scif_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +sh_scif_putc(serial_channel *chan, unsigned char c) +{ + cyg_uint16 _fdr, _sr; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCFDR, _fdr); + if (((_fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) < 15) { +// Transmit FIFO has room for another char + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCFTDR, c); + // Clear FIFO-empty/transmit end flags (read back sr first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_TDFE); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +// Note: Input is running wo FIFO enabled, so the counter is not checked here. +static unsigned char +sh_scif_getc(serial_channel *chan) +{ + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + unsigned char c; + cyg_uint16 _sr; + + do { + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + } while ((_sr & CYGARC_REG_SCIF_SCSSR_RDF) == 0); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, c); + + // Clear buffer full flag (read back first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_RDF); + + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +sh_scif_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != sh_scif_config_port(chan, config, false) ) + return -EINVAL; + } + break; +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + sh_scif_info *ser_chan = (sh_scif_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->ctrl_base; + cyg_uint32 *f = (cyg_uint32 *)xbuf; + if ( *len < *f ) + return -EINVAL; + + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) { + // Control RX RTC/CTS flow control by disabling/enabling + // RX interrupt. When disabled, FIFO will fill up and + // clear RTS. + cyg_uint8 _scscr; + HAL_READ(base+SCIF_SCSCR, _scscr); + if (*f) // we should throttle + _scscr &= ~CYGARC_REG_SCIF_SCSCR_RIE; + else // we should no longer throttle + _scscr |= CYGARC_REG_SCIF_SCSCR_RIE; + HAL_WRITE(base+SCIF_SCSCR, _scscr); + } +#ifdef CYGHWR_SH_SCIF_FLOW_DSRDTR + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX ) { + // Control RX DSR/DTR flow control via platform specific macro + CYGHWR_SH_SCIF_FLOW_DSRDTR_RX(chan, *f); + } +#endif + } + break; + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + { + // Handle CTS/RTS flag + if ( chan->config.flags & + (CYGNUM_SERIAL_FLOW_RTSCTS_RX | CYGNUM_SERIAL_FLOW_RTSCTS_TX )){ + cyg_uint8 _scfcr; + sh_scif_info *ser_chan = (sh_scif_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->ctrl_base; + cyg_uint8 *f = (cyg_uint8 *)xbuf; + + HAL_READ(base+SCIF_SCFCR, _scfcr); + if (*f) // enable RTS/CTS flow control + _scfcr |= CYGARC_REG_SCIF_SCFCR_MCE; + else // disable RTS/CTS flow control + _scfcr &= ~CYGARC_REG_SCIF_SCFCR_MCE; + HAL_WRITE(base+SCIF_SCFCR, _scfcr); + } +#ifndef CYGHWR_SH_SCIF_FLOW_DSRDTR + // Clear DSR/DTR flag as it's not supported. + if (chan->config.flags & + (CYGNUM_SERIAL_FLOW_DSRDTR_RX|CYGNUM_SERIAL_FLOW_DSRDTR_TX)) { + chan->config.flags &= ~(CYGNUM_SERIAL_FLOW_DSRDTR_RX| + CYGNUM_SERIAL_FLOW_DSRDTR_TX); + return -EINVAL; + } +#else + return CYGHWR_SH_SCIF_FLOW_DSRDTR_CONFIG(chan); +#endif + } + break; +#endif + + CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF + + default: + return -EINVAL; + } + return ENOERR; +} + + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + +// Must be called with serial interrupts disabled +static xmt_req_reply_t +sh_scif_start_dma_xmt(serial_channel *chan) +{ + int chars_avail; + unsigned char* chars; + xmt_req_reply_t res; + + // We can transfer the full buffer - ask how much to transfer + res = (chan->callbacks->data_xmt_req)(chan, chan->out_cbuf.len, + &chars_avail, &chars); + if (CYG_XMT_OK == res) { + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint32 dma_base = sh_chan->dma_xmt_base; + cyg_uint32 scr; + + // Save the length so it can be used in the DMA DSR + sh_chan->dma_xmt_len = chars_avail; + + // Flush cache for the area + HAL_DCACHE_FLUSH((cyg_haladdress)chars, chars_avail); + + // Program DMA + HAL_WRITE_UINT32(dma_base+CYGARC_REG_CHCR, 0); // disable and clear + HAL_WRITE_UINT32(dma_base+CYGARC_REG_SAR, (cyg_uint32)chars); + HAL_WRITE_UINT32(dma_base+CYGARC_REG_DAR, + (sh_chan->ctrl_base+SCIF_SCFTDR) & 0x0fffffff); + HAL_WRITE_UINT32(dma_base+CYGARC_REG_DMATCR, chars_avail); + // Source increments, dest static, byte transfer, enable + // interrupt on completion. + HAL_WRITE_UINT32(dma_base+CYGARC_REG_CHCR, + sh_chan->dma_xmt_cr_flags | CYGARC_REG_CHCR_SM0 \ + | CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE); + + // Enable serial interrupts + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, scr); + scr |= CYGARC_REG_SCIF_SCSCR_TIE; + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, scr); + } + + return res; +} + +// must be called with serial interrupts masked +static void +sh_scif_stop_dma_xmt(serial_channel *chan) +{ + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint32 dma_base = sh_chan->dma_xmt_base; + cyg_uint32 cr; + + // Disable DMA engine and interrupt enable flag. Should be safe + // to do since it's triggered by the serial interrupt which has + // already been disabled. + HAL_READ_UINT32(dma_base+CYGARC_REG_CHCR, cr); + cr &= ~(CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE); + HAL_WRITE_UINT32(dma_base+CYGARC_REG_CHCR, cr); + + // Did transfer complete? + HAL_READ_UINT32(dma_base+CYGARC_REG_CHCR, cr); + if (0 == (cr & CYGARC_REG_CHCR_TE)) { + // Transfer incomplete. Report actually transferred amount of data + // back to the serial driver. + int chars_left; + HAL_READ_UINT32(dma_base+CYGARC_REG_DMATCR, chars_left); + CYG_ASSERT(chars_left > 0, "DMA incomplete, but no data left"); + CYG_ASSERT(chars_left <= sh_chan->dma_xmt_len, + "More data remaining than was attempted transferred"); + + (chan->callbacks->data_xmt_done)(chan, + sh_chan->dma_xmt_len - chars_left); + } + +#ifdef CYGDBG_USE_ASSERTS + { + cyg_uint32 dmaor; + HAL_READ_UINT32(CYGARC_REG_DMAOR, dmaor); + CYG_ASSERT(0== (dmaor & (CYGARC_REG_DMAOR_AE | CYGARC_REG_DMAOR_NMIF)), + "DMA error"); + } +#endif + + // The DMA engine is free again. + sh_chan->dma_xmt_running = false; +} + +// Serial xmt DMA completion interrupt handler (ISR) +static cyg_uint32 +sh_dma_xmt_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint32 _cr; + + // mask serial interrupt + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _cr); + _cr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit interrupt + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _cr); + + // mask DMA interrupt and disable engine + HAL_READ_UINT32(sh_chan->dma_xmt_base+CYGARC_REG_CHCR, _cr); + _cr &= ~(CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE); + HAL_WRITE_UINT32(sh_chan->dma_xmt_base+CYGARC_REG_CHCR, _cr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial xmt DMA completion interrupt handler (DSR) +static void +sh_dma_xmt_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + + (chan->callbacks->data_xmt_done)(chan, sh_chan->dma_xmt_len); + + // Try to load the engine again. + sh_chan->dma_xmt_running = + (CYG_XMT_OK == sh_scif_start_dma_xmt(chan)) ? true : false; +} +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + + +// Enable the transmitter on the device +static void +sh_scif_start_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + xmt_req_reply_t _block_status = CYG_XMT_DISABLED; + + if (sh_chan->tx_enabled) + return; + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + // Check if the engine is already running. If so, return. Note + // that there will never be a race on this flag - the caller of + // this function is respecting a per-channel lock. + if (sh_chan->dma_xmt_running) + return; + // If the channel uses DMA, try to start a DMA job for this - + // but handle the case where the job doesn't start by falling + // back to the FIFO/interrupt based code. + if (sh_chan->dma_enable) { + _block_status = sh_scif_start_dma_xmt(chan); + CYG_ASSERT(_block_status != CYG_XMT_EMPTY, + "start_xmit called with empty buffers!"); + sh_chan->dma_xmt_running = + (CYG_XMT_OK == _block_status) ? true : false; + } +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + + if (CYG_XMT_DISABLED == _block_status) { + // Mask interrupts while changing the CR since a rx + // interrupt or another thread doing the same in the + // middle of this would result in a bad CR state. + cyg_drv_isr_lock(); + { + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_TIE; // Enable xmit interrupt +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) { + // Enable transmitter - this automatically disables + // the receiver in the hardware. Doing it explicitly + // (like for async RX/TX below) causes more spurious + // characters to be read when re-enabling the + // receiver. + _scr |= CYGARC_REG_SCIF_SCSCR_TE; + } +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + if (sh_chan->async_rxtx_mode) { + // Enable transmitter + _scr |= CYGARC_REG_SCIF_SCSCR_TE; + // Disable receiver + _scr &= ~CYGARC_REG_SCIF_SCSCR_RE; + } +#endif + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + sh_chan->tx_enabled = true; + } + cyg_drv_isr_unlock(); + } +} + +// Disable the transmitter on the device +static void +sh_scif_stop_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + + // In IrDA and async mode the transmitter needs to be disabled, so + // wait for transmission to complete within reason: disable it + // after 0.1s + if (0 +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + || sh_chan->irda_mode +#endif +#if defined(CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX) + || sh_chan->async_rxtx_mode +#endif + ) { + cyg_uint16 sr; + int i = 1000; + do { + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, sr); + if (sr & CYGARC_REG_SCIF_SCSSR_TEND) break; + HAL_DELAY_US(100); + } while (i-- > 0); + } + + // Mask interrupts while changing the CR since a rx interrupt or + // another thread doing the same in the middle of this would + // result in a bad CR state. + cyg_drv_isr_lock(); + { + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit interrupt +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) { +#ifdef CYGHWR_IO_SERIAL_SH_SCIF_IRDA_TXRX_COMPENSATION + // In IrDA mode there will be generated spurious RX + // events when the TX unit is switched on. Eat that + // character. + cyg_uint8 _junk; + cyg_uint16 _sr; + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, _junk); + + // Clear buffer full flag (read back first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR)); +#endif + // Disable transmitter + _scr &= ~CYGARC_REG_SCIF_SCSCR_TE; + } +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + if (sh_chan->async_rxtx_mode) { + // Enable receiver again + _scr |= CYGARC_REG_SCIF_SCSCR_RE; + // Disable transmitter + _scr &= ~CYGARC_REG_SCIF_SCSCR_TE; + } +#endif + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + } + cyg_drv_isr_unlock(); + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + // If the channel uses DMA, stop the DMA engine. + if (sh_chan->dma_xmt_running) + sh_scif_stop_dma_xmt(chan); + else // dangling else! +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + sh_chan->tx_enabled = false; +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +sh_scif_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // mask out tx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +sh_scif_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + xmt_req_reply_t _block_status = CYG_XMT_DISABLED; + cyg_uint16 _fdr, _sr; + int _space, _chars_avail; + unsigned char* _chars; + CYG_ADDRWORD _base = sh_chan->ctrl_base; + + // Always check if we're supposed to be enabled; the driver runs + // with DSRs disabled, and a DSR may have been posted (but not + // executed) before the interrupt was masked. + if (!sh_chan->tx_enabled) + return; + +#ifdef CYGHWR_SH_SCIF_FLOW_DSRDTR + CYGHWR_SH_SCIF_FLOW_DSRDTR_TX(chan); +#endif + + // How many chars can we stuff into the FIFO? + HAL_READ_UINT16(_base+SCIF_SCFDR, _fdr); + _space = 16 - ((_fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift); + + // Try to do the transfer most efficiently + _block_status = (chan->callbacks->data_xmt_req)(chan, _space, + &_chars_avail, &_chars); + if (CYG_XMT_OK == _block_status) { + // Transfer the data in block(s). + do { + int i = _chars_avail; + while (i--) { + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCFTDR, *_chars++); + _space--; + } + (chan->callbacks->data_xmt_done)(chan, _chars_avail); + } while (_space > 0 && + (CYG_XMT_OK == (chan->callbacks->data_xmt_req)(chan, _space, + &_chars_avail, + &_chars))); + } else if (CYG_XMT_DISABLED == _block_status) { + // Transfer char-by-char, but stop if the transmitter + // gets disabled. + while (_space-- && sh_chan->tx_enabled) + (chan->callbacks->xmt_char)(chan); + } + + // Clear FIFO-empty/transmit end flags (read back sr first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_TDFE); + + if (sh_chan->tx_enabled) { + cyg_uint8 _scr; + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_TIE; // unmask tx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + } +} + +// Serial I/O - low level RX interrupt handler (ISR) +static cyg_uint32 +sh_scif_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +sh_scif_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + cyg_uint16 _fdr, _sr; + int _avail, _space_avail; + unsigned char* _space; + rcv_req_reply_t _block_status; + + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCFDR, _fdr); + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + + _avail = _fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK; + if (_avail > 0) { + _block_status = (chan->callbacks->data_rcv_req)(chan, _avail, + &_space_avail, &_space); + if (CYG_RCV_OK == _block_status) { + // Transfer the data in block(s). + do { + int i = _space_avail; + while(i--) { + cyg_uint8 _c; + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, _c); + *_space++ = _c; + _avail--; + } + (chan->callbacks->data_rcv_done)(chan, _space_avail); + } while (_avail > 0 && + (CYG_RCV_OK == (chan->callbacks->data_rcv_req)(chan, _avail, + &_space_avail, + &_space))); + } else { + // Transfer the data char-by-char both for CYG_RCV_FULL + // and CYG_RCV_DISABLED, leaving all policy decisions with + // the IO driver. + while(_avail--) { + cyg_uint8 _c; + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + } + } else { + CYG_ASSERT(_avail > 0, "No data to be read in RX DSR"); + } + + // Clear buffer full flag (read back first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR)); + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); +} + +// Serial I/O - low level error interrupt handler (ISR) +static cyg_uint32 +sh_scif_er_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level error interrupt handler (DSR) +static void +sh_scif_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint16 _ssr, _ssr_mask; +#ifdef SCIF_SC2SSR + cyg_uint8 _ssr2; +#endif + cyg_uint8 _scr; +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + cyg_serial_line_status_t stat; +#endif + + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _ssr); + _ssr_mask = CYGARC_REG_SCIF_SCSSR_CLEARMASK; + // Clear the ER bit + _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_ER; + + +#ifdef SCIF_SC2SSR + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SC2SSR, _ssr2); + if (_ssr2 & CYGARC_REG_SCIF_SC2SSR_ORER) { + _ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER; + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SC2SSR, _ssr2); + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat ); + } +#endif + if (_ssr & CYGARC_REG_SCIF_SCSSR_FER) { + // _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_FER; // FER is read-only +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat ); +#endif + } + if (_ssr & CYGARC_REG_SCIF_SCSSR_PER) { + // _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_PER; // PER is read-only +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat ); +#endif + } + if (_ssr & CYGARC_REG_SCIF_SCSSR_BRK) { + _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_BRK; +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_BREAK; + (chan->callbacks->indicate_status)(chan, &stat ); +#endif + } + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _ssr_mask); + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); +} + +#endif // ifdef CYGDAT_IO_SERIAL_SH_SCIF_INL diff --git a/ecos/packages/devs/serial/sh/se77x9/current/ChangeLog b/ecos/packages/devs/serial/sh/se77x9/current/ChangeLog new file mode 100644 index 0000000..a8fab66 --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/ChangeLog @@ -0,0 +1,41 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_se77x9.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_se77x9_scif.inl: CYGINT_IO_SERIAL_SH_SCIF_DMA is + now booldata. Rename sh3_scif to sh_scif. Register renaming. + +2001-06-19 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_se77x9.cdl: Disable COM1 driver for now since it + breaks eCos. + +2001-06-18 Jesper Skov <jskov@redhat.com> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/se77x9/current/cdl/ser_sh_se77x9.cdl b/ecos/packages/devs/serial/sh/se77x9/current/cdl/ser_sh_se77x9.cdl new file mode 100644 index 0000000..aac93f0 --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/cdl/ser_sh_se77x9.cdl @@ -0,0 +1,193 @@ +# ==================================================================== +# +# ser_sh_se77x9.cdl +# +# eCos serial SH/SE77X9 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 2001-06-18 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SE77X9 { + display "SH3 SE77X9 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_SH77X9_SE77X9 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Hitachi SH3 SE77X9 board, based on the generic SH SCI driver." + + + # FIXME: This really belongs in the SH_SCIF package + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_REQUIRED { + display "SH SCI driver required" + } + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/sh_sh3_se77x9_16x5x.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_sh_se77x9.h>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_INL <cyg/io/sh_sh3_se77x9_scif.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_CFG <pkgconf/io_serial_sh_se77x9.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_SH_SE77X9_COM1 { + display "SH SE77X9 serial 1 driver (SuperIO)" + flavor bool + calculated 0 + description " + This option includes the serial device driver for the COM1 + port. FIXME: Disabled due to being broken." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_SH_SE77X9_COM1_NAME { + display "Device name for COM1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for COM1." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BAUD { + display "Baud rate for COM1" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the COM1 port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE { + display "Buffer size for COM1" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the COM1 port." + } + } + + # SCIF port + cdl_component CYGPKG_IO_SERIAL_SH_SE77X9_COM2 { + display "SE77X9 serial, SCIF port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for SCIF + port 2." + + implements CYGINT_IO_SERIAL_SH_SCIF_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_SH_SE77X9_COM2_NAME { + display "Device name" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the serial + port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BAUD { + display "Baud rate" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the serial driver." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE { + display "Buffer size" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the serial driver." + } + + cdl_option CYGSEM_IO_SERIAL_SH_SE77X9_COM2_DMA { + display "Enable SCIF serial driver DMA" + active_if CYGINT_HAL_SH_DMA_CHANNELS + implements CYGINT_HAL_SH_DMA_CHANNELS_USED + implements CYGINT_IO_SERIAL_SH_SCIF_DMA + default_value 1 + description " + Enable DMA for this port." + } + } + + cdl_component CYGPKG_IO_SERIAL_SH_SE77X9_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_SE77X9_COM2 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-se77x9\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_SE77X9_COM2_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty2\"" + } + } +} +# EOF ser_sh_se77x9.cdl diff --git a/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_16x5x.inl b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_16x5x.inl new file mode 100644 index 0000000..5ec4e5b --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_16x5x.inl @@ -0,0 +1,123 @@ +#ifndef CYGONCE_DEVS_SH_SE77X9_16X5X_H +#define CYGONCE_DEVS_SH_SE77X9_16X5X_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_se77x9_16x5x.inl +// +// Serial I/O specification for Hitachi SE77X9 platform. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-06-18 +// Purpose: Specifies serial resources for the platform. +// Description: This file can be include from the 16x5x driver sources. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial_sh_se77x9.h> + +//----------------------------------------------------------------------------- +// Baud rate specification, based on raw 1.8462MHz clock (/16) + +static unsigned short select_baud[] = { + 0, // Unused + 2307, // 50 + 1538, // 75 + 1048, // 110 + 857, // 134.5 + 769, // 150 + 576, // 200 + 384, // 300 + 192, // 600 + 96, // 1200 + 64, // 1800 + 48, // 2400 + 32, // 3600 + 24, // 4800 + 16, // 7200 + 12, // 9600 + 8, // 14400 + 6, // 19200 + 3, // 38400 + 2, // 57600 + 1, // 115200 + 0, // 230400 +}; + +#ifdef CYGPKG_IO_SERIAL_SH_SE77X9_COM1 +static pc_serial_info se77x9_serial_info1 = {0xb04007f0, CYGNUM_HAL_INTERRUPT_COM1}; +#if CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE > 0 +static unsigned char se77x9_serial_out_buf1[CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE]; +static unsigned char se77x9_serial_in_buf1[CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(se77x9_serial_channel1, + pc_serial_funs, + se77x9_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &se77x9_serial_out_buf1[0], sizeof(se77x9_serial_out_buf1), + &se77x9_serial_in_buf1[0], sizeof(se77x9_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(se77x9_serial_channel1, + pc_serial_funs, + se77x9_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(se77x9_serial_io1, + CYGDAT_IO_SERIAL_SH_SE77X9_COM1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &se77x9_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_SH_SE77X9_COM1 + +#endif // CYGONCE_DEVS_SH_SE77X9_SCIF_H diff --git a/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_scif.inl b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_scif.inl new file mode 100644 index 0000000..a9905f0 --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_scif.inl @@ -0,0 +1,113 @@ +#ifndef CYGONCE_DEVS_SH_SE77X9_SCIF_H +#define CYGONCE_DEVS_SH_SE77X9_SCIF_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_se77x9_scif.inl +// +// Serial I/O specification for Hitachi SE77X9 platform. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-06-18 +// Purpose: Specifies serial resources for the platform. +// Description: This file can be include from either SCI or SCIF/IRDA driver +// sources and should specify driver information as required +// for the platform. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial_sh_se77x9.h> + +#ifdef CYGPKG_IO_SERIAL_SH_SE77X9_COM2 +static sh_scif_info se77x9_serial_info2 = { + er_int_num : CYGNUM_HAL_INTERRUPT_SCIF_ERI2, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_RXI2, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_TXI2, + ctrl_base : CYGARC_REG_SCIF_SCSMR2, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA +# ifdef CYGSEM_IO_SERIAL_SH_SE77X9_COM2_DMA + dma_enable : true,// we want DMA for this channel + dma_xmt_cr_flags : CYGARC_REG_CHCR_RS_SCIF_TX +# else + dma_enable : false // No DMA +# endif +#endif +}; + +#if CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE > 0 +static unsigned char se77x9_serial_out_buf2[CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE]; +static unsigned char se77x9_serial_in_buf2[CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(se77x9_serial_channel2, + sh_scif_funs, + se77x9_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &se77x9_serial_out_buf2[0], + sizeof(se77x9_serial_out_buf2), + &se77x9_serial_in_buf2[0], + sizeof(se77x9_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(se77x9_serial_channel2, + sh_scif_funs, + se77x9_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io2, + CYGDAT_IO_SERIAL_SH_SE77X9_COM2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_scif_init, + sh_scif_lookup, // Serial driver may need initializing + &se77x9_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_SH_SE77X9_COM2 + +#endif // CYGONCE_DEVS_SH_SE77X9_SCIF_H diff --git a/ecos/packages/devs/serial/sh/sh4_202_md/current/ChangeLog b/ecos/packages/devs/serial/sh/sh4_202_md/current/ChangeLog new file mode 100644 index 0000000..5a1f496 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sh4_202_md/current/ChangeLog @@ -0,0 +1,27 @@ +2003-09-18 Jonathan Larmour <jifl@eCosCentric.com> + + * New package, based on se77x9 driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/sh4_202_md/current/cdl/ser_sh4_202_md.cdl b/ecos/packages/devs/serial/sh/sh4_202_md/current/cdl/ser_sh4_202_md.cdl new file mode 100644 index 0000000..e365b57 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sh4_202_md/current/cdl/ser_sh4_202_md.cdl @@ -0,0 +1,149 @@ +# ==================================================================== +# +# ser_sh4_202_md.cdl +# +# eCos SH4-202 MicroDev serial configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jlarmour +# Contributors: +# Date: 2003-09-18 +# Description: Based on se77x9 driver by jskov. +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SH4_202_MD { + display "SH4-202 MicroDev serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_SH4_202_MD + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + SuperH SH4-202 MicroDev board, based on the generic SH SCIF driver." + + + # FIXME: This really belongs in the SH_SCIF package + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_REQUIRED { + display "SH SCIF driver required" + } + + # SCIF port + cdl_component CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 { + display "SH4-202 MicroDev SCIF serial port driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SCIF + port on the SH4-202 MicroDev development board." + + implements CYGINT_IO_SERIAL_SH_SCIF_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + implements CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + implements CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_INL <cyg/io/sh4_202_md_scif.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_CFG <pkgconf/io_serial_sh_sh4_202_md.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_option CYGDAT_IO_SERIAL_SH_SH4_202_MD_SERIAL1_NAME { + display "Device name" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the serial + port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BAUD { + display "Baud rate" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the serial driver." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE { + display "Buffer size" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the serial driver." + } + +# DMA not yet implemented +# cdl_option CYGSEM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_DMA { +# display "Enable SCIF serial driver DMA" +# active_if CYGINT_HAL_SH_DMA_CHANNELS +# implements CYGINT_HAL_SH_DMA_CHANNELS_USED +# implements CYGINT_IO_SERIAL_SH_SCIF_DMA +# default_value 1 +# description " +# Enable DMA for this port." +# } +# } + + cdl_component CYGPKG_IO_SERIAL_SH_SH4_202_MD_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-sh4_202_md\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_SH4_202_MD_SERIAL1_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} +# EOF ser_sh_sh4_202_md.cdl diff --git a/ecos/packages/devs/serial/sh/sh4_202_md/current/include/sh4_202_md_scif.inl b/ecos/packages/devs/serial/sh/sh4_202_md/current/include/sh4_202_md_scif.inl new file mode 100644 index 0000000..6745f61 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sh4_202_md/current/include/sh4_202_md_scif.inl @@ -0,0 +1,117 @@ +#ifndef CYGONCE_DEVS_SH_SH4_202_MD_SCIF_H +#define CYGONCE_DEVS_SH_SH4_202_MD_SCIF_H + +//========================================================================== +// +// devs/serial/sh/sh4_202_md_scif.inl +// +// Serial I/O specification for SuperH SH4-202 MicroDev development board +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2003-09-18 +// Purpose: Specifies serial resources for the platform. +// Description: This file can be include from either SCI or SCIF/IRDA driver +// sources and should specify driver information as required +// for the platform. This file was derived from the se77x9 +// driver. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial_sh_sh4_202_md.h> + +#ifdef CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 +static sh_scif_info sh4_202_md_serial_info1 = { + er_int_num : CYGNUM_HAL_INTERRUPT_SCIF_ERI, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_RXI, + br_int_num : CYGNUM_HAL_INTERRUPT_SCIF_BRI, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_TXI, + ctrl_base : CYGARC_REG_SCIF_SCSMR2, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA +# ifdef CYGSEM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_DMA + dma_enable : true,// we want DMA for this channel + dma_xmt_cr_flags : CYGARC_REG_CHCR_RS_SCIF_TX +# else + dma_enable : false // No DMA +# endif +#endif +}; + +#if CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE > 0 +static unsigned char sh4_202_md_serial_out_buf1[CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE]; +static unsigned char sh4_202_md_serial_in_buf1[CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sh4_202_md_serial_channel1, + sh_scif_funs, + sh4_202_md_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sh4_202_md_serial_out_buf1[0], + sizeof(sh4_202_md_serial_out_buf1), + &sh4_202_md_serial_in_buf1[0], + sizeof(sh4_202_md_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(sh4_202_md_serial_channel1, + sh_scif_funs, + sh4_202_md_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io1, + CYGDAT_IO_SERIAL_SH_SH4_202_MD_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_scif_init, + sh_scif_lookup, // Serial driver may need initializing + &sh4_202_md_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 + +#endif // CYGONCE_DEVS_SH_SH4_202_MD_SCIF_H + +// EOF sh4_202_md_scif.inl diff --git a/ecos/packages/devs/serial/sparclite/sleb/current/ChangeLog b/ecos/packages/devs/serial/sparclite/sleb/current/ChangeLog new file mode 100644 index 0000000..eab025c --- /dev/null +++ b/ecos/packages/devs/serial/sparclite/sleb/current/ChangeLog @@ -0,0 +1,1187 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sparclite_sleb.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_sparclite_sleb.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sparclite_sleb.cdl: Moved testing parameters here. + + * src/sleb_sdtr.c: Removed obsolete sleb_sdtr_set_config function. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sleb_sdtr.c (sleb_sdtr_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sparclite_sleb.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sparclite/sleb/current/cdl/ser_sparclite_sleb.cdl b/ecos/packages/devs/serial/sparclite/sleb/current/cdl/ser_sparclite_sleb.cdl new file mode 100644 index 0000000..6e40576 --- /dev/null +++ b/ecos/packages/devs/serial/sparclite/sleb/current/cdl/ser_sparclite_sleb.cdl @@ -0,0 +1,209 @@ +# ==================================================================== +# +# ser_sparclite_sleb.cdl +# +# eCos serial SPARClite/SLEB configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_SPARCLITE_SLEB { + display "SPARClite SLEB serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SPARCLITE_SLEB + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + SPARClite SLEB." + + compile -library=libextras.a sleb_sdtr.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_sparclite_sleb.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1 { + display "SPARClite SLEB serial CON1 port driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SPARClite + SLEB CON1 port." + + cdl_option CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON1_NAME { + display "Device name for SPARClite SLEB serial CON1 port" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name for the SPARClite SLEB + CON1 port." + } + + cdl_option CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BAUD { + display "Baud rate for the SPARClite SLEB serial CON1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 19200 + description " + This option specifies the default baud rate (speed) for the + SPARClite SLEB CON1." + } + + cdl_option CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE { + display "Buffer size for the SPARClite SLEB serial CON1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the SPARClite SLEB CON1." + } +} +cdl_component CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON2 { + display "SPARClite SLEB serial CON2 port driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SPARClite + SLEB CON2 port." + + cdl_option CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON2_NAME { + display "Device name for SPARClite SLEB serial CON2 port" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the SPARClite SLEB + CON2 port." + } + + cdl_option CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BAUD { + display "Baud rate for the SPARClite SLEB serial CON2 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 19200 + description " + This option specifies the default baud rate (speed) for the + SPARClite SLEB CON2." + } + + cdl_option CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE { + display "Buffer size for the SPARClite SLEB serial CON2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the SPARClite SLEB CON2." + } +} + + cdl_component CYGPKG_IO_SERIAL_SPARCLITE_SLEB_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_SPARCLITE_SLEB_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1 + + implements CYGINT_IO_SERIAL_TEST_SKIP_38400 + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sparcl\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_OVERRIDE_INT_1 CYGNUM_HAL_INTERRUPT_9" + puts $::cdl_header "#define CYGPRI_SER_TEST_OVERRIDE_INT_2 CYGNUM_HAL_INTERRUPT_10" + } + } +} + +# EOF ser_sparclite_sleb.cdl diff --git a/ecos/packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.c b/ecos/packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.c new file mode 100644 index 0000000..847625e --- /dev/null +++ b/ecos/packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.c @@ -0,0 +1,400 @@ +//========================================================================== +// +// io/serial/sparclite/sleb_sdtr.c +// +// Serial I/O interface module for SPARClite Eval Board (SLEB) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: SLEB serial I/O module +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/io.h> +#include <pkgconf/io_serial.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB + +#include "sleb_sdtr.h" + +extern void diag_printf(const char *fmt, ...); + +#define BUFSIZE 128 + +typedef struct sleb_sdtr_info { + CYG_ADDRWORD base; + CYG_WORD tx_int_num; + CYG_WORD rx_int_num; + cyg_interrupt tx_serial_interrupt; + cyg_handle_t tx_serial_interrupt_handle; + cyg_interrupt rx_serial_interrupt; + cyg_handle_t rx_serial_interrupt_handle; + cyg_uint8 cmd_reg; + bool xmit_enabled; +} sleb_sdtr_info; + +static bool sleb_sdtr_init(struct cyg_devtab_entry *tab); +static bool sleb_sdtr_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo sleb_sdtr_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char sleb_sdtr_getc(serial_channel *chan); +static Cyg_ErrNo sleb_sdtr_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void sleb_sdtr_start_xmit(serial_channel *chan); +static void sleb_sdtr_stop_xmit(serial_channel *chan); + +static cyg_uint32 sleb_sdtr_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sleb_sdtr_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 sleb_sdtr_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sleb_sdtr_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(sleb_sdtr_funs, + sleb_sdtr_putc, + sleb_sdtr_getc, + sleb_sdtr_set_config, + sleb_sdtr_start_xmit, + sleb_sdtr_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1 +static sleb_sdtr_info sleb_sdtr_info0 = {SLEB_SDTR0_BASE, SLEB_SDTR0_TX_INT, SLEB_SDTR0_RX_INT}; +#if CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE > 0 +static unsigned char sleb_sdtr_out_buf0[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE]; +static unsigned char sleb_sdtr_in_buf0[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sleb_sdtr_channel0, + sleb_sdtr_funs, + sleb_sdtr_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sleb_sdtr_out_buf0[0], sizeof(sleb_sdtr_out_buf0), + &sleb_sdtr_in_buf0[0], sizeof(sleb_sdtr_in_buf0) + ); +#else +static SERIAL_CHANNEL(sleb_sdtr_channel0, + sleb_sdtr_funs, + sleb_sdtr_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sleb_sdtr_io0, + CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sleb_sdtr_init, + sleb_sdtr_lookup, // Serial driver may need initializing + &sleb_sdtr_channel0 + ); +#endif // CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1 + +#ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON2 +static sleb_sdtr_info sleb_sdtr_info1 = {SLEB_SDTR1_BASE, SLEB_SDTR1_TX_INT, SLEB_SDTR1_RX_INT}; +#if CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE > 0 +static unsigned char sleb_sdtr_out_buf1[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE]; +static unsigned char sleb_sdtr_in_buf1[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sleb_sdtr_channel1, + sleb_sdtr_funs, + sleb_sdtr_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sleb_sdtr_out_buf1[0], sizeof(sleb_sdtr_out_buf1), + &sleb_sdtr_in_buf1[0], sizeof(sleb_sdtr_in_buf1) + ); +#else +static SERIAL_CHANNEL(sleb_sdtr_channel1, + sleb_sdtr_funs, + sleb_sdtr_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sleb_sdtr_io1, + CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sleb_sdtr_init, + sleb_sdtr_lookup, // Serial driver may need initializing + &sleb_sdtr_channel1 + ); +#endif // CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON2 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +sleb_sdtr_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + CYG_ADDRWORD port = sdtr_chan->base; + cyg_int32 baud_divisor; + cyg_int32 clk, tval; + unsigned char mode; +#if 0 + if ((new_config->baud < CYGNUM_SERIAL_BAUD_MIN) || (new_config->baud > CYGNUM_SERIAL_BAUD_MAX)) + return false; // Invalid baud rate +#endif + baud_divisor = select_baud[new_config->baud]; + if (baud_divisor == 0) + return false; // Unsupported baud rate + // Reset the port + HAL_SPARC_86940_WRITE(SDTR_CONTROL(port), SDTR_CMD_RST); + // Write the mode + mode = SDTR_MODE_MODE_ASYNC16 | + select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_SPARC_86940_WRITE(SDTR_CONTROL(port), mode); + // Set baud rate clock. + // ***** CAUTION! Both ports use the same time, thus they must both run at the same baud rate! + clk = *SLEB_CLOCK_SWITCH; // Compute board speed + if (clk & 0x80) clk = 10; + clk = (clk & 0x3F) * 1000000; // in MHz + tval = (clk / (baud_divisor * 32)) - 1; + HAL_SPARC_86940_WRITE(SLEB_TIMER3_RELOAD, tval); + // Set up control register + sdtr_chan->cmd_reg = SDTR_CMD_RTS | SDTR_CMD_DTR | SDTR_CMD_TxEN; +#ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1 + // Cygmon needs the receiver + if ((chan->out_cbuf.len != 0) || (chan == &sleb_sdtr_channel0)) { +#else + if (chan->out_cbuf.len != 0) { +#endif + sdtr_chan->cmd_reg |= SDTR_CMD_RxEN; + } + if (init) { + sdtr_chan->xmit_enabled = false; + } + HAL_SPARC_86940_WRITE(SDTR_CONTROL(port), sdtr_chan->cmd_reg); + if (new_config != &chan->config) + chan->config = *new_config; + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +sleb_sdtr_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("SLEB SERIAL init - dev: %x.%d.%d\n", sdtr_chan->base, sdtr_chan->tx_int_num, sdtr_chan->rx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(sdtr_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sleb_sdtr_tx_ISR, + sleb_sdtr_tx_DSR, + &sdtr_chan->tx_serial_interrupt_handle, + &sdtr_chan->tx_serial_interrupt); + cyg_drv_interrupt_attach(sdtr_chan->tx_serial_interrupt_handle); + cyg_drv_interrupt_mask(sdtr_chan->tx_int_num); + cyg_drv_interrupt_create(sdtr_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sleb_sdtr_rx_ISR, + sleb_sdtr_rx_DSR, + &sdtr_chan->rx_serial_interrupt_handle, + &sdtr_chan->rx_serial_interrupt); + cyg_drv_interrupt_attach(sdtr_chan->rx_serial_interrupt_handle); + cyg_drv_interrupt_unmask(sdtr_chan->rx_int_num); + } + sleb_sdtr_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +sleb_sdtr_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +sleb_sdtr_putc(serial_channel *chan, unsigned char c) +{ + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + CYG_ADDRWORD port = sdtr_chan->base; + cyg_uint8 status; + HAL_SPARC_86940_READ(SDTR_STATUS(port), status); + if (status & SDTR_STAT_TxRDY) { +// Transmit buffer is empty + HAL_SPARC_86940_WRITE(SDTR_TXDATA(port), c); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +sleb_sdtr_getc(serial_channel *chan) +{ + unsigned char c; + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + CYG_ADDRWORD port = sdtr_chan->base; + cyg_uint8 status; + HAL_SPARC_86940_READ(SDTR_STATUS(port), status); + while ((status & SDTR_STAT_RxRDY) == 0) + HAL_SPARC_86940_READ(SDTR_STATUS(port), status); // Wait for char + HAL_SPARC_86940_READ(SDTR_RXDATA(port), c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +sleb_sdtr_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != sleb_sdtr_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +sleb_sdtr_start_xmit(serial_channel *chan) +{ + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + sdtr_chan->xmit_enabled = true; + cyg_drv_interrupt_unmask(sdtr_chan->tx_int_num); +} + +// Disable the transmitter on the device +static void +sleb_sdtr_stop_xmit(serial_channel *chan) +{ + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + cyg_drv_interrupt_mask(sdtr_chan->tx_int_num); + sdtr_chan->xmit_enabled = false; +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +sleb_sdtr_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + cyg_drv_interrupt_mask(sdtr_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(sdtr_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +sleb_sdtr_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (sdtr_chan->xmit_enabled) + cyg_drv_interrupt_unmask(sdtr_chan->tx_int_num); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +sleb_sdtr_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + cyg_drv_interrupt_mask(sdtr_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +sleb_sdtr_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv; + CYG_ADDRWORD port = sdtr_chan->base; + cyg_uint8 status, c; + HAL_SPARC_86940_READ(SDTR_STATUS(port), status); + if ((status & SDTR_STAT_RxRDY) != 0) { + HAL_SPARC_86940_READ(SDTR_RXDATA(port), c); + (chan->callbacks->rcv_char)(chan, c); + } + cyg_drv_interrupt_acknowledge(sdtr_chan->rx_int_num); + cyg_drv_interrupt_unmask(sdtr_chan->rx_int_num); +} + +#endif // CYGPKG_IO_SERIAL_SPARCLITE_SLEB diff --git a/ecos/packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.h b/ecos/packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.h new file mode 100644 index 0000000..d9c0b5f --- /dev/null +++ b/ecos/packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.h @@ -0,0 +1,166 @@ +#ifndef CYGONCE_SLEB_SDTR_H +#define CYGONCE_SLEB_SDTR_H +//========================================================================== +// +// io/serial/sparclite/sleb_sdtr.c +// +// Serial I/O interface module for SPARClite Eval Board (SLEB) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: SLEB serial I/O module +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_io.h> // For I/O macros + +#define reg(n) ((n)*4) + +// SDTR Registers +#define SDTR_TXDATA(base) base+reg(0) +#define SDTR_RXDATA(base) base+reg(0) +#define SDTR_STATUS(base) base+reg(1) +#define SDTR_CONTROL(base) base+reg(1) + +// Mode register +#define SDTR_MODE_MODE_MASK 0x03 // Mode selection bits (mask) +#define SDTR_MODE_MODE_SYNC 0x00 // Synchronous mode +#define SDTR_MODE_MODE_ASYNC1 0x01 // Async - clock/1 +#define SDTR_MODE_MODE_ASYNC16 0x02 // Async - clock/16 +#define SDTR_MODE_MODE_ASYNC64 0x03 // Async - clock/64 +#define SDTR_MODE_DTB_MASK 0x0C // Number of data bits (mask) +#define SDTR_MODE_DTB_5 0x00 // 5 bits / char +#define SDTR_MODE_DTB_6 0x04 // 6 bits / char +#define SDTR_MODE_DTB_7 0x08 // 7 bits / char +#define SDTR_MODE_DTB_8 0x0C // 8 bits / char +#define SDTR_MODE_PARITY_MASK 0x30 // Parity modes (mask) +#define SDTR_MODE_PARITY_ENABLE 0x10 // Enable parity +#define SDTR_MODE_PARITY_NONE 0x00 // No parity (parity disabled) +#define SDTR_MODE_PARITY_ODD 0x00 // Odd parity +#define SDTR_MODE_PARITY_EVEN 0x20 // Even parity +#define SDTR_MODE_STOP_BITS_MASK 0xC0 // Number of stop bits (mask) +#define SDTR_MODE_STOP_BITS_1 0x40 // 1 stop bit +#define SDTR_MODE_STOP_BITS_1_5 0x80 // 1.5 stop bits +#define SDTR_MODE_STOP_BITS_2 0xC0 // 2 stop bits + +// Command register +#define SDTR_CMD_TxEN 0x01 // Enable transmitter +#define SDTR_CMD_DTR 0x02 // Assert DTR +#define SDTR_CMD_RxEN 0x04 // Enable receiver +#define SDTR_CMD_BREAK 0x08 // Send break +#define SDTR_CMD_EFR 0x10 // Error flag reset +#define SDTR_CMD_RTS 0x20 // Assert RTS +#define SDTR_CMD_RST 0x40 // Internal RESET +#define SDTR_CMD_EHM 0x80 // Enable Hunt mode + +// Status register +#define SDTR_STAT_TxRDY 0x01 // Transmitter ready +#define SDTR_STAT_RxRDY 0x02 // Receiver ready +#define SDTR_STAT_TxEMP 0x04 // Transmitter empty +#define SDTR_STAT_PERR 0x08 // Parity error +#define SDTR_STAT_OERR 0x10 // Overrun error +#define SDTR_STAT_FERR 0x20 // Framing error +#define SDTR_STAT_SYBRK 0x40 // Break +#define SDTR_STAT_DSR 0x80 // State of DSR signal + +// Offsets to standard SDTR elements +#define SLEB_SDTR0_BASE (8*4) +#define SLEB_SDTR0_TX_INT 9 +#define SLEB_SDTR0_RX_INT 10 +#define SLEB_SDTR1_BASE (12*4) +#define SLEB_SDTR1_TX_INT 6 +#define SLEB_SDTR1_RX_INT 7 +#define SLEB_TIMER3_CONTROL reg(29) +#define SLEB_TIMER3_RELOAD reg(30) + +// On-board switch, used to determine baud rate +#define SLEB_CLOCK_SWITCH (volatile unsigned char *)0x01000003 + +static unsigned char select_word_length[] = { + SDTR_MODE_DTB_5, // 5 bits / word (char) + SDTR_MODE_DTB_6, + SDTR_MODE_DTB_7, + SDTR_MODE_DTB_8 +}; + +static unsigned char select_stop_bits[] = { + 0, + SDTR_MODE_STOP_BITS_1, // 1 stop bit + SDTR_MODE_STOP_BITS_1_5, // 1.5 stop bit + SDTR_MODE_STOP_BITS_2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + SDTR_MODE_PARITY_NONE, // No parity + SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_EVEN, // Even parity + SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_ODD, // ODD parity + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +#endif // CYGONCE_SLEB_SDTR_H + diff --git a/ecos/packages/devs/serial/v85x/v850/current/ChangeLog b/ecos/packages/devs/serial/v85x/v850/current/ChangeLog new file mode 100644 index 0000000..c40ada1 --- /dev/null +++ b/ecos/packages/devs/serial/v85x/v850/current/ChangeLog @@ -0,0 +1,83 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_v85x_v850.cdl: Remove irrelevant doc link. + +2001-03-21 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_v85x_v850.cdl: Default driver on if CYGPKG_IO_SERIAL_DEVICES + enabled - like other drivers. + Descriptions should not be specific to SA1. + + * src/v85x_v850_serial.h: Generate baud table dependent on CPU + frequency always. + * src/v85x_v850_serial.c (v850_serial_config_port): Normalize + baud settings from above table before setting. + (v850_serial_putc): Silence warning. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_v85x_v850.cdl: Moved testing parameters here. + +2000-10-09 Gary Thomas <gthomas@redhat.com> + + * src/v85x_v850_serial.c (v850_serial_config_port): Fix baud clock + setup. + +2000-10-04 Gary Thomas <gthomas@redhat.com> + + * src/v85x_v850_serial.c (v850_serial_tx_timeout): Correct arguments. + +2000-09-06 Gary Thomas <gthomas@redhat.com> + + * src/v85x_v850_serial.h: + * src/v85x_v850_serial.c: Better handling of V850 variants (SA1,SB1) + +2000-08-31 Gary Thomas <gthomas@redhat.com> + + * src/v85x_v850_serial.c (v850_serial_config_port): Better handling + of cpu xtal frequency for baud rate calculations. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/v85x_v850_serial.c (v850_serial_set_config): Now use keys to make + more flexible. + +2000-07-19 Gary Thomas <gthomas@redhat.com> + + * src/v85x_v850_serial.h: Base baud rate calculations on CPU frequency. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-05-28 Gary Thomas <gthomas@redhat.com> + + * src/v85x_v850_serial.h: + * src/v85x_v850_serial.c: + * cdl/ser_v85x_v850.cdl: New file(s). + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/v85x/v850/current/cdl/ser_v85x_v850.cdl b/ecos/packages/devs/serial/v85x/v850/current/cdl/ser_v85x_v850.cdl new file mode 100644 index 0000000..c9eb9c6 --- /dev/null +++ b/ecos/packages/devs/serial/v85x/v850/current/cdl/ser_v85x_v850.cdl @@ -0,0 +1,131 @@ +# ==================================================================== +# +# ser_v85x_v850.cdl +# +# eCos serial NEC/V850 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Original data: gthomas +# Contributors: jlarmour +# Date: 2000-05-26 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_V85X_V850 { + display "NEC V850 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_V85X_V850 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + NEC V850." + + compile -library=libextras.a v85x_v850_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_v85x_v850.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_V85X_V850_SERIAL0 { + display "NEC V850 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the NEC V850 + SA1 (70F3017) and SB1 (70F3033) devices, port 0." + + cdl_option CYGDAT_IO_SERIAL_V85X_V850_SERIAL0_NAME { + display "Device name for NEC V850 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + NEC V850, port 0." + } + + cdl_option CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BAUD { + display "Baud rate for the NEC V850 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + NEC V850, port 0." + } + + cdl_option CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BUFSIZE { + display "Buffer size for the NEC V850 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the NEC V850, port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_V85X_V850_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_V85X_V850_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_V85X_V850_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"v85x/v850\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } + +} diff --git a/ecos/packages/devs/serial/v85x/v850/current/src/v85x_v850_serial.c b/ecos/packages/devs/serial/v85x/v850/current/src/v85x_v850_serial.c new file mode 100644 index 0000000..6818f07 --- /dev/null +++ b/ecos/packages/devs/serial/v85x/v850/current/src/v85x_v850_serial.c @@ -0,0 +1,359 @@ +//========================================================================== +// +// io/serial/v85x/v85x_v850_serial.c +// +// NEC V850 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas,jlarmour +// Date: 2001-03-21 +// Purpose: V850 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif +#include CYGBLD_HAL_TARGET_H + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK +#include <cyg/kernel/kapi.h> +#endif + +#ifdef CYGPKG_IO_SERIAL_V85X_V850 + +#include "v85x_v850_serial.h" + +typedef struct v850_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt[3]; + cyg_handle_t serial_interrupt_handle[3]; + cyg_bool tx_busy; +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + cyg_alarm tx_timeout; + cyg_handle_t tx_timeout_handle; +#endif +} v850_serial_info; + +static bool v850_serial_init(struct cyg_devtab_entry *tab); +static bool v850_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo v850_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char v850_serial_getc(serial_channel *chan); +static Cyg_ErrNo v850_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void v850_serial_start_xmit(serial_channel *chan); +static void v850_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 v850_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void v850_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(v850_serial_funs, + v850_serial_putc, + v850_serial_getc, + v850_serial_set_config, + v850_serial_start_xmit, + v850_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_V85X_V850_SERIAL0 +static v850_serial_info v850_serial_info0 = {V850_REG_ASIM0, + CYGNUM_HAL_VECTOR_INTSER0}; +#if CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BUFSIZE > 0 +static unsigned char v850_serial_out_buf0[CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BUFSIZE]; +static unsigned char v850_serial_in_buf0[CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(v850_serial_channel0, + v850_serial_funs, + v850_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &v850_serial_out_buf0[0], sizeof(v850_serial_out_buf0), + &v850_serial_in_buf0[0], sizeof(v850_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(v850_serial_channel0, + v850_serial_funs, + v850_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_V85X_V850_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(v850_serial_io0, + CYGDAT_IO_SERIAL_V85X_V850_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + v850_serial_init, + v850_serial_lookup, // Serial driver may need initializing + &v850_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_V85X_V850_SERIAL0 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +v850_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)v850_chan->base; + unsigned char parity = select_parity[new_config->parity]; + unsigned char word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5]; + unsigned char stop_bits = select_stop_bits[new_config->stop]; + int divisor, count; + + if ((select_baud[new_config->baud].count == 0) || + (word_length == 0xFF) || + (parity == 0xFF) || + (stop_bits == 0xFF)) { + return false; // Unsupported configuration + } + port->asim = ASIM_TxRx_Tx | ASIM_TxRx_Rx | parity | word_length | stop_bits; + count = select_baud[new_config->baud].count; + divisor = select_baud[new_config->baud].divisor; + + while (count > 0xFF) { + count >>= 1; + divisor++; + } + + port->brgc = count; + + port->brgm = divisor & 0x07; +#if CYGINT_HAL_V850_VARIANT_SB1 + port->brgm1 = divisor >> 3; +#endif + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK +// +// The serial ports on the V850 are incredibly stupid. There is no +// interface status register which can tell you if it is possible to +// read or write a character! The only way to discern this is by using +// interrupts [or at least an interrupt register and polling it]. Thus +// the serial transmit code has a problem in that it will be required by +// upper layers to "send until full". The only way to decide "not full" is +// that an interrupt has happened. If the serial driver is being mixed +// with diagnostic I/O, then serial transmit interrupts will possibly be +// lost. +// +// This code attempts to compenstate by using a kernel alarm to reset the +// "device is busy" flag after some timeout. The timeout period will be +// sufficiently long so as to not interfere with normal interrupt handling. +// +static void +v850_serial_tx_timeout(cyg_handle_t alarm, cyg_addrword_t p) +{ + v850_serial_info *v850_chan = (v850_serial_info *)p; + v850_chan->tx_busy = false; +} +#endif + +// Function to initialize the device. Called at bootstrap time. +static bool +v850_serial_init(struct cyg_devtab_entry *tab) +{ + int i; + serial_channel *chan = (serial_channel *)tab->priv; + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + cyg_handle_t h; +#endif +#ifdef CYGDBG_IO_INIT + diag_printf("V850 SERIAL init - dev: %x.%d\n", v850_chan->base, v850_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + for (i = 0; i < 3; i++) { + cyg_drv_interrupt_create(v850_chan->int_num+i, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + v850_serial_ISR, + v850_serial_DSR, + &v850_chan->serial_interrupt_handle[i], + &v850_chan->serial_interrupt[i]); + cyg_drv_interrupt_attach(v850_chan->serial_interrupt_handle[i]); + cyg_drv_interrupt_unmask(v850_chan->int_num+i); +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + cyg_clock_to_counter(cyg_real_time_clock(), &h); + cyg_alarm_create(h, v850_serial_tx_timeout, (cyg_addrword_t)v850_chan, + &v850_chan->tx_timeout_handle, &v850_chan->tx_timeout); +#endif + } + } + v850_chan->tx_busy = false; + return v850_serial_config_port(chan, &chan->config, true); +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +v850_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +v850_serial_putc(serial_channel *chan, unsigned char c) +{ + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)v850_chan->base; + if (!v850_chan->tx_busy) { + v850_chan->tx_busy = true; + port->txs = c; +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + cyg_alarm_initialize(v850_chan->tx_timeout_handle, cyg_current_time()+10, 0); +#endif + return true; + } else { + return false; // Couldn't send, tx was busy + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +v850_serial_getc(serial_channel *chan) +{ + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)v850_chan->base; + return port->rxs; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +v850_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != v850_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +v850_serial_start_xmit(serial_channel *chan) +{ + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); // Kick transmitter (if necessary) + cyg_drv_interrupt_unmask(v850_chan->int_num+INT_Tx); // Enable Tx interrupt +} + +// Disable the transmitter on the device +static void +v850_serial_stop_xmit(serial_channel *chan) +{ + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(v850_chan->int_num+INT_Tx); // Disable Tx interrupt +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +v850_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(vector); + cyg_drv_interrupt_acknowledge(vector); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +v850_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + v850_serial_info *v850_chan = (v850_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)v850_chan->base; + switch (vector-(v850_chan->int_num)) { + case INT_ERR: + case INT_Rx: + (chan->callbacks->rcv_char)(chan, port->rxs); + break; + case INT_Tx: + v850_chan->tx_busy = false; +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + cyg_alarm_initialize(v850_chan->tx_timeout_handle, 0, 0); +#endif + (chan->callbacks->xmt_char)(chan); + break; + } + cyg_drv_interrupt_unmask(vector); +} +#endif + +// EOF v85x_v850_serial.c diff --git a/ecos/packages/devs/serial/v85x/v850/current/src/v85x_v850_serial.h b/ecos/packages/devs/serial/v85x/v850/current/src/v85x_v850_serial.h new file mode 100644 index 0000000..9ad39c7 --- /dev/null +++ b/ecos/packages/devs/serial/v85x/v850/current/src/v85x_v850_serial.h @@ -0,0 +1,164 @@ +#ifndef CYGONCE_V85X_V850_SERIAL_H +#define CYGONCE_V85X_V850_SERIAL_H + +// ==================================================================== +// +// v850_ceb_serial.h +// +// Device I/O - Description of NEC V850 serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas,jlarmour +// Date: 2001-03-21 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on NEC V850/SA1 & SB1 + +#include <pkgconf/system.h> +#include CYGBLD_HAL_TARGET_H + +#include <cyg/hal/v850_common.h> + +struct serial_port { + unsigned char asim; // Serial interface mode + unsigned char _filler0; + unsigned char asis; // Serial interface status + unsigned char _filler1; + unsigned char brgc; // Baud rate control + unsigned char _filler2; + unsigned char txs; // Transmit shift register + unsigned char _filler3; + unsigned char rxs; // Receive shift register + unsigned char _filler4[5]; + unsigned char brgm; // Baud rate mode + unsigned char _filler5; +#if CYGINT_HAL_V850_VARIANT_SB1 + unsigned char _filler6[0x10]; + unsigned char brgm1; // Baud rate overflow +#endif +}; + +// Relative interrupt numbers +#define INT_ERR 0 // Receive error condition +#define INT_Rx 1 // Receive data +#define INT_Tx 2 // Transmit data + +// Serial interface mode +#define ASIM_TxRx_MASK (3<<6) // Receive & Transmit enables +#define ASIM_TxRx_Rx (1<<6) // Receive enable +#define ASIM_TxRx_Tx (2<<6) // Transmit enable +#define ASIM_Parity_MASK (3<<4) // Parity mode bits +#define ASIM_Parity_none (0<<4) // No parity +#define ASIM_Parity_space (1<<4) // Send zero bit, ignore errors +#define ASIM_Parity_odd (2<<4) // Odd parity +#define ASIM_Parity_even (3<<4) // Even parity +#define ASIM_Length_MASK (1<<3) // Character length select +#define ASIM_Length_7 (0<<3) // 7 bit chars +#define ASIM_Length_8 (1<<3) // 8 bit chars +#define ASIM_Stop_MASK (1<<2) // Stop bit select +#define ASIM_Stop_1 (0<<2) // 1 stop bit +#define ASIM_Stop_2 (1<<2) // 2 stop bits +#define ASIM_Error_MASK (1<<1) // Receive error select +#define ASIM_Error_enable (0<<1) // Issue interrupt on receive error +#define ASIM_Error_disable (1<<1) // No interrupts on receive error + +// Serial interface status (errors only) +#define ASIS_OVE (1<<0) // Overrun error +#define ASIS_FE (1<<1) // Framing error +#define ASIS_PE (1<<2) // Parity error + +static unsigned char select_word_length[] = { + 0xFF, // 5 bits / word (char) + 0xFF, + ASIM_Length_7, + ASIM_Length_8 +}; + +static unsigned char select_stop_bits[] = { + 0, + ASIM_Stop_1, // 1 stop bit + 0xFF, // 1.5 stop bit + ASIM_Stop_2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + ASIM_Parity_none, // No parity + ASIM_Parity_even, // Even parity + ASIM_Parity_odd, // Odd parity + 0xFF, // Mark parity + ASIM_Parity_space, // Space parity +}; + +static struct v850_baud { + unsigned int count; + unsigned int divisor; +} select_baud[] = { +// Baud rate values, using defined system clock +#define BAUDCOUNT(X) ((CYGHWR_HAL_V85X_CPU_FREQ/2)/(X)) + {0, 0}, // Unused + {0, 0}, // 50 + {0, 0}, // 75 + {0, 0}, // 110 + {0, 0}, // 134.5 + {0, 0}, // 150 + {0, 0}, // 200 + {0, 0}, // 300 + {0, 0}, // 600 + {BAUDCOUNT(1200), 1}, // 1200 + {0, 0}, // 1800 + {BAUDCOUNT(2400), 1}, // 2400 + {0, 0}, // 3600 + {BAUDCOUNT(4800), 1}, // 4800 + {0, 0}, // 7200 + {BAUDCOUNT(9600), 1}, // 9600 + {0, 0}, // 14400 + {BAUDCOUNT(19200), 1}, // 19200 + {BAUDCOUNT(38400), 1}, // 38400 + {0, 0}, // 57600 + {0, 0}, // 115200 + {0, 0}, // 230400 +}; + +#endif // CYGONCE_V85X_V850_SERIAL_H + +// EOF v85x_v850_serial.h |