diff options
Diffstat (limited to 'ecos/packages/devs/serial/mips')
22 files changed, 7095 insertions, 0 deletions
diff --git a/ecos/packages/devs/serial/mips/atlas/current/ChangeLog b/ecos/packages/devs/serial/mips/atlas/current/ChangeLog new file mode 100644 index 0000000..7c6ef46 --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/ChangeLog @@ -0,0 +1,43 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_atlas.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_atlas.cdl: + Fix 234000->230400 typo. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/atlas_serial.c (atlas_serial_set_config): Now use keys to make + more flexible. + +2000-07-14 Drew Moseley <dmoseley@redhat.com> + + * cdl/ser_mips_atlas.cdl: New file. Implement a serial driver for the mips Atlas board + * src/atlas_serial.c: Ditto. + * src/atlas_serial.h: Ditto. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl b/ecos/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl new file mode 100644 index 0000000..68d5d0e --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl @@ -0,0 +1,157 @@ +# ==================================================================== +# +# ser_mips_atlas.cdl +# +# eCos serial MIPS/ATLAS configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): dmoseley +# Original data: gthomas +# Contributors: +# Date: 2000-06-23 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_ATLAS { + display "MIPS ATLAS serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_ATLAS + + requires CYGPKG_ERROR + include_dir cyg/io +# include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + MIPS ATLAS." + + compile -library=libextras.a atlas_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_atlas.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +# FIXME: Bad name +cdl_option CYGPKG_IO_SERIAL_MIPS_ATLAS_POLLED_MODE { + display "MIPS ATLAS polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the MIPS ATLAS should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_MIPS_ATLAS_SERIAL_A { + display "MIPS ATLAS serial port driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the 16C550C on the + MIPS ATLAS." + + cdl_option CYGDAT_IO_SERIAL_MIPS_ATLAS_SERIAL_A_NAME { + display "Device name for MIPS ATLAS serial port" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name on the MIPS ATLAS." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BAUD { + display "Baud rate for the MIPS ATLAS serial port driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MIPS ATLAS 16c550c port." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE { + display "Buffer size for the MIPS ATLAS serial port driver" + flavor data + legal_values 0 to 8192 + default_value 512 + description " + This option specifies the size of the internal buffers used + for the MIPS ATLAS 16c550c port." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_ATLAS_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_ATLAS_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_ATLAS_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_mips_atlas.cdl diff --git a/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.c b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.c new file mode 100644 index 0000000..df264ed --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.c @@ -0,0 +1,372 @@ +//========================================================================== +// +// atlas_serial.c +// +// Serial device driver for ATLAS on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dmoseley, based on POWERPC driver by jskov +// Contributors: gthomas, jskov, dmoseley +// Date: 2000-06-23 +// Purpose: ATLAS serial device driver +// Description: ATLAS serial device driver +// +// To Do: +// Put in magic to effectively use the FIFOs. Transmitter FIFO fill is a +// problem, and setting receiver FIFO interrupts to happen only after +// n chars may conflict with hal diag. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_ATLAS + +#include "atlas_serial.h" + +typedef struct atlas_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; + cyg_uint8 iir; +} atlas_serial_info; + +static bool atlas_serial_init(struct cyg_devtab_entry *tab); +static bool atlas_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo atlas_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char atlas_serial_getc(serial_channel *chan); +static Cyg_ErrNo atlas_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void atlas_serial_start_xmit(serial_channel *chan); +static void atlas_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 atlas_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void atlas_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(atlas_serial_funs, + atlas_serial_putc, + atlas_serial_getc, + atlas_serial_set_config, + atlas_serial_start_xmit, + atlas_serial_stop_xmit + ); + +static atlas_serial_info atlas_serial_info0 ={ATLAS_SER_16550_BASE_A, + CYGNUM_HAL_INTERRUPT_SER}; + +#if CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE > 0 +static unsigned char atlas_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE]; +static unsigned char atlas_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(atlas_serial_channel0, + atlas_serial_funs, + atlas_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &atlas_serial_out_buf0[0], + sizeof(atlas_serial_out_buf0), + &atlas_serial_in_buf0[0], + sizeof(atlas_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(atlas_serial_channel0, + atlas_serial_funs, + atlas_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_ATLAS_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(atlas_serial_io0, + CYGDAT_IO_SERIAL_MIPS_ATLAS_SERIAL_A_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + atlas_serial_init, + atlas_serial_lookup, // Serial driver may need initializing + &atlas_serial_channel0 + ); + + + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +atlas_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + cyg_uint8 _lcr, _ier; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + // + // We may need to increase the timeout before causing a break reset. + // According to the Atlas Users Manual (Document MD00005) The BRKRES + // register will need to be programmed with a value larger that 0xA (the default) + // if we are going to use a baud rate lower than 2400. + // + if (new_config->baud <= CYGNUM_SERIAL_BAUD_2400) + { + // For now, just disable the break reset entirely. + HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, 0); + } else { + // Put the break reset state back to the default + HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, HAL_ATLAS_BRKRES_DEFAULT_VALUE); + } + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(port+SER_16550_IER, _ier); + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set databits, stopbits and parity. + _lcr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + if (init) { + // Enable and clear FIFO + HAL_WRITE_UINT8(port+SER_16550_FCR, + (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); + + if (chan->out_cbuf.len != 0) { + HAL_WRITE_UINT8(port+SER_16550_IER, SIO_IER_ERDAI); + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + } + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +atlas_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("ATLAS SERIAL init - dev: %x.%d\n", atlas_chan->base, atlas_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(atlas_chan->int_num, + 0, // can change IRQ0 priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + atlas_serial_ISR, + atlas_serial_DSR, + &atlas_chan->serial_interrupt_handle, + &atlas_chan->serial_interrupt); + cyg_drv_interrupt_attach(atlas_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(atlas_chan->int_num); + } + atlas_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +atlas_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +atlas_serial_putc(serial_channel *chan, unsigned char c) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _lsr; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + if (_lsr & SIO_LSR_THRE) { + // Transmit buffer is empty + HAL_WRITE_UINT8(port+SER_16550_THR, c); + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +atlas_serial_getc(serial_channel *chan) +{ + unsigned char c; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _lsr; + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ((_lsr & SIO_LSR_DR) == 0); + HAL_READ_UINT8(port+SER_16550_RBR, c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +atlas_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != atlas_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +atlas_serial_start_xmit(serial_channel *chan) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier |= IER_XMT; // Enable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + + // We should not need to call this here. THRE Interrupts are enabled, and the DSR + // below calls this function. However, sometimes we get called with Master Interrupts + // disabled, and thus the DSR never runs. This is unfortunate because it means we + // will be doing multiple processing steps for the same thing. + (chan->callbacks->xmt_char)(chan); +} + +// Disable the transmitter on the device +static void +atlas_serial_stop_xmit(serial_channel *chan) +{ + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier &= ~IER_XMT; // Disable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +atlas_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(atlas_chan->int_num); + cyg_drv_interrupt_acknowledge(atlas_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +atlas_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + atlas_serial_info *atlas_chan = (atlas_serial_info *)chan->dev_priv; + cyg_addrword_t port = atlas_chan->base; + cyg_uint8 _iir; + + HAL_READ_UINT8(port+SER_16550_IIR, _iir); + _iir &= SIO_IIR_ID_MASK; + if ( ISR_Tx_Empty == _iir ) { + (chan->callbacks->xmt_char)(chan); + } else if (( ISR_Rx_Avail == _iir ) || ( ISR_Rx_Char_Timeout == _iir )) { + cyg_uint8 _c; + HAL_READ_UINT8(port+SER_16550_RBR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + + cyg_drv_interrupt_unmask(atlas_chan->int_num); +} + +#endif + +//------------------------------------------------------------------------- +// EOF atlas_serial.c diff --git a/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.h b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.h new file mode 100644 index 0000000..1b78b9d --- /dev/null +++ b/ecos/packages/devs/serial/mips/atlas/current/src/atlas_serial.h @@ -0,0 +1,213 @@ +//========================================================================== +// +// io/serial/mips/atlas/atlas_serial.h +// +// MIPS Atlas Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dmoseley, based on PowerPC driver by jskov +// Contributors:gthomas, jskov, dmoseley +// Date: 2000-06-23 +// Purpose: Atlas Serial definitions +//####DESCRIPTIONEND#### +//========================================================================== + +// Description of serial ports on Atlas board + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_None 0x01 +#define ISR_Rx_Line_Status 0x06 +#define ISR_Rx_Avail 0x04 +#define ISR_Rx_Char_Timeout 0x0C +#define ISR_Tx_Empty 0x02 +#define IRS_Modem_Status 0x00 + +// FIFO control register +#define FCR_ENABLE 0x01 +#define FCR_CLEAR_RCVR 0x02 +#define FCR_CLEAR_XMIT 0x04 + + +//////////////////////////////////////////////////////////// +// Clean this up. + +#define ATLAS_SER_16550_BASE_A 0xBF000900 +#define SER_16550_BASE ATLAS_SER_16550_BASE_A + +//----------------------------------------------------------------------------- +// Define the serial registers. The Atlas board is equipped with a 16550C +// serial chip. +#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 +#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define SER_16550_IER 0x08 // interrupt enable register, read/write, dlab = 0 +#define SER_16550_DLM 0x08 // divisor latch (MS), read/write, dlab = 1 +#define SER_16550_IIR 0x10 // interrupt identification reg, read, dlab = 0 +#define SER_16550_FCR 0x10 // fifo control register, write, dlab = 0 +#define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1 +#define SER_16550_LCR 0x18 // line control register, read/write +#define SER_16550_MCR 0x20 // modem control register, read/write +#define SER_16550_LSR 0x28 // line status register, read +#define SER_16550_MSR 0x30 // modem status register, read +#define SER_16550_SCR 0x38 // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO +///////////////////////////////////////// + + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// FIXME: calc all properly +// The Atlas board has a 3.6864 MHz crystal +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 2094, // 110 + 0, // 134.5 + 1536, // 150 + 0, // 200 + 768, // 300 + 384, // 600 + 192, // 1200 + 0, // 1800 + 96, // 2400 + 0, // 3600 + 48, // 4800 + 32, // 7200 + 24, // 9600 + 16, // 14400 + 12, // 19200 + 6, // 38400 + 4, // 57600 + 2, // 115200 + 1, // 230400 +}; + diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/ChangeLog b/ecos/packages/devs/serial/mips/idt79s334a/current/ChangeLog new file mode 100644 index 0000000..01c0c41 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/ChangeLog @@ -0,0 +1,38 @@ +2003-03-09 Tim Michals <t.michals@attbi.com> + + * cdl/ser_mipsidt_334a.cdl: Add configuration for second serial port. + * src/mipsidt_serial.c: Updated support for dual serial ports + * src/mipsidt_serial.h: Add some helpful extra defines for debug. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mipsidt_334a.cdl: Remove irrelevant doc link. + +2003-02-13 Tim Michals <t.michals@attbi.com> +2003-02-13 Jonathan Larmour <jifl@eCosCentric.com> + + * New package - support for MIPS IDT 79s334a board. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/cdl/ser_mipsidt_334a.cdl b/ecos/packages/devs/serial/mips/idt79s334a/current/cdl/ser_mipsidt_334a.cdl new file mode 100644 index 0000000..b3748d5 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/cdl/ser_mipsidt_334a.cdl @@ -0,0 +1,196 @@ +# ==================================================================== +# +# ser_mipsidt_334a.cdl +# +# eCos serial MIPS/IDT 334a reference platform configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): tmichals +# Original data: dmoseley +# Contributors: +# Date: 2003-02-13 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_IDT79S334A { + display "MIPS IDT79RC32344 reference platform serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_IDT32334 + + requires CYGPKG_ERROR + include_dir cyg/io +# include_files ; # none _exported_ whatsoever + description " + This package contains the serial device drivers for the + MIPS IDT79RC32334 reference platform." + + compile -library=libextras.a mipsidt_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_idt79s334a.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + +cdl_option CYGPKG_IO_SERIAL_MIPS_POLLED_MODE { + display "MIPS IDT polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the MIPS should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A { + display "MIPS IDT79S334A serial port driver 0" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the 16C550 on the + MIPS IDT79S334A." + + cdl_option CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_NAME { + display "Device name for MIPS IDT79S334A serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name on the MIPS IDT79S334A." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BAUD { + display "Baud rate for the MIPS IDT79S334A serial port driver 0" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 115200 + description " + This option specifies the default baud rate (speed) for the + MIPS 16c550 port." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE { + display "Buffer size for the MIPS IDT79S334A serial port driver 0" + flavor data + legal_values 0 to 8192 + default_value 512 + description " + This option specifies the size of the internal buffers used + for the MIPS IDT79S334A 16c550c port." + } +} + +cdl_component CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B { + display "MIPS IDT79S334A serial port driver 1" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the 16C550 on the + MIPS IDT79S334A." + + cdl_option CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_NAME { + display "Device name for MIPS IDT79S334A serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name on the MIPS IDT79S334A." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BAUD { + display "Baud rate for the MIPS IDT79S334A serial port driver 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 115200 + description " + This option specifies the default baud rate (speed) for the + MIPS 16c550 port." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE { + display "Buffer size for the MIPS IDT79S334A serial port driver 1" + flavor data + legal_values 0 to 8192 + default_value 512 + description " + This option specifies the size of the internal buffers used + for the MIPS IDT79S334A 16c550c port." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_IDT79S334A_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_IDT79S334A_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_IDT79S334A_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_mipsidt_334A.cdl diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.c b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.c new file mode 100755 index 0000000..6943c64 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.c @@ -0,0 +1,409 @@ +//========================================================================== +// +// mipsidt_serial.c +// +// Serial device driver for MIPS IDT79s334a reference platform on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals based on driver by dmoseley, based on POWERPC driver by jskov +// Contributors: gthomas, jskov, dmoseley, tmichals +// Date: 2003-02-13 +// Purpose: MIPS IDT79s334a reference platform serial device driver +// Description: IDT MIPS serial device driver +// +// To Do: +// Put in magic to effectively use the FIFOs. Transmitter FIFO fill is a +// problem, and setting receiver FIFO interrupts to happen only after +// n chars may conflict with hal diag. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_IDT79S334A + +#include "mipsidt_serial.h" + +typedef struct mipsidt_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; + cyg_uint8 iir; +} mipsidt_serial_info; + +static bool mipsidt_serial_init(struct cyg_devtab_entry *tab); +static bool mipsidt_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo mipsidt_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char mipsidt_serial_getc(serial_channel *chan); +static Cyg_ErrNo mipsidt_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void mipsidt_serial_start_xmit(serial_channel *chan); +static void mipsidt_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 mipsidt_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void mipsidt_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(mipsidt_serial_funs, + mipsidt_serial_putc, + mipsidt_serial_getc, + mipsidt_serial_set_config, + mipsidt_serial_start_xmit, + mipsidt_serial_stop_xmit + ); + + +#ifdef CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A +static mipsidt_serial_info mipsidt_serial_info0 ={IDTMIPS_SER_16550_BASE_A, + CYGNUM_HAL_INTERRUPT_SIO_0}; + +#if CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE > 0 +static unsigned char mipsidt_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE]; +static unsigned char mipsidt_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mipsidt_serial_channel0, + mipsidt_serial_funs, + mipsidt_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mipsidt_serial_out_buf0[0], + sizeof(mipsidt_serial_out_buf0), + &mipsidt_serial_in_buf0[0], + sizeof(mipsidt_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(mipsidt_serial_channel0, + mipsidt_serial_funs, + mipsidt_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(mipsidt_serial_io0, + CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_A_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mipsidt_serial_init, + mipsidt_serial_lookup, // Serial driver may need initializing + &mipsidt_serial_channel0 + ); + +#endif + +#ifdef CYGPKG_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B +static mipsidt_serial_info mipsidt_serial_info1 ={IDTMIPS_SER_16550_BASE_B, + CYGNUM_HAL_INTERRUPT_SIO_1}; + +#if CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE > 0 +static unsigned char mipsidt_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE]; +static unsigned char mipsidt_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(mipsidt_serial_channel1, + mipsidt_serial_funs, + mipsidt_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &mipsidt_serial_out_buf1[0], + sizeof(mipsidt_serial_out_buf1), + &mipsidt_serial_in_buf1[0], + sizeof(mipsidt_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(mipsidt_serial_channel1, + mipsidt_serial_funs, + mipsidt_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(mipsidt_serial_io1, + CYGDAT_IO_SERIAL_MIPS_IDT79S334A_SERIAL_B_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + mipsidt_serial_init, + mipsidt_serial_lookup, // Serial driver may need initializing + &mipsidt_serial_channel1 + ); + +#endif + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +mipsidt_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint32 baud_divisor = select_baud[new_config->baud]; ; + cyg_uint8 _lcr, _ier; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + baud_divisor = (CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL * 10) / (16 * select_baud[new_config->baud]); + + baud_divisor +=5; + baud_divisor = ((cyg_int32)baud_divisor) / 10; + + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(port+SER_16550_IER, _ier); + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set databits, stopbits and parity. + _lcr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + if (init) { + // Enable and clear FIFO + HAL_WRITE_UINT8(port+SER_16550_FCR, + (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); + + if (chan->out_cbuf.len != 0) { + HAL_WRITE_UINT8(port+SER_16550_IER, SIO_IER_ERDAI); + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + } + } else { + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + } + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +mipsidt_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("IDT SERIAL init - dev: %x.%d\n", mipsidt_chan->base, mipsidt_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(mipsidt_chan->int_num, + 0, // can change IRQ0 priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + mipsidt_serial_ISR, + mipsidt_serial_DSR, + &mipsidt_chan->serial_interrupt_handle, + &mipsidt_chan->serial_interrupt); + cyg_drv_interrupt_attach(mipsidt_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(mipsidt_chan->int_num); + } + mipsidt_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +mipsidt_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +mipsidt_serial_putc(serial_channel *chan, unsigned char c) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _lsr; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + if (((_lsr & (SIO_LSR_THRE | SIO_LSR_TEMT)) == 0x60)) { + // Transmit buffer is empty + HAL_WRITE_UINT8(port+SER_16550_THR, c); + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +mipsidt_serial_getc(serial_channel *chan) +{ + unsigned char c; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _lsr; + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ((_lsr & SIO_LSR_DR) == 0); + HAL_READ_UINT8(port+SER_16550_RBR, c); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +mipsidt_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != mipsidt_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +mipsidt_serial_start_xmit(serial_channel *chan) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier |= IER_XMT; // Enable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); + + // We should not need to call this here. THRE Interrupts are enabled, and the DSR + // below calls this function. However, sometimes we get called with Master Interrupts + // disabled, and thus the DSR never runs. This is unfortunate because it means we + // will be doing multiple processing steps for the same thing. + (chan->callbacks->xmt_char)(chan); +} + +// Disable the transmitter on the device +static void +mipsidt_serial_stop_xmit(serial_channel *chan) +{ + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _ier; + + HAL_READ_UINT8(port+SER_16550_IER, _ier); + _ier &= ~IER_XMT; // Disable xmit interrupt + HAL_WRITE_UINT8(port+SER_16550_IER, _ier); +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +mipsidt_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(mipsidt_chan->int_num); + cyg_drv_interrupt_acknowledge(mipsidt_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +mipsidt_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; + cyg_addrword_t port = mipsidt_chan->base; + cyg_uint8 _iir; + + HAL_READ_UINT8(port+SER_16550_IIR, _iir); + _iir &= SIO_IIR_ID_MASK; + if ( ISR_Tx_Empty == _iir ) { + (chan->callbacks->xmt_char)(chan); + } else if (( ISR_Rx_Avail == _iir ) || ( ISR_Rx_Char_Timeout == _iir )) { + cyg_uint8 _c; + HAL_READ_UINT8(port+SER_16550_RBR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + + cyg_drv_interrupt_unmask(mipsidt_chan->int_num); +} + +#endif + +//------------------------------------------------------------------------- +// EOF mipsidt_serial.c diff --git a/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.h b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.h new file mode 100755 index 0000000..7975d78 --- /dev/null +++ b/ecos/packages/devs/serial/mips/idt79s334a/current/src/mipsidt_serial.h @@ -0,0 +1,218 @@ +//========================================================================== +// +// io/serial/mips/idt79s334a/mipsidt_serial.h +// +// MIPS IDT79S334A Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals based on driver by dmoseley, based on POWERPC driver by jskov +// Contributors: gthomas, jskov, dmoseley, tmichals +// Date: 2003-02-13 +// Date: 2003-02-13 +// Purpose: MIPS IDT79s334a reference platform serial device driver definitions. +// Description: IDT MIPS serial device driver definitions. +//####DESCRIPTIONEND#### +//========================================================================== + +// Description of serial ports on IDT board + +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_None 0x01 +#define ISR_Rx_Line_Status 0x06 +#define ISR_Rx_Avail 0x04 +#define ISR_Rx_Char_Timeout 0x0C +#define ISR_Tx_Empty 0x02 +#define IRS_Modem_Status 0x00 + +// FIFO control register +#define FCR_ENABLE 0x01 +#define FCR_CLEAR_RCVR 0x02 +#define FCR_CLEAR_XMIT 0x04 + + +//////////////////////////////////////////////////////////// +// Clean this up. + +#define IDTMIPS_SER_16550_BASE_A 0xB8000803 +#define IDTMIPS_SER_16550_BASE_B 0xB8000823 +#define SER_16550_BASE IDTMIPS_SER_16550_BASE_A +#define INTR_COM0_REG 0xB8000554 +#define INTR_COM1_REG 0xB8000564 + +//----------------------------------------------------------------------------- +// Define the serial registers. The IDT board is equipped with a 16550C +// serial chip. +#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 +#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define SER_16550_IER 0x04 // interrupt enable register, read/write, dlab = 0 +#define SER_16550_DLM 0x04 // divisor latch (MS), read/write, dlab = 1 +#define SER_16550_IIR 0x08 // interrupt identification reg, read, dlab = 0 +#define SER_16550_FCR 0x08 // fifo control register, write, dlab = 0 +#define SER_16550_AFR 0x08 // alternate function reg, read/write, dlab = 1 +#define SER_16550_LCR 0x0c // line control register, read/write +#define SER_16550_MCR 0x10 // modem control register, read/write +#define SER_16550_LSR 0x14 // line status register, read +#define SER_16550_MSR 0x18 // modem status register, read +#define SER_16550_SCR 0x1c // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO +///////////////////////////////////////// + + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + + +static unsigned int select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 134, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +// EOF mipsidt_serial.h diff --git a/ecos/packages/devs/serial/mips/jmr3904/current/ChangeLog b/ecos/packages/devs/serial/mips/jmr3904/current/ChangeLog new file mode 100644 index 0000000..91f4a29 --- /dev/null +++ b/ecos/packages/devs/serial/mips/jmr3904/current/ChangeLog @@ -0,0 +1,1185 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_jmr3904.cdl: Remove irrelevant doc link. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: + Fix 234000->230400 typo. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/tx3904_serial.c (tx3904_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_mips_jmr3904.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl b/ecos/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl new file mode 100644 index 0000000..cf922eb --- /dev/null +++ b/ecos/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl @@ -0,0 +1,219 @@ +# ==================================================================== +# +# ser_mips_jmr3904.cdl +# +# eCos serial MIPS/JMR3904 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_TX39_JMR3904 { + display "TX39 JMR3904 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_TX39_JMR3904 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + TX39 JMR3904." + + compile -library=libextras.a tx3904_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_tx39_jmr3904.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +# FIXME: Bad name +cdl_option CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE { + display "TX39 JMR3904 polled mode serial drivers" + flavor bool + default_value 0 + description " + If asserted, this option specifies that the serial device + drivers for the TX39 JMR3904 should be polled-mode instead of + interrupt driven." +} + +cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 { + display "TX39 JMR3904 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 0 on the + TX39 JMR3904." + + cdl_option CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL0_NAME { + display "Device name for TX39 JMR3904 serial port 0" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the device name port 0 on the TX39 JMR3904." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BAUD { + display "Baud rate for the TX39 JMR3904 serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + TX39 JMR3904 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE { + display "Buffer size for the TX39 JMR3904 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the TX39 JMR3904 port 0." + } +} +cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 { + display "TX39 JMR3904 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for port 1 on + the TX39 JMR3904." + + cdl_option CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL1_NAME { + display "Device name for TX39 JMR3904 serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name port 1 on the TX39 JMR3904." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD { + display "Baud rate for the TX39 JMR3904 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + TX39 JMR3904 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE { + display "Buffer size for the TX39 JMR3904 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the TX39 JMR3904 port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_TX39_JMR3904_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_TX39_JMR3904_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_TX39_JMR3904_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + + implements CYGINT_IO_SERIAL_TEST_SKIP_9600 + implements CYGINT_IO_SERIAL_TEST_SKIP_57600 + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN + implements CYGINT_IO_SERIAL_TEST_SKIP_STOP_2 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"tx39jmr\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_jmr3904.cdl diff --git a/ecos/packages/devs/serial/mips/jmr3904/current/src/tx3904_serial.c b/ecos/packages/devs/serial/mips/jmr3904/current/src/tx3904_serial.c new file mode 100644 index 0000000..0552d65 --- /dev/null +++ b/ecos/packages/devs/serial/mips/jmr3904/current/src/tx3904_serial.c @@ -0,0 +1,756 @@ +//========================================================================== +// +// tx3904_serial.c +// +// Serial device driver for TX3904 on-chip serial devices +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-03-3 +// Purpose: TX3904 serial device driver +// Description: TX3904 serial device driver +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/io_serial.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904 + +cyg_bool cyg_hal_is_break(char *buf, int size); +void cyg_hal_user_break( CYG_ADDRWORD *regs ); + +//------------------------------------------------------------------------- + +extern void diag_printf(const char *fmt, ...); + +//------------------------------------------------------------------------- +// Forward definitions + +static bool tx3904_serial_init(struct cyg_devtab_entry *tab); +static bool tx3904_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo tx3904_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char tx3904_serial_getc(serial_channel *chan); +static Cyg_ErrNo tx3904_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void tx3904_serial_start_xmit(serial_channel *chan); +static void tx3904_serial_stop_xmit(serial_channel *chan); + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE +static cyg_uint32 tx3904_serial_ISR(cyg_vector_t vector, cyg_addrword_t data, cyg_addrword_t *regs); +static void tx3904_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#endif + + +//------------------------------------------------------------------------- +// TX3904 serial line control register values: + +// Offsets to serial control registers from base +#define SERIAL_CR 0x00 +#define SERIAL_SR 0x04 +#define SERIAL_ICR 0x08 +#define SERIAL_ISR 0x0C +#define SERIAL_FCR 0x10 +#define SERIAL_BRG 0x14 +#define SERIAL_TXB 0x20 +#define SERIAL_RXB 0x30 + +// Status register bits +#define ISR_RXRDY 0x01 +#define ISR_TXRDY 0x02 +#define ISR_ERROR 0x04 + +// Control register bits +#define LCR_SB1 0x0000 +#define LCR_SB1_5 0x0000 +#define LCR_SB2 0x0004 +#define LCR_PN 0x0000 // Parity mode - none +#define LCR_PS 0x0000 // Forced "space" parity +#define LCR_PM 0x0000 // Forced "mark" parity +#define LCR_PE 0x0018 // Parity mode - even +#define LCR_PO 0x0010 // Parity mode - odd +#define LCR_WL5 0x0001 // not supported - use 7bit +#define LCR_WL6 0x0001 // not supported - use 7bit +#define LCR_WL7 0x0001 // 7 bit chars +#define LCR_WL8 0x0000 // 8 bit chars + +#define LCR_BRG 0x0020 // Select baud rate generator + +#define ICR_RXE 0x0001 // receive enable +#define ICR_TXE 0x0002 // transmit enable + +//------------------------------------------------------------------------- +// Tables to map input values to hardware settings + +static unsigned char select_word_length[] = { + LCR_WL5, // 5 bits / word (char) + LCR_WL6, + LCR_WL7, + LCR_WL8 +}; + +static unsigned char select_stop_bits[] = { + 0, + LCR_SB1, // 1 stop bit + LCR_SB1_5, // 1.5 stop bit + LCR_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + LCR_PN, // No parity + LCR_PE, // Even parity + LCR_PO, // Odd parity + LCR_PM, // Mark parity + LCR_PS, // Space parity +}; + +// The values in this table plug straight into the BRG register +// in the serial driver hardware. They comprise a baud rate divisor +// in the bottom 8 bits and a clock selector in the top 8 bits. +// These figures all come from Toshiba. + +#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0x0300|20, // 600 + 0x0300|10, // 1200 + 0, // 1800 + 0x0300|05, // 2400 + 0, // 3600 + 0x0300|10, // 4800 + 0, // 7200 + 0x0200|05, // 9600 + 0, // 14400 + 0x0100|10, // 19200 + 0x0100|05, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0x0300|27, // 600 + 0x0200|54, // 1200 + 0, // 1800 + 0x0200|27, // 2400 + 0, // 3600 + 0x0100|54, // 4800 + 0, // 7200 + 0x0100|27, // 9600 + 0, // 14400 + 0x0000|54, // 19200 + 0x0000|27, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#else + +#error Unsupported CPU frequency + +#endif + +//------------------------------------------------------------------------- +// Info for each serial device controlled + +typedef struct tx3904_serial_info { + CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt interrupt; + cyg_handle_t interrupt_handle; + cyg_uint8 input_char; + cyg_bool input_char_valid; + cyg_bool output_ready; + cyg_uint16 cur_baud; +} tx3904_serial_info; + +//------------------------------------------------------------------------- +// Callback functions exported by this driver + +static SERIAL_FUNS(tx3904_serial_funs, + tx3904_serial_putc, + tx3904_serial_getc, + tx3904_serial_set_config, + tx3904_serial_start_xmit, + tx3904_serial_stop_xmit + ); + +//------------------------------------------------------------------------- +// Hardware info for each serial line + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 +static tx3904_serial_info tx3904_serial_info0 = { + 0xFFFFF300, + CYGNUM_HAL_INTERRUPT_SIO_0 +}; +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE > 0 +static unsigned char tx3904_serial_out_buf0[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE]; +static unsigned char tx3904_serial_in_buf0[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 +static tx3904_serial_info tx3904_serial_info1 = { + 0xFFFFF400, + CYGNUM_HAL_INTERRUPT_SIO_1 +}; +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE > 0 +static unsigned char tx3904_serial_out_buf1[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE]; +static unsigned char tx3904_serial_in_buf1[CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE]; +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 + +//------------------------------------------------------------------------- +// Channel descriptions: + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE +#define SIZEOF_BUF(_x_) 0 +#else +#define SIZEOF_BUF(_x_) sizeof(_x_) +#endif + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(tx3904_serial_channel0, + tx3904_serial_funs, + tx3904_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &tx3904_serial_out_buf0[0], + SIZEOF_BUF(tx3904_serial_out_buf0), + &tx3904_serial_in_buf0[0], + SIZEOF_BUF(tx3904_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(tx3904_serial_channel0, + tx3904_serial_funs, + tx3904_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 +#if CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE > 0 +static SERIAL_CHANNEL_USING_INTERRUPTS(tx3904_serial_channel1, + tx3904_serial_funs, + tx3904_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &tx3904_serial_out_buf1[0], + SIZEOF_BUF(tx3904_serial_out_buf1), + &tx3904_serial_in_buf1[0], + SIZEOF_BUF(tx3904_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(tx3904_serial_channel1, + tx3904_serial_funs, + tx3904_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 + +//------------------------------------------------------------------------- +// And finally, the device table entries: + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 +DEVTAB_ENTRY(tx3904_serial_io0, + CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + tx3904_serial_init, + tx3904_serial_lookup, // Serial driver may need initializing + &tx3904_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 +DEVTAB_ENTRY(tx3904_serial_io1, + CYGDAT_IO_SERIAL_TX39_JMR3904_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + tx3904_serial_init, + tx3904_serial_lookup, // Serial driver may need initializing + &tx3904_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL1 + +// ------------------------------------------------------------------------ +// Delay for some number of character times. This is based on the baud +// rate currently set. We use the numbers that plug in to the BRG +// clock select and divider to control two loops. The innermost delay +// loop uses a count that is derived from dividing the CPU frequency +// by the BRG granularity (and we then add 1 to compensate for any +// rounding). This gives the number of cycles that the innermost loop +// must consume. For the sake of simplicity we assume that this loop +// will take 1 cycle per loop, which is roughly true in optimized +// code. + +void delay_char_time(tx3904_serial_info *tx3904_chan, int n) +{ + static cyg_uint16 clock_val[4] = { 4, 16, 64, 256 }; + cyg_uint16 baud_val = select_baud[tx3904_chan->cur_baud]; + cyg_count32 clock_loop = clock_val[baud_val>>8]; + cyg_count32 div_loop = baud_val & 0xFF; + cyg_count32 bit_time = ((CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL)/(2457600)) + 1; + + n *= 11; // allow for start and stop bits and 8 data bits + + while( n-- ) + { + cyg_count32 i,j,k; + + for( i = 0; i < clock_loop; i++ ) + for( j = 0; j < div_loop; j++ ) + for( k = 0; k < bit_time; k++ ) + continue; + } +} + +//------------------------------------------------------------------------- + +static bool +tx3904_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 cr = 0; + cyg_uint16 icr = 0; + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + + if (baud_divisor == 0) + return false; // Invalid baud rate selected + + // set up other config values: + + cr |= select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + cr |= select_stop_bits[new_config->stop]; + cr |= select_parity[new_config->parity]; + + // Source transfer clock from BRG + cr |= LCR_BRG; + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + // Enable RX interrupts only at present +#ifdef CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0 + if ((chan->out_cbuf.len != 0) || (chan == &tx3904_serial_channel0)) { +#else + if (chan->out_cbuf.len != 0) { +#endif + icr |= ICR_RXE; + } +#endif + + // Avoid any interrupts while we are fiddling with the line parameters. + cyg_drv_interrupt_mask(tx3904_chan->int_num); + + + // In theory we should wait here for the transmitter to drain the + // FIFO so we dont change the line parameters with characters + // unsent. Unfortunately the TX39 serial devices do not allow us + // to discover when the FIFO is empty. + + delay_char_time(tx3904_chan, 8); + + // Disable device entirely. +// HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_CR, 0); +// HAL_WRITE_UINT8(tx3904_chan->base+SERIAL_ICR, 0); + + // Reset the FIFOs + + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_FCR, 7); + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_FCR, 0); + + // Set up baud rate + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_BRG, baud_divisor ); + + // Write CR into hardware + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_CR, cr); + + // Write ICR into hardware + HAL_WRITE_UINT16(tx3904_chan->base+SERIAL_ICR, icr); + + // Re-enable interrupts. + cyg_drv_interrupt_unmask(tx3904_chan->int_num); + + // Save current baud rate + tx3904_chan->cur_baud = new_config->baud; + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +//------------------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. + +bool tx3904_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + + tx3904_chan->cur_baud = CYGNUM_SERIAL_BAUD_38400; + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + if (chan->out_cbuf.len != 0) { + // Install and enable the interrupt + cyg_drv_interrupt_create(tx3904_chan->int_num, + 4, // Priority + (cyg_addrword_t)chan, // Data item passed to interrupt handler + (cyg_ISR_t *)tx3904_serial_ISR, + tx3904_serial_DSR, + &tx3904_chan->interrupt_handle, + &tx3904_chan->interrupt); + cyg_drv_interrupt_attach(tx3904_chan->interrupt_handle); + cyg_drv_interrupt_unmask(tx3904_chan->int_num); + } +#endif + + tx3904_serial_config_port(chan, &chan->config, true); + + return true; +} + +//------------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) + +static Cyg_ErrNo +tx3904_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +//------------------------------------------------------------------------- +// Return 'true' if character is sent to device + +bool +tx3904_serial_putc(serial_channel *chan, unsigned char c) +{ + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 isr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + if( isr & ISR_TXRDY ) + { + HAL_WRITE_UINT8( tx3904_chan->base+SERIAL_TXB, c ); + + isr &= ~ISR_TXRDY; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + return true; + } + else return false; +} + +//------------------------------------------------------------------------- + +unsigned char +tx3904_serial_getc(serial_channel *chan) +{ + unsigned char c; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 isr; + + do + { + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + // Eliminate any RX errors + if( isr & ISR_ERROR ) + { + cyg_uint16 sr = 0; + + isr &= ISR_ERROR; + +// HAL_READ_UINT16( tx3904_chan->base+SERIAL_SR, sr ); + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_SR, sr ); + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + } + + } while( (isr & ISR_RXRDY) != ISR_RXRDY ); + + HAL_READ_UINT8( tx3904_chan->base+SERIAL_RXB, c ); + + isr &= ~ISR_RXRDY; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + return c; +} + +//------------------------------------------------------------------------- + +static Cyg_ErrNo +tx3904_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != tx3904_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------------------------------------------- +// Enable the transmitter on the device + +static void +tx3904_serial_start_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 icr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); + + icr |= ICR_TXE; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); +#endif +} + +//------------------------------------------------------------------------- +// Disable the transmitter on the device + +static void +tx3904_serial_stop_xmit(serial_channel *chan) +{ +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint16 icr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); + + icr &= ~ICR_TXE; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ICR, icr ); +#endif +} + +//------------------------------------------------------------------------- +// Serial I/O - low level interrupt handlers (ISR) + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + +static cyg_uint32 +tx3904_serial_ISR(cyg_vector_t vector, cyg_addrword_t data, cyg_addrword_t *regs) +{ + serial_channel *chan = (serial_channel *)data; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint8 isr; + cyg_uint32 result = 0; + + cyg_drv_interrupt_mask(tx3904_chan->int_num); + cyg_drv_interrupt_acknowledge(tx3904_chan->int_num); + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + // Eliminate any RX errors + if( isr & ISR_ERROR ) + { + cyg_uint16 sr = 0; + + isr &= ~ISR_ERROR; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_SR, sr ); + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_SR, 0 ); + } + + // Check for a TX interrupt and set the flag if so. + if( isr & ISR_TXRDY ) + { + isr &= ~ISR_TXRDY; + + tx3904_chan->output_ready = true; + + result |= CYG_ISR_CALL_DSR; // Cause DSR to be run + } + + + // Check here for an RX interrupt and fetch the character. If it + // is a ^C then call into GDB stub to handle it. + + if( isr & ISR_RXRDY ) + { + cyg_uint8 rxb; + HAL_READ_UINT8( tx3904_chan->base+SERIAL_RXB, rxb ); + + isr &= ~ISR_RXRDY; + + if( cyg_hal_is_break( &rxb , 1 ) ) + cyg_hal_user_break( regs ); + else + { + tx3904_chan->input_char = rxb; + tx3904_chan->input_char_valid = true; + result |= CYG_ISR_CALL_DSR; // Cause DSR to be run + } + + } + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + return result; +} + + +#endif + +//------------------------------------------------------------------------- +// Serial I/O - high level interrupt handler (DSR) + +#ifndef CYGPKG_IO_SERIAL_TX39_JMR3904_POLLED_MODE + +static void +tx3904_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + tx3904_serial_info *tx3904_chan = (tx3904_serial_info *)chan->dev_priv; + cyg_uint8 isr; + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + if( tx3904_chan->input_char_valid ) + { + (chan->callbacks->rcv_char)(chan, tx3904_chan->input_char); + + tx3904_chan->input_char_valid = false; + +#if 0 + // And while we are here, pull any further characters out of the + // FIFO. This should help to reduce the interrupt rate. + + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + + while( isr & ISR_RXRDY ) + { + cyg_uint8 rxb; + HAL_READ_UINT8( tx3904_chan->base+SERIAL_RXB, rxb ); + + (chan->callbacks->rcv_char)(chan, rxb); + + isr &= ~ISR_RXRDY; + + HAL_WRITE_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + HAL_READ_UINT16( tx3904_chan->base+SERIAL_ISR, isr ); + } +#endif + + } + + if( tx3904_chan->output_ready ) + { + (chan->callbacks->xmt_char)(chan); + + tx3904_chan->output_ready = false; + } + + cyg_drv_interrupt_unmask(tx3904_chan->int_num); +} + +#endif +#endif // CYGPKG_IO_SERIAL_TX39_JMR3904 + +//------------------------------------------------------------------------- +// EOF tx3904_serial.c diff --git a/ecos/packages/devs/serial/mips/ref4955/current/ChangeLog b/ecos/packages/devs/serial/mips/ref4955/current/ChangeLog new file mode 100644 index 0000000..fbaff46 --- /dev/null +++ b/ecos/packages/devs/serial/mips/ref4955/current/ChangeLog @@ -0,0 +1,60 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_ref4955.cdl: Remove irrelevant doc link. + +2000-09-18 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_ref4955.cdl: Use CDL to specify testing parameters. + + * include/mips_tx49_ref4955_ser.inl: Follow type naming changes in + generic driver. + +2000-09-14 Jesper Skov <jskov@redhat.com> + + * include/mips_tx49_ref4955_ser.inl: Use with generic 16x5x serial + driver. + * src/ref4955_serial.c: Deleted. + * src/ref4955_serial.h: Deleted. + * cdl/ser_mips_ref4955.cdl: Changed accordingly. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/ref4955_serial.c (pc_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-05-25 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_ref4955.cdl: + * src/ref4955_serial.h: + * src/ref4955_serial.c: + REF4955 serial driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl b/ecos/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl new file mode 100644 index 0000000..4570fe3 --- /dev/null +++ b/ecos/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl @@ -0,0 +1,182 @@ +# ==================================================================== +# +# ser_mips_ref4955.cdl +# +# eCos serial MIPS/REF4955 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 2000-05-24 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_REF4955 { + display "REF4955 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_TX49_REF4955 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + REF4955." + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/mips_tx49_ref4955_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_mips_ref4955.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 { + display "REF4955 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the + REF4955 port 0." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED +# implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW +# implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME { + display "Device name for the REF4955 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the + REF4955 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD { + display "Baud rate for the REF4955 serial port 0 driver" + flavor data + legal_values { 1200 2400 4800 9600 14400 19200 38400 57600 115200} + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the REF4955 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE { + display "Buffer size for the REF4955 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the REF4955 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL1 { + display "REF4955 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the + REF4955 port 1." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED +# implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW +# implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL1_NAME { + display "Device name for the REF4955 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for + the REF4955 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD { + display "Baud rate for the REF4955 serial port 1 driver" + flavor data + legal_values { 1200 2400 4800 9600 14400 19200 38400 57600 115200} + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the REF4955 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE { + display "Buffer size for the REF4955 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the REF4955 port 1." + } + } + + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"ref4955\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_ref4955.cdl diff --git a/ecos/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl b/ecos/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl new file mode 100644 index 0000000..ea514f3 --- /dev/null +++ b/ecos/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl @@ -0,0 +1,176 @@ +//========================================================================== +// +// devs/serial/mips/ref4955/src/mips_tx49_ref4955_ser.inl +// +// REF4955 Serial I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 2000-05-24 +// Purpose: REF4955 Serial definitions +//####DESCRIPTIONEND#### +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// There are two serial ports. +#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1 +#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2 + +//----------------------------------------------------------------------------- +// The REF4955 board has a 14.318 MHz crystal, but the PC87338 part +// uses a 24MHz internal clock for baud rate calculation. +#define BAUD_DIVISOR(_x_) 24000000/13/16/(_x_) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + BAUD_DIVISOR(1200), + 0, // 1800 + BAUD_DIVISOR(2400), + 0, // 3600 + BAUD_DIVISOR(4800), + 0 , // 7200 + BAUD_DIVISOR(9600), + BAUD_DIVISOR(14400), + BAUD_DIVISOR(19200), + BAUD_DIVISOR(38400), + BAUD_DIVISOR(57600), + BAUD_DIVISOR(115200), + 0, // 230400 +}; + +//----------------------------------------------------------------------------- +// Port 0 descriptors + +#ifdef CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 +static pc_serial_info pc_serial_info0 = {CYG_DEVICE_SERIAL_SCC1, + CYGNUM_HAL_INTERRUPT_DEBUG_UART}; +#if CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE > 0 +static unsigned char pc_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE]; +static unsigned char pc_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf0[0], + sizeof(pc_serial_out_buf0), + &pc_serial_in_buf0[0], + sizeof(pc_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io0, + CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel0 + ); +#endif + +//----------------------------------------------------------------------------- +// Port 1 descriptors + +#ifdef CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL1 +static pc_serial_info pc_serial_info1 = {CYG_DEVICE_SERIAL_SCC2, + CYGNUM_HAL_INTERRUPT_USER_UART}; +#if CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE > 0 +static unsigned char pc_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE]; +static unsigned char pc_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf1[0], + sizeof(pc_serial_out_buf1), + &pc_serial_in_buf1[0], + sizeof(pc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io1, + CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel1 + ); +#endif + +// EOF mips_tx49_ref4955_ser.inl diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/ChangeLog b/ecos/packages/devs/serial/mips/upd985xx/current/ChangeLog new file mode 100644 index 0000000..4b52d82 --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/ChangeLog @@ -0,0 +1,43 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_upd985xx.cdl: Remove irrelevant doc link. + +2002-02-11 Jesper Skov <jskov@redhat.com> + + * src/upd985xx_serial.c (upd985xx_serial_init): Fix compile error. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_upd985xx.cdl: + Fix 234000->230400 typo. + +2001-07-18 Hugo Tyson <hmt@redhat.com> + + * src/upd985xx_serial.c: + * src/upd985xx_serial.h: + * cdl/ser_mips_upd985xx.cdl: + New files; implement asynchronous serial device for uPD985xx. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/cdl/ser_mips_upd985xx.cdl b/ecos/packages/devs/serial/mips/upd985xx/current/cdl/ser_mips_upd985xx.cdl new file mode 100644 index 0000000..6669288 --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/cdl/ser_mips_upd985xx.cdl @@ -0,0 +1,164 @@ +# ==================================================================== +# +# ser_mips_upd985xx.cdl +# +# eCos serial MIPS/Upd985xx configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): hmt +# Contributors: gthomas +# Date: 2001-07-17 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_UPD985XX { + display "NEC uPD985xx serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_UPD985XX + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + NEC MIPS uPD985xx system-on-chip device." + + compile -library=libextras.a upd985xx_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_upd985xx.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL0 { + display "MIPS UPD985XX serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the MIPS UPD985XX + serial port." + + cdl_option CYGDAT_IO_SERIAL_MIPS_UPD985XX_SERIAL0_NAME { + display "Device name for MIPS UPD985XX serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of the serial device for the + MIPS UPD985XX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BAUD { + display "Baud rate for the MIPS UPD985XX serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + MIPS UPD985XX port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE { + display "Buffer size for the MIPS UPD985XX serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MIPS UPD985XX port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_UPD985XX_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_UPD985XX_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_UPD985XX_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_UPD985XX_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_UPD985XX_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"upd985xx\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_upd985xx.cdl diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.c b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.c new file mode 100644 index 0000000..402ea9c --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.c @@ -0,0 +1,312 @@ +//========================================================================== +// +// io/serial/mips/upd985xx/upd985xx_serial.c +// +// NEC MIPS uPD985xx Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: gthomas +// Date: 2001-07-17 +// Purpose: NEC MIPS uPD985xx Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#include "upd985xx_serial.h" + +typedef struct upd985xx_serial_info { +// CYG_ADDRWORD base; + CYG_WORD int_num; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} upd985xx_serial_info; + +static bool upd985xx_serial_init(struct cyg_devtab_entry *tab); +static bool upd985xx_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo upd985xx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char upd985xx_serial_getc(serial_channel *chan); +static Cyg_ErrNo upd985xx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void upd985xx_serial_start_xmit(serial_channel *chan); +static void upd985xx_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 upd985xx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void upd985xx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(upd985xx_serial_funs, + upd985xx_serial_putc, + upd985xx_serial_getc, + upd985xx_serial_set_config, + upd985xx_serial_start_xmit, + upd985xx_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL0 +static upd985xx_serial_info upd985xx_serial_info0 = { + // base: (CYG_ADDRWORD)UPD985XX_UART3_CONTROL0, + int_num: CYGNUM_HAL_INTERRUPT_UART, +}; +#if CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE > 0 +static unsigned char upd985xx_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE]; +static unsigned char upd985xx_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS( + upd985xx_serial_channel0, + upd985xx_serial_funs, + upd985xx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &upd985xx_serial_out_buf0[0], sizeof(upd985xx_serial_out_buf0), + &upd985xx_serial_in_buf0[0], sizeof(upd985xx_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL( + upd985xx_serial_channel0, + upd985xx_serial_funs, + upd985xx_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_UPD985XX_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(upd985xx_serial_io0, + CYGDAT_IO_SERIAL_MIPS_UPD985XX_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + upd985xx_serial_init, + upd985xx_serial_lookup, // Serial driver may need initializing + &upd985xx_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_UPD985XX_SERIAL1 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +upd985xx_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + unsigned char parity; + unsigned char word_length; + unsigned char stop_bits; + int baud; + + parity = select_parity[new_config->parity]; + word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5]; + stop_bits = select_stop_bits[new_config->stop]; + baud = select_baud[new_config->baud]; + + if ((word_length == 0xFF) || + (parity == 0xFF) || + (stop_bits == 0xFF)) { + return false; // Unsupported configuration + } + + // First ensure we are accessing the right registers. + // Clear the divisor latch access bit + *UARTLCR &=~UARTLCR_DLAB; + + // Disable Receiver and Transmitter + // No such thing in uPD985xx - but we can mask interrupts: + *UARTIER = 0; + + // Clear sticky (writable) status bits. + // Ensure it's in 16550 mode at least: + *UARTFCR = UARTFCR_16550_MODE; + + // Set parity, word length, stop bits (keep DLAB clear) + *UARTLCR = word_length | parity | stop_bits; + + // Set the desired baud rate. + *UARTLCR |= UARTLCR_DLAB; + *UARTDLM = (baud >> 8) & 0xff; + *UARTDLL = baud & 0xff; + *UARTLCR &=~UARTLCR_DLAB; + + // Enable the receiver (with interrupts) and the transmitter. + *UARTIER = UARTIER_ERBFI; + + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +upd985xx_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + upd985xx_serial_info *upd985xx_chan = (upd985xx_serial_info *)chan->dev_priv; + int res; +#ifdef CYGDBG_IO_INIT + diag_printf("UPD985XX SERIAL init - dev: %x.%d\n", 0 /* upd985xx_chan->base */, + upd985xx_chan->int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(upd985xx_chan->int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + upd985xx_serial_ISR, + upd985xx_serial_DSR, + &upd985xx_chan->serial_interrupt_handle, + &upd985xx_chan->serial_interrupt); + cyg_drv_interrupt_attach(upd985xx_chan->serial_interrupt_handle); + cyg_drv_interrupt_unmask(upd985xx_chan->int_num); + } + res = upd985xx_serial_config_port(chan, &chan->config, true); + return res; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +upd985xx_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +upd985xx_serial_putc(serial_channel *chan, unsigned char c) +{ + if ( 0 == (UARTLSR_THRE & *UARTLSR) ) + return false; + *UARTTHR = (unsigned int)c; + return true; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +upd985xx_serial_getc(serial_channel *chan) +{ + while ( 0 == (UARTLSR_DR & *UARTLSR) ) + /* do nothing */ ; + + return (char)*UARTRBR; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +upd985xx_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != upd985xx_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +upd985xx_serial_start_xmit(serial_channel *chan) +{ + (chan->callbacks->xmt_char)(chan); // Kick transmitter (if necessary) + *UARTIER |= UARTIER_ERBEI; // enable interrupts +} + +// Disable the transmitter on the device +static void +upd985xx_serial_stop_xmit(serial_channel *chan) +{ + *UARTIER &=~UARTIER_ERBEI; // disable interrupts +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +upd985xx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(vector); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +upd985xx_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + + int stat = *UARTIIR; + + stat &= UARTIIR_UIID_MASK; + + if (stat == UARTIIR_TX_EMPTY) { + (chan->callbacks->xmt_char)(chan); + } + if (stat == UARTIIR_RXD_AVAIL) { + while (0 != (UARTLSR_DR & *UARTLSR)) { + (chan->callbacks->rcv_char)(chan, (char)*UARTRBR); + } + } + cyg_drv_interrupt_acknowledge(vector); + cyg_drv_interrupt_unmask(vector); +} + +// ------------------------------------------------------------------------ +// EOF upd985xx_serial.c diff --git a/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.h b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.h new file mode 100644 index 0000000..ad9f96c --- /dev/null +++ b/ecos/packages/devs/serial/mips/upd985xx/current/src/upd985xx_serial.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_MIPS_UPD985XX_SERIAL_H +#define CYGONCE_MIPS_UPD985XX_SERIAL_H +// ==================================================================== +// +// upd985xx_serial.h +// +// Device I/O - Description of NEC MIPS uPD985xx serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: gthomas +// Date: 2001-07-17 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on NEC MIPS uPD985xx + +#include <cyg/hal/hal_arch.h> // Register definitions + +static unsigned char select_word_length[] = { + 0xFF, // 5 bits / word (char) + 0xFF, // 6 + UARTLCR_7, // 7 + UARTLCR_8 // 8 +}; + +static unsigned char select_stop_bits[] = { + 0xFF, // N/A + UARTLCR_STB1, // 1 stop bit + 0xFF, // 1.5 stop bit + UARTLCR_STB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + UARTLCR_NOP, // No parity + UARTLCR_EP, // Even parity + UARTLCR_OP, // Odd parity + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + UARTDLL_VAL( 50 ), // 50 + UARTDLL_VAL( 75 ), // 75 + UARTDLL_VAL( 110 ), // 110 + 0, // 134.5 + UARTDLL_VAL( 150 ), // 150 + UARTDLL_VAL( 200 ), // 200 + UARTDLL_VAL( 300 ), // 300 + UARTDLL_VAL( 600 ), // 600 + UARTDLL_VAL( 1200 ), // 1200 + UARTDLL_VAL( 1800 ), // 1800 + UARTDLL_VAL( 2400 ), // 2400 + UARTDLL_VAL( 3600 ), // 3600 + UARTDLL_VAL( 4800 ), // 4800 + UARTDLL_VAL( 7200 ), // 7200 + UARTDLL_VAL( 9600 ), // 9600 + UARTDLL_VAL( 14400 ), // 14400 + UARTDLL_VAL( 19200 ), // 19200 + UARTDLL_VAL( 38400 ), // 38400 + UARTDLL_VAL( 57600 ), // 57600 + UARTDLL_VAL( 115200 ), // 115200 + UARTDLL_VAL( 230400 ), // 230400 +}; + +#endif // CYGONCE_MIPS_UPD985XX_SERIAL_H + +// ------------------------------------------------------------------------ +// EOF upd985xx_serial.h diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/ChangeLog b/ecos/packages/devs/serial/mips/vrc437x/current/ChangeLog new file mode 100644 index 0000000..88678cc --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/ChangeLog @@ -0,0 +1,1206 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_mips_vrc437x.cdl: Remove irrelevant doc link. + +2001-09-18 Nick Garnett <nickg@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + * src/vrc437x_serial.h: + * src/vrc437x_serial.c: + Fixed VRC4373 -> VRC437X conversions that were missed. + Also made default baud rates 38400 rather than 9600. + +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + Fix 234000->230400 typo. + +2001-09-07 Nick Garnett <nickg@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + * src/vrc437x_serial.h: + * src/vrc437x_serial.c: + Moved this entire tree over to vrc437x from vrc4373 to make it + generic to both kinds of board. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_vrc4373.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/vrc4373_serial.c (vrc4373_serial_set_config): Now use keys + to make more flexible. + +2000-07-22 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/vrc4373_serial.c (vrc4373_serial_init): Add comment about broken + interrupt handling + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_mips_vrc4373.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl b/ecos/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl new file mode 100644 index 0000000..fb459a0 --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl @@ -0,0 +1,202 @@ +# ==================================================================== +# +# ser_mips_vrc437x.cdl +# +# eCos serial MIPS/VRC437X configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_VRC437X { + display "VRC437X serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_VR4300_VRC437X + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + VRC437X." + + compile -library=libextras.a vrc437x_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_vrc437x.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 { + display "VRC437X serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the VRC437X port 0." + + cdl_option CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME { + display "Device name for the VRC437X serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the VRC437X + port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD { + display "Baud rate for the VRC437X serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + VRC437X port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE { + display "Buffer size for the VRC437X serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the VRC437X port 0." + } +} +cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 { + display "VRC437X serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the VRC437X port 1." + + cdl_option CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL1_NAME { + display "Device name for the VRC437X serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + VRC437X port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD { + display "Baud rate for the VRC437X serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + VRC437X port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE { + display "Buffer size for the VRC437X serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the VRC437X port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_VRC437X_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_VRC437X_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"vrc437X\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_vrc437x.cdl diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c new file mode 100644 index 0000000..96dc6d3 --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c @@ -0,0 +1,493 @@ +//========================================================================== +// +// io/serial/mips/vrc437x_serial.c +// +// Mips VRC437X Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-15 +// Purpose: VRC437X Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X + +#include "vrc437x_serial.h" + +#if defined(CYGPKG_HAL_MIPS_LSBFIRST) +#define VRC437X_SCC_BASE 0xC1000000 +#elif defined(CYGPKG_HAL_MIPS_MSBFIRST) +#define VRC437X_SCC_BASE 0xC1000003 +#else +#error MIPS endianness not defined by configuration +#endif + +#define VRC437X_SCC_INT CYGNUM_HAL_INTERRUPT_DUART +#define SCC_CHANNEL_A 4 +#define SCC_CHANNEL_B 0 + +extern void diag_printf(const char *fmt, ...); + +typedef struct vrc437x_serial_info { + CYG_ADDRWORD base; + unsigned char regs[16]; // Known register state (since hardware is write-only!) +} vrc437x_serial_info; + +static bool vrc437x_serial_init(struct cyg_devtab_entry *tab); +static bool vrc437x_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo vrc437x_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char vrc437x_serial_getc(serial_channel *chan); +static Cyg_ErrNo vrc437x_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void vrc437x_serial_start_xmit(serial_channel *chan); +static void vrc437x_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void vrc437x_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(vrc437x_serial_funs, + vrc437x_serial_putc, + vrc437x_serial_getc, + vrc437x_serial_set_config, + vrc437x_serial_start_xmit, + vrc437x_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 +static vrc437x_serial_info vrc437x_serial_info0 = {VRC437X_SCC_BASE+SCC_CHANNEL_A}; +#if CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE > 0 +static unsigned char vrc437x_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE]; +static unsigned char vrc437x_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(vrc437x_serial_channel0, + vrc437x_serial_funs, + vrc437x_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &vrc437x_serial_out_buf0[0], sizeof(vrc437x_serial_out_buf0), + &vrc437x_serial_in_buf0[0], sizeof(vrc437x_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(vrc437x_serial_channel0, + vrc437x_serial_funs, + vrc437x_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(vrc437x_serial_io0, + CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + vrc437x_serial_init, + vrc437x_serial_lookup, // Serial driver may need initializing + &vrc437x_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 +static vrc437x_serial_info vrc437x_serial_info1 = {VRC437X_SCC_BASE+SCC_CHANNEL_B}; +#if CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE > 0 +static unsigned char vrc437x_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE]; +static unsigned char vrc437x_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(vrc437x_serial_channel1, + vrc437x_serial_funs, + vrc437x_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &vrc437x_serial_out_buf1[0], sizeof(vrc437x_serial_out_buf1), + &vrc437x_serial_in_buf1[0], sizeof(vrc437x_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(vrc437x_serial_channel1, + vrc437x_serial_funs, + vrc437x_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(vrc437x_serial_io1, + CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + vrc437x_serial_init, + vrc437x_serial_lookup, // Serial driver may need initializing + &vrc437x_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 + +static cyg_interrupt vrc437x_serial_interrupt; +static cyg_handle_t vrc437x_serial_interrupt_handle; + +// Table which maps hardware channels (A,B) to software ones +struct serial_channel *vrc437x_chans[] = { +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 // Hardware channel A + &vrc437x_serial_channel0, +#else + 0, +#endif +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 // Hardware channel B + &vrc437x_serial_channel1, +#else + 0, +#endif +}; + +// Support functions which access the serial device. Note that this chip requires +// a substantial delay after each access. + +#define SCC_DELAY 100 +inline static void +scc_delay(void) +{ + int i; + for (i = 0; i < SCC_DELAY; i++) ; +} + +inline static void +scc_write_reg(volatile unsigned char *reg, unsigned char val) +{ + scc_delay(); + *reg = val; +} + +inline static unsigned char +scc_read_reg(volatile unsigned char *reg) +{ + unsigned char val; + scc_delay(); + val = *reg; + return (val); +} + +inline static unsigned char +scc_read_ctl(volatile struct serial_port *port, int reg) +{ + if (reg != 0) { + scc_write_reg(&port->scc_ctl, reg); + } + return (scc_read_reg(&port->scc_ctl)); +} + +inline static void +scc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val) +{ + if (reg != 0) { + scc_write_reg(&port->scc_ctl, reg); + } + scc_write_reg(&port->scc_ctl, val); +} + +inline static unsigned char +scc_read_dat(volatile struct serial_port *port) +{ + return (scc_read_reg(&port->scc_dat)); +} + +inline static void +scc_write_dat(volatile struct serial_port *port, unsigned char val) +{ + scc_write_reg(&port->scc_dat, val); +} + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +vrc437x_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + cyg_int32 baud_rate = select_baud[new_config->baud]; + cyg_int32 baud_divisor; + unsigned char *regs = &vrc437x_chan->regs[0]; + if (baud_rate == 0) return false; + // Compute state of registers. The register/control state needs to be kept in + // the shadow variable 'regs' because the hardware registers can only be written, + // not read (in general). + if (init) { + // Insert appropriate resets? + if (chan->out_cbuf.len != 0) { + regs[R1] = WR1_IntAllRx; + regs[R9] = WR9_MIE | WR9_NoVector; + } else { + regs[R1] = 0; + regs[R9] = 0; + } + // Clocks are from the baud rate generator + regs[R11] = WR11_TRxCBR | WR11_TRxCOI | WR11_TxCBR | WR11_RxCBR; + regs[R14] = WR14_BRenable | WR14_BRSRC; + regs[R10] = 0; // Unused in this [async] mode + regs[R15] = 0; + } + regs[R3] = WR3_RxEnable | select_word_length_WR3[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + regs[R4] = WR4_X16CLK | select_stop_bits[new_config->stop] | select_parity[new_config->parity]; + regs[R5] = WR5_TxEnable | select_word_length_WR5[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + baud_divisor = BRTC(baud_rate); + regs[R12] = baud_divisor & 0xFF; + regs[R13] = baud_divisor >> 8; + // Now load the registers + scc_write_ctl(port, R4, regs[R4]); + scc_write_ctl(port, R10, regs[R10]); + scc_write_ctl(port, R3, regs[R3] & ~WR3_RxEnable); + scc_write_ctl(port, R5, regs[R5] & ~WR5_TxEnable); + scc_write_ctl(port, R1, regs[R1]); + scc_write_ctl(port, R9, regs[R9]); + scc_write_ctl(port, R11, regs[R11]); + scc_write_ctl(port, R12, regs[R12]); + scc_write_ctl(port, R13, regs[R13]); + scc_write_ctl(port, R14, regs[R14]); + scc_write_ctl(port, R15, regs[R15]); + scc_write_ctl(port, R3, regs[R3]); + scc_write_ctl(port, R5, regs[R5]); + // Update configuration + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +vrc437x_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + static bool init = false; +#ifdef CYGDBG_IO_INIT + diag_printf("VRC437X SERIAL init '%s' - dev: %x\n", tab->name, vrc437x_chan->base); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (!init && chan->out_cbuf.len != 0) { + init = true; +// Note that the hardware is rather broken. The interrupt status needs to +// be read using only channel A + cyg_drv_interrupt_create(VRC437X_SCC_INT, + 99, + (cyg_addrword_t)VRC437X_SCC_BASE+SCC_CHANNEL_A, + vrc437x_serial_ISR, + vrc437x_serial_DSR, + &vrc437x_serial_interrupt_handle, + &vrc437x_serial_interrupt); + cyg_drv_interrupt_attach(vrc437x_serial_interrupt_handle); + cyg_drv_interrupt_unmask(VRC437X_SCC_INT); + } + vrc437x_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +vrc437x_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +vrc437x_serial_putc(serial_channel *chan, unsigned char c) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + if (scc_read_ctl(port, R0) & RR0_TxEmpty) { +// Transmit buffer is empty + scc_write_dat(port, c); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +vrc437x_serial_getc(serial_channel *chan) +{ + unsigned char c; + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + while ((scc_read_ctl(port, R0) & RR0_RxAvail) == 0) ; // Wait for char + c = scc_read_dat(port); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +vrc437x_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != vrc437x_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +vrc437x_serial_start_xmit(serial_channel *chan) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + if ((vrc437x_chan->regs[R1] & WR1_TxIntEnab) == 0) { + CYG_INTERRUPT_STATE old; + HAL_DISABLE_INTERRUPTS(old); + vrc437x_chan->regs[R1] |= WR1_TxIntEnab; // Enable Tx interrupt + scc_write_ctl(port, R1, vrc437x_chan->regs[R1]); + (chan->callbacks->xmt_char)(chan); // Send first character to start xmitter + HAL_RESTORE_INTERRUPTS(old); + } +} + +// Disable the transmitter on the device +static void +vrc437x_serial_stop_xmit(serial_channel *chan) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + if ((vrc437x_chan->regs[R1] & WR1_TxIntEnab) != 0) { + CYG_INTERRUPT_STATE old; + HAL_DISABLE_INTERRUPTS(old); + vrc437x_chan->regs[R1] &= ~WR1_TxIntEnab; // Disable Tx interrupt + scc_write_ctl(port, R1, vrc437x_chan->regs[R1]); + HAL_RESTORE_INTERRUPTS(old); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(VRC437X_SCC_INT); + cyg_drv_interrupt_acknowledge(VRC437X_SCC_INT); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +inline static void +vrc437x_int(serial_channel *chan, unsigned char stat) +{ + vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base; + // Note: 'stat' value is interrupt status register, shifted into "B" position + if (stat & RR3_BRxIP) { + // Receive interrupt + unsigned char c; + c = scc_read_dat(port); + (chan->callbacks->rcv_char)(chan, c); + } + if (stat & RR3_BTxIP) { + // Transmit interrupt + (chan->callbacks->xmt_char)(chan); + } + if (stat & RR3_BExt) { + // Status interrupt (parity error, framing error, etc) + } +} + +// Serial I/O - high level interrupt handler (DSR) +// Note: This device presents a single interrupt for both channels. Thus the +// interrupt handler has to query the device and decide which channel needs service. +// Additionally, more than one interrupt condition may be present so this needs to +// be done in a loop until all interrupt requests have been handled. +// Also note that the hardware is rather broken. The interrupt status needs to +// be read using only channel A (pointed to by 'data') +static void +vrc437x_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan; + volatile struct serial_port *port = (volatile struct serial_port *)data; + unsigned char stat; + while (true) { + stat = scc_read_ctl(port, R3); + if (stat & (RR3_AExt | RR3_ATxIP | RR3_ARxIP)) { + chan = vrc437x_chans[0]; // Hardware channel A + vrc437x_int(chan, stat>>3); // Handle interrupt + } else if (stat & (RR3_BExt | RR3_BTxIP | RR3_BRxIP)) { + chan = vrc437x_chans[1]; // Hardware channel B + vrc437x_int(chan, stat); // Handle interrupt + } else { + // No more interrupts, all done + break; + } + } + cyg_drv_interrupt_unmask(VRC437X_SCC_INT); +} +#endif diff --git a/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h new file mode 100644 index 0000000..23e4127 --- /dev/null +++ b/ecos/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h @@ -0,0 +1,343 @@ +#ifndef CYGONCE_MIPS_VRC437X_SERIAL_H +#define CYGONCE_MIPS_VRC437X_SERIAL_H + +// ==================================================================== +// +// vrc437x_serial.h +// +// Device I/O - Description of Mips VRC437X serial hardware +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-15 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Mips VRC437X +// Based on Zilog 85C30 SCC + +struct serial_port { + unsigned char _byte[16]; +}; + +#define scc_ctl _byte[0] +#define scc_dat _byte[8] + +#define R0 0 /* Register selects */ +#define R1 1 +#define R2 2 +#define R3 3 +#define R4 4 +#define R5 5 +#define R6 6 +#define R7 7 +#define R8 8 +#define R9 9 +#define R10 10 +#define R11 11 +#define R12 12 +#define R13 13 +#define R14 14 +#define R15 15 + +/* Write Register 0 */ +#define WR0_NullCode 0x00 /* Null Code */ +#define WR0_PointHigh 0x08 /* Select upper half of registers */ +#define WR0_ResExtInt 0x10 /* Reset Ext. Status Interrupts */ +#define WR0_SendAbort 0x18 /* HDLC Abort */ +#define WR0_ResRxIntFC 0x20 /* Reset RxINT on First Character */ +#define WR0_ResTxP 0x28 /* Reset TxINT Pending */ +#define WR0_ErrReset 0x30 /* Error Reset */ +#define WR0_ResHiIUS 0x38 /* Reset highest IUS */ + +#define WR0_ResRxCRC 0x40 /* Reset Rx CRC Checker */ +#define WR0_ResTxCRC 0x80 /* Reset Tx CRC Checker */ +#define WR0_ResEOMlatch 0xC0 /* Reset EOM latch */ + +/* Write Register 1 */ + +#define WR1_ExtIntEnab 0x01 /* Ext Int Enable */ +#define WR1_TxIntEnab 0x02 /* Tx Int Enable */ +#define WR1_ParSpec 0x04 /* Parity is special condition */ + +#define WR1_RxIntDisab 0x00 /* Rx Int Disable */ +#define WR1_RxIntFCE 0x08 /* Rx Int on First Character Only or Error */ +#define WR1_IntAllRx 0x10 /* Int on all Rx Characters or error */ +#define WR1_IntErrRx 0x18 /* Int on error only */ + +#define WR1_WtRdyRT 0x20 /* Wait/Ready on R/T */ +#define WR1_WtFnRdyFn 0x40 /* Wait/FN/Ready FN */ +#define WR1_WtRdyEnab 0x80 /* Wait/Ready Enable */ + +/* Write Register #2 (Interrupt Vector) */ + +/* Write Register 3 */ + +#define WR3_RxEnable 0x01 /* Rx Enable */ +#define WR3_SyncInhibit 0x02 /* Sync Character Load Inhibit */ +#define WR3_AddrSearch 0x04 /* Address Search Mode (SDLC) */ +#define WR3_RxCRC_ENAB 0x08 /* Rx CRC Enable */ +#define WR3_EntHuntMode 0x10 /* Enter Hunt Mode */ +#define WR3_AutoEnab 0x20 /* Auto Enables */ +#define WR3_Rx5 0x00 /* Rx 5 Bits/Character */ +#define WR3_Rx7 0x40 /* Rx 7 Bits/Character */ +#define WR3_Rx6 0x80 /* Rx 6 Bits/Character */ +#define WR3_Rx8 0xc0 /* Rx 8 Bits/Character */ +#define WR3_RxNbitsMask 0xc0 + +/* Write Register 4 */ + +#define WR4_ParityEn 0x01 /* Parity Enable */ +#define WR4_ParityEven 0x02 /* Parity Even/Odd* */ + +#define WR4_SyncEnable 0x00 /* Sync Modes Enable */ +#define WR4_SB1 0x04 /* 1 stop bit/char */ +#define WR4_SB15 0x08 /* 1.5 stop bits/char */ +#define WR4_SB2 0x0c /* 2 stop bits/char */ +#define WR4_SB_MASK 0x0c + +#define WR4_Monsync 0x00 /* 8 Bit Sync character */ +#define WR4_Bisync 0x10 /* 16 bit sync character */ +#define WR4_SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ +#define WR4_EXtSync 0x30 /* External Sync Mode */ + +#define WR4_X1CLK 0x00 /* x1 clock mode */ +#define WR4_X16CLK 0x40 /* x16 clock mode */ +#define WR4_X32CLK 0x80 /* x32 clock mode */ +#define WR4_X64CLK 0xC0 /* x64 clock mode */ +#define WR4_XCLK_MASK 0xC0 + +/* Write Register 5 */ + +#define WR5_TxCRCEnab 0x01 /* Tx CRC Enable */ +#define WR5_RTS 0x02 /* RTS */ +#define WR5_SDLC_CRC 0x04 /* SDLC/CRC-16 */ +#define WR5_TxEnable 0x08 /* Tx Enable */ +#define WR5_SendBreak 0x10 /* Send Break */ +#define WR5_Tx5 0x00 /* Tx 5 bits (or less)/character */ +#define WR5_Tx7 0x20 /* Tx 7 bits/character */ +#define WR5_Tx6 0x40 /* Tx 6 bits/character */ +#define WR5_Tx8 0x60 /* Tx 8 bits/character */ +#define WR5_TxNbitsMask 0x60 +#define WR5_DTR 0x80 /* DTR */ + +/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ + +/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ + +/* Write Register 8 (transmit buffer) */ + +/* Write Register 9 (Master interrupt control) */ +#define WR9_VIS 0x01 /* Vector Includes Status */ +#define WR9_NoVector 0x02 /* No Vector */ +#define WR9_DLC 0x04 /* Disable Lower Chain */ +#define WR9_MIE 0x08 /* Master Interrupt Enable */ +#define WR9_StatHi 0x10 /* Status high */ +#define WR9_NoReset 0x00 /* No reset on write to R9 */ +#define WR9_ResetB 0x40 /* Reset channel B */ +#define WR9_ResetA 0x80 /* Reset channel A */ +#define WR9_HwReset 0xc0 /* Force hardware reset */ + +/* Write Register 10 (misc control bits) */ +#define WR10_Bit6 0x01 /* 6 bit/8bit sync */ +#define WR10_LoopMode 0x02 /* SDLC Loop mode */ +#define WR10_AbrtUnder 0x04 /* Abort/flag on SDLC xmit underrun */ +#define WR10_MarkIdle 0x08 /* Mark/flag on idle */ +#define WR10_GAOP 0x10 /* Go active on poll */ +#define WR10_NRZ 0x00 /* NRZ mode */ +#define WR10_NRZI 0x20 /* NRZI mode */ +#define WR10_FM1 0x40 /* FM1 (transition = 1) */ +#define WR10_FM0 0x60 /* FM0 (transition = 0) */ +#define WR10_CRCPS 0x80 /* CRC Preset I/O */ + +/* Write Register 11 (Clock Mode control) */ +#define WR11_TRxCXT 0x00 /* TRxC = Xtal output */ +#define WR11_TRxCTC 0x01 /* TRxC = Transmit clock */ +#define WR11_TRxCBR 0x02 /* TRxC = BR Generator Output */ +#define WR11_TRxCDP 0x03 /* TRxC = DPLL output */ +#define WR11_TRxCOI 0x04 /* TRxC O/I */ +#define WR11_TxCRTxCP 0x00 /* Transmit clock = RTxC pin */ +#define WR11_TxCTRxCP 0x08 /* Transmit clock = TRxC pin */ +#define WR11_TxCBR 0x10 /* Transmit clock = BR Generator output */ +#define WR11_TxCDPLL 0x18 /* Transmit clock = DPLL output */ +#define WR11_RxCRTxCP 0x00 /* Receive clock = RTxC pin */ +#define WR11_RxCTRxCP 0x20 /* Receive clock = TRxC pin */ +#define WR11_RxCBR 0x40 /* Receive clock = BR Generator output */ +#define WR11_RxCDPLL 0x60 /* Receive clock = DPLL output */ +#define WR11_RTxCX 0x80 /* RTxC Xtal/No Xtal */ + +/* Write Register 12 (lower byte of baud rate generator time constant) */ + +/* Write Register 13 (upper byte of baud rate generator time constant) */ + +/* Write Register 14 (Misc control bits) */ +#define WR14_BRenable 0x01 /* Baud rate generator enable */ +#define WR14_BRSRC 0x02 /* Baud rate generator source */ +#define WR14_DTRreq 0x04 /* DTR/Request function */ +#define WR14_AutoEcho 0x08 /* Auto Echo */ +#define WR14_LoopBack 0x10 /* Local loopback */ +#define WR14_Search 0x20 /* Enter search mode */ +#define WR14_RMC 0x40 /* Reset missing clock */ +#define WR14_NoDPLL 0x60 /* Disable DPLL */ +#define WR14_SSBR 0x80 /* Set DPLL source = BR generator */ +#define WR14_SSRTxC 0xa0 /* Set DPLL source = RTxC */ +#define WR14_SFMM 0xc0 /* Set FM mode */ +#define WR14_SNRZI 0xe0 /* Set NRZI mode */ + +/* Write Register 15 (external/status interrupt control) */ +#define WR15_ZCIE 0x02 /* Zero count IE */ +#define WR15_DCDIE 0x08 /* DCD IE */ +#define WR15_SYNCIE 0x10 /* Sync/hunt IE */ +#define WR15_CTSIE 0x20 /* CTS IE */ +#define WR15_TxUIE 0x40 /* Tx Underrun/EOM IE */ +#define WR15_BRKIE 0x80 /* Break/Abort IE */ + +/* Read Register 0 */ +#define RR0_RxAvail 0x01 /* Rx Character Available */ +#define RR0_Zcount 0x02 /* Zero count */ +#define RR0_TxEmpty 0x04 /* Tx Buffer empty */ +#define RR0_DCD 0x08 /* DCD */ +#define RR0_SyncHunt 0x10 /* Sync/hunt */ +#define RR0_CTS 0x20 /* CTS */ +#define RR0_TxEOM 0x40 /* Tx underrun */ +#define RR0_BrkAbort 0x80 /* Break/Abort */ + +/* Read Register 1 */ +#define RR1_AllSent 0x01 /* All sent */ +/* Residue Data for 8 Rx bits/char programmed */ +#define RR1_RES3 0x08 /* 0/3 */ +#define RR1_RES4 0x04 /* 0/4 */ +#define RR1_RES5 0x0c /* 0/5 */ +#define RR1_RES6 0x02 /* 0/6 */ +#define RR1_RES7 0x0a /* 0/7 */ +#define RR1_RES8 0x06 /* 0/8 */ +#define RR1_RES18 0x0e /* 1/8 */ +#define RR1_RES28 0x00 /* 2/8 */ +/* Special Rx Condition Interrupts */ +#define RR1_PariryError 0x10 /* Parity error */ +#define RR1_RxOverrun 0x20 /* Rx Overrun Error */ +#define RR1_FrameError 0x40 /* CRC/Framing Error */ +#define RR1_EndOfFrame 0x80 /* End of Frame (SDLC) */ + +/* Read Register 2 (channel b only) - Interrupt vector */ + +/* Read Register 3 (interrupt pending register) ch a only */ +#define RR3_BExt 0x01 /* Channel B Ext/Stat IP */ +#define RR3_BTxIP 0x02 /* Channel B Tx IP */ +#define RR3_BRxIP 0x04 /* Channel B Rx IP */ +#define RR3_AExt 0x08 /* Channel A Ext/Stat IP */ +#define RR3_ATxIP 0x10 /* Channel A Tx IP */ +#define RR3_ARxIP 0x20 /* Channel A Rx IP */ + +/* Read Register 8 (receive data register) */ + +/* Read Register 10 (misc status bits) */ +#define RR10_OnLoop 0x02 /* On loop */ +#define RR10_LoopSend 0x10 /* Loop sending */ +#define RR10_Clk2Mis 0x40 /* Two clocks missing */ +#define RR10_Clk1Mis 0x80 /* One clock missing */ + +/* Read Register 12 (lower byte of baud rate generator constant) */ + +/* Read Register 13 (upper byte of baud rate generator constant) */ + +/* Read Register 15 (value of WR 15) */ + +#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) +#define DUART_CLOCK 4915200 /* Z8530 duart */ +#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ + +static unsigned char select_word_length_WR3[] = { + WR3_Rx5, // 5 bits / word (char) + WR3_Rx6, + WR3_Rx7, + WR3_Rx8 +}; + +static unsigned char select_word_length_WR5[] = { + WR5_Tx5, // 5 bits / word (char) + WR5_Tx6, + WR5_Tx7, + WR5_Tx8 +}; + +static unsigned char select_stop_bits[] = { + 0, + WR4_SB1, // 1 stop bit + WR4_SB15, // 1.5 stop bit + WR4_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + 0, // No parity + WR4_ParityEn | WR4_ParityEven, // Even parity + WR4_ParityEn, // Odd parity + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_MIPS_VRC437X_SERIAL_H |