u-boot-toradex.git - U-Boot bootloader for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2023-02-01	riscv: cpu: check U-Mode before counteren write	Nikita Shubin
2022-11-15	riscv: Fix detecting FPU support in standard extension	Yu Chien Peter Lin
2022-09-26	riscv: Introduce AVAILABLE_HARTS	Rick Chen
2022-09-26	spl: introduce SPL_XIP to config	Nikita Shubin
2022-03-10	event: Convert arch_cpu_init_dm() to use events	Simon Glass
2021-10-18	riscv: Remove OF_PRIOR_STAGE from RISC-V boards	Ilias Apalodimas
2021-10-07	sysreset: provide SBI based sysreset driver	Heinrich Schuchardt
2021-05-24	treewide: Convert macro and uses of __section(foo) to __section("foo")	Marek Behún
2021-05-05	riscv: cpu: Add callback to init each core	Green Wan
2020-09-30	riscv: Clear pending IPIs on initialization	Sean Anderson
2020-07-24	riscv: Make SiFive HiFive Unleashed board boot again	Bin Meng
2020-07-01	riscv: Add option to support RISC-V privileged spec 1.9	Sean Anderson
2020-07-01	riscv: Clean up IPI initialization code	Sean Anderson
2020-05-18	common: Drop linux/bitops.h from common header	Simon Glass
2020-05-18	common: Drop init.h from common header	Simon Glass
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer
2019-08-15	riscv: Access CSRs using CSR numbers	Bin Meng
2019-05-09	riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...	Rick Chen
2019-05-09	riscv: Introduce CONFIG_XIP to support booting from flash	Rick Chen
2019-04-08	riscv: add support for multi-hart systems	Lukas Auer
2018-12-18	riscv: Do some basic architecture level cpu initialization	Bin Meng
2018-12-18	riscv: Update supports_extension() to use desc from cpu driver	Bin Meng
2018-12-18	riscv: Remove non-DM version of print_cpuinfo()	Bin Meng
2018-12-18	riscv: Probe cpus during boot	Bin Meng
2018-11-26	riscv: save hart ID and device tree passed by prior boot stage	Lukas Auer
2018-10-03	riscv: Add a helper routine to print CPU information	Bin Meng