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path: root/arch/riscv/cpu
AgeCommit message (Expand)Author
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang
2023-02-17configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin
2023-02-17riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPLYu Chien Peter Lin
2023-02-17riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang
2023-02-01riscv: ax25: bypass malloc when spl fit boots from ramRick Chen
2023-02-01riscv: ae350: Enable CCTL_SUENRick Chen
2023-02-01riscv: cpu: check U-Mode before counteren writeNikita Shubin
2022-11-15riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ...Tom Rini
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen
2022-09-26spl: introduce SPL_XIP to configNikita Shubin
2022-09-23board_f: Fix types for board_get_usable_ram_top()Pali Rohár
2022-08-11riscv: ae350: Fix XIP config boot failureLeo Yu-Chi Liang
2022-08-11riscv: cpu: set gp before board_init_f_init_reserveNikita Shubin
2022-06-23linker_lists: Rename sections to remove . prefixAndrew Scull
2022-06-06Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini
2022-03-10event: Convert arch_cpu_init_dm() to use eventsSimon Glass
2021-12-02riscv: Enable SPI flash env for SiFive Unmatched.Thomas Skibo
2021-10-18riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas
2021-10-07riscv: ae350: enable Coherence Manager for ae350Leo Yu-Chi Liang
2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt
2021-09-07board: sifive: use ccache driver instead of helper functionZong Li
2021-08-17riscv: cpu: fu740: Fix typo of dateZong Li
2021-07-28i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li
2021-05-31riscv: cpu: fu740: clear feature disable CSRGreen Wan
2021-05-31drivers: clk: add fu740 supportGreen Wan
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún
2021-05-19riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng
2021-05-14Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng
2021-05-05riscv: cpu: fu740: clear feature disable CSRGreen Wan
2021-05-05riscv: cpu: Add callback to init each coreGreen Wan
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini
2021-02-03riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass
2020-12-14riscv: fix the wrong swap value registerBrad Kim
2020-11-28riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel
2020-10-26timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson
2020-09-30riscv: Add some comments to start.SSean Anderson
2020-09-30riscv: Ensure gp is NULL or points to valid dataSean Anderson
2020-09-30riscv: Consolidate fences into AMOs for available_harts_lockSean Anderson
2020-09-30riscv: Clear pending IPIs on initializationSean Anderson
2020-09-30Revert "riscv: Clear pending interrupts before enabling IPIs"Sean Anderson
2020-09-30riscv: Rework riscv timer driver to only support S-modeSean Anderson