diff options
Diffstat (limited to 'ecos/packages/devs/serial/sh')
19 files changed, 4769 insertions, 0 deletions
diff --git a/ecos/packages/devs/serial/sh/cq7708/current/ChangeLog b/ecos/packages/devs/serial/sh/cq7708/current/ChangeLog new file mode 100644 index 0000000..e32de66 --- /dev/null +++ b/ecos/packages/devs/serial/sh/cq7708/current/ChangeLog @@ -0,0 +1,62 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_cq7708.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_cq7708_sci.inl: Serial register renaming. + +2002-04-23 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_cq7708_sci.inl (sh_serial_info): Use variant + register definition for base. + +2000-10-03 Jesper Skov <jskov@redhat.co.uk> + + * cdl/ser_sh_cq7708.cdl: Added testing parameters. + + * include/sh_sh3_cq7708_sci.inl: Use named elements in structure + initializer. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Moved to SCI package. + * scr/sh_sci_cq7708.inl: moved... + * include/sh_sh3_cq7708_sci.inl: ... to here. + * cdl/ser_sh_cq7708.cdl: Matching changes. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh_sci_serial.c (sh_serial_set_config): Now use keys to make + more flexible. + +2000-06-23 Jesper Skov <jskov@redhat.com> + + + * Imported sources contributed by Haruki Kashiwaya + (kashiwaya at redhat dot com). Still need to fix this to properly + share the driver with the EDK (and any other platform using SCI). + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/cq7708/current/cdl/ser_sh_cq7708.cdl b/ecos/packages/devs/serial/sh/cq7708/current/cdl/ser_sh_cq7708.cdl new file mode 100644 index 0000000..01aa6fd --- /dev/null +++ b/ecos/packages/devs/serial/sh/cq7708/current/cdl/ser_sh_cq7708.cdl @@ -0,0 +1,130 @@ +# ==================================================================== +# +# ser_sh_cq7708.cdl +# +# eCos serial SH/CQ7708 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_CQ7708 { + display "SH3 cq7708 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_SH7708_CQ7708 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + CQ SH3 cq7708 board, based on the generic SH SCI driver." + + # FIXME: This really belongs in the SH_SCI package + cdl_interface CYGINT_IO_SERIAL_SH_SCI_REQUIRED { + display "SH SCI driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_INL <cyg/io/sh_sh3_cq7708_sci.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_CFG <pkgconf/io_serial_sh_cq7708.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_SH_CQ7708_SERIAL1 { + display "SH3 CQ7708 serial 1 device driver (SCI)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SCI + port." + + implements CYGINT_IO_SERIAL_SH_SCI_REQUIRED + + cdl_option CYGDAT_IO_SERIAL_SH_CQ7708_SERIAL1_NAME { + display "Device name for SH3 CQ7708 SCI" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BAUD { + display "Baud rate for the SH SCI driver" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE { + display "Buffer size for the SH SCI driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the SCI port." + } + } + + cdl_component CYGPKG_IO_SERIAL_SH_CQ7708_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_CQ7708_SERIAL1 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-cq7708\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_CQ7708_SERIAL1_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} +# EOF ser_sh_cq7708.cdl diff --git a/ecos/packages/devs/serial/sh/cq7708/current/include/sh_sh3_cq7708_sci.inl b/ecos/packages/devs/serial/sh/cq7708/current/include/sh_sh3_cq7708_sci.inl new file mode 100644 index 0000000..fcf6210 --- /dev/null +++ b/ecos/packages/devs/serial/sh/cq7708/current/include/sh_sh3_cq7708_sci.inl @@ -0,0 +1,104 @@ +#ifndef CYGONCE_DEVS_SH_CQ7708_SCI_H +#define CYGONCE_DEVS_SH_CQ7708_SCI_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_cq7708_sci.inl +// +// Serial I/O Interface Module definitions for SH3/CQ7708 +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-06-16 +// Purpose: Defines SCI serial resources for SH3/CQ7708. +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + + +#include <pkgconf/io_serial_sh_cq7708.h> + +static sh_sci_info sh_serial_info = +{ + data : CYGARC_REG_SCI_SCSPTR, + er_int_num : CYGNUM_HAL_INTERRUPT_SCI_ERI, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCI_RXI, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCI_TXI, + ctrl_base : CYGARC_REG_SCI_SCSMR +}; + +#if CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE > 0 +static unsigned char sh_serial_out_buf[CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE]; +static unsigned char sh_serial_in_buf[CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sh_serial_out_buf[0], + sizeof(sh_serial_out_buf), + &sh_serial_in_buf[0], + sizeof(sh_serial_in_buf) + ); +#else +static SERIAL_CHANNEL(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_CQ7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io, + CYGDAT_IO_SERIAL_SH_CQ7708_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_serial_init, + sh_serial_lookup, // Serial driver may need initializing + &sh_serial_channel + ); + +#endif // CYGONCE_DEVS_SH_CQ7708_SCI_H diff --git a/ecos/packages/devs/serial/sh/edk7708/current/ChangeLog b/ecos/packages/devs/serial/sh/edk7708/current/ChangeLog new file mode 100644 index 0000000..6d6ee70 --- /dev/null +++ b/ecos/packages/devs/serial/sh/edk7708/current/ChangeLog @@ -0,0 +1,1204 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_edk7708.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_edk7708_sci.inl: Serial register renaming. + +2002-04-23 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_edk7708_sci.inl (sh_serial_info): Use variant + register definition for base. + +2000-10-03 Jesper Skov <jskov@redhat.co.uk> + + * cdl/ser_sh_edk7708.cdl: Added testing parameters. + + * include/sh_sh3_edk7708_sci.inl: Use named elements in structure + initializer. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Moved to SCI package. + * src/sh_sci_7708.inl: Moved ... + * include/sh_sh3_edk7708_sci.inl: ... to here. + * cdl/ser_sh_edk7708.cdl: Matching changes. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh_sci_serial.c (sh_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sh_edk7708.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-11 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Move compile statement into a + sub-component. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/edk7708/current/cdl/ser_sh_edk7708.cdl b/ecos/packages/devs/serial/sh/edk7708/current/cdl/ser_sh_edk7708.cdl new file mode 100644 index 0000000..e71d578 --- /dev/null +++ b/ecos/packages/devs/serial/sh/edk7708/current/cdl/ser_sh_edk7708.cdl @@ -0,0 +1,130 @@ +# ==================================================================== +# +# ser_sh_edk7708.cdl +# +# eCos serial SH/EDK7708 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_EDK7708 { + display "SH3 EDK7708 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_EDK7708 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Hitachi SH3 EDK7708 board, based on the generic SH SCI driver." + + # FIXME: This really belongs in the SH_SCI package + cdl_interface CYGINT_IO_SERIAL_SH_SCI_REQUIRED { + display "SH SCI driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_INL <cyg/io/sh_sh3_edk7708_sci.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCI_CFG <pkgconf/io_serial_sh_edk7708.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_SH_EDK7708_SERIAL1 { + display "SH EDK7708 serial 1 driver (SCI)" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SCI + port." + + implements CYGINT_IO_SERIAL_SH_SCI_REQUIRED + + cdl_option CYGDAT_IO_SERIAL_SH_EDK7708_SERIAL1_NAME { + display "Device name for SH3 EDK7708 SCI" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BAUD { + display "Baud rate for the SH SCI driver" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the SCI port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE { + display "Buffer size for the SH SCI driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the SCI port." + } + } + + cdl_component CYGPKG_IO_SERIAL_SH_EDK7708_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_EDK7708_SERIAL1 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-edk7708\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_EDK7708_SERIAL1_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} +# EOF ser_sh_edk7708.cdl diff --git a/ecos/packages/devs/serial/sh/edk7708/current/include/sh_sh3_edk7708_sci.inl b/ecos/packages/devs/serial/sh/edk7708/current/include/sh_sh3_edk7708_sci.inl new file mode 100644 index 0000000..12a1b67 --- /dev/null +++ b/ecos/packages/devs/serial/sh/edk7708/current/include/sh_sh3_edk7708_sci.inl @@ -0,0 +1,104 @@ +#ifndef CYGONCE_DEVS_SH_EDK7708_SCI_H +#define CYGONCE_DEVS_SH_EDK7708_SCI_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_edk7708_sci.inl +// +// Serial I/O specification for Hitachi EDK7708 platform. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-06-16 +// Purpose: Defines SCI serial resources for SH3/7708. +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + + +#include <pkgconf/io_serial_sh_edk7708.h> + +static sh_sci_info sh_serial_info = +{ + data : CYGARC_REG_SCI_SCSPTR, + er_int_num : CYGNUM_HAL_INTERRUPT_SCI_ERI, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCI_RXI, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCI_TXI, + ctrl_base : CYGARC_REG_SCI_SCSMR +}; + +#if CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE > 0 +static unsigned char sh_serial_out_buf[CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE]; +static unsigned char sh_serial_in_buf[CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sh_serial_out_buf[0], + sizeof(sh_serial_out_buf), + &sh_serial_in_buf[0], + sizeof(sh_serial_in_buf) + ); +#else +static SERIAL_CHANNEL(sh_serial_channel, + sh_serial_funs, + sh_serial_info, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_EDK7708_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io, + CYGDAT_IO_SERIAL_SH_EDK7708_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_serial_init, + sh_serial_lookup, // Serial driver may need initializing + &sh_serial_channel + ); + +#endif // CYGONCE_DEVS_SH_EDK7708_SCI_H diff --git a/ecos/packages/devs/serial/sh/sci/current/ChangeLog b/ecos/packages/devs/serial/sh/sci/current/ChangeLog new file mode 100644 index 0000000..34de3a0 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sci/current/ChangeLog @@ -0,0 +1,156 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_sci.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Register renaming. + +2002-04-23 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Compute register offsets from register + definitions. Don't define SCI base. + +2001-02-26 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c (sh_serial_er_DSR): Enable interrupts on + exit. + +2000-09-26 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_sci.cdl: Minor hack to allow both SCI and SCIF + packages to be used at the same time. + * src/sh_sci_serial.c: Same. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_sci_serial.c: Moved to generic SH SCI package. + * ChangeLog: Removed all non-SCI related references. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh_sci_serial.c (sh_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sh_edk7708.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-11 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Move compile statement into a + sub-component. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + serial_devio => cyg_io_serial_devio + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/sci/current/cdl/ser_sh_sci.cdl b/ecos/packages/devs/serial/sh/sci/current/cdl/ser_sh_sci.cdl new file mode 100644 index 0000000..de85cc4 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sci/current/cdl/ser_sh_sci.cdl @@ -0,0 +1,112 @@ +# ==================================================================== +# +# ser_sh_sci.cdl +# +# eCos serial SH/SCI configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SCI { + display "SH SCI serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH + + active_if CYGINT_IO_SERIAL_SH_SCI_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + SCI module in Hitachi SH CPUs." + + compile -library=libextras.a sh_sci_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_sh_sci.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_SH_SCI_CFG"; + } + + cdl_component CYGPKG_IO_SERIAL_SH_SCI_OPTIONS { + display "SCI serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_IO_SERIAL_SH_SCI_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_SH_SCI_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_sh_sci.cdl diff --git a/ecos/packages/devs/serial/sh/sci/current/src/sh_sci_serial.c b/ecos/packages/devs/serial/sh/sci/current/src/sh_sci_serial.c new file mode 100644 index 0000000..79d7c73 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sci/current/src/sh_sci_serial.c @@ -0,0 +1,545 @@ +//========================================================================== +// +// io/serial/sh/sh_sci_serial.c +// +// SH Serial SCI I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 1999-05-24 +// Purpose: SH Serial I/O module (interrupt driven version) +// Description: +// +// Note: Since interrupt sources from the same SCI channel share the same +// interrupt level, there is no risk of races when altering the +// channel's control register from ISRs and DSRs. However, when +// altering the control register from user-level code, interrupts +// must be disabled while the register is being accessed. +// +// FIXME: Receiving in polled mode prevents duplex transfers from working for +// some reason. +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +// FIXME: This is necessary since the SCIF driver may be overriding +// CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two +// different drivers. +#include <pkgconf/io_serial_sh_sci.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> + +#include <cyg/hal/sh_regs.h> + +// Only compile driver if an inline file with driver details was selected. +#ifdef CYGDAT_IO_SERIAL_SH_SCI_INL + +// Find the SCI controller register layout from the SCI0 definitions +#if defined(CYGARC_REG_SCI_SCSMR0) +# define SCI_SCSMR (CYGARC_REG_SCI_SCSMR0-CYGARC_REG_SCI_SCSMR0) // serial mode register +# define SCI_SCBRR (CYGARC_REG_SCI_SCBRR0-CYGARC_REG_SCI_SCSMR0) // bit rate register +# define SCI_SCSCR (CYGARC_REG_SCI_SCSCR0-CYGARC_REG_SCI_SCSMR0) // serial control register +# define SCI_SCTDR (CYGARC_REG_SCI_SCTDR0-CYGARC_REG_SCI_SCSMR0) // transmit data register +# define SCI_SCSSR (CYGARC_REG_SCI_SCSSR0-CYGARC_REG_SCI_SCSMR0) // serial status register +# define SCI_SCRDR (CYGARC_REG_SCI_SCRDR0-CYGARC_REG_SCI_SCSMR0) // receive data register +# define SCI_SCSPTR (CYGARC_REG_SCI_SCSPTR0-CYGARC_REG_SCI_SCSMR0)// serial port register +#elif defined(CYGARC_REG_SCI_SCSMR) +# define SCI_SCSMR (CYGARC_REG_SCI_SCSMR-CYGARC_REG_SCI_SCSMR) // serial mode register +# define SCI_SCBRR (CYGARC_REG_SCI_SCBRR-CYGARC_REG_SCI_SCSMR) // bit rate register +# define SCI_SCSCR (CYGARC_REG_SCI_SCSCR-CYGARC_REG_SCI_SCSMR) // serial control register +# define SCI_SCTDR (CYGARC_REG_SCI_SCTDR-CYGARC_REG_SCI_SCSMR) // transmit data register +# define SCI_SCSSR (CYGARC_REG_SCI_SCSSR-CYGARC_REG_SCI_SCSMR) // serial status register +# define SCI_SCRDR (CYGARC_REG_SCI_SCRDR-CYGARC_REG_SCI_SCSMR) // receive data register +# define SCI_SCSPTR (CYGARC_REG_SCI_SCSPTR-CYGARC_REG_SCI_SCSMR) // serial port register +#else +# error "Missing register offsets" +#endif + +static short select_word_length[] = { + -1, + -1, + CYGARC_REG_SCI_SCSMR_CHR, // 7 bits + 0 // 8 bits +}; + +static short select_stop_bits[] = { + -1, + 0, // 1 stop bit + -1, + CYGARC_REG_SCI_SCSMR_STOP // 2 stop bits +}; + +static short select_parity[] = { + 0, // No parity + CYGARC_REG_SCI_SCSMR_PE, // Even parity + CYGARC_REG_SCI_SCSMR_PE|CYGARC_REG_SCI_SCSMR_OE, // Odd parity + -1, + -1 +}; + +static unsigned short select_baud[] = { + 0, // Unused + CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50), + CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75), + CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110), + CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134), + CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150), + CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200), + CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300), + CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600), + CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200), + CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800), + CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400), + CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600), + CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800), + CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200), + CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600), + CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400), + CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200), + CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400), + CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600), + CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200), + CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400) +}; + + +typedef struct sh_sci_info { + CYG_ADDRWORD data; // Pointer to data register + + CYG_WORD er_int_num, // Error interrupt number + rx_int_num, // Receive interrupt number + tx_int_num; // Transmit interrupt number + + CYG_ADDRWORD ctrl_base; // Base address of SCI controller + + cyg_interrupt serial_er_interrupt, + serial_rx_interrupt, + serial_tx_interrupt; + cyg_handle_t serial_er_interrupt_handle, + serial_rx_interrupt_handle, + serial_tx_interrupt_handle; + + bool tx_enabled; +} sh_sci_info; + +static bool sh_serial_init(struct cyg_devtab_entry *tab); +static bool sh_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo sh_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char sh_serial_getc(serial_channel *chan); +static Cyg_ErrNo sh_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void sh_serial_start_xmit(serial_channel *chan); +static void sh_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(sh_serial_funs, + sh_serial_putc, + sh_serial_getc, + sh_serial_set_config, + sh_serial_start_xmit, + sh_serial_stop_xmit + ); + +#include CYGDAT_IO_SERIAL_SH_SCI_INL + +// Internal function to actually configure the hardware to desired baud rate, +// etc. +static bool +sh_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, + bool init) +{ + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr, _smr; + + // Check configuration request + if ((-1 == select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)]) + || -1 == select_stop_bits[new_config->stop] + || -1 == select_parity[new_config->parity] + || baud_divisor == 0) + return false; + + // Disable SCI interrupts while changing hardware + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, 0); + + // Set databits, stopbits and parity. + _smr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr); + + // Set baud rate. + _smr &= ~CYGARC_REG_SCI_SCSMR_CKSx_MASK; + _smr |= baud_divisor >> 8; + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr); + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff); + + // Clear the status register. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, 0); + + if (init) { + // Always enable transmitter and receiver. + _scr = CYGARC_REG_SCI_SCSCR_TE | CYGARC_REG_SCI_SCSCR_RE; + + if (chan->out_cbuf.len != 0) + _scr |= CYGARC_REG_SCI_SCSCR_TIE; // enable tx interrupts + + if (chan->in_cbuf.len != 0) + _scr |= CYGARC_REG_SCI_SCSCR_RIE; // enable rx interrupts + } + + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +sh_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("SH SERIAL init - dev: %x.%d\n", + sh_chan->data, sh_chan->rx_int_num); +#endif + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(sh_chan->tx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_serial_tx_ISR, + sh_serial_tx_DSR, + &sh_chan->serial_tx_interrupt_handle, + &sh_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_unmask(sh_chan->tx_int_num); + sh_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + // Receive interrupt + cyg_drv_interrupt_create(sh_chan->rx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_serial_rx_ISR, + sh_serial_rx_DSR, + &sh_chan->serial_rx_interrupt_handle, + &sh_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle); + // Receive error interrupt + cyg_drv_interrupt_create(sh_chan->er_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_serial_er_ISR, + sh_serial_er_DSR, + &sh_chan->serial_er_interrupt_handle, + &sh_chan->serial_er_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle); + // This unmasks both interrupt sources. + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); + } + sh_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +sh_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +sh_serial_putc(serial_channel *chan, unsigned char c) +{ + cyg_uint8 _ssr; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + if (_ssr & CYGARC_REG_SCI_SCSSR_TDRE) { +// Transmit buffer is empty + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCTDR, c); + // Clear empty flag. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_TDRE); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +sh_serial_getc(serial_channel *chan) +{ + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + unsigned char c; + cyg_uint8 _ssr; + + do { + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + } while ((_ssr & CYGARC_REG_SCI_SCSSR_RDRF) == 0); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, c); + + // Clear buffer full flag. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF); + + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +sh_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != sh_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +sh_serial_start_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + sh_chan->tx_enabled = true; + + // Mask the interrupts (all sources of the unit) while changing + // the CR since a rx interrupt in the middle of this would result + // in a bad CR state. + cyg_drv_interrupt_mask(sh_chan->rx_int_num); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_TIE; // Enable xmit interrupt + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); +} + +// Disable the transmitter on the device +static void +sh_serial_stop_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + sh_chan->tx_enabled = false; + + // Mask the interrupts (all sources of the unit) while changing + // the CR since a rx interrupt in the middle of this would result + // in a bad CR state. + cyg_drv_interrupt_mask(sh_chan->rx_int_num); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_TIE; // Disable xmit interrupt + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_TIE; // mask out tx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + + (chan->callbacks->xmt_char)(chan); + + if (sh_chan->tx_enabled) { + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_TIE; // unmask tx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + } +} + +// Serial I/O - low level RX interrupt handler (ISR) +static cyg_uint32 +sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_RIE; // mask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _ssr, _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + if (_ssr & CYGARC_REG_SCI_SCSSR_RDRF) { + cyg_uint8 _c; + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, _c); + // Clear buffer full flag. + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, + CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF); + + (chan->callbacks->rcv_char)(chan, _c); + } + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); +} + +static volatile int sh_serial_error_orer = 0; +static volatile int sh_serial_error_fer = 0; +static volatile int sh_serial_error_per = 0; + +// Serial I/O - low level error interrupt handler (ISR) +static cyg_uint32 +sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCI_SCSCR_RIE; // mask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level error interrupt handler (DSR) +static void +sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv; + cyg_uint8 _ssr, _ssr2, _scr; + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr); + _ssr2 = CYGARC_REG_SCI_SCSSR_CLEARMASK; + + if (_ssr & CYGARC_REG_SCI_SCSSR_ORER) { + _ssr2 &= ~CYGARC_REG_SCI_SCSSR_ORER; + sh_serial_error_orer++; + } + if (_ssr & CYGARC_REG_SCI_SCSSR_FER) { + _ssr2 &= ~CYGARC_REG_SCI_SCSSR_FER; + sh_serial_error_fer++; + } + if (_ssr & CYGARC_REG_SCI_SCSSR_PER) { + _ssr2 &= ~CYGARC_REG_SCI_SCSSR_PER; + sh_serial_error_per++; + } + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr2); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); + _scr |= CYGARC_REG_SCI_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr); +} + +#endif // ifdef CYGDAT_IO_SERIAL_SH_SCI_INL diff --git a/ecos/packages/devs/serial/sh/scif/current/ChangeLog b/ecos/packages/devs/serial/sh/scif/current/ChangeLog new file mode 100644 index 0000000..1184485 --- /dev/null +++ b/ecos/packages/devs/serial/sh/scif/current/ChangeLog @@ -0,0 +1,188 @@ +2005-08-04 Andrew Lunn <andrew.lunn@ascom.ch> +2005-05-02 Hajime Ishitani <pigmon@mail.snd.co.jp> + + * src/sh_scif_serial.c: support SH4 register access + +2003-03-18 Gary Thomas <gary@mlbassoc.com> + + * src/sh_scif_serial.c (sh_scif_set_config): + Flag for CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE is 32 bits. + +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_scif.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Added SH2 support. Added break interrupt + support. Added IrDA support. Added async RX/TX support. Added + support for platforms to add config keys and handle flow + control. Register renaming. + + * cdl/ser_sh_scif.cdl: Added async RX/TX and IRDA support. Also + added interface for support of break interrupts. + +2002-01-30 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_tx_DSR): Stop single-character + transmit if transmitter gets disabled. This does not change the + (output) semantics of the code, but does prevent it from looping + over the full size of the FIFO calling the (inactive) xmt_char + callback. + +2001-02-27 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_er_DSR): Clear break flag. + +2001-02-26 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_er_DSR): Enable interrupts on + exit. Clear ER flag. + +2000-10-23 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Include cyg_ass.h + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c (sh3_scif_set_config): Changes to the flow + control handling. Renamed DMA variables. + +2000-10-12 Jonathan Larmour <jlarmour@redhat.com> + + * src/sh_scif_serial.c: return -EINVAL when unsupported flow control + mode requested. + +2000-10-06 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Change to new block call syntax. + Clean up start_xmit code. Do block transfers in serial DSRs. + +2000-10-03 Jesper Skov <jskov@redhat.co.uk> + + * src/sh_scif_serial.c: Fixed receive FIFO problem. Added Line + Status handling. Don't enable TX interrupts in initialization. + * src/sh_scif_serial.c: Added DMA support. Added RTS/CTS control. + * cdl/ser_sh_scif.cdl: Added DMA interface. + +2000-09-26 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_scif.cdl: Minor hack to allow both SCI and SCIF + packages to be used at the same time. + * src/sh_scif_serial.c: Same. + +2000-09-25 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Use the SCI macros for baud rate + calculation. + +2000-09-05 Jesper Skov <jskov@redhat.com> + + * src/sh_scif_serial.c: Moved to separate SCIF package. + * ChangeLog: Cleaned out all non-SCIF related entries. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sh3_scif_serial.c (sh3_scif_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_sh_scif.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-11 Jesper Skov <jskov@redhat.com> + + * src/sh3_scif_serial.c: Can't get input FIFO to work properly. + Disabled for now. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-10 Jesper Skov <jskov@redhat.com> + + * src/sh/sh3_scif_serial.c: + Working, but FIFO isn't enabled due to an interrupt problem. + +2000-04-04 Jesper Skov <jskov@redhat.com> + + * src/sh/sh3_scif_serial.c: FIFO related changes. + +2000-04-03 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_scif.cdl: + * src/sh/sh_scif_serial.c: + Added SCIF driver, based on SCI driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/scif/current/cdl/ser_sh_scif.cdl b/ecos/packages/devs/serial/sh/scif/current/cdl/ser_sh_scif.cdl new file mode 100644 index 0000000..49793f2 --- /dev/null +++ b/ecos/packages/devs/serial/sh/scif/current/cdl/ser_sh_scif.cdl @@ -0,0 +1,176 @@ +# ==================================================================== +# +# ser_sh_scif.cdl +# +# eCos serial SH/SCIF configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 2000-04-04 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SCIF { + display "SH SCIF serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH + + active_if CYGINT_IO_SERIAL_SH_SCIF_REQUIRED + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + SCIF module in Hitachi SH CPUs." + + compile -library=libextras.a sh_scif_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#ifndef CYGDAT_IO_SERIAL_DEVICE_HEADER" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_sh_scif.h>" + puts $::cdl_system_header "#endif" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + + puts $::cdl_header "#include <pkgconf/system.h>"; + puts $::cdl_header "#include CYGDAT_IO_SERIAL_SH_SCIF_CFG"; + } + + # The driver tries to be effective with FIFO transfers + implements CYGINT_IO_SERIAL_BLOCK_TRANSFER + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_DMA { + display "SCIF serial driver DMA support" + flavor booldata + description " + The serial driver can use DMA to move data from the + transmit buffer to the serial controller if the CPU + supports it." + } + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX { + display "SCIF async RX/TX support" + flavor booldata + description " + By enabling this option, the SCIF driver will + be able to support controllers with transceivers + that are asynchronous (RS4xx). This will cause + RX to be disabled before TX is enabled, and vice + versa." + } + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_IRDA { + display "SCIF IrDA support" + flavor booldata + description " + By enabling this option, the SCIF driver will + be able to support controllers in IrDA mode." + } + + cdl_option CYGHWR_IO_SERIAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION { + display "SCIF IrDA TX/RX switch compensation" + default_value 1 + active_if CYGINT_IO_SERIAL_SH_SCIF_IRDA + description " + When switching from TX mode to RX mode, the controller causes + a spurious 0xff character to be received at speeds up to + 57600 baud. At higher baud rates, more spurious characters + may be received. Enabling this option tries to remove the + spurious characters, but since there are no errors reported + from the controller, it is impossible to do so with any kind + of precision. + Having this option enabled allows some eCos serial tests to + run. There is a matching option in the SH2 HAL controlling a + similar kludge for the polled driver, making RedBoot usable. + It is an incomplete kludge however, and for any real use of + the IrDA mode for data transmission, the option should be + disabled, and a protocol capable of handling the spurious + receive characters must be used on top of the driver. + Note that the problem is exaggerated when the baud rate is + changed." + } + + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT { + display "Controller uses BR interrupts" + flavor booldata + description " + Some controllers route BREAK interrupts to the + error interrupt vector. Others have a separate + vector. When this interface is implemented, the + driver will handle the separate BR vector." + } + + cdl_component CYGPKG_IO_SERIAL_SH_SCIF_OPTIONS { + display "SCIF serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_SH_SCIF_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_SH_SCIF_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} +# EOF ser_sh_scif.cdl diff --git a/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c b/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c new file mode 100644 index 0000000..1eb28a4 --- /dev/null +++ b/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c @@ -0,0 +1,1095 @@ +//========================================================================== +// +// io/serial/sh/scif/sh_scif_serial.c +// +// SH Serial IRDA/SCIF I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 2000-04-04 +// Purpose: SH Serial IRDA/SCIF I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +// FIXME: This is necessary since the SCI driver may be overriding +// CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two +// different drivers. +#include <pkgconf/io_serial_sh_scif.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/io/serial.h> + +#include <cyg/hal/sh_regs.h> +#include <cyg/hal/hal_cache.h> + +// Only compile driver if an inline file with driver details was selected. +#ifdef CYGDAT_IO_SERIAL_SH_SCIF_INL + +#if defined(CYGPKG_HAL_SH_SH2) +// The SCIF controller register layout on the SH2 +// The controller base is defined in the board specification file. +# define SCIF_SCSMR 0x00 // serial mode register +# define SCIF_SCBRR 0x02 // bit rate register +# define SCIF_SCSCR 0x04 // serial control register +# define SCIF_SCFTDR 0x06 // transmit data register +# define SCIF_SC1SSR 0x08 // serial status register 1 +# define SCIF_SCSSR SCIF_SC1SSR +# define SCIF_SC2SSR 0x0a // serial status register 2 +# define SCIF_SCFRDR 0x0c // receive data register +# define SCIF_SCFCR 0x0e // FIFO control +# define SCIF_SCFDR 0x10 // FIFO data count register +# define SCIF_SCFER 0x12 // FIFO error register +# define SCIF_SCIMR 0x14 // IrDA mode register +# define HAL_READ(x,y) HAL_READ_UINT8(x,y) +# define HAL_WRITE(x,y) HAL_WRITE_UINT8(x,y) + +#elif defined(CYGPKG_HAL_SH_SH3) +// The SCIF controller register layout on the SH3 +// The controller base is defined in the board specification file. +# define SCIF_SCSMR 0x00 // serial mode register +# define SCIF_SCBRR 0x02 // bit rate register +# define SCIF_SCSCR 0x04 // serial control register +# define SCIF_SCFTDR 0x06 // transmit data register +# define SCIF_SCSSR 0x08 // serial status register +# define SCIF_SCFRDR 0x0a // receive data register +# define SCIF_SCFCR 0x0c // FIFO control +# define SCIF_SCFDR 0x0e // FIFO data count register +# define HAL_READ(x,y) HAL_READ_UINT8(x,y) +# define HAL_WRITE(x,y) HAL_WRITE_UINT8(x,y) +#elif defined(CYGPKG_HAL_SH_SH4) +// The SCIF controller register layout on the SH4 +// The controller base is defined in the board specification file. +# define SCIF_SCSMR 0x00 // serial mode register +# define SCIF_SCBRR 0x04 // bit rate register +# define SCIF_SCSCR 0x08 // serial control register +# define SCIF_SCFTDR 0x0C // transmit data register +# define SCIF_SCSSR 0x10 // serial status register +# define SCIF_SCFRDR 0x14 // receive data register +# define SCIF_SCFCR 0x18 // FIFO control +# define SCIF_SCFDR 0x1C // FIFO data count register +# define HAL_READ(x,y) HAL_READ_UINT16(x,y) +# define HAL_WRITE(x,y) HAL_WRITE_UINT16(x,y) +#else +# error "Unsupported variant" +#endif + +static short select_word_length[] = { + -1, + -1, + CYGARC_REG_SCIF_SCSMR_CHR, // 7 bits + 0 // 8 bits +}; + +static short select_stop_bits[] = { + -1, + 0, // 1 stop bit + -1, + CYGARC_REG_SCIF_SCSMR_STOP // 2 stop bits +}; + +static short select_parity[] = { + 0, // No parity + CYGARC_REG_SCIF_SCSMR_PE, // Even parity + CYGARC_REG_SCIF_SCSMR_PE|CYGARC_REG_SCIF_SCSMR_OE, // Odd parity + -1, + -1 +}; + +static unsigned short select_baud[] = { + 0, // Unused + CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50), + CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75), + CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110), + CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134), + CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150), + CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200), + CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300), + CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600), + CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200), + CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800), + CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400), + CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600), + CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800), + CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200), + CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600), + CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400), + CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200), + CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400), + CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600), + CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200), + CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400) +}; + +typedef struct sh_scif_info { + CYG_WORD er_int_num, // Error interrupt number +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + br_int_num, // Break interrupt number +#endif + rx_int_num, // Receive interrupt number + tx_int_num; // Transmit interrupt number + + CYG_ADDRWORD ctrl_base; // Base address of SCI controller + + cyg_interrupt serial_er_interrupt, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + serial_br_interrupt, +#endif + serial_rx_interrupt, + serial_tx_interrupt; + cyg_handle_t serial_er_interrupt_handle, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + serial_br_interrupt_handle, +#endif + serial_rx_interrupt_handle, + serial_tx_interrupt_handle; + + volatile bool tx_enabled; // expect tx _serial_ interrupts +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + bool irda_mode; +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + bool async_rxtx_mode; +#endif + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + cyg_bool dma_enable; // Set if DMA mode + cyg_uint32 dma_xmt_cr_flags; // CR flags for DMA mode + CYG_WORD dma_xmt_int_num; // DMA xmt completion interrupt + CYG_ADDRWORD dma_xmt_base; // Base address of DMA channel + int dma_xmt_len; // length transferred by DMA + cyg_interrupt dma_xmt_interrupt; + cyg_handle_t dma_xmt_interrupt_handle; + volatile cyg_bool dma_xmt_running; // expect tx _dma_ interrupts +#endif +} sh_scif_info; + +static bool sh_scif_init(struct cyg_devtab_entry *tab); +static bool sh_scif_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo sh_scif_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char sh_scif_getc(serial_channel *chan); +static Cyg_ErrNo sh_scif_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void sh_scif_start_xmit(serial_channel *chan); +static void sh_scif_stop_xmit(serial_channel *chan); + +static cyg_uint32 sh_scif_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_scif_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_scif_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_scif_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +static cyg_uint32 sh_scif_er_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_scif_er_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA +static cyg_uint32 sh_dma_xmt_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void sh_dma_xmt_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); +#endif + +static SERIAL_FUNS(sh_scif_funs, + sh_scif_putc, + sh_scif_getc, + sh_scif_set_config, + sh_scif_start_xmit, + sh_scif_stop_xmit + ); + +// Get the board specification +#include CYGDAT_IO_SERIAL_SH_SCIF_INL + +// Allow platform to define handling of additional config keys +#ifndef CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF +# define CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF +#endif + +// Internal function to actually configure the hardware to desired baud rate, +// etc. +static bool +sh_scif_config_port(serial_channel *chan, cyg_serial_info_t *new_config, + bool init) +{ + cyg_uint16 baud_divisor = select_baud[new_config->baud]; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr, _smr; + cyg_uint16 _sr; + CYG_ADDRWORD base = sh_chan->ctrl_base; + + // Check configuration request + if ((-1 == select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)]) + || -1 == select_stop_bits[new_config->stop] + || -1 == select_parity[new_config->parity] + || baud_divisor == 0) + return false; + + // Disable SCI interrupts while changing hardware + HAL_READ(base+SCIF_SCSCR, _scr); + HAL_WRITE(base+SCIF_SCSCR, 0); + + // Reset FIFO. + HAL_WRITE(base+SCIF_SCFCR, + CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST); + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + sh_chan->async_rxtx_mode = false; +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) { + // In IrDA mode, the configuration is hardwired and the mode + // bits should not be set +#ifdef CYGARC_REG_SCIF_SCSMR_IRMOD + _smr = CYGARC_REG_SCIF_SCSMR_IRMOD; +#elif defined(SCIF_SCIMR) + _smr = 0; + HAL_WRITE_UINT8(base+SCIF_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD); +#endif + } else +#endif + { + // Set databits, stopbits and parity. + _smr = select_word_length[(new_config->word_length - + CYGNUM_SERIAL_WORD_LENGTH_5)] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA +#ifdef SCIF_SCIMR + // Disable IrDA mode + HAL_WRITE(base+SCIF_SCIMR, 0); +#endif +#endif + } + HAL_WRITE(base+SCIF_SCSMR, _smr); + + // Set baud rate. + _smr &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK; + _smr |= baud_divisor >> 8; + HAL_WRITE(base+SCIF_SCSMR, _smr); + HAL_WRITE_UINT8(base+SCIF_SCBRR, baud_divisor & 0xff); + + // FIXME: Should delay 1/<baud> second here. + + // Clear the status register (read first). + HAL_READ_UINT16(base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(base+SCIF_SCSSR, 0); + + // Bring FIFO out of reset and set FIFO trigger marks + // + // Note that the RX FIFO size must be smaller when flow control is + // enabled. This due to observations made by running the flow2 + // serial test. The automatic RTS de-assertion happens + // (apparently) when the FIFO fills past the trigger count - + // causing the sender to stop transmission. But there's a lag + // before transmission is stopped, and if the FIFO fills in that + // time, data will be lost. Thus, seeing as HW flow control is + // presumed used for prevention of data loss, set the trigger + // level so the sender has time to stop transmission before the + // FIFO fills up. + // + // The trigger setting of 8 allows test flow2 to complete without + // problems. It tests duplex data transmission at 115200 + // baud. Depending on the lag time between the de-assertion of RTS + // and actual transmission stop, it may be necessary to reduce the + // trigger level further. +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + HAL_WRITE(base+SCIF_SCFCR, + CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8); +#else + HAL_WRITE(base+SCIF_SCFCR, + CYGARC_REG_SCIF_SCFCR_RTRG_14|CYGARC_REG_SCIF_SCFCR_TTRG_8); +#endif + + if (init) { + // Always enable received and (for normal mode) transmitter + _scr = CYGARC_REG_SCIF_SCSCR_TE | CYGARC_REG_SCIF_SCSCR_RE; +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + if (sh_chan->async_rxtx_mode) + _scr = CYGARC_REG_SCIF_SCSCR_RE; +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) + _scr = CYGARC_REG_SCIF_SCSCR_RE; +#endif + + if (chan->in_cbuf.len != 0) + _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // enable rx interrupts + } + + HAL_WRITE(base+SCIF_SCSCR, _scr); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +sh_scif_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("SH SERIAL init - dev: %x.%d\n", + sh_chan->ctrl_base, sh_chan->rx_int_num); +#endif + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(sh_chan->tx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_tx_ISR, + sh_scif_tx_DSR, + &sh_chan->serial_tx_interrupt_handle, + &sh_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_unmask(sh_chan->tx_int_num); + sh_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + // Receive interrupt + cyg_drv_interrupt_create(sh_chan->rx_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_rx_ISR, + sh_scif_rx_DSR, + &sh_chan->serial_rx_interrupt_handle, + &sh_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle); + // Receive error interrupt + cyg_drv_interrupt_create(sh_chan->er_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_er_ISR, + sh_scif_er_DSR, + &sh_chan->serial_er_interrupt_handle, + &sh_chan->serial_er_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle); +#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + // Break error interrupt + cyg_drv_interrupt_create(sh_chan->br_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_scif_er_ISR, + sh_scif_er_DSR, + &sh_chan->serial_br_interrupt_handle, + &sh_chan->serial_br_interrupt); + cyg_drv_interrupt_attach(sh_chan->serial_br_interrupt_handle); +#endif + // This unmasks all interrupt sources. + cyg_drv_interrupt_unmask(sh_chan->rx_int_num); + } + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + // Assign DMA channel and interrupt if requested + if (sh_chan->dma_enable) { + // FIXME: Need a cleaner way to assign DMA channels + static int dma_channel = 0; +#if defined(CYGPKG_HAL_SH_SH2) + sh_chan->dma_xmt_int_num = dma_channel+CYGNUM_HAL_INTERRUPT_DMAC0_TE; +#elif defined(CYGPKG_HAL_SH_SH3) + sh_chan->dma_xmt_int_num = dma_channel+CYGNUM_HAL_INTERRUPT_DMAC_DEI0; +#else +# error "No interrupt defined for variant" +#endif + sh_chan->dma_xmt_base = (dma_channel*0x10)+CYGARC_REG_SAR0; + dma_channel++; + + // Enable the DMA engines. + HAL_WRITE_UINT16(CYGARC_REG_DMAOR, CYGARC_REG_DMAOR_DME); + + cyg_drv_interrupt_create(sh_chan->dma_xmt_int_num, + 3, + (cyg_addrword_t)chan, // Data item passed to interrupt handler + sh_dma_xmt_ISR, + sh_dma_xmt_DSR, + &sh_chan->dma_xmt_interrupt_handle, + &sh_chan->dma_xmt_interrupt); + cyg_drv_interrupt_attach(sh_chan->dma_xmt_interrupt_handle); + cyg_drv_interrupt_unmask(sh_chan->dma_xmt_int_num); + } + sh_chan->dma_xmt_running = false; +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + + sh_scif_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +sh_scif_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +sh_scif_putc(serial_channel *chan, unsigned char c) +{ + cyg_uint16 _fdr, _sr; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCFDR, _fdr); + if (((_fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) < 15) { +// Transmit FIFO has room for another char + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCFTDR, c); + // Clear FIFO-empty/transmit end flags (read back sr first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_TDFE); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +// Note: Input is running wo FIFO enabled, so the counter is not checked here. +static unsigned char +sh_scif_getc(serial_channel *chan) +{ + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + unsigned char c; + cyg_uint16 _sr; + + do { + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + } while ((_sr & CYGARC_REG_SCIF_SCSSR_RDF) == 0); + + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, c); + + // Clear buffer full flag (read back first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_RDF); + + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +sh_scif_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != sh_scif_config_port(chan, config, false) ) + return -EINVAL; + } + break; +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + sh_scif_info *ser_chan = (sh_scif_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->ctrl_base; + cyg_uint32 *f = (cyg_uint32 *)xbuf; + if ( *len < *f ) + return -EINVAL; + + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) { + // Control RX RTC/CTS flow control by disabling/enabling + // RX interrupt. When disabled, FIFO will fill up and + // clear RTS. + cyg_uint8 _scscr; + HAL_READ(base+SCIF_SCSCR, _scscr); + if (*f) // we should throttle + _scscr &= ~CYGARC_REG_SCIF_SCSCR_RIE; + else // we should no longer throttle + _scscr |= CYGARC_REG_SCIF_SCSCR_RIE; + HAL_WRITE(base+SCIF_SCSCR, _scscr); + } +#ifdef CYGHWR_SH_SCIF_FLOW_DSRDTR + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX ) { + // Control RX DSR/DTR flow control via platform specific macro + CYGHWR_SH_SCIF_FLOW_DSRDTR_RX(chan, *f); + } +#endif + } + break; + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + { + // Handle CTS/RTS flag + if ( chan->config.flags & + (CYGNUM_SERIAL_FLOW_RTSCTS_RX | CYGNUM_SERIAL_FLOW_RTSCTS_TX )){ + cyg_uint8 _scfcr; + sh_scif_info *ser_chan = (sh_scif_info *)chan->dev_priv; + cyg_addrword_t base = ser_chan->ctrl_base; + cyg_uint8 *f = (cyg_uint8 *)xbuf; + + HAL_READ(base+SCIF_SCFCR, _scfcr); + if (*f) // enable RTS/CTS flow control + _scfcr |= CYGARC_REG_SCIF_SCFCR_MCE; + else // disable RTS/CTS flow control + _scfcr &= ~CYGARC_REG_SCIF_SCFCR_MCE; + HAL_WRITE(base+SCIF_SCFCR, _scfcr); + } +#ifndef CYGHWR_SH_SCIF_FLOW_DSRDTR + // Clear DSR/DTR flag as it's not supported. + if (chan->config.flags & + (CYGNUM_SERIAL_FLOW_DSRDTR_RX|CYGNUM_SERIAL_FLOW_DSRDTR_TX)) { + chan->config.flags &= ~(CYGNUM_SERIAL_FLOW_DSRDTR_RX| + CYGNUM_SERIAL_FLOW_DSRDTR_TX); + return -EINVAL; + } +#else + return CYGHWR_SH_SCIF_FLOW_DSRDTR_CONFIG(chan); +#endif + } + break; +#endif + + CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF + + default: + return -EINVAL; + } + return ENOERR; +} + + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + +// Must be called with serial interrupts disabled +static xmt_req_reply_t +sh_scif_start_dma_xmt(serial_channel *chan) +{ + int chars_avail; + unsigned char* chars; + xmt_req_reply_t res; + + // We can transfer the full buffer - ask how much to transfer + res = (chan->callbacks->data_xmt_req)(chan, chan->out_cbuf.len, + &chars_avail, &chars); + if (CYG_XMT_OK == res) { + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint32 dma_base = sh_chan->dma_xmt_base; + cyg_uint32 scr; + + // Save the length so it can be used in the DMA DSR + sh_chan->dma_xmt_len = chars_avail; + + // Flush cache for the area + HAL_DCACHE_FLUSH((cyg_haladdress)chars, chars_avail); + + // Program DMA + HAL_WRITE_UINT32(dma_base+CYGARC_REG_CHCR, 0); // disable and clear + HAL_WRITE_UINT32(dma_base+CYGARC_REG_SAR, (cyg_uint32)chars); + HAL_WRITE_UINT32(dma_base+CYGARC_REG_DAR, + (sh_chan->ctrl_base+SCIF_SCFTDR) & 0x0fffffff); + HAL_WRITE_UINT32(dma_base+CYGARC_REG_DMATCR, chars_avail); + // Source increments, dest static, byte transfer, enable + // interrupt on completion. + HAL_WRITE_UINT32(dma_base+CYGARC_REG_CHCR, + sh_chan->dma_xmt_cr_flags | CYGARC_REG_CHCR_SM0 \ + | CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE); + + // Enable serial interrupts + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, scr); + scr |= CYGARC_REG_SCIF_SCSCR_TIE; + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, scr); + } + + return res; +} + +// must be called with serial interrupts masked +static void +sh_scif_stop_dma_xmt(serial_channel *chan) +{ + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint32 dma_base = sh_chan->dma_xmt_base; + cyg_uint32 cr; + + // Disable DMA engine and interrupt enable flag. Should be safe + // to do since it's triggered by the serial interrupt which has + // already been disabled. + HAL_READ_UINT32(dma_base+CYGARC_REG_CHCR, cr); + cr &= ~(CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE); + HAL_WRITE_UINT32(dma_base+CYGARC_REG_CHCR, cr); + + // Did transfer complete? + HAL_READ_UINT32(dma_base+CYGARC_REG_CHCR, cr); + if (0 == (cr & CYGARC_REG_CHCR_TE)) { + // Transfer incomplete. Report actually transferred amount of data + // back to the serial driver. + int chars_left; + HAL_READ_UINT32(dma_base+CYGARC_REG_DMATCR, chars_left); + CYG_ASSERT(chars_left > 0, "DMA incomplete, but no data left"); + CYG_ASSERT(chars_left <= sh_chan->dma_xmt_len, + "More data remaining than was attempted transferred"); + + (chan->callbacks->data_xmt_done)(chan, + sh_chan->dma_xmt_len - chars_left); + } + +#ifdef CYGDBG_USE_ASSERTS + { + cyg_uint32 dmaor; + HAL_READ_UINT32(CYGARC_REG_DMAOR, dmaor); + CYG_ASSERT(0== (dmaor & (CYGARC_REG_DMAOR_AE | CYGARC_REG_DMAOR_NMIF)), + "DMA error"); + } +#endif + + // The DMA engine is free again. + sh_chan->dma_xmt_running = false; +} + +// Serial xmt DMA completion interrupt handler (ISR) +static cyg_uint32 +sh_dma_xmt_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint32 _cr; + + // mask serial interrupt + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _cr); + _cr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit interrupt + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _cr); + + // mask DMA interrupt and disable engine + HAL_READ_UINT32(sh_chan->dma_xmt_base+CYGARC_REG_CHCR, _cr); + _cr &= ~(CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE); + HAL_WRITE_UINT32(sh_chan->dma_xmt_base+CYGARC_REG_CHCR, _cr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial xmt DMA completion interrupt handler (DSR) +static void +sh_dma_xmt_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + + (chan->callbacks->data_xmt_done)(chan, sh_chan->dma_xmt_len); + + // Try to load the engine again. + sh_chan->dma_xmt_running = + (CYG_XMT_OK == sh_scif_start_dma_xmt(chan)) ? true : false; +} +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + + +// Enable the transmitter on the device +static void +sh_scif_start_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + xmt_req_reply_t _block_status = CYG_XMT_DISABLED; + + if (sh_chan->tx_enabled) + return; + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + // Check if the engine is already running. If so, return. Note + // that there will never be a race on this flag - the caller of + // this function is respecting a per-channel lock. + if (sh_chan->dma_xmt_running) + return; + // If the channel uses DMA, try to start a DMA job for this - + // but handle the case where the job doesn't start by falling + // back to the FIFO/interrupt based code. + if (sh_chan->dma_enable) { + _block_status = sh_scif_start_dma_xmt(chan); + CYG_ASSERT(_block_status != CYG_XMT_EMPTY, + "start_xmit called with empty buffers!"); + sh_chan->dma_xmt_running = + (CYG_XMT_OK == _block_status) ? true : false; + } +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + + if (CYG_XMT_DISABLED == _block_status) { + // Mask interrupts while changing the CR since a rx + // interrupt or another thread doing the same in the + // middle of this would result in a bad CR state. + cyg_drv_isr_lock(); + { + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_TIE; // Enable xmit interrupt +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) { + // Enable transmitter - this automatically disables + // the receiver in the hardware. Doing it explicitly + // (like for async RX/TX below) causes more spurious + // characters to be read when re-enabling the + // receiver. + _scr |= CYGARC_REG_SCIF_SCSCR_TE; + } +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + if (sh_chan->async_rxtx_mode) { + // Enable transmitter + _scr |= CYGARC_REG_SCIF_SCSCR_TE; + // Disable receiver + _scr &= ~CYGARC_REG_SCIF_SCSCR_RE; + } +#endif + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + sh_chan->tx_enabled = true; + } + cyg_drv_isr_unlock(); + } +} + +// Disable the transmitter on the device +static void +sh_scif_stop_xmit(serial_channel *chan) +{ + cyg_uint8 _scr; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + + // In IrDA and async mode the transmitter needs to be disabled, so + // wait for transmission to complete within reason: disable it + // after 0.1s + if (0 +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + || sh_chan->irda_mode +#endif +#if defined(CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX) + || sh_chan->async_rxtx_mode +#endif + ) { + cyg_uint16 sr; + int i = 1000; + do { + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, sr); + if (sr & CYGARC_REG_SCIF_SCSSR_TEND) break; + HAL_DELAY_US(100); + } while (i-- > 0); + } + + // Mask interrupts while changing the CR since a rx interrupt or + // another thread doing the same in the middle of this would + // result in a bad CR state. + cyg_drv_isr_lock(); + { + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit interrupt +#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA + if (sh_chan->irda_mode) { +#ifdef CYGHWR_IO_SERIAL_SH_SCIF_IRDA_TXRX_COMPENSATION + // In IrDA mode there will be generated spurious RX + // events when the TX unit is switched on. Eat that + // character. + cyg_uint8 _junk; + cyg_uint16 _sr; + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, _junk); + + // Clear buffer full flag (read back first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR)); +#endif + // Disable transmitter + _scr &= ~CYGARC_REG_SCIF_SCSCR_TE; + } +#endif +#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + if (sh_chan->async_rxtx_mode) { + // Enable receiver again + _scr |= CYGARC_REG_SCIF_SCSCR_RE; + // Disable transmitter + _scr &= ~CYGARC_REG_SCIF_SCSCR_TE; + } +#endif + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + } + cyg_drv_isr_unlock(); + +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA + // If the channel uses DMA, stop the DMA engine. + if (sh_chan->dma_xmt_running) + sh_scif_stop_dma_xmt(chan); + else // dangling else! +#endif // CYGINT_IO_SERIAL_SH_SCIF_DMA + sh_chan->tx_enabled = false; +} + +// Serial I/O - low level tx interrupt handler (ISR) +static cyg_uint32 +sh_scif_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // mask out tx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level tx interrupt handler (DSR) +static void +sh_scif_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + xmt_req_reply_t _block_status = CYG_XMT_DISABLED; + cyg_uint16 _fdr, _sr; + int _space, _chars_avail; + unsigned char* _chars; + CYG_ADDRWORD _base = sh_chan->ctrl_base; + + // Always check if we're supposed to be enabled; the driver runs + // with DSRs disabled, and a DSR may have been posted (but not + // executed) before the interrupt was masked. + if (!sh_chan->tx_enabled) + return; + +#ifdef CYGHWR_SH_SCIF_FLOW_DSRDTR + CYGHWR_SH_SCIF_FLOW_DSRDTR_TX(chan); +#endif + + // How many chars can we stuff into the FIFO? + HAL_READ_UINT16(_base+SCIF_SCFDR, _fdr); + _space = 16 - ((_fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift); + + // Try to do the transfer most efficiently + _block_status = (chan->callbacks->data_xmt_req)(chan, _space, + &_chars_avail, &_chars); + if (CYG_XMT_OK == _block_status) { + // Transfer the data in block(s). + do { + int i = _chars_avail; + while (i--) { + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCFTDR, *_chars++); + _space--; + } + (chan->callbacks->data_xmt_done)(chan, _chars_avail); + } while (_space > 0 && + (CYG_XMT_OK == (chan->callbacks->data_xmt_req)(chan, _space, + &_chars_avail, + &_chars))); + } else if (CYG_XMT_DISABLED == _block_status) { + // Transfer char-by-char, but stop if the transmitter + // gets disabled. + while (_space-- && sh_chan->tx_enabled) + (chan->callbacks->xmt_char)(chan); + } + + // Clear FIFO-empty/transmit end flags (read back sr first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_TDFE); + + if (sh_chan->tx_enabled) { + cyg_uint8 _scr; + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_TIE; // unmask tx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + } +} + +// Serial I/O - low level RX interrupt handler (ISR) +static cyg_uint32 +sh_scif_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level rx interrupt handler (DSR) +static void +sh_scif_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + cyg_uint16 _fdr, _sr; + int _avail, _space_avail; + unsigned char* _space; + rcv_req_reply_t _block_status; + + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCFDR, _fdr); + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + + _avail = _fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK; + if (_avail > 0) { + _block_status = (chan->callbacks->data_rcv_req)(chan, _avail, + &_space_avail, &_space); + if (CYG_RCV_OK == _block_status) { + // Transfer the data in block(s). + do { + int i = _space_avail; + while(i--) { + cyg_uint8 _c; + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, _c); + *_space++ = _c; + _avail--; + } + (chan->callbacks->data_rcv_done)(chan, _space_avail); + } while (_avail > 0 && + (CYG_RCV_OK == (chan->callbacks->data_rcv_req)(chan, _avail, + &_space_avail, + &_space))); + } else { + // Transfer the data char-by-char both for CYG_RCV_FULL + // and CYG_RCV_DISABLED, leaving all policy decisions with + // the IO driver. + while(_avail--) { + cyg_uint8 _c; + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCFRDR, _c); + (chan->callbacks->rcv_char)(chan, _c); + } + } + } else { + CYG_ASSERT(_avail > 0, "No data to be read in RX DSR"); + } + + // Clear buffer full flag (read back first) + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _sr); + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, + CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR)); + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); +} + +// Serial I/O - low level error interrupt handler (ISR) +static cyg_uint32 +sh_scif_er_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint8 _scr; + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level error interrupt handler (DSR) +static void +sh_scif_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv; + cyg_uint16 _ssr, _ssr_mask; +#ifdef SCIF_SC2SSR + cyg_uint8 _ssr2; +#endif + cyg_uint8 _scr; +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + cyg_serial_line_status_t stat; +#endif + + HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _ssr); + _ssr_mask = CYGARC_REG_SCIF_SCSSR_CLEARMASK; + // Clear the ER bit + _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_ER; + + +#ifdef SCIF_SC2SSR + HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SC2SSR, _ssr2); + if (_ssr2 & CYGARC_REG_SCIF_SC2SSR_ORER) { + _ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER; + HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SC2SSR, _ssr2); + stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR; + (chan->callbacks->indicate_status)(chan, &stat ); + } +#endif + if (_ssr & CYGARC_REG_SCIF_SCSSR_FER) { + // _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_FER; // FER is read-only +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR; + (chan->callbacks->indicate_status)(chan, &stat ); +#endif + } + if (_ssr & CYGARC_REG_SCIF_SCSSR_PER) { + // _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_PER; // PER is read-only +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_PARITYERR; + (chan->callbacks->indicate_status)(chan, &stat ); +#endif + } + if (_ssr & CYGARC_REG_SCIF_SCSSR_BRK) { + _ssr_mask &= ~CYGARC_REG_SCIF_SCSSR_BRK; +#ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS + stat.which = CYGNUM_SERIAL_STATUS_BREAK; + (chan->callbacks->indicate_status)(chan, &stat ); +#endif + } + HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _ssr_mask); + + HAL_READ(sh_chan->ctrl_base+SCIF_SCSCR, _scr); + _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts + HAL_WRITE(sh_chan->ctrl_base+SCIF_SCSCR, _scr); +} + +#endif // ifdef CYGDAT_IO_SERIAL_SH_SCIF_INL diff --git a/ecos/packages/devs/serial/sh/se77x9/current/ChangeLog b/ecos/packages/devs/serial/sh/se77x9/current/ChangeLog new file mode 100644 index 0000000..a8fab66 --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/ChangeLog @@ -0,0 +1,41 @@ +2003-02-24 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_sh_se77x9.cdl: Remove irrelevant doc link. + +2002-05-08 Jesper Skov <jskov@redhat.com> + + * include/sh_sh3_se77x9_scif.inl: CYGINT_IO_SERIAL_SH_SCIF_DMA is + now booldata. Rename sh3_scif to sh_scif. Register renaming. + +2001-06-19 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_se77x9.cdl: Disable COM1 driver for now since it + breaks eCos. + +2001-06-18 Jesper Skov <jskov@redhat.com> + + * New package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/se77x9/current/cdl/ser_sh_se77x9.cdl b/ecos/packages/devs/serial/sh/se77x9/current/cdl/ser_sh_se77x9.cdl new file mode 100644 index 0000000..aac93f0 --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/cdl/ser_sh_se77x9.cdl @@ -0,0 +1,193 @@ +# ==================================================================== +# +# ser_sh_se77x9.cdl +# +# eCos serial SH/SE77X9 configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: +# Date: 2001-06-18 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SE77X9 { + display "SH3 SE77X9 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_SH77X9_SE77X9 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Hitachi SH3 SE77X9 board, based on the generic SH SCI driver." + + + # FIXME: This really belongs in the SH_SCIF package + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_REQUIRED { + display "SH SCI driver required" + } + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/sh_sh3_se77x9_16x5x.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_sh_se77x9.h>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_INL <cyg/io/sh_sh3_se77x9_scif.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_CFG <pkgconf/io_serial_sh_se77x9.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_SH_SE77X9_COM1 { + display "SH SE77X9 serial 1 driver (SuperIO)" + flavor bool + calculated 0 + description " + This option includes the serial device driver for the COM1 + port. FIXME: Disabled due to being broken." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_SH_SE77X9_COM1_NAME { + display "Device name for COM1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for COM1." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BAUD { + display "Baud rate for COM1" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the COM1 port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE { + display "Buffer size for COM1" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the COM1 port." + } + } + + # SCIF port + cdl_component CYGPKG_IO_SERIAL_SH_SE77X9_COM2 { + display "SE77X9 serial, SCIF port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for SCIF + port 2." + + implements CYGINT_IO_SERIAL_SH_SCIF_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_SH_SE77X9_COM2_NAME { + display "Device name" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the serial + port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BAUD { + display "Baud rate" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the serial driver." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE { + display "Buffer size" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the serial driver." + } + + cdl_option CYGSEM_IO_SERIAL_SH_SE77X9_COM2_DMA { + display "Enable SCIF serial driver DMA" + active_if CYGINT_HAL_SH_DMA_CHANNELS + implements CYGINT_HAL_SH_DMA_CHANNELS_USED + implements CYGINT_IO_SERIAL_SH_SCIF_DMA + default_value 1 + description " + Enable DMA for this port." + } + } + + cdl_component CYGPKG_IO_SERIAL_SH_SE77X9_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_SE77X9_COM2 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-se77x9\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_SE77X9_COM2_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty2\"" + } + } +} +# EOF ser_sh_se77x9.cdl diff --git a/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_16x5x.inl b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_16x5x.inl new file mode 100644 index 0000000..5ec4e5b --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_16x5x.inl @@ -0,0 +1,123 @@ +#ifndef CYGONCE_DEVS_SH_SE77X9_16X5X_H +#define CYGONCE_DEVS_SH_SE77X9_16X5X_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_se77x9_16x5x.inl +// +// Serial I/O specification for Hitachi SE77X9 platform. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-06-18 +// Purpose: Specifies serial resources for the platform. +// Description: This file can be include from the 16x5x driver sources. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial_sh_se77x9.h> + +//----------------------------------------------------------------------------- +// Baud rate specification, based on raw 1.8462MHz clock (/16) + +static unsigned short select_baud[] = { + 0, // Unused + 2307, // 50 + 1538, // 75 + 1048, // 110 + 857, // 134.5 + 769, // 150 + 576, // 200 + 384, // 300 + 192, // 600 + 96, // 1200 + 64, // 1800 + 48, // 2400 + 32, // 3600 + 24, // 4800 + 16, // 7200 + 12, // 9600 + 8, // 14400 + 6, // 19200 + 3, // 38400 + 2, // 57600 + 1, // 115200 + 0, // 230400 +}; + +#ifdef CYGPKG_IO_SERIAL_SH_SE77X9_COM1 +static pc_serial_info se77x9_serial_info1 = {0xb04007f0, CYGNUM_HAL_INTERRUPT_COM1}; +#if CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE > 0 +static unsigned char se77x9_serial_out_buf1[CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE]; +static unsigned char se77x9_serial_in_buf1[CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(se77x9_serial_channel1, + pc_serial_funs, + se77x9_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &se77x9_serial_out_buf1[0], sizeof(se77x9_serial_out_buf1), + &se77x9_serial_in_buf1[0], sizeof(se77x9_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(se77x9_serial_channel1, + pc_serial_funs, + se77x9_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(se77x9_serial_io1, + CYGDAT_IO_SERIAL_SH_SE77X9_COM1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &se77x9_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_SH_SE77X9_COM1 + +#endif // CYGONCE_DEVS_SH_SE77X9_SCIF_H diff --git a/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_scif.inl b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_scif.inl new file mode 100644 index 0000000..a9905f0 --- /dev/null +++ b/ecos/packages/devs/serial/sh/se77x9/current/include/sh_sh3_se77x9_scif.inl @@ -0,0 +1,113 @@ +#ifndef CYGONCE_DEVS_SH_SE77X9_SCIF_H +#define CYGONCE_DEVS_SH_SE77X9_SCIF_H + +//========================================================================== +// +// io/serial/sh/sh_sh3_se77x9_scif.inl +// +// Serial I/O specification for Hitachi SE77X9 platform. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-06-18 +// Purpose: Specifies serial resources for the platform. +// Description: This file can be include from either SCI or SCIF/IRDA driver +// sources and should specify driver information as required +// for the platform. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial_sh_se77x9.h> + +#ifdef CYGPKG_IO_SERIAL_SH_SE77X9_COM2 +static sh_scif_info se77x9_serial_info2 = { + er_int_num : CYGNUM_HAL_INTERRUPT_SCIF_ERI2, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_RXI2, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_TXI2, + ctrl_base : CYGARC_REG_SCIF_SCSMR2, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA +# ifdef CYGSEM_IO_SERIAL_SH_SE77X9_COM2_DMA + dma_enable : true,// we want DMA for this channel + dma_xmt_cr_flags : CYGARC_REG_CHCR_RS_SCIF_TX +# else + dma_enable : false // No DMA +# endif +#endif +}; + +#if CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE > 0 +static unsigned char se77x9_serial_out_buf2[CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE]; +static unsigned char se77x9_serial_in_buf2[CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(se77x9_serial_channel2, + sh_scif_funs, + se77x9_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &se77x9_serial_out_buf2[0], + sizeof(se77x9_serial_out_buf2), + &se77x9_serial_in_buf2[0], + sizeof(se77x9_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(se77x9_serial_channel2, + sh_scif_funs, + se77x9_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SE77X9_COM2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io2, + CYGDAT_IO_SERIAL_SH_SE77X9_COM2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_scif_init, + sh_scif_lookup, // Serial driver may need initializing + &se77x9_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_SH_SE77X9_COM2 + +#endif // CYGONCE_DEVS_SH_SE77X9_SCIF_H diff --git a/ecos/packages/devs/serial/sh/sh4_202_md/current/ChangeLog b/ecos/packages/devs/serial/sh/sh4_202_md/current/ChangeLog new file mode 100644 index 0000000..5a1f496 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sh4_202_md/current/ChangeLog @@ -0,0 +1,27 @@ +2003-09-18 Jonathan Larmour <jifl@eCosCentric.com> + + * New package, based on se77x9 driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/devs/serial/sh/sh4_202_md/current/cdl/ser_sh4_202_md.cdl b/ecos/packages/devs/serial/sh/sh4_202_md/current/cdl/ser_sh4_202_md.cdl new file mode 100644 index 0000000..e365b57 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sh4_202_md/current/cdl/ser_sh4_202_md.cdl @@ -0,0 +1,149 @@ +# ==================================================================== +# +# ser_sh4_202_md.cdl +# +# eCos SH4-202 MicroDev serial configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jlarmour +# Contributors: +# Date: 2003-09-18 +# Description: Based on se77x9 driver by jskov. +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_SH_SH4_202_MD { + display "SH4-202 MicroDev serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_SH_SH4_202_MD + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + SuperH SH4-202 MicroDev board, based on the generic SH SCIF driver." + + + # FIXME: This really belongs in the SH_SCIF package + cdl_interface CYGINT_IO_SERIAL_SH_SCIF_REQUIRED { + display "SH SCIF driver required" + } + + # SCIF port + cdl_component CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 { + display "SH4-202 MicroDev SCIF serial port driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the SCIF + port on the SH4-202 MicroDev development board." + + implements CYGINT_IO_SERIAL_SH_SCIF_REQUIRED + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + implements CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX + implements CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_INL <cyg/io/sh4_202_md_scif.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_SH_SCIF_CFG <pkgconf/io_serial_sh_sh4_202_md.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_option CYGDAT_IO_SERIAL_SH_SH4_202_MD_SERIAL1_NAME { + display "Device name" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the serial + port." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BAUD { + display "Baud rate" + flavor data + legal_values { 4800 9600 14400 19200 38400 57600 115200 } + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the serial driver." + } + + cdl_option CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE { + display "Buffer size" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the serial driver." + } + +# DMA not yet implemented +# cdl_option CYGSEM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_DMA { +# display "Enable SCIF serial driver DMA" +# active_if CYGINT_HAL_SH_DMA_CHANNELS +# implements CYGINT_HAL_SH_DMA_CHANNELS_USED +# implements CYGINT_IO_SERIAL_SH_SCIF_DMA +# default_value 1 +# description " +# Enable DMA for this port." +# } +# } + + cdl_component CYGPKG_IO_SERIAL_SH_SH4_202_MD_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + no_define + active_if CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"sh-sh4_202_md\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_SER_DEV CYGDAT_IO_SERIAL_SH_SH4_202_MD_SERIAL1_NAME" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} +# EOF ser_sh_sh4_202_md.cdl diff --git a/ecos/packages/devs/serial/sh/sh4_202_md/current/include/sh4_202_md_scif.inl b/ecos/packages/devs/serial/sh/sh4_202_md/current/include/sh4_202_md_scif.inl new file mode 100644 index 0000000..6745f61 --- /dev/null +++ b/ecos/packages/devs/serial/sh/sh4_202_md/current/include/sh4_202_md_scif.inl @@ -0,0 +1,117 @@ +#ifndef CYGONCE_DEVS_SH_SH4_202_MD_SCIF_H +#define CYGONCE_DEVS_SH_SH4_202_MD_SCIF_H + +//========================================================================== +// +// devs/serial/sh/sh4_202_md_scif.inl +// +// Serial I/O specification for SuperH SH4-202 MicroDev development board +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2003-09-18 +// Purpose: Specifies serial resources for the platform. +// Description: This file can be include from either SCI or SCIF/IRDA driver +// sources and should specify driver information as required +// for the platform. This file was derived from the se77x9 +// driver. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial_sh_sh4_202_md.h> + +#ifdef CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 +static sh_scif_info sh4_202_md_serial_info1 = { + er_int_num : CYGNUM_HAL_INTERRUPT_SCIF_ERI, + rx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_RXI, + br_int_num : CYGNUM_HAL_INTERRUPT_SCIF_BRI, + tx_int_num : CYGNUM_HAL_INTERRUPT_SCIF_TXI, + ctrl_base : CYGARC_REG_SCIF_SCSMR2, +#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA +# ifdef CYGSEM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_DMA + dma_enable : true,// we want DMA for this channel + dma_xmt_cr_flags : CYGARC_REG_CHCR_RS_SCIF_TX +# else + dma_enable : false // No DMA +# endif +#endif +}; + +#if CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE > 0 +static unsigned char sh4_202_md_serial_out_buf1[CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE]; +static unsigned char sh4_202_md_serial_in_buf1[CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(sh4_202_md_serial_channel1, + sh_scif_funs, + sh4_202_md_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &sh4_202_md_serial_out_buf1[0], + sizeof(sh4_202_md_serial_out_buf1), + &sh4_202_md_serial_in_buf1[0], + sizeof(sh4_202_md_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(sh4_202_md_serial_channel1, + sh_scif_funs, + sh4_202_md_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_SH4_202_MD_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(sh_serial_io1, + CYGDAT_IO_SERIAL_SH_SH4_202_MD_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + sh_scif_init, + sh_scif_lookup, // Serial driver may need initializing + &sh4_202_md_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_SH_SH4_202_MD_SERIAL1 + +#endif // CYGONCE_DEVS_SH_SH4_202_MD_SCIF_H + +// EOF sh4_202_md_scif.inl |