diff options
author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
---|---|---|
committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/cortexm/kinetis | |
parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/cortexm/kinetis')
107 files changed, 16426 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog new file mode 100644 index 0000000..910b14e --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog @@ -0,0 +1,49 @@ +2013-04-09 Tomas Frydrych <tomas@sleepfive.com> + + * cdl/hal_cortexm_kinetis_kwikstik.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/kwikstik_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2012-11-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_kwikstik.cdl: + Sync with variant changes due to hardware floating point support. + Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM. [Bugzilla 1001607] + +2011-12-15 Tomas Frydrych <tomas@sleepfive.com> + + * cdl/hal_cortexm_kinetis_kwikstik.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * src/kwikstik_misc.c: + New package -- Freescale Kwikstik board, based on twr_k40x256 board. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl new file mode 100644 index 0000000..8c16ffe --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl @@ -0,0 +1,297 @@ +##========================================================================== +## +## hal_cortexm_kinetis_kwikstik.cdl +## +## Cortex-M Freescale KwikStik platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011, 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Tomas Frydrych <tomas@sleepfive.com> +## Contributor(s): jld +## Date: 2011-12-15 +## Original: hal_cortexm_kinetis_twr_k40x256.cdl by Ilija Kocho +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_KWIKSTIK { + display "Freescale Kinetis KwikStik Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_kwikstik.h + include_dir cyg/hal + hardware + + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) } + + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" } + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" + implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 } + + implements CYGINT_IO_SERIAL_FREESCALE_UART5 + implements CYGINT_IO_FREESCALE_I2C1 + implements CYGINT_HAL_FREESCALE_UART5 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + + description " + The Freescale KwikStik Platform HAL package provides + the support needed to run eCos on the KwikStik development + system. This package can also be used for other boards that + employ a controller from Kinetis families." + + compile kwikstik_misc.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_kwikstik.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale KwikStik\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platform Reference Clock Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 4000000 + legal_values { 32768 4000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This optionchooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console + port if the console and GDB port are the same." + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a + ROM monitor, i.e. applications will be loaded into RAM on the + board, and this ROM monitor may process exceptions or interrupts + generated from the application. This enables features such as + utilizing a separate interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_KWIKSTIK_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h new file mode 100644 index 0000000..f14c402 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tomas Frydrych <tomas@sleepfive.com> +// Original: Cloned from plf_arch.h for twr-k40x256 board by Ilija Kocho +// Date: 2011-12-15 +// Purpose: Kwikstick platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_kwikstik.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h new file mode 100644 index 0000000..6c083a9 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tomas Frydrych <tomas@sleepfive.com> +// Original: Cloned from plf_intr.h for twr-k40x256 board by Ilija Kocho +// Date: 2011-12-15 +// Purpose: Kwikstik platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_kwikstik.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h new file mode 100644 index 0000000..feb6fae --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h @@ -0,0 +1,110 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tomas Frydrych <tomas@sleepfive.com> +// Original: Based on plf_io.h for twr-k40x256 board by Ilija Kocho +// Date: 2011-12-15 +// Purpose: Kwikstik platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_kwikstik.h> + + +// UART PINs + +#ifndef CYGHWR_HAL_FREESCALE_UART5_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 9, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 8, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_FREESCALE_UART5_PIN_RX +# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_FREESCALE_UART5_PIN_TX +# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_FREESCALE_UART5_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_FREESCALE_UART5_PIN_CTS +#endif + +// LCD +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_M 0x40000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_S 30 + +#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_M) +#endif + +// I2C pins +# define CYGHWR_HAL_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 0, 6, 0) +# define CYGHWR_HAL_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 1, 6, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c new file mode 100644 index 0000000..e43fcd6 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c @@ -0,0 +1,255 @@ +//========================================================================== +// +// kwikstik_misc.c +// +// Cortex-M4 Kwikstik HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tomas Frydrych <tomas@sleepfive.com> +// Original: Cloned from twr_k40x256_misc.c by Ilija Kocho +// Date: 2011-12-15 +// Description: Miscellaneous code for platform hal. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_kwikstik.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) + hal_wdog_disable(); + hal_misc_init(); + hal_start_clocks(); +#endif +#if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED) + // Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM + // Relocate data from ROM to RAM + { + register cyg_uint32 *ram_p, *rom_p; + for( ram_p = &__ram_data_start, rom_p = &__rom_data_start; + ram_p < &__ram_data_end; + ram_p++, rom_p++ ) + *ram_p = *rom_p; + } + + // Relocate data from ROM to SRAM + { + register cyg_uint32 *ram_p, *sram_p; + for( ram_p = &__sram_data_start, sram_p = &__srom_data_start; + ram_p < &__sram_data_end; + ram_p++, sram_p++ ) + *ram_p = *sram_p; + } +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash +#endif +#ifdef CYGMEM_REGION_flexnvm + { CYGMEM_REGION_flexnvm, CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1 }, // On-chip flexnvm (DFlash) +#endif +#ifdef CYGMEM_REGION_flexram + { CYGMEM_REGION_flexram, CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1 }, // On-chip flexram +#endif +#ifdef CYGMEM_REGION_eeeprom0 + { CYGMEM_REGION_eeeprom0, CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1 }, // On-chip Enhanced EEPROM +#endif +#ifdef CYGMEM_REGION_eeeprom1 + { CYGMEM_REGION_eeeprom1, CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1 }, // On-chip Enhanced EEPROM +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram +#define CASE_CYGMEM_REGION_SRAM 1 + case CASE_CYGMEM_REGION_SRAM: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#else +#define CASE_CYGMEM_REGION_SRAM 0 +#endif +#ifdef CYGMEM_REGION_flexram +#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1) + case CASE_CYGMEM_REGION_FLEXRAM: + *start = (unsigned char *)CYGMEM_REGION_flexram; + *end = (unsigned char *)(CYGMEM_REGION_flexram + + CYGMEM_REGION_flexram_SIZE); + break; +#else +#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM) +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + + +//========================================================================== +// EOF kwikstik_misc.c diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog new file mode 100644 index 0000000..21c726c --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog @@ -0,0 +1,72 @@ +2013-04-09 Tomas Frydrych <tomas@sleepfive.com> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k40x256_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2012-11-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + Sync with variant changes due to hardware floating point support. + Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM. [Bugzilla 1001607] + +2012-10-25 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k40x256_misc.c: Initialization for separate SRAM regions + synchronized with variant. [Bugzilla 1001606] + +2012-05-19 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: Reference per-package + documentation. + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * doc/twr_k40x512.sgml: + New file -- TWR-K40X512 platform documentation. [Bug 1001580] + +2012-01-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + * include/plf_io.h: + * src/twr_k40x256_misc.c: + Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus. + Updated for early clock start. [Bugzilla 1001450] + +2011-08-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * src/twr_k40x256_misc.c: + New package -- Freescale TWR-K40X256 board. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl new file mode 100644 index 0000000..2455088 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl @@ -0,0 +1,316 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k40x256.cdl +## +## Cortex-M Freescale TWR-K40X256 platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011, 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-07-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256 { + display "Freescale Kinetis TWR-K40X256 Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k40x256.h + include_dir cyg/hal + doc ref/kinetis-twr-k40x256.html + hardware + + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) } + + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" } + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" + implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 } + + implements CYGINT_IO_SERIAL_FREESCALE_UART3 + implements CYGINT_IO_FREESCALE_I2C0 + implements CYGINT_IO_FREESCALE_I2C1 + + implements CYGINT_HAL_FREESCALE_UART3 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + + description " + The Freescale TWR K40X256 Platform HAL package provides + the support needed to run eCos on the TWR K40X256 development + system. This package can also be used for other boards that + employ a controller from Kinetis families." + + compile twr_k40x256_misc.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K40X256\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platform Reference Clock Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 8000000 + legal_values { 32768 8000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This optionchooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console + port if the console and GDB port are the same." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + calculated 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a + ROM monitor, i.e. applications will be loaded into RAM on the + board, and this ROM monitor may process exceptions or interrupts + generated from the application. This enables features such as + utilizing a separate interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK40X256_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml new file mode 100644 index 0000000..e521bca --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml @@ -0,0 +1,75 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- twr_k40x256.sgml --> +<!-- --> +<!-- TWR-K40X256 board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>--> + +<refentry id="kinetis-twr-k40x256"> + <refmeta> + <refentrytitle>TWR-K40X256-KIT Development kit</refentrytitle> + </refmeta> + <refnamediv> + <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256</refname> + <refpurpose>eCos Support for the Freescale TWR-K40X256 development kit</refpurpose> + </refnamediv> + + <refsect1 id="kinetis-twr-k40x256-description"><title>Description</title> + <para> + The Freescale TWR-K40X256-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var"> + Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers K40 and K30 microcontroller + subfamilies. K40X256 is a high end member comprising 256 KiB FLASH, 256 KiB FlexMemory and 64 KiB SRAM, + as well as rich set of communication interfaces including USB, UARTs CAN, SPI and I2C. + K40 controllers also feature a Segment LCD controller, a DMA controller and a FlexBus + external memory interface. They are mixed signal devices featuring 16 bit ADC and 12 bit DAC. + </para> + </refsect1> + <refsect1 id="kinetis-twr-k40x256-config"><title>Configuration</title> + <refsect2 id="kinetis-twr-k40x256-config-hardware"><title>Hardware Setup</title> + <para> + No changes to the factory default setup are necessary. + </para> + <refsect3 id="twr-k40x256-clocking"><title>Clocking</title> + <para> + The TWR-K40X256 uses an 8MHz crystal as a clock reference which is stated as a requirement in the platform package. + </para> + </refsect3> + <refsect3 id="twr-k40x256-memory"><title>Memory</title> + <para> K40X245 has two 32KiB SRAM banks giving a total of 64KiB on chip SRAM. </para> + </refsect3> + </refsect2> + </refsect1> +</refentry> + +<!-- </part> --> diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h new file mode 100644 index 0000000..6d35948 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Purpose: TWR-K40X256 platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h new file mode 100644 index 0000000..f23f2e3 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K40X256 platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h new file mode 100644 index 0000000..fe85537 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h @@ -0,0 +1,113 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K40X256 platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> + + +// UART PINs + +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +#endif + + +// DSPI +// DSPI Pins + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(B, 2, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(B, 3, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c new file mode 100644 index 0000000..b895c36 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c @@ -0,0 +1,233 @@ +//========================================================================== +// +// twr_k40x256_misc.c +// +// Cortex-M4 TWR-K40X256 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) + hal_wdog_disable(); + hal_misc_init(); + hal_start_clocks(); +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash +#endif +#ifdef CYGMEM_REGION_flexnvm + { CYGMEM_REGION_flexnvm, CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1 }, // On-chip flexnvm (DFlash) +#endif +#ifdef CYGMEM_REGION_flexram + { CYGMEM_REGION_flexram, CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1 }, // On-chip flexram +#endif +#ifdef CYGMEM_REGION_eeeprom0 + { CYGMEM_REGION_eeeprom0, CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1 }, // On-chip Enhanced EEPROM +#endif +#ifdef CYGMEM_REGION_eeeprom1 + { CYGMEM_REGION_eeeprom1, CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1 }, // On-chip Enhanced EEPROM +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram +#define CASE_CYGMEM_REGION_SRAM 1 + case CASE_CYGMEM_REGION_SRAM: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#else +#define CASE_CYGMEM_REGION_SRAM 0 +#endif +#ifdef CYGMEM_REGION_flexram +#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1) + case CASE_CYGMEM_REGION_FLEXRAM: + *start = (unsigned char *)CYGMEM_REGION_flexram; + *end = (unsigned char *)(CYGMEM_REGION_flexram + + CYGMEM_REGION_flexram_SIZE); + break; +#else +#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM) +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k40x256_misc.c diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog new file mode 100644 index 0000000..84b0c4e --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog @@ -0,0 +1,39 @@ +2013-07-02 John Dallaway <john@dallaway.org.uk> + + * doc/twr_k60f120m.sgml: Fix missing </para>. + +2013-06-02 Mike Jones <mjones@proclivis.com.> + + * cdl/hal_cortexm_kinetis_twr_k60f120m.cdl: New + * doc/twr_k60f120m.sgml: New + * include/plf_intr.h: New + * include/plf_io.h: New + * include/plf_arch.h: New + * misc/redboot_K60_ROM_FPU.ecm: New + * src/twr_k60f120m_misc.c: New + + Add support for K60F120M [ Bugzilla 1001861 ] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl new file mode 100644 index 0000000..14d9e19 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl @@ -0,0 +1,399 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k60f120m.cdl +## +## Cortex-M Freescale TWR-K60F120M platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Contrib(s): Mike Jones <mjones@proclivis.com> +## Date: 2013-06-02 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M { + display "Freescale Kinetis TWR-K60F120M Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k60f120m.h + include_dir cyg/hal + doc ref/kinetis-twr-k60f120m.html + hardware + description " + The Freescale TWR K60F120M Platform HAL package provides the support + needed to run eCos on the TWR K60F120M development system. This package + can also be used for other boards that employ a controller from Kinetis + families." + + compile twr_k60f120m_misc.c + + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET) + implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" } + + implements CYGINT_HAL_CACHE + + requires { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 60 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 70 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 } + requires { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies + CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 } + requires { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies + CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 } + + implements CYGINT_IO_SERIAL_FREESCALE_UART5 + implements CYGINT_IO_FREESCALE_I2C0 + + implements CYGINT_HAL_FREESCALE_UART5 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 + implements CYGINT_HAL_CORTEXM_KINETIS_150 + + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 } + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) } + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K60F120M\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP { + display "Platform suggested system frequency setpoint" + flavor data + no_define + legal_values 96000000 100000000 120000000 150000000 200000000 + default_value 120000000 + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP { + display "Platform suggested auxiliary frequency setpoint" + flavor data + no_define + legal_values 96000000 100000000 120000000 150000000 200000000 + default_value 120000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platgorm XTAL/OSC Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 50000000 + legal_values { 12000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ { + display "Platform XTAL1/OSC1 Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + default_value 50000000 + legal_values { 12000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP { + display "Platform requred XTAL1 || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This option chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console port + if the console and GDB port are the same." + } + + cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK { + display "ENET MII MDC clock provided by HAL" + flavor data + active_if CYGPKG_DEVS_ETH_FREESCALE_ENET + parent CYGPKG_DEVS_ETH_FREESCALE_ENET + calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS + description " + ENET needs a clock with typical frequency of up to 2.5 MHz for + MII MDC. The input clock, typically provided by HAL, is further + divided by ENET according to setting of ENET MSCR register in order to + provide frequency within 2.5 MHz range." + } + + cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT { + display "IEEE 1588 Port" + active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + flavor data + default_value { "B" } + legal_values { "B" "C" "User" } + description " + Digital I/O provided by HAL for ENET IEEE 1588 timers." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + requires { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE) + && CYGINT_DEVS_SPI_DSPI_DMA_USE) + implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" } + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + legal_values { 0 1 2 3 4 5 } + default_value 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + implements CYGINT_FREESCALE_DSPI1_CS1 + implements CYGINT_FREESCALE_DSPI1_CS2 + implements CYGINT_FREESCALE_DSPI1_CS3 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60F120M_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml new file mode 100644 index 0000000..d2c133a --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml @@ -0,0 +1,113 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- twr_k60f120m.sgml --> +<!-- --> +<!-- TWR-K60F120M board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contrib(s): Mike Jones --> +<!-- Contact(s): mjones@proclivis.com --> +<!-- Date: 2013/06/02 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>--> + +<refentry id="kinetis-twr-k60f120m"> + <refmeta> + <refentrytitle>TWR-K60F120M Development kit</refentrytitle> + </refmeta> + <refnamediv> + <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M</refname> + <refpurpose>eCos Support for Freescale TWR-K60F120M development kit</refpurpose> + </refnamediv> + + <refsect1 id="kinetis-twr-k60f120m-description"><title>Description</title> + <para> + The Freescale TWR-K60F120M is a development kit for <link linkend="hal-cortexm-kinetis-var"> + Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers the K60 + microcontroller subfamily. K60FN1M0 is a high end member comprising on-chip 1 MiB FLASH + and 128 KiB SRAM memory as well as a 16 KiB unified cache. + K60 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs + CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM + external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. + </para> + </refsect1> + <refsect1 id="kinetis-twr-k60f120m-config"><title>Configuration</title> + <refsect2 id="kinetis-twr-k60f120m-config-hardware"><title>Hardware Setup</title> + <refsect3 id="kinetis-twr-k60f120m-config-hardware-cpu"><title>TWR-K60F120M setup</title> + <para> + Factory jumper settings on TWR-K60F120M are fitted for standalone operation of the board. + In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed + on both TWR-K60F120M and TWR-SER. Jumper settings for TWR-SER are given in + <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K60F120M + settings. + </para> + <table frame="all"><title>TWR-K60F120M Jumper setting</title> + <tgroup cols="3" align="center"> + <colspec colnum="1" colname="jumper" colwidth="1*" > + <colspec colnum="2" colname="jumpset" colwidth="1*" > + <colspec colnum="3" colname="desc" colwidth="3*" > + <thead> + <row> + <entry>Jumper</entry> + <entry>Setting</entry> + <entry>Description</entry> + </row> + </thead> + <tbody> + <row> + <entry>J18</entry> + <entry>ON</entry> + <entry>On board 50MHz oscillator is disabled</entry> + </row> + <row> + <entry>J19</entry> + <entry>ON</entry> + <entry>On board 50MHz oscillator is powered</entry> + </row> + </tbody> + </tgroup> + </table> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k60f120m-config-ecos"><title>eCos Configuration</title> + <refsect3 id="twr-k60f120m-clocking"><title>Clocking</title> + <para> + The TWR-K60F120M package defines requirements for the platform clocking. + </para> + </refsect3> + <refsect3 id="twr-k60f120m-memory"><title>Memory</title> + <para> + The K60 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM. + </para> + </refsect3> + </refsect2> + </refsect1> +</refentry> + +<!--</part>--> diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h new file mode 100644 index 0000000..b9eed4b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contrib(s): Mike Jones <mjones@proclivis.com> +// Date: 2013-06-02 +// Purpose: TWR-K60F120M platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h new file mode 100644 index 0000000..d4eb499 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contrib(s): Mike Jones <mjones@proclivis.com> +// Purpose: TWR-K60F120M platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h new file mode 100644 index 0000000..6abb4d2 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h @@ -0,0 +1,175 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contrib(s): Mike Jones <mjones@proclivis.com> +// Date: 2013-06-02 +// Purpose: TWR-K60F120M platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h> + + +// UART PINs +#ifndef CYGHWR_HAL_FREESCALE_UART5_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 9, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 8, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_FREESCALE_UART5_PIN_RX +# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_FREESCALE_UART5_PIN_TX +# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_FREESCALE_UART5_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_FREESCALE_UART5_PIN_CTS +#endif + +#ifndef CYGHWR_HAL_FREESCALE_UART0_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PIN(A, 1, 2, 0) +# define CYGHWR_HAL_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PIN(A, 2, 2, 0) +# define CYGHWR_HAL_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_FREESCALE_UART0_PIN_RX +# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_FREESCALE_UART0_PIN_TX +# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_FREESCALE_UART0_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_FREESCALE_UART0_PIN_CTS +#endif + +// ENET PINs + +// MDIO +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0) +// Both RMII and MII interface +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1 CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0 CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0 CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1 CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0) +// RMII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0) +// MII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3 CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2 CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2 CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3 CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0) +// IEEE 1588 timers +#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0) + +#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0) +#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0) +#endif + +// DSPI +// DSPI Pins + +#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) +#define KINETIS_PIN_SPI1_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define KINETIS_PIN_SPI1_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) +#define KINETIS_PIN_SPI1_0_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0) + +# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm new file mode 100644 index 0000000..e0bb505 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm @@ -0,0 +1,83 @@ +# Redboot minimal configuration +# Target: TWR-K60F120M +# Startup: ROM + + +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "RedBoot Kinetis TWR-K60F120M" ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU { + user_value 1 +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH { + user_value ALL +}; + +cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { + user_value 1 +}; + +cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { +# user_value 1 +#}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -2 +}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT { + user_value 16 +}; + +#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { +# user_value 0x20000 +#}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + user_value ROM +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA { + user_value 1 +}; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c new file mode 100644 index 0000000..34bc5e7 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c @@ -0,0 +1,252 @@ +//========================================================================== +// +// twr_k60f120m_misc.c +// +// Cortex-M4 TWR-K60N512 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contrib(s): Mike Jones <mjones@proclivis.com> +// Date: 2013-06-02 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if !defined(CYG_HAL_STARTUP_RAM) + cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P; + + hal_wdog_disable(); + hal_misc_init(); + + // if ACKISO is set you must clear ackiso before calling pll_init + // or pll init hangs waiting for OSC to initialize + if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M) + pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M; + + hal_start_clocks(); +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M; + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // System bus RAM partition +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#elif defined CYGMEM_REGION_sram_l + { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank +#endif +#ifdef CYGMEM_REGION_ramcod + { CYGMEM_REGION_ramcod, CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition +#endif +#ifdef CYGMEM_REGION_ramnc + { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM partition +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash [currently none] +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 } // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) && + ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#endif +#ifdef CYGMEM_REGION_sram_l +# define CASE_CODE 3 +# define CASE_RAMNC 4 + case 2: + *start = (unsigned char *)CYGMEM_REGION_sram_l; + *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE); + break; +#else +# define CASE_CODE 2 +# define CASE_RAMNC 3 +#endif + +#ifdef CYGMEM_REGION_ramcod + case CASE_CODE: + *start = (unsigned char *)CYGMEM_REGION_ramcod; + *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE); + break; +#endif + +#ifdef CYGMEM_REGION_ramnc + case CASE_RAMNC: + *start = (unsigned char *)CYGMEM_REGION_ramnc; + *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k60f120m_misc.c diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog new file mode 100644 index 0000000..41b6295 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog @@ -0,0 +1,66 @@ +2013-04-09 Tomas Frydrych <tomas@sleepfive.com> + + * cdl/hal_cortexm_kinetis_twr_k60n512.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k60n512_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2012-10-25 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k60n512_misc.c: Initialization for separate SRAM regions + synchronized with variant. [Bugzilla 1001606] + +2012-05-19 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_kinetis_twr_k60n512.cdl: Reference per-package + documentation. + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * doc/twr_k60n512.sgml: + New file -- TWR-K60N512 platform documentation. [Bug 1001580] + +2012-01-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512.cdl: + * include/plf_io.h: + * src/twr_k60n512_misc.c: + Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus. + Updated for early clock start. [Bugzilla 1001450] + +2011-03-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * src/twr_k60n512_misc.c: + New package -- Freescale TWR-K60N512 board. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl new file mode 100644 index 0000000..b6472de --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl @@ -0,0 +1,332 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k60n512.cdl +## +## Cortex-M Freescale TWR-K60N512 platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011, 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-02-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512 { + display "Freescale Kinetis TWR-K60N512 Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k60n512.h + include_dir cyg/hal + doc ref/kinetis-twr-k60n512.html + hardware + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET) + implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" } + + implements CYGINT_IO_SERIAL_FREESCALE_UART3 + implements CYGINT_IO_FREESCALE_I2C0 + + implements CYGINT_HAL_FREESCALE_UART3 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + description " + The Freescale TWR K60N512 Platform HAL package provides the support + needed to run eCos on the TWR K60N512 development system. This package + can also be used for other boards that employ a controller from Kinetis + families." + + compile twr_k60n512_misc.c + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) } + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K60N512\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platform Clock Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 50000000 + legal_values { 25000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This option chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console port + if the console and GDB port are the same." + } + + cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK { + display "ENET MII MDC clock provided by HAL" + flavor data + active_if CYGPKG_DEVS_ETH_FREESCALE_ENET + parent CYGPKG_DEVS_ETH_FREESCALE_ENET + calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS + description " + ENET needs a clock with typical frequency of up to 2.5 MHz for + MII MDC. The input clock, typically provided by HAL, is further + divided by ENET according to setting of ENET MSCR register in order to + provide frequency within 2.5 MHz range." + } + + cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT { + display "IEEE 1588 Port" + active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + flavor data + default_value { "B" } + legal_values { "B" "C" "User" } + description " + Digital I/O provided by HAL for ENET IEEE 1588 timers." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + calculated 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60N512_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml new file mode 100644 index 0000000..d7c0175 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml @@ -0,0 +1,134 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- twr_k60n512.sgml --> +<!-- --> +<!-- TWR-K60N512 board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>--> + +<refentry id="kinetis-twr-k60n512"> + <refmeta> + <refentrytitle>TWR-K60N512-KIT Development kit</refentrytitle> + </refmeta> + <refnamediv> + <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512</refname> + <refpurpose>eCos Support for the Freescale TWR-K60N512 development kit</refpurpose> + </refnamediv> + + <refsect1 id="kinetis-twr-k60n512-description"><title>Description</title> + <para> + The Freescale TWR-K60N512-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var"> + Freescale Kinetis</link> Cortex-M4 based microcontrollers. + It covers K60, K10 and K20 microcontroller families. + K60N512 is a high end member comprising 512 KiB FLASH and 128 KiB SRAM, + as well as rich set of communication interfaces inclduing Ethernet USB, UARTs CAN, SPI and I2C. + K60 micro-controllres also have a DMA controller and a FlexBus external memory interface. + They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. + </para> + </refsect1> + + <refsect1 id="kinetis-twr-k60n512-config"><title>Configuration</title> + <refsect2 id="kinetis-twr-k60n512-config-hardware"><title>Hardware Setup</title> + <para> + Factory jumper settings on the TWR-K60N512 are fitted for standalone operation of the TWR-K60N512. + In order to use it with the Ethernet PHY on TWR-SER, some jumpers have to be changed from their factory + settings on both TWR-K60N512 and TWR-SER: + </para> + <table frame="all"><title>TWR-K60N512 Jumper setting differences from factory settings</title> + <tgroup cols="3" align="center"> + <colspec colnum="1" colname="jumper" colwidth="1*" > + <colspec colnum="2" colname="jumpset" colwidth="1*" > + <colspec colnum="3" colname="desc" colwidth="3*" > + <thead> + <row> + <entry>Jumper</entry> + <entry>Setting</entry> + <entry>Description</entry> + </row> + </thead> + <tbody> + <row> + <entry>J6</entry> + <entry>2-3</entry> + <entry>Select TWR-SER oscillator as clock source.</entry> + </row> + </tbody> + </tgroup> + </table> + + <table frame="all"><title>TWR-SER Jumper settings differences from factory settings</title> + <tgroup cols="3" align="center"> + <colspec colnum="1" colname="jumper" colwidth="1*" > + <colspec colnum="2" colname="jumpset" colwidth="1*" > + <colspec colnum="3" colname="desc" colwidth="3*" > + <thead> + <row> + <entry>Jumper</entry> + <entry>Setting</entry> + <entry>Description</entry> + </row> + </thead> + <tbody> + <row> + <entry>J2</entry> + <entry>3-4</entry> + <entry>Ethernet PHY clock select: 50MHz</entry> + </row> + <row> + <entry>J3</entry> + <entry>2-3</entry> + <entry>Route 50MHz to CLOCKIN0</entry> + </row> + <row> + <entry>J12</entry> + <entry>9-10</entry> + <entry>Ethernet PHY config: select RMII mode</entry> + </row> + </tbody> + </tgroup> + </table> + </refsect2> + <refsect2 id="kinetis-twr-k60n512-config-ecos"><title>eCos Configuration</title> + <refsect3 id="twr-k60n512-clocking"><title>Clocking</title> + <para> + TWR-K60N512 uses default Kinetis variant clocking. + </para> + </refsect3> + <refsect3 id="twr-k60n512-memory"><title>Memory</title> + <para> K60 has two 64KiB SRAM banks giving a total of 128KiB on chip SRAM. </para> + </refsect3> + </refsect2> + </refsect1> +</refentry> + +<!--</part>--> diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h new file mode 100644 index 0000000..cb6ab53 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Purpose: TWR-K60N512 platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h new file mode 100644 index 0000000..530458c --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K60N512 platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h new file mode 100644 index 0000000..76a46f8 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h @@ -0,0 +1,151 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K60N512 platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h> + + +// UART PINs + +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +#endif + +// ENET PINs + +// MDIO +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0) +// Both RMII and MII interface +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1 CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0 CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0 CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1 CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0) +// RMII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0) +// MII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3 CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2 CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2 CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3 CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0) +// IEEE 1588 timers +#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0) + +#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0) +#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0) +#endif + + +// DSPI +// DSPI Pins + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c new file mode 100644 index 0000000..146499f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c @@ -0,0 +1,208 @@ +//========================================================================== +// +// twr_k60n512_misc.c +// +// Cortex-M4 TWR-K60N512 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) + hal_wdog_disable(); + hal_misc_init(); + hal_start_clocks(); +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k60n512_misc.c diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog new file mode 100644 index 0000000..9f52f91 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog @@ -0,0 +1,103 @@ +2013-04-28 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl: + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h: (New) + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi: (New) + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h: + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi: + * include/pkgconf/mlt_kinetis_flash_sram2s_ram.h: (Remove) + * include/pkgconf/mlt_kinetis_flash_sram2s_ram.ldi: (Remove) + * include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h: + * include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi: + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h: + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi: + * include/plf_io.h: + * misc/redboot_K60_FXM_SST25XX_ROM.ecm: (New) + * src/twr_k60n512_fxm_misc.c: + Rich memory layout for FlexBus RAM with support for caching. + Remove redundant MLT files. [ Bugzilla 1001837 ] + +2013-04-09 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k60n512_fxm_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2012-11-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl: + Removed (obsolete) implementation of CYGINT_HAL_CORTEXM4_CODE. + +2012-10-25 Ilija Kocho <ilijak@siva.com.mk> + + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi: + * src/twr_k60n512_misc_fxm.c: Initialization for separate SRAM regions + synchronized with variant. [Bugzilla 1001606] + +2012-01-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl, + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi + * /src/twr_k60n512_fxm_misc.c + Fixed memory layout for FlexBus memory. Add different pin options + [Bugzilla 1001579] + +2012-01-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/hal_kinetis_flexbus.h + * src/twr_k60n512_fxm_misc.c: + * include/pkgconf/mltkinetis_flash_sram2s_extram_rom.h + * include/pkgconf/mltkinetis_flash_sram2s_extram_rom.ldi + * include/pkgconf/mltkinetis_flash_sram2s_jtag.h + * include/pkgconf/mltkinetis_flash_sram2s_jtag.ldi + * include/pkgconf/mltkinetis_flash_sram2s_ram.h + * include/pkgconf/mltkinetis_flash_sram2s_ram.ldi + * include/pkgconf/mltkinetis_flash_unisram_extram.h + * include/pkgconf/mltkinetis_flash_unisram_extram_jtag.h + * include/pkgconf/mltkinetis_flash_unisram_extram_jtag.ldi + * include/pkgconf/mltkinetis_flash_unisram_extram.ldi + * include/pkgconf/mltkinetis_flash_unisram_extram_ram.h + * include/pkgconf/mltkinetis_flash_unisram_extram_ram.ldi + * include/pkgconf/mltkinetis_flash_unisram_extram_rom.h + * include/pkgconf/mltkinetis_flash_unisram_extram_rom.ldi + * include/pkgconf/mltkinetis_flash_unisram_jtag.h + * include/pkgconf/mltkinetis_flash_unisram_jtag.ldi + * include/pkgconf/mltkinetis_flash_unisram_ram.h + * include/pkgconf/mltkinetis_flash_unisram_ram.ldi + New package -- Freescale TWR-K60N512-FXM board. [Bugzilla 1001450] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl new file mode 100644 index 0000000..5f370ce --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl @@ -0,0 +1,648 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k60n512_fxm.cdl +## +## Cortex-M Freescale TWR-K60N512 + TWR-FXM platform HAL configuration +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-09-26 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512_FXM { + display "Freescale Kinetis TWR-K60N512-FXM Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k60n512_fxm.h + include_dir cyg/hal + hardware + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + implements CYGINT_IO_FREESCALE_I2C0 + implements CYGINT_IO_SERIAL_FREESCALE_UART4 + implements CYGINT_HAL_FREESCALE_UART4 + + description " + The Freescale TWR K60N512 FXM Platform package provides the support + needed to run eCos on the TWR K60N512 development system equipped + with TWR-FXM external memory board. This package + can also be used for other boards that employ a controller from Kinetis + families." + + compile twr_k60n512_fxm_misc.c + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) } + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K60N512-FXM\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYG_HAL_STARTUP_PLF { + display "By platform" + flavor data + parent CYG_HAL_STARTUP_ENV + default_value { "ROM" } + legal_values { "ByVariant" "ROM" "RAM" } + requires { CYG_HAL_STARTUP_PLF != "ByVariant" implies + CYGPKG_HAL_CORTEXM_KINETIS_FBRAM == 1 } + + description " + Startup tupes provided by the platform, in addition to variant + startup types. + If 'ByVariant' is selected, then startup type shall be selected from + the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup builds + application similar to Variant's 'ROM' but using external RAM (FlexBus). + 'RAM' startup builds application intended for loading by RedBoot into + external RAM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT_PLF { + display "Memory layout by platform" + flavor data + no_define + active_if { CYG_HAL_STARTUP_PLF != "ByVariant" } + implements CYGINT_HAL_CORTEXM_KINETIS_FBRAM + parent CYGHWR_MEMORY_LAYOUT + calculated { + (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" : + (CYG_HAL_STARTUP == "RAM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_ram" : + (CYG_HAL_STARTUP == "ROM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_rom" : + "Error!" } + description "Combination of 'Startup type' and 'Kinetis member in use' + produces the memory layout." + + cdl_option CYGHWR_MEMORY_RAM_RESERVED { + display "Reserved RAM space \[Bytes\]" + flavor data + legal_values 0 to 0x40000 + default_value 0x20000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platform Clock Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + default_value 50000000 + legal_values { 25000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 1 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console port if the + console and GDB port are the same." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + calculated 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + } + } + + cdl_option CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR { + display "SST25XX Flash Mapping Address" + flavor data + parent CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 + default_value 0xD0000000 + } + cdl_component CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_BUS { + display "SST25xx SPI bus" + flavor data + parent CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + + cdl_option CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_CS { + display "Device number (CS)" + flavor data + calculated 1 + implements CYGINT_FREESCALE_DSPI1_CS1 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGPKG_HAL_EXTRN_MEMORY { + display "External memory devices" + parent CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS + flavor none + active_if { + CYGHWR_HAL_KINETIS_FB_CS0 || CYGHWR_HAL_KINETIS_FB_CS1 || + CYGHWR_HAL_KINETIS_FB_CS2 || CYGHWR_HAL_KINETIS_FB_CS3 || + CYGHWR_HAL_KINETIS_FB_CS4 || CYGHWR_HAL_KINETIS_FB_CS5 + } + description " + This is a container for memory devices attached to + external bus such as RAM, FLASH, etc." + } +# FlexBus Implementation + implements CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + implements CYGINT_HAL_EXTRN_MEMORY + +# CS0 Implementation + implements CYGINT_HAL_KINETIS_FB_CS0 + implements CYGINT_DEVS_RAM0_MICRON_CELLULAR + requires { is_active(CYGPKG_HAL_CORTEXM_KINETIS_FBRAM) implies + CYGHWR_HAL_KINETIS_FBR_SIZE == CYGHWR_HAL_KINETIS_FB_CS0_SIZE } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_AR { + display "Base address" + flavor data + parent CYGHWR_HAL_KINETIS_FB_CS0 + default_value 0x60000000 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_SIZE { + display "Size \[Bytes\]" + flavor data + legal_values { 0x00040000 0x00400000 CYGHWR_RAM0_MICRON_CELLULAR_SIZE } + parent CYGHWR_HAL_KINETIS_FB_CS0 + default_value CYGHWR_RAM0_MICRON_CELLULAR_SIZE + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_BASE { + display "Memory base address" + flavor data + parent CYGHWR_HAL_KINETIS_FB_CS0 + calculated CYGHWR_HAL_KINETIS_FB_CS0_AR + } + + cdl_component CYGHWR_HAL_KINETIS_FB_CS0_MR { + display "Mask register" + flavor data + parent CYGHWR_HAL_KINETIS_FB_CS0 + default_value 0x00FF0001 + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_MR_WP { + display "Write protect" + flavor bool + default_value 0 + } + } + + cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR { + display "Control register" + flavor none + parent CYGHWR_HAL_KINETIS_FB_CS0 + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_WS { + display "Wait states" + flavor data + default_value 3 + legal_values 0 to 63 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BLS { + display "Byte lane shift" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_AA { + display "Auto acknowledge enable" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR_PSB { + display "Port size (bits)" + flavor data + legal_values { 32 8 16 "-16" } + default_value 16 + + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_SWSEN { + display "Secondary wait states enable" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_SWS { + display "Secondary wait states" + flavor data + legal_values 0 to 63 + default_value 0 + + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_EXALE { + display "Extended address latch enable" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_ASET { + display "Address setup" + flavor data + legal_values { 0 1 2 3 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_RDAH { + display "Read address hold or deselect" + flavor data + legal_values { 0 1 2 3 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_WRAH { + display "Write address hold or deselect" + flavor data + legal_values { 0 1 2 3 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BEM { + display "Byte enable mode" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BSTR { + display "Burst read enable" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BSTW { + display "Burst write enable" + flavor data + legal_values { 0 1 } + default_value 0 + } + } + + cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR_IS { + display "Control register initial setting." + flavor none + parent CYGHWR_HAL_KINETIS_FB_CS0 + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_WS { + display "Wait states" + flavor data + default_value 3 + legal_values 0 to 63 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_AA { + display "Auto acknowledge enable" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_SWSEN { + display "Secondary wait states enable" + flavor data + legal_values { 0 1 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_SWS { + display "Secondary wait states" + flavor data + legal_values 0 to 63 + default_value 0 + + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_EXALE { + display "Extended address latch enable" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_ASET { + display "Address setup" + flavor data + legal_values { 0 1 2 3 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_RDAH { + display "Read address hold or deselect" + flavor data + legal_values { 0 1 2 3 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_WRAH { + display "Write address hold or deselect" + flavor data + legal_values { 0 1 2 3 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BEM { + display "Byte enable mode" + flavor data + legal_values { 0 1 } + default_value 1 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BSTR { + display "Burst read enable" + flavor data + legal_values { 0 1 } + default_value 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BSTW { + display "Burst write enable" + flavor data + legal_values { 0 1 } + default_value 0 + } + } +# CS0 Implementation End +# FlexBus Implementation End + + cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE { + display "External RAM size" + flavor data + calculated CYGHWR_HAL_KINETIS_FB_CS0_SIZE + } + + cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE { + display "External RAM base address" + flavor data + calculated CYGHWR_HAL_KINETIS_FB_CS0_BASE + } + + cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK { + display "ENET MII MDC clock provided by HAL" + flavor data + active_if CYGPKG_DEVS_ETH_FREESCALE_ENET + parent CYGPKG_DEVS_ETH_FREESCALE_ENET + calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS + description " + ENET needs a clock with typical frequency of up to 2.5 MHz for + MII MDC. The input clock, typically provided by HAL, is further + divided by ENET according to setting of ENET MSCR register in order to + provide frequency within 2.5 MHz range." + } + + cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT { + display "IEEE 1588 Port" + active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + flavor data + default_value { "B" } + legal_values { "B" "C" "User" } + description " + Digital I/O provided by HAL for ENET IEEE 1588 timers." + } + + + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60N512_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description "This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h new file mode 100644 index 0000000..ac10c73 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h @@ -0,0 +1,143 @@ +#ifndef CYGONCE_FLEXBUS_H +#define CYGONCE_FLEXBUS_H +//============================================================================= +// +// flexbus.h +// +// Kinetis FlexBus specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-08-05 +// Purpose: Kinetis FlexBus specific registers +// Description: +// Usage: #include <cyg/hal/flexbus.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Flexbus pins + +#define KINETIS_PIN_FB_OPT CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M +#define KINETIS_PIN_FB 5 +#define KINETIS_PIN_FB6 6 + +#define CYGHWR_KINETIS_FB_PIN_AD0 CYGHWR_HAL_KINETIS_PIN(D, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD1 CYGHWR_HAL_KINETIS_PIN(D, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD2 CYGHWR_HAL_KINETIS_PIN(D, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD3 CYGHWR_HAL_KINETIS_PIN(D, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD4 CYGHWR_HAL_KINETIS_PIN(D, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD5 CYGHWR_HAL_KINETIS_PIN(C, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD6 CYGHWR_HAL_KINETIS_PIN(C, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD7 CYGHWR_HAL_KINETIS_PIN(C, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD8 CYGHWR_HAL_KINETIS_PIN(C, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD9 CYGHWR_HAL_KINETIS_PIN(C, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD10 CYGHWR_HAL_KINETIS_PIN(C, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD11 CYGHWR_HAL_KINETIS_PIN(C, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD12 CYGHWR_HAL_KINETIS_PIN(C, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD13 CYGHWR_HAL_KINETIS_PIN(C, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD14 CYGHWR_HAL_KINETIS_PIN(C, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD15 CYGHWR_HAL_KINETIS_PIN(B, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD16 CYGHWR_HAL_KINETIS_PIN(B, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD17 CYGHWR_HAL_KINETIS_PIN(B, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD18 CYGHWR_HAL_KINETIS_PIN(B, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD19 CYGHWR_HAL_KINETIS_PIN(B, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD20 CYGHWR_HAL_KINETIS_PIN(B, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD21 CYGHWR_HAL_KINETIS_PIN(B, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD22 CYGHWR_HAL_KINETIS_PIN(B, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD23 CYGHWR_HAL_KINETIS_PIN(B, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD24 CYGHWR_HAL_KINETIS_PIN(C, 15, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD25 CYGHWR_HAL_KINETIS_PIN(C, 14, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD26 CYGHWR_HAL_KINETIS_PIN(C, 13, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD27 CYGHWR_HAL_KINETIS_PIN(C, 12, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD28 CYGHWR_HAL_KINETIS_PIN(B, 23, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD29 CYGHWR_HAL_KINETIS_PIN(B, 22, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD30 CYGHWR_HAL_KINETIS_PIN(B, 21, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD31 CYGHWR_HAL_KINETIS_PIN(B, 20, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_A16 CYGHWR_HAL_KINETIS_PIN(D, 8, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A17 CYGHWR_HAL_KINETIS_PIN(D, 9, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A18 CYGHWR_HAL_KINETIS_PIN(D, 10, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A19 CYGHWR_HAL_KINETIS_PIN(D, 11, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A20 CYGHWR_HAL_KINETIS_PIN(D, 12, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A21 CYGHWR_HAL_KINETIS_PIN(D, 13, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A22 CYGHWR_HAL_KINETIS_PIN(D, 14, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A23 CYGHWR_HAL_KINETIS_PIN(D, 15, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_CLKOUT CYGHWR_HAL_KINETIS_PIN(C, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF \ + CYGHWR_HAL_KINETIS_PIN(C, 3, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define CYGHWR_KINETIS_FB_PIN_RW CYGHWR_HAL_KINETIS_PIN(C, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_OE CYGHWR_HAL_KINETIS_PIN(B, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +// Following pins are additionally multiplexed by FB_CSPMCR + +#define CYGHWR_KINETIS_FB_PIN_BE23_16 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BE31_24 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BE15_8 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BE7_0 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_BLS15_8 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BLS7_0 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BLS23_16 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BLS31_24 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_CS5 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS4 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(D, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS0_LOW \ + CYGHWR_HAL_KINETIS_PIN(D, 1, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define CYGHWR_KINETIS_FB_PIN_TSIZ0 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_TSIZ1 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_TST CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_ALE CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_TS CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_TA CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) + +//----------------------------------------------------------------------------- +// end of flexbus.h +#endif // CYGONCE_FLEXBUS_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h new file mode 100644 index 0000000..daf0474 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi new file mode 100644 index 0000000..6095daa --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -0,0 +1,41 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h new file mode 100644 index 0000000..a00ce95 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -0,0 +1,40 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi new file mode 100644 index 0000000..3888a13 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -0,0 +1,49 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h new file mode 100644 index 0000000..53dceb8 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi new file mode 100644 index 0000000..f8330ee --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h new file mode 100644 index 0000000..b466a08 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi new file mode 100644 index 0000000..bab581b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -0,0 +1,39 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h new file mode 100644 index 0000000..5c6db56 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi new file mode 100644 index 0000000..b43ce41 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -0,0 +1,47 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h new file mode 100644 index 0000000..5370f8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h @@ -0,0 +1,24 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi new file mode 100644 index 0000000..e74d8a9 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH security configuration. Must be present at 0x00000400 + // Warning: Omitting FLASH security configuration or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_security 0x00000400 : { KEEP (*(.flash_security)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h new file mode 100644 index 0000000..329056b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Purpose: TWR-K60N512-FXM platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h new file mode 100644 index 0000000..a443eed --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K60N512-FXM platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h new file mode 100644 index 0000000..6b2ddab --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h @@ -0,0 +1,194 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K60N512 platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> + +// UART PINs + +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# if 0 +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 5, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 4, 3, 0) +# elif 0 +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# else +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# endif +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# if 0 +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +# endif +#endif + +#if 1 +#ifndef CYGHWR_HAL_FREESCALE_UART4_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 25, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 24, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + + +# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_FREESCALE_UART4_PIN_RX +# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_FREESCALE_UART4_PIN_TX +# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_FREESCALE_UART4_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_FREESCALE_UART4_PIN_CTS + +#endif +#endif + + +// ENET PINs + +// MDIO +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0) +// Both RMII and MII interface +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1 CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0 CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0 CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1 CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0) +// RMII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0) +// MII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3 CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2 CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2 CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3 CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0) +// IEEE 1588 timers +#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0) + +#if defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_B) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0) +#elif defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_C) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0) +#endif + +// FlexBus Memory +#define CYGHWR_HAL_FB_CSPMCR_G1_SEL CYGHWR_HAL_FB_CSPMCR_G1_TS +#define CYGHWR_HAL_FB_CSPMCR_G2_SEL CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 +#define CYGHWR_HAL_FB_CSPMCR_G3_SEL CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 +#define CYGHWR_HAL_FB_CSPMCR_G4_SEL CYGHWR_HAL_FB_CSPMCR_G4_CS2 +#define CYGHWR_HAL_FB_CSPMCR_G5_SEL CYGHWR_HAL_FB_CSPMCR_G5_TA + +#define CYGHWR_HAL_FB_CSPMCR_SETSEL (CYGHWR_HAL_FB_CSPMCR_G1_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G2_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G3_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G4_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G5_SEL ) + +// DSPI +// DSPI Pins + +#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) + +#define KINETIS_PIN_SPI1_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) + +#define KINETIS_PIN_SPI1_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm new file mode 100644 index 0000000..59dd5b0 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm @@ -0,0 +1,81 @@ +# Redboot minimal configuration +# Target: TWR-K70F120M +# Startup: ROM with external RAM + + +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "RedBoot Kinetis TWR-K60N512-FXM" ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_component CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 { + user_value 1 +}; + +cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP { + user_value 100000000 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE { + user_value 16384 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { +# user_value 1 +#}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -4 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -8 +}; + +#cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT { +# user_value 16 +#}; + +#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { +# user_value 0x20000 +#}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + user_value ROM +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA { + user_value 1 +}; + + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c new file mode 100644 index 0000000..5a17836 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c @@ -0,0 +1,446 @@ +//========================================================================== +// +// twr_k60n512_fxm_misc.c +// +// Cortex-M3 TWR-K60N512 EVAL + TWR_FXM HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS +#include <cyg/hal/hal_kinetis_flexbus.h> +#include <cyg/devs/ram_micron_cellularram.h> + +// Dependent on FlexBus memory properties up to two flexbus setting stages +// may be needed + +// Macro for final setting of CSCR +// Final settings take place when system clock is completely initialized and +// it is possible to program FlexBus memory with desired setting. +#define CYGHWR_HAL_FB_CSCR(__bits,__cs) \ + VALUE_(CYGHWR_HAL_FB_CSCR_##__bits##_S, \ + CYGHWR_HAL_KINETIS_FB_CS##__cs##_CR_##__bits) + +#define CYGHWR_HAL_KINETIS_FB_CS_CR(__cs) ( CYGHWR_HAL_FB_CSCR(SWS, __cs) + \ + CYGHWR_HAL_FB_CSCR(SWSEN, __cs) + CYGHWR_HAL_FB_CSCR(EXALE, __cs) + \ + CYGHWR_HAL_FB_CSCR(ASET, __cs) + CYGHWR_HAL_FB_CSCR(RDAH, __cs) + \ + CYGHWR_HAL_FB_CSCR(WRAH, __cs) + CYGHWR_HAL_FB_CSCR(WS, __cs) + \ + CYGHWR_HAL_FB_CSCR(BLS, __cs) + CYGHWR_HAL_FB_CSCR(AA, __cs) + \ + CYGHWR_HAL_FB_CSCR(PS, __cs) + CYGHWR_HAL_FB_CSCR(BEM, __cs) + \ + CYGHWR_HAL_FB_CSCR(BSTR, __cs) + CYGHWR_HAL_FB_CSCR(BSTW, __cs)) + +// Macros for initial settings of CSCR +// Initial settings are used immediately after boot and make it possible to +// utilize FlexBus memory with it's power-up setting. +#define CYGHWR_HAL_FB_CSCR_IS(__bits,__cs) \ + VALUE_(CYGHWR_HAL_FB_CSCR_##__bits##_S, \ + CYGHWR_HAL_KINETIS_FB_CS##__cs##_CR_IS_##__bits) + +#define CYGHWR_HAL_KINETIS_FB_CS_CR_IS(__cs) ( CYGHWR_HAL_FB_CSCR_IS(SWS, __cs) + \ + CYGHWR_HAL_FB_CSCR_IS(SWSEN, __cs) + CYGHWR_HAL_FB_CSCR_IS(EXALE, __cs) + \ + CYGHWR_HAL_FB_CSCR_IS(ASET, __cs) + CYGHWR_HAL_FB_CSCR_IS(RDAH, __cs) + \ + CYGHWR_HAL_FB_CSCR_IS(WRAH, __cs) + CYGHWR_HAL_FB_CSCR_IS(WS, __cs) + \ + CYGHWR_HAL_FB_CSCR(BLS, __cs) + CYGHWR_HAL_FB_CSCR_IS(AA, __cs) + \ + CYGHWR_HAL_FB_CSCR(PS, __cs) + CYGHWR_HAL_FB_CSCR_IS(BEM, __cs) + \ + CYGHWR_HAL_FB_CSCR_IS(BSTR, __cs) + CYGHWR_HAL_FB_CSCR_IS(BSTW, __cs)) + +// Functions for final and initial FlexBus setting +// Description is with the code below. +static inline void hal_flexbus_init_initial(void); +static inline void hal_flexbus_init_final(void); +#endif // CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) + hal_wdog_disable(); + hal_misc_init(); +# ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS + { + // This delay is needed for Micron RAM wake-up. + cyg_uint32 busy_delay; + for(busy_delay = 0x100000; busy_delay; busy_delay--) + __asm__ volatile ("nop\n"); + + hal_flexbus_init_initial(); + + hal_start_clocks(); + + for(busy_delay = 0x100000; busy_delay; busy_delay--) + __asm__ volatile ("nop\n"); + + hal_flexbus_init_final(); + } +# else + hal_start_clocks(); +# endif +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS + +// FlexBus + +static const cyg_uint32 const flexbus_pins[] = { + CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF, + + CYGHWR_KINETIS_FB_PIN_CS0, + CYGHWR_KINETIS_FB_PIN_OE, + CYGHWR_KINETIS_FB_PIN_RW, +# if 0 //(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M) + CYGHWR_KINETIS_FB_PIN_BLS7_0, + CYGHWR_KINETIS_FB_PIN_BLS15_8, +# else + CYGHWR_KINETIS_FB_PIN_BE23_16, + CYGHWR_KINETIS_FB_PIN_BE31_24, +# endif + CYGHWR_KINETIS_FB_PIN_TS, + + CYGHWR_KINETIS_FB_PIN_AD0, + CYGHWR_KINETIS_FB_PIN_AD1, + CYGHWR_KINETIS_FB_PIN_AD2, + CYGHWR_KINETIS_FB_PIN_AD3, + CYGHWR_KINETIS_FB_PIN_AD4, + CYGHWR_KINETIS_FB_PIN_AD5, + CYGHWR_KINETIS_FB_PIN_AD6, + CYGHWR_KINETIS_FB_PIN_AD7, + CYGHWR_KINETIS_FB_PIN_AD8, + CYGHWR_KINETIS_FB_PIN_AD9, + CYGHWR_KINETIS_FB_PIN_AD10, + CYGHWR_KINETIS_FB_PIN_AD11, + CYGHWR_KINETIS_FB_PIN_AD12, + CYGHWR_KINETIS_FB_PIN_AD13, + CYGHWR_KINETIS_FB_PIN_AD14, + CYGHWR_KINETIS_FB_PIN_AD15, + CYGHWR_KINETIS_FB_PIN_AD16, + CYGHWR_KINETIS_FB_PIN_AD17 +# if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 + , + CYGHWR_KINETIS_FB_PIN_AD18, + CYGHWR_KINETIS_FB_PIN_AD19, + CYGHWR_KINETIS_FB_PIN_AD20, + CYGHWR_KINETIS_FB_PIN_AD21 +# if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000 + , + CYGHWR_KINETIS_FB_PIN_AD22, + CYGHWR_KINETIS_FB_PIN_AD23 +# if 0 //!(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M) + , + CYGHWR_KINETIS_FB_PIN_AD24, + CYGHWR_KINETIS_FB_PIN_AD25, + CYGHWR_KINETIS_FB_PIN_AD26, + CYGHWR_KINETIS_FB_PIN_AD27, + CYGHWR_KINETIS_FB_PIN_AD28, + CYGHWR_KINETIS_FB_PIN_AD29, + CYGHWR_KINETIS_FB_PIN_AD30, + CYGHWR_KINETIS_FB_PIN_AD31 +# endif +# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000 +# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 +}; + +static const cyg_uint32 const flexbus_pins_final_diff[] = { + CYGHWR_KINETIS_FB_PIN_CLKOUT +}; + +// Initialize FlexBus for use until we have main clock. +// Asynchronous mode. +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_flexbus_init_initial(void) +{ + cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P; + + CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS); + +# ifdef CYGHWR_HAL_KINETIS_FB_CS0 + fb_p->csel[0] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS0_AR, + CYGHWR_HAL_KINETIS_FB_CS0_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(0) }; +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS1 + fb_p->csel[1] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS1_AR, + CYGHWR_HAL_KINETIS_FB_CS1_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(1) }; +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS2 + fb_p->csel[2] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS2_AR, + CYGHWR_HAL_KINETIS_FB_CS2_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(2) }; +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS3 + fb_p->csel[3] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS3_AR, + CYGHWR_HAL_KINETIS_FB_CS3_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(3) }; +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS4 + fb_p->csel[4] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS4_AR, + CYGHWR_HAL_KINETIS_FB_CS4_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(4) }; +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS4 + fb_p->csel[5] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS5_AR, + CYGHWR_HAL_KINETIS_FB_CS5_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(5) }; +# endif + + fb_p->cspmcr = CYGHWR_HAL_FB_CSPMCR_SETSEL; + + HAL_SET_PINS(flexbus_pins); +} + +// Initialize FlexBus to it's normal working condition +// Synchronous mode with burst support +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_flexbus_init_final(void) +{ + cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P; + + // Enable RAM synchronous/burst mode + ram_micron_reg_set(CYGHWR_DEVS_RAM_MICRON_BCR, + CYGHWR_RAM0_MICRON_BCR_SETTO, + (cyg_uint16 *)CYGHWR_HAL_KINETIS_FB_CS0_AR, + CYGHWR_RAM0_MICRON_CELLULAR_SIZE); + + // Apply FlexBus clock... + HAL_SET_PINS(flexbus_pins_final_diff); + + // ...and final CS setting for burst, etc. +# ifdef CYGHWR_HAL_KINETIS_FB_CS0 + fb_p->csel[0].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(0); +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS1 + fb_p->csel[1].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(1); +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS2 + fb_p->csel[2].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(2); +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS3 + fb_p->csel[3].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(3); +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS4 + fb_p->csel[4].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(4); +# endif +# ifdef CYGHWR_HAL_KINETIS_FB_CS5 + fb_p->csel[5].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(5); +# endif +} + +#endif // CYGHWR_HAL_CORTEXM_KINETIS_FLEXBUS + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // System bus RAM partition +#if 1 //def CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#elif defined CYGMEM_REGION_sram_l + { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank +#endif +#ifdef CYGMEM_REGION_ramcod + { CYGMEM_REGION_ramcod, CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition +#endif +#ifdef CYGMEM_REGION_ramnc + { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM partition +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash [currently none] +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 } // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) && + ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external RAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#endif +#ifdef CYGMEM_REGION_sram_l +# define CASE_CODE 3 +# define CASE_RAMNC 4 + case 2: + *start = (unsigned char *)CYGMEM_REGION_sram_l; + *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE); + break; +#else +# define CASE_CODE 2 +# define CASE_RAMNC 3 +#endif + +#ifdef CYGMEM_REGION_ramcod + case CASE_CODE: + *start = (unsigned char *)CYGMEM_REGION_ramcod; + *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE); + break; +#endif + +#ifdef CYGMEM_REGION_ramnc + case CASE_RAMNC: + *start = (unsigned char *)CYGMEM_REGION_ramnc; + *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k60n512_fxm_misc.c diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog new file mode 100644 index 0000000..1d90bda --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog @@ -0,0 +1,110 @@ +2013-04-09 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + + Add requirement for WRITETHRU data cache startup mode when eDMA is in use. + Sync with change in eDMA driver [ Bugzilla 1001838 ] + +2013-04-09 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k70f120m_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2013-03-09 Ilija Kocho <ilijak@siva.com.mk> + + * misc/redboot_K70_ROM_FPU.ecm: Add ECM file + +2012-11-30 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Sync with variant changes due to + hardware floating point support. Implements CYGINT_HAL_FPV4_SP_D16. + Changed maximum peripheral bus clocks to 75MHz. + [Bugzilla 1001607] + +2012-11-04 Ilija Kocho <ilijak@siva.com.mk> + + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi: + Recognize 256 Bytes space for virtual vectors in sram. + + * twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + Add settings for Kinetis internal flash. [Bugzilla 1001561] + +2012-09-28 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h + * current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi + * current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h + * current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi + * src/twr_k70f120m_misc.c: + Synchronized with Kinetis variant changes to SDRAM controller support. + Memory layouts adapted to separate data and code cacing partitions. + [Bugzilla 1001606] + +2012-05-19 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Reference per-package + documentation. + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * doc/twr_k70f120m.sgml: + New file -- TWR-K70F120M platform documentation. [Bug 1001580] + +2012-05-17 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + Bug fix: Do not implement external memory interface if Platform startup is + not selected. [ Bugzilla 1001590 ] + +2012-02-25 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h: + * pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi: + * pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h: + * pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi: + * pkgconf/mlt_kinetis_flash_unisram_extram_ram.h: + * pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi: + * pkgconf/mlt_kinetis_flash_unisram_extram_rom.h: + * pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi: + * src/twr_k70f120m_misc.c: + New package -- Freescale TWR-K70F120M board. [Bugzilla 1001579] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl new file mode 100644 index 0000000..6d469cf --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl @@ -0,0 +1,444 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k70f120m.cdl +## +## Cortex-M Freescale TWR-K70F120M platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2012-02-25 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M { + display "Freescale Kinetis TWR-K70F120M Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k70f120m.h + include_dir cyg/hal + doc ref/kinetis-twr-k70f120m.html + hardware + description " + The Freescale TWR K70F120M Platform HAL package provides the support + needed to run eCos on the TWR K70F120M development system. This package + can also be used for other boards that employ a controller from Kinetis + families." + + compile twr_k70f120m_misc.c + + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET) + implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" } + + implements CYGINT_HAL_CACHE + + requires { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 70 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 } + requires { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies + CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 } + requires { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies + CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 } + + implements CYGINT_IO_SERIAL_FREESCALE_UART2 + implements CYGINT_IO_FREESCALE_I2C0 + + implements CYGINT_HAL_FREESCALE_UART2 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 + implements CYGINT_HAL_CORTEXM_KINETIS_150 + + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 } + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) } + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K70F120M\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYG_HAL_STARTUP_PLF { + display "By platform" + flavor data + parent CYG_HAL_STARTUP_ENV + default_value { "ROM" } + legal_values { "ByVariant" "ROM" "RAM" } + + requires { CYG_HAL_STARTUP_PLF != "ByVariant" implies + CYGPKG_HAL_CORTEXM_KINETIS_DDRMC == 1 } + + description " + Startup tupes provided by the platform, in addition to variant + startup types. + If 'ByVariant' is selected, then startup type shall be selected + from the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup + builds application similar to Variant's 'ROM' but using external + RAM (DDRAM). 'RAM' startup builds application intended for loading + by RedBoot into external RAM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT_PLF { + display "Memory layout by platform" + flavor data + active_if { CYG_HAL_STARTUP_PLF != "ByVariant" } + implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM + no_define + parent CYGHWR_MEMORY_LAYOUT + calculated { + (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" : + (CYG_HAL_STARTUP == "RAM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_ram" : + (CYG_HAL_STARTUP == "ROM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_rom" : + "Error!" + } + description " + Combination of 'Startup type' and 'Kinetis member in use' + produces the memory layout." + + cdl_option CYGHWR_MEMORY_RAM_RESERVED { + display "Reserved RAM space \[Bytes\]" + flavor data + legal_values 0 to 0x40000 + default_value 0x20000 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP { + display "Platform suggested system frequency setpoint" + flavor data + no_define + legal_values 96000000 100000000 120000000 150000000 200000000 + default_value 120000000 + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP { + display "Platform suggested auxiliary frequency setpoint" + flavor data + no_define + legal_values 96000000 100000000 120000000 150000000 200000000 + default_value 120000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platgorm XTAL/OSC Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 50000000 + legal_values { 12000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ { + display "Platform XTAL1/OSC1 Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + default_value 50000000 + legal_values { 12000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP { + display "Platform requred XTAL1 || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This option chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console port + if the console and GDB port are the same." + } + + cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK { + display "ENET MII MDC clock provided by HAL" + flavor data + active_if CYGPKG_DEVS_ETH_FREESCALE_ENET + parent CYGPKG_DEVS_ETH_FREESCALE_ENET + calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS + description " + ENET needs a clock with typical frequency of up to 2.5 MHz for + MII MDC. The input clock, typically provided by HAL, is further + divided by ENET according to setting of ENET MSCR register in order to + provide frequency within 2.5 MHz range." + } + + cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT { + display "IEEE 1588 Port" + active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + flavor data + default_value { "B" } + legal_values { "B" "C" "User" } + description " + Digital I/O provided by HAL for ENET IEEE 1588 timers." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + requires { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE) + && CYGINT_DEVS_SPI_DSPI_DMA_USE) + implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" } + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + legal_values { 0 1 2 3 4 5 } + default_value 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + implements CYGINT_FREESCALE_DSPI1_CS1 + implements CYGINT_FREESCALE_DSPI1_CS2 + implements CYGINT_FREESCALE_DSPI1_CS3 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK70F120M_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml new file mode 100644 index 0000000..6178f5b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml @@ -0,0 +1,165 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- twr_k70f120m.sgml --> +<!-- --> +<!-- TWR-K70F120M board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>--> + +<refentry id="kinetis-twr-k70f120m"> + <refmeta> + <refentrytitle>TWR-K70F120M Development kit</refentrytitle> + </refmeta> + <refnamediv> + <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M</refname> + <refpurpose>eCos Support for Freescale TWR-K70F120M development kit</refpurpose> + </refnamediv> + + <refsect1 id="kinetis-twr-k70f120m-description"><title>Description</title> + <para> + The Freescale TWR-K70F120M is a development kit for <link linkend="hal-cortexm-kinetis-var"> + Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers K70, K60, K10 and K20 + microcontroller subfamilies. K70FN1M0 is a high end member comprising on-chip 1 MiB FLASH + and 128 KiB SRAM memory as well as a 16 KiB unified cache. + K70 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs + CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM + external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. + </para> + </refsect1> + <refsect1 id="kinetis-twr-k70f120m-config"><title>Configuration</title> + <refsect2 id="kinetis-twr-k70f120m-config-hardware"><title>Hardware Setup</title> + <refsect3 id="kinetis-twr-k70f120m-config-hardware-cpu"><title>TWR-K70F120M setup</title> + <para> + Factory jumper settings on TWR-K70F120M are fitted for standalone operation of the board. + In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed + on both TWR-K70F120M and TWR-SER. Jumper settings for TWR-SER are given in + <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K70F120M + settings. + </para> + <table frame="all"><title>TWR-K70F120M Jumper setting</title> + <tgroup cols="3" align="center"> + <colspec colnum="1" colname="jumper" colwidth="1*" > + <colspec colnum="2" colname="jumpset" colwidth="1*" > + <colspec colnum="3" colname="desc" colwidth="3*" > + <thead> + <row> + <entry>Jumper</entry> + <entry>Setting</entry> + <entry>Description</entry> + </row> + </thead> + <tbody> + <row> + <entry>J19</entry> + <entry>OFF</entry> + <entry>On board 50MHz oscillator is not powered</entry> + </row> + </tbody> + </tgroup> + </table> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k70f120m-config-ecos"><title>eCos Configuration</title> + <refsect3 id="twr-k70f120m-clocking"><title>Clocking</title> + <para> + The TWR-K70F120M package defines requirements for the platform clocking. + </para> + </refsect3> + <refsect3 id="twr-k70f120m-memory"><title>Memory</title> + <para> + The K70 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM. In addition, on-board there is + 128 MiB of external RAM (SDRAM) and 256 MiB of NAND Flash. + External RAM is divided in two regions: + </para> + <variablelist> + <varlistentry> + <term>ram</term> + <listitem><para> Regular RAM.</para></listitem> + </varlistentry> + <varlistentry> + <term>ramnc</term> + <listitem><para>Non cached RAM. This region contains <literal>.noncache</literal> section.</para></listitem> + </varlistentry> + </variablelist> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k70f120m-memory"><title>Memory layouts</title> + <para> + Additional platform memory layouts follow the <link linkend="kinetis-var-memory">variant</link> + ones only by putting all RAM sections except <literal>.sram</literal> in the <literal>ram</literal> region. + The linker file names incorporate the segment <filename>_extram_</filename>. + </para> + <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-location"><title>Linker + Script Location</title> + <para> + Linker scripts are found at: + <filename class="directory">hal/kinetis/twr-k70f120m/<version>/include/pkgconf</filename> + </para> + </refsect3> + <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-naming"><title>Linker Script Naming</title> + <para> + Linker script file names have following form: + <filename>mlt_kinetis_<NVM>_<SRAM>_<STARTUP_extram.ldi</filename> + where <filename>PLF</filename> is an optional extension for platform specific scripts and + other segments have meaning as described <link linkend="kinetis-var-table-ldscript-naming">here</link>. + </para> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k70f120m-startup"><title>Startup types</title> + <para> + The platform startup <literal>CYG_HAL_STARTUP_PLF</literal> offers the following startups: + </para> + <variablelist> + <varlistentry> + <term><literal>ROM (Platform)</literal></term> + <listitem><para>Normal startup for stand-alone operation. The eCos image has to be flashed + in internal flash. External RAM is used as main memory. + </para> + <para> + Note: This startup has a name like the one in the variant but generates different images + by invoking a different set of linker scripts. + </para></listitem></varlistentry> + <varlistentry> + <term><literal>RAM (Platform)</literal></term> + <listitem><para>The image is loaded in external RAM by means of RedBoot. + </para></listitem></varlistentry> + <varlistentry> + <term><literal>ByVariant</literal></term> + <listitem><para>Activates the <link linkend="kinetis-var-startup">variant startup types</link>. + </para></listitem></varlistentry> + </variablelist> + </refsect2> + </refsect1> +</refentry> + +<!--</part>--> diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h new file mode 100644 index 0000000..80ff30e --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi new file mode 100644 index 0000000..feb1b8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -0,0 +1,41 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h new file mode 100644 index 0000000..bdfde58 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -0,0 +1,40 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi new file mode 100644 index 0000000..4a09a9b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -0,0 +1,49 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h new file mode 100644 index 0000000..69ba037 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi new file mode 100644 index 0000000..3cd913d --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -0,0 +1,39 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h new file mode 100644 index 0000000..e0339ca --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi new file mode 100644 index 0000000..694fb95 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -0,0 +1,47 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h new file mode 100644 index 0000000..3e631ed --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-02-15 +// Purpose: TWR-K70F120M platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h new file mode 100644 index 0000000..0d92bd6 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2012-02-25 +// Purpose: TWR-K70F120M platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h new file mode 100644 index 0000000..1329b3c --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h @@ -0,0 +1,171 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2012-02-25 +// Purpose: TWR-K70F120M platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> + + +// UART PINs +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +#endif + +#ifndef CYGHWR_HAL_FREESCALE_UART2_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_FREESCALE_UART2_PIN_RX +# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_FREESCALE_UART2_PIN_TX +# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_FREESCALE_UART2_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_FREESCALE_UART2_PIN_CTS +#endif + +// ENET PINs + +// MDIO +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0) +// Both RMII and MII interface +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1 CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0 CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0 CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1 CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0) +// RMII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0) +// MII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3 CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2 CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2 CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3 CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0) +// IEEE 1588 timers +#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0) + +#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0) +#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0) +#endif + +// DSPI +// DSPI Pins + +#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) +#define KINETIS_PIN_SPI1_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define KINETIS_PIN_SPI1_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) +#define KINETIS_PIN_SPI1_0_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 18, 4, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 19, 4, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm new file mode 100644 index 0000000..d1e3c8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm @@ -0,0 +1,83 @@ +# Redboot minimal configuration +# Target: TWR-K70F120M +# Startup: ROM with external RAM + + +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "RedBoot Kinetis TWR-K70F120M" ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU { + user_value 1 +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH { + user_value ALL +}; + +cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { + user_value 1 +}; + +cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { +# user_value 1 +#}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -2 +}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT { + user_value 16 +}; + +#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { +# user_value 0x20000 +#}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + user_value ROM +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA { + user_value 1 +}; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c new file mode 100644 index 0000000..08500ef --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c @@ -0,0 +1,316 @@ +//========================================================================== +// +// twr_k70f120m_misc.c +// +// Cortex-M4 TWR-K60N512 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-02-25 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +#ifdef CYGHWR_HAL_DDR_SYNC_MODE +#define SYNC_ASYNC 0x3 +#else +#define SYNC_ASYNC 0 +#endif + +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +// DDRAM controller setup parameters +const cyg_uint32 kinetis_ddr_cfg[] = { + 0x00000400, // DDR_CR00 + 0x02000031, // DDR_CR02 + 0x02020506, // DDR_CR03 + 0x06090202, // DDR_CR04 + 0x02020302, // DDR_CR05 + 0x02904002, // DDR_CR06 + 0x01000303, // DDR_CR07 + 0x05030201, // DDR_CR08 + 0x020000c8, // DDR_CR09 + 0x03003207, // DDR_CR10 + 0x01000000, // DDR_CR11 + 0x04920031, // DDR_CR12 + 0x00000005, // DDR_CR13 + 0x00C80002, // DDR_CR14 + 0x00000032, // DDR_CR15 + 0x00000001, // DDR_CR16 + 0x00030300, // DDR_CR20 + 0x00040232, // DDR_CR21 + 0x00000000, // DDR_CR22 + 0x00040302, // DDR_CR23 + 0x0A010201, // DDR_CR25 + 0x0101FFFF, // DDR_CR26 + 0x01010101, // DDR_CR27 + 0x00000003, // DDR_CR28 + 0x00000000, // DDR_CR29 + 0x00000001, // DDR_CR30 + 0x02020101, // DDR_CR34 + 0x01010201, // DDR_CR36 + 0x00000200, // DDR_CR37 + 0x00200000, // DDR_CR38 + 0x01010020, // DDR_CR39 + 0x00002000 | SYNC_ASYNC, // DDR_CR40 + 0x01010020, // DDR_CR41 + 0x00002000 | SYNC_ASYNC, // DDR_CR42 + 0x01010020, // DDR_CR43 + 0x00000000 | SYNC_ASYNC, // DDR_CR44 + 0x03030303, // DDR_CR45 + 0x02006401, // DDR_CR46 + 0x01020202, // DDR_CR47 + 0x01010064, // DDR_CR48 + 0x00020101, // DDR_CR49 + 0x00000064, // DDR_CR50 + 0x02000602, // DDR_CR52 + 0x03c80000, // DDR_CR53 + 0x03c803c8, // DDR_CR54 + 0x03c803c8, // DDR_CR55 + 0x020303c8, // DDR_CR56 + 0x01010002 // DDR_CR57 +}; +#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if !defined(CYG_HAL_STARTUP_RAM) + cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P; + + hal_wdog_disable(); + hal_misc_init(); + + // if ACKISO is set you must clear ackiso before calling pll_init + // or pll init hangs waiting for OSC to initialize + if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M) + pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M; + + hal_start_clocks(); +# ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + HAL_CORTEXM_KINETIS_DDRMC_INIT( kinetis_ddr_cfg ); +# endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M; + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // System bus RAM partition +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#elif defined CYGMEM_REGION_sram_l + { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank +#endif +#ifdef CYGMEM_REGION_ramcod + { CYGMEM_REGION_ramcod, CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition +#endif +#ifdef CYGMEM_REGION_ramnc + { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM partition +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash [currently none] +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 } // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) && + ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#endif +#ifdef CYGMEM_REGION_sram_l +# define CASE_CODE 3 +# define CASE_RAMNC 4 + case 2: + *start = (unsigned char *)CYGMEM_REGION_sram_l; + *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE); + break; +#else +# define CASE_CODE 2 +# define CASE_RAMNC 3 +#endif + +#ifdef CYGMEM_REGION_ramcod + case CASE_CODE: + *start = (unsigned char *)CYGMEM_REGION_ramcod; + *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE); + break; +#endif + +#ifdef CYGMEM_REGION_ramnc + case CASE_RAMNC: + *start = (unsigned char *)CYGMEM_REGION_ramnc; + *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k70f120m_misc.c diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/var/current/ChangeLog new file mode 100644 index 0000000..1130967 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -0,0 +1,207 @@ +2014-02-13 Ilija Kocho <ilijak@siva.com.mk> + + * cortexm/kinetis/var/current/include/var_intr.h: + Add interrupt numbers for second eDMA controller. + + * cortexm/kinetis/var/current/include/var_io_clkgat.h: + Add clock gating for ADC2 + + * cortexm/kinetis/var/current/include/var_io_gpio.h: + Add GPIO port F. + +2013-04-28 Ilija Kocho <ilijak@siva.com.mk> + + * include/var_intr.h : Redefine CYGNUM_HAL_INTERRUPT_RTC_RTC because of + conflict with same named macro defined in hal_intr.h (Cortex-M architecture). + Define some interrrupt numbers, previously reservrd. + * include/var_io.h : Upgrade RTC registers. [ Bugzilla 1001904 ] + +2013-06-12 Mike Jones <mike@proclivis.com> + + * include/var_io_gpio.h + Clean up macros to support interrupts and set/get features. + +2013-04-28 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: + * cdl/kinetis_ddram.cdl: (New file) + * cdl/kinetis_fbram.cdl: (New file) + Add FlexBus RAM configuration and caching, DDRAM CDL moved + to a separate file. Updated FlexNVM configuration with 512KiB FlexNVM + and 16KiB FlexMemory. + * cdl/kinetis_clocking.cdl: CYGINT_HAL_CORTEXM_KINETIS_150 + moved to hal_cortexm_kinetis.cdl + * include/var_io_lmem.h, include/hal_cache.h: Add more cache functions. + [ Bugzilla 1001837 ] + +2013-04-09 Tomas Frydrych <tomas@sleepfive.com> + + * cdl/kinetis_irq_scheme.cdl: + * include/var_io_devs.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * include/var_io.h, include/var_io_clkgat.h, include/var_io_devs.h, + * src/hal_diag.c, src/kinetis_ddram.c, src/kinetis_misc.c + Add clock gating management and API. [ Bugzilla 1001814 ] + +2012-11-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: Changes to Kinetis part builder related to + addition of archhitectural hardware floating point support. + CYGHWR_HAL_CORTEXM_KINETIS_FPU and CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM + look and feel like other name building options. Added new Kinetis + members to part selection. + * include/var_io.h, src/kinetis_misc.c: Enumerated PORT F. + [Bugzilla 1001607] + +2012-11-04 Ilija Kocho <ilijak@siva.com.mk> + + * include/var_io.h: Define register access to FTFL module. + Contributed by Nicolas Aujoux at 2012-09-07 [Bugzilla 1001561] + +2012-09-28 Ilija Kocho <ilijak@siva.com.mk> + + * var/current/cdl/hal_cortexm_kinetis.cdl + * var/current/cdl/kinetis_clocking.cdl + * var/current/doc/kinetis.sgml + * var/current/include/hal_cache.h + * var/current/include/var_io_ddrmc.h + * var/current/include/var_io_lmem.h + * var/current/src/kinetis_ddram.c + * var/current/src/kinetis_misc.c: + Separate data and code caches, as well as text indentation suggested by Jifl. + Fixes to cache and SDRAM CDL and functions Improved SDRAM controller + support due to better manufacturer documentation: Configurable pad control. + [Bugzilla 1001606] + +2012-08-01 Ilija Kocho <ilijak@siva.com.mk> + + * include/var_io.h, src/kinetis_misc.c: Add functions and macros + for clock gating control to Kinetis. [Bugzilla 1001642] + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * include/hal_cache.h, src/kinetis_misc.c: Provide for cache + enablement in RAM startup mode [Bugzilla 1001606] + +2012-05-19 John Dallaway <john@dallaway.org.uk> + + * doc/kinetis.sgml: Close <para> and <refsect2> blocks. + * cdl/hal_cortexm_kinetis.cdl: Reference per-package documentation. + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * doc/kinetis_begin.sgml: + * doc/kinetis_end.sgml: + * doc/kinetis.sgml: + New files -- Kinetis variant documentation. [Bug 1001580] + +2012-05-17 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: + Bug fix: Do not refer external memory if Platform startup is + not selected. [ Bugzilla 1001590 ] + +2012-05-04 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: + * src/kinetis_clocking.cdl: + * src/kinetis_clocking.c: + * include/hal_cache.h + * include/var_io_lmem.h: + * include/var_io_ddrmc.h: + * include/var_io_devs.h: + * include/var_io.h: + * src/kinetis_ddram.c: + * src/kinetis_misc.c: + Add: Clocking support for PLL1 (K70), DDRAM controller + Cache, eDMA - 32 chan. [Bugzilla 1001579] + +2012-01-11 Tomas Frydrych <tomas@sleepfive.com> + + * include/var_io.h: + Allow for overriding of CYGHWR_HAL_KINETIS_SIM_SCGC?_ALL_M mask + from platform definitions. + + * include/var_io_devs.h: + Define base pointer for SLCD controller + +2012-01-05 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/kinetis_irq_scheme.cdl + Centralized IRQ priority scheme. + + * cdl/hal_cortexm_kinetis.cdl: + * cdl/kinetis_flexbus.cdl + * include/var_io_devs.h: + * include/var_io.h: + * src/kinetis_clocking.c: + * src/kinetis_misc.c: + Add I/O defs for eDMA, DSPI. Add flexbus control. + CYG_HAL_STARTUP parenthed bt CYG_HAL_STARTUP_ENV. + Early clock start [Bugzilla 1001450] + +2011-11-15 Tomas Frydrych <tomas@sleepfive.com> + + * include/var_io_gpio.h: + Convenience macros for manipulating GPIO pins. + +2011-10-19 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: + * cdl/kinetis_clocking.cdl: + * src/hal_diag.c: + * src/kinetis_misc.c: + * src/kinetis_clocking.c: + * include/hal_cache.h: + * include/hal_diag.h: + * include/plf_stub.h: + * include/variant.inc: + * include/var_arch.h: + * include/var_intr.h: + * include/var_io.h: + * include/var_io_devs.h: + * include/var_io_flexbus.h: + * include/pkgconf/mlt_kinetis_flash_sram2s_rom.h + * include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi + * include/pkgconf/mlt_kinetis_flash_sram2s_sram.h + * include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_rom.h + * include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_sram.h + * include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi + * include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h + * include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi + * include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h + * include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi + New package -- Freescale Kinetis variant HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl new file mode 100644 index 0000000..e8ee8f8 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl @@ -0,0 +1,867 @@ +##========================================================================== +## +## hal_cortexm_kinetis.cdl +## +## Cortex-M Freescale Kinetis variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2010-12-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS { + display "Freescale Kinetis Cortex-M4 Variant" + parent CYGPKG_HAL_CORTEXM + doc ref/hal-cortexm-kinetis-var.html + hardware + include_dir cyg/hal + define_header hal_cortexm_kinetis.h + description " + This package provides generic support for the Freescale Cortex-M4 + based Kinetis microcontroller family. + It is also necessary to select a variant and platform HAL package." + + compile hal_diag.c kinetis_misc.c kinetis_clocking.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + requires { CYGHWR_HAL_CORTEXM == "M4" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_kinetis.h>" + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS { + display "Kinetis part" + flavor data + calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM . + CYGHWR_HAL_CORTEXM_KINETIS_FPU . CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM . + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME } + description " + Kinetis family has several sub-families, with various peripheral + sets and CPU options. Each sub-family consists of several + members differing by sizes of on-chip FLASH and SRAM. This + control, enables the user to build Kinetis member part and so + tailor HAL for a specific microcontroller by selection of + microcontroller's properties such as microcontroller sub-family, + memory options, etc." + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM { + display "Sub-family" + flavor data + no_define + default_value { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT } + legal_values { 10 11 12 20 21 22 30 40 50 51 60 61 70 } + description " + Kinetis family consists of several sub-families differing by + features and CPU power." + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT { + display "Default sub-family" + flavor data + no_define + default_value { 60 } + legal_values { 10 11 12 20 21 22 30 40 50 51 60 61 70 } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FPU { + display "Floating Point Unit part name option" + flavor data + no_define + legal_values { "D" "F" } + default_value { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT } + description " + Select whether the part has Floating Point Unit. \"F\" - stands for + parts with FPU, while \"D\" for ones without. Note: + Selection of part with FPU does not imply that the FPU is used - + CYGHWR_HAL_CORTEXM_FPU activates the FPU." + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT { + display "Default FPU part name option" + flavor data + no_define + legal_values { "D" "F" } + default_value { "D" } + } + + cdl_option CYGIMP_HAL_CORTEXM_KINETIS_FPU { + display "FPU implemented" + no_define + calculated { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" } + active_if { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" } + implements CYGINT_HAL_FPV4_SP_D16 + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM { + display "FlexNVM name option" + flavor data + no_define + legal_values { "N" "X" } + default_value { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT } + description "Select whether the part has FlexNVM." + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT { + display "Default FlexNVM name option" + flavor data + no_define + legal_values { "N" "X" } + default_value { "N" } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME { + display "Flash name segment" + flavor data + no_define + legal_values { 32 64 96 128 256 512 "1M0" } + default_value { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT } + description " + Flash size is represented in part name encoded as KiB + (e.g. 512) or MiB (e.g. 1M0)." + + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT { + display "Default Flash name segment" + flavor data + no_define + legal_values { 32 64 96 128 256 512 "1M0" } + default_value { 512 } + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_REV { + display "Kinetis revision" + flavor data + legal_values { 1 2 } + default_value 1 + description " Revision" + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_150 { + display "Is a 150MHz device" + description " + 150Mhz and 120MHz devices have some properties different than 100MHz + devices of same types. This interface shall be implemented if the + device is 150Mhz or 120MHz." + } + } + + cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { + display "CPU exception priority level bits" + flavor data + default_value 4 + description " + This option defines the number of bits used to encode the + exception priority levels that this variant of the Cortex-M + CPU implements." + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING { + display "Clocking" + flavor data + no_define + calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG + description "Configure system clock and subsystem clocking." + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP { + display "System frequency clock setpoint" + flavor data + legal_values 32768 to 220000000 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP ? + CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP : 96000000 } + description "Desired system clock frequency" + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP { + display "Auxiliary clock frequency setpoint" + flavor data + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + legal_values 32768 to 220000000 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP ? + CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 } + description "Desired auxiliary clock frequency" + } + + script kinetis_clocking.cdl + } + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { + display "Clock interrupt ISR priority" + flavor data + calculated CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP + description "Set clock ISR priority. Default setting is lowest priority." + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR + description " + The period defined here is something of a fake, it is + expressed in terms of a notional 1MHz clock. The value + actually installed in the hardware is calculated from + the current settings of the clock generation hardware." + } + } + + cdl_option CYG_HAL_STARTUP_VAR { + display "By variant" + flavor data + parent CYG_HAL_STARTUP_ENV + default_value { (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ? + "ByPlatform" : "ROM" } + legal_values { "ROM" "SRAM" } + active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant")) + description " + 'ROM' startup builds a stand-alone application which will + be placed into flash. SRAM startup builds application + intended for loading in on-chip SRAM by means of JTAG/SWD. + Note: Variant Startup Type can be overriden/overloaded by + Platform Startup Type." + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type calculator" + flavor data + parent CYG_HAL_STARTUP_ENV + calculated { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ? + CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR} + no_define + define -file system.h CYG_HAL_STARTUP + description " + Startup type defines what type of application shall be built. + Startup type can be defined by variant (CYG_HAL_STARTUP_VAR) + or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF { + display "FlexNVM configuration" + flavor none + no_define + active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" } + requires { + CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <= + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE { + display "Enhanced EEPROM (EEE)" + flavor bool; + + cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE { + display "EEE Size \[Bytes\]" + flavor data + legal_values { 0 32 64 128 256 512 1024 2048 4096 + CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 8196 : 0 + CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 16384 : 0 + } + default_value CYGHWR_HAL_KINETIS_FLEXRAM_SIZE + } + + cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT { + display "EEE Split ratio" + flavor data + legal_values { 0 2 4 8 } + default_value 0 + description " + Enhanced EEPROM is split in two partitions that are + represented by separate sections in MLT files. + The split, CYGHWR_HAL_KINETIS_EEE_SPLIT, represents + partition size ratio where EEE0 partition size is + 1/CYGHWR_HAL_KINETIS_EEE_SPLIT of EEE size, and EEE1 + is the rest. As a special arrangement + (CYGHWR_HAL_KINETIS_EEE_SPLIT == 0) is a PHONY, where + split equals 2 but in MLT files whole EEE is counted + as a single section." + + cdl_option CYGHWR_HAL_KINETIS_EEE0_SIZE { + display "e_eeprom0 section size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 ? + CYGHWR_HAL_KINETIS_EEE_SIZE / + CYGHWR_HAL_KINETIS_EEE_SPLIT : + CYGHWR_HAL_KINETIS_EEE_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_EEE1_SIZE { + display "e_eeprom1 section size \[Bytes\]" + flavor data + active_if { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 } + calculated { CYGHWR_HAL_KINETIS_EEE_SIZE - + CYGHWR_HAL_KINETIS_EEE0_SIZE } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB { + display "FlexNVM partition used for EEE \[KiB\]" + flavor data + calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512 ? + CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB : + CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB { + display "FlexNVM partition used for EEE \[KiB\]" + flavor data + active_if CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 256 + default_value 32 + legal_values { 32 64 128 192 224 256 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB { + display "FlexNVM partition used for EEE \[KiB\]" + flavor data + active_if CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512 + default_value 64 + legal_values { 64 128 256 384 448 512 } + } + } + } + + cdl_component CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE { + display "FlexNVM D Flash" + flavor data + active_if { CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB < + CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB} + calculated { + 1024 * ( CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB - + CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB) + } + } + + cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_RAM { + display "Flexram ordinary RAM" + flavor data + active_if { !CYGHWR_HAL_CORTEXM_KINETIS_EEE } + calculated CYGHWR_HAL_KINETIS_FLEXRAM_SIZE + } + + cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_SIZE { + display "Flexram size" + flavor data + legal_values { 4096 16384 } + default_value CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 ? 16384 : 4096 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB { + display "FlexNVM size \[KiB\]" + flavor data + calculated CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + parent CYG_HAL_STARTUP_ENV + calculated { + (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF : + (CYG_HAL_STARTUP == "ROM" ) ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_rom" : + (CYG_HAL_STARTUP == "SRAM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_sram" : + "undefined" } + description " + Combination of 'Startup type' and 'Kinetis part' + produces the memory layout." + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED { + display "Unified on chip SRAM region" + flavor bool + default_value { 1 } + description " + Kinetis have two equal SRAM banks SRAM_L and SRAM_U that + occupy consecutive memory blocks with \(possibility for + simultaneous\) access from on separate buses. + SRAM_L is placed below 0x20000000 and SRAM_U above 0x20000000. + This option provides for selection between memory layout with + single (unified) (S)RAM region and layout with two separate + (S)RAM regions." + } + + cdl_option CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION { + display "Utilize \".kinetis_misc\" section for HAL" + flavor bool + default_value { CYG_HAL_STARTUP == "ROM" } + active_if { CYG_HAL_STARTUP == "ROM" } + description " + Kinetis use FLASH locations between 0x400 and 0x40F for FLASH + security configuration. This leaves FLASH area below 0x400 + out of standard linker sections. Special section + \".kinetis_misc\" provides linker access to this area. + Setting this option instructs linker to place some HAL + (variant/platform) \"misc.\" functions in this area." + } + + cdl_option CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION { + display "HAL diag. in \".kinetis_misc\" section" + flavor bool + active_if CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION + default_value 0 + description " + By default only misc. HAL functions are stored in + \".kinetis_misc\" section. In addition HAL diagnostc + functions may be placed as well." + } + + cdl_component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES { + display "On chip memory resources" + flavor none + no_define + description " + View and manage on-chip memory resources. + Output is used for naming of 'mlt' files." + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB { + display "On chip Flash option \[KiB\]" + flavor data + calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0") + ? 1024 : CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB { + display "Kinetis on chip SRAM size \[KiB\]" + flavor data + calculated { + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 1024 || + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 512) ? 128 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 256) ? 64 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 128) ? 32 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 96 || + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 64) ? 16 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 32) ? 8 : + "Unknown" + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT { + display "SRAM layout" + flavor data + no_define + calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? + "unisram" : + "sram2s" + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT { + display "On-chip memory layout" + flavor data + no_define + calculated {(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" ? "flexnvm_": "flash_") + . CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT } + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_SIZE { + display "Kinetis on chip FLASH size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB * 0x400 } + } + + cdl_option CYGHWR_HAL_KINETIS_SRAM_SIZE { + display "Kinetis on chip SRAM size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB * 0x400 } + } + + cdl_option CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE { + display "Kinetis onchip RAM bank size" + flavor data + calculated { CYGHWR_HAL_KINETIS_SRAM_SIZE/2 } + } + + cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE { + display "Kinetis on chip FlexNVM FLASH size" + flavor data + active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" } + calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB + - CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 } + } + + cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE { + display "Kinetis on chip FlexRAM size" + flavor data + active_if { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X") && + !CYGHWR_HAL_CORTEXM_KINETIS_EEE } + calculated { CYGHWR_HAL_KINETIS_FLEXRAM_SIZE } + } + } + + cdl_interface CYGINT_HAL_CACHE { + display "Platform has cache" + flavor bool + } + + cdl_interface CYGINT_HAL_HAS_NONCACHED { + display "Platform has non-cached regions" + flavor bool + } + + cdl_component CYGPKG_HAL_KINETIS_CACHE { + display "Cache memory" + flavor bool + + default_value CYGINT_HAL_CACHE + active_if (CYGINT_HAL_CACHE) + } + + cdl_component CYGHWR_HAL_NONCACHED { + display "Non cached RAM memory regions" + flavor booldata + active_if CYGINT_HAL_HAS_NONCACHED + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + description " + Non cached memory sections may be usful for storage that + is unsuitable for caching, such as sharing buffers between + the CPU and other bus masters such as DMA, ENET, etc. + The \".sram\" section is located in the internal SRAM, + which is is always present and never cached. + Additionaly, as an option, a partition of external memory: + DDRAM or FlexRAM, if one is present, can be configured + non-cached and accommodate \".noncache\" section." + + cdl_option CYGHWR_HAL_ENET_TCD_SECTION { + display "Ethernet buffer descriptor memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".sram\"" } + + description "Ethernet is a bus master so buffers/buffer + descriptos must reside in non-cached memory" + } + + cdl_option CYGHWR_HAL_ENET_BUF_SECTION { + display "Ethernet buffer memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + description "Ethernet is a bus master so buffers/buffer + descriptos must reside in non-cached memory" + } + + cdl_option CYGHWR_HAL_EDMA_TCD_SECTION { + display "eDMA transfer control descriptor memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".sram\"" } + + description "eDMA is a bus master so buffers/buffer + descriptos must reside in non-cached memory" + } + + cdl_option CYGHWR_HAL_EDMA_BUF_SECTION { + display "eDMA buffer memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + description "eDMA is a bus master so buffers/buffer + descriptos must reside in non-cached memory" + } + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_DDRAM { + display "Platform uses DDRAM" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides DDRAM and if DDRAM is + used on target hardware" + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC { + display "DDRAM" + flavor bool + active_if CYGINT_HAL_CORTEXM_KINETIS_DDRAM + default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM + description "DDRAM on Kinetis is mirrored at several address ranges. + Each mirror has its own caching options that may include: + non-cached, write-through and write-back. + By eCos configuration, DDRAM is split in 3 partitions: + Cached, Non-cached and Code. + Cached partition is intended for general purpose main memory. + Non-cached partition is convenient for sharing + buffers with other bus masters such as Ethernet controller, + DMA, etc. Code partition is for executable code." + + requires CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + compile kinetis_ddram.c + + script kinetis_ddram.cdl + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FBRAM { + display "Platform uses FlexBus RAM" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides FlexBus and if FlexBus is + used on target hardware" + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM { + display "FlexBus RAM" + flavor bool + active_if CYGINT_HAL_CORTEXM_KINETIS_FBRAM + default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM + requires CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS + description "FBRAM on Kinetis is mirrored at several address ranges. + Each mirror has its own caching options that may include: + non-cached, write-through and write-back. + By eCos configuration, FlexBus RAM is split in 3 partitions: + Cached, Non-cached and Code. + Cached partition is intended for general purpose main memory. + Non-cached partition is convenient for sharing + buffers with other bus masters such as Ethernet controller, + DMA, etc. Code partition is for executable code." + + script kinetis_fbram.cdl + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS { + display "Platform uses FlexBus" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides FlexBus and if FlexBus is + used on target hardware" + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS { + display "FlexBus" + flavor bool + active_if CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + description "FlexBus provides access for external memory." + + script kinetis_flexbus.cdl + } + + cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF { + display "Flash configuration field" + flavor none + no_define + + active_if { CYG_HAL_STARTUP == "ROM" } + + description " + The program flash memory contains a 16-byte flash + configuration field that stores default protection settings + (loaded on reset) and security information that allows the MCU to + restrict access to the flash module. + Note: Changing some values in Flash configuration field may make + flash inaccessible and disable further re-programming of the flash + permanently. Consult respective Kinetis' documentation before dealing + with the Flash configuration field. Default values are equal + to the factory values." + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY { + display "Backdoor comparison key" + flavor data + default_value { "\{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff \}" } + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT { + display "Program flash protection" + flavor data + default_value { "\{ 0xff, 0xff, 0xff, 0xff \}" } + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC { + display "Flash security byte" + flavor data + default_value 0xfe + + description " + Note: FSEC default value is deliberately set to + 0xfe in order to disable chip lockout." + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT { + display "Flash nonvolatile option byte" + flavor data + default_value 0xff + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT { + display "Data flash protection byte" + flavor data + default_value 0xff + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT { + display "EEPROM protection byte" + flavor data + default_value 0xff + } + } + + cdl_option CYGNUM_HAL_KINETIS_MEM_SEGMENTS { + display "RAM memory segments" + flavor data + no_define + active_if is_active(CYGBLD_REDBOOT_MAX_MEM_SEGMENTS) + requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS >= CYGNUM_HAL_KINETIS_MEM_SEGMENTS } + + calculated { + ((CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? 1 : 2) + + (CYGPKG_HAL_CORTEXM_KINETIS_DDRMC ? 2 : 0) + + (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE ? 1 : 0) + + (CYGPKG_HAL_CORTEXM_KINETIS_FBRAM ? 2 : 0) + + (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE ? 1 : 0)) + } + } + + for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { + + cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] { + display "Platform provides UART [set ::channel] HAL" + flavor bool + description " + This interface will be implemented if the specific + controller being used has on-chip UART [set ::channel], + and if that UART is accessible on the target hardware." + } + + cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS { + display "Platform provides HAL for UART[set ::channel] hardware flow control." + flavor bool + description " + This interface will be implemented if the specific + on-chip UART [set ::channel] has RTS/CTS flow control + that is accessible on the target hardware." + } + } + + cdl_interface CYGINT_HAL_DMA { + display "Platform uses DMA" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides DMA and if DMA is + used on target hardware" + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR { + display "Variant IRQ priority defaults" + no_define + flavor none + parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME + description " + Interrupt priorities defined by Kinetis variant" + script kinetis_irq_scheme.cdl + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS { + display "Build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package." + + cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Kinetis variant HAL package. These flags + are used in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Kinetis variant HAL package. These flags + are removed from the set of global flags if present." + } + } +} + +# EOF hal_cortexm_kinetis.cdl diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl new file mode 100644 index 0000000..0d785d1 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl @@ -0,0 +1,978 @@ +##========================================================================== +## +## kinetis_clocking.cdl +## +## Cortex-M Freescale Kinetis Clocking +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-10-19 +## +######DESCRIPTIONEND#### +## +##========================================================================== + + +# cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING +# display "Clocking" + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ { + display "System frequency actual value" + flavor data + calculated { + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC ? + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC : + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC ? + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC : + (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL || + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1) ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV: + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV : + 0 + } + description "Operating system clock frequency." + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG { + display "MCG" + flavor data + no_define + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK . " " . + ((CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ+500000)/1000000) . "MHz, " . ( + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") ? + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS : + CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC) + + } + description "Multipurpose Clock Generator" + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK { + display "System clock source" + flavor data + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 ? "PLL1" : "PLL" } + legal_values { + "PLL" "FLL" "EXT_REFCLK" ( CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 ? "PLL1" : "PLL" ) + } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" implies + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 1 + } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" implies + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 + } + description " + Select one of 3 options for MCG output clock: + PLL or FLL oscillator or External reference clock." + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT { + display "EXT_REFCLK source clock settings" + flavor none + no_define + active_if { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK") || + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") + } + description "Set External Reference Clock frequency and type." + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT0 { + display "External freq ref 0" + flavor data + no_define + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS . " " . + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ + } + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS { + display "Clock type" + flavor data + default_value { "OSC" } + legal_values { "OSC" "XTAL" "RTC"} + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000) + } + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies + (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) || + ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000))) + } + + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768) + } + + description " + Ext reference can be External oscillator or a crystal + for the on-chip oscillator or Real Time Clock." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ { + display "Clock frequency" + flavor data + legal_values 0 to 50000000 + default_value { + is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ? + CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ : + 4000000 + } + description "External oscillator or crystal reference in Hz." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP { + display "XTAL parallel C \[pF\]" + flavor data + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 } + default_value 0 + description " + The oscillator has 4 on-chip capacitors that combined + produce capacitance in parallel to the crystal." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1 { + display "External freq ref 1" + flavor data + no_define + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS . " " . + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ + } + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS { + display "Clock type" + flavor data + default_value { "OSC" } + legal_values { "OSC" "XTAL" } + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC") implies + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 50000000) + } + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL") implies + (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 3000000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 32000000)) || + ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 32000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 40000))) + } + + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 0) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 0) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ == 32768) + } + + description " + Ext reference can be External oscillator or a crystal + for the on-chip oscillator or Real Time Clock." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ { + display "Clock frequency" + flavor data + legal_values 0 to 50000000 + default_value { + is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ) ? + CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ : + 4000000 + } + description "External oscillator or crystal reference in Hz." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP { + display "XTAL parallel C \[pF\]" + flavor data + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 } + default_value 0 + description " + The oscillator has 4 on-chip capacitors that combined + produce capacitance in parallel to the crystal." + } + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL { + display "FLL / PLL configuration" + flavor none + no_define + description " + PLL / FLL parameters are being calculated on a + base of required system frequrncy and output as well as + reference oscillator/frequency settings." + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP { + display "PLL/FLL output frequency set point" + flavor data + legal_values 32768 to 220000000 + calculated { + ((CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL") || + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")) ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP : + CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP + } + description "Desired PLL output frequency." + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC { + display "Reference clock source for FLL or PLL" + flavor data + default_value { "EXT_REFCLK" } + + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "INT_RC_32KHZ") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + + legal_values { "INT_RC_32KHZ" "EXT_REFCLK" "EXT_REFCLK1" } + description " + PLL/FLL oscillators can use one of external reference + clock references as well as Low (32768 Hz) or High (2MHz) + Frequency Internal oscillator" + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_PLL1_REFSRC { + display "Reference clock source for PLL1" + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + flavor data + default_value { "EXT_REFCLK" } + + legal_values { "EXT_REFCLK" "EXT_REFCLK1" } + description " + PLL1 oscillator can use one of 2 external reference clock + references." + } + + cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ { + display "Reference frequency." + flavor data + calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ? + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ : + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC + == "INT_RC_32KHZ" ? 32768 : 2000000 ) + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL { + display "FLL oscillator" + flavor none + no_define + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE { + display "Reference frequency range" + flavor data + legal_values 0 1 2 + calculated { + CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ > 8000000 ? 2 : + CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 1000000 ? 1 : + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 32000) && + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ <= 40000)) ? 0 : + -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV { + display "Calculated FLL divider" + flavor data + calculated { + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE >= 1 ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+32768*16) / (32768*32)) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+16384) / 32768) : -1) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG { + display "FLL divider register value" + flavor data + legal_values 0 1 2 3 4 5 6 7 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) <= 5 ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : 5 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS { + display "DCO Range Select" + flavor data + legal_values 0 1 2 3 + default_value { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 80000000 ? 3 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 60000000 ? 2 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 40000000 ? 1 : 0 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 { + display "DCO max. frequency with 32768 reference" + flavor data + legal_values { 0 0x80 } + default_value { + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) || + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) || + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) || + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 9600000)) ? + 0x80 : 0x00 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT { + display "FLL factor" + flavor data + calculated { + (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 == 0x80) ? + ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ? 732 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1464 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 2197 : 2929 ) : + ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ? 640 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1280 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 1920 : 2560 ) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN { + display "DCO input frequency" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG == 0 ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 1 : 32 ) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG * + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 2 : 64))) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN_CHECK { + display "DCO input frequency check" + flavor data + no_define + legal_values { "OK" "NOK" "not applicable" } + calculated { + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) && + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) ? + "OK" : "NOK" ) : + "NotApplicable" + } + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" } + requires { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) && + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV { + display "FLL output frequency actual value" + flavor data + calculated {CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN * + CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT } + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL { + display "PLL oscillator" + flavor bool + default_value 1 +# { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? 0 : 1 } +# active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || +# CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" +# } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL { + display "100 Mhz line" + flavor none + no_define + active_if !CYGINT_HAL_CORTEXM_KINETIS_150 + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + calculated { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ? + 3800000 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ? + 3000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 : + 300000 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV { + display "PLL External Reference Divider" + flavor data + legal_values 1 to 25 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 2000000 to 4000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV { + display "VCO Divider" + flavor data + legal_values 24 to 55 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV { + display "PLL output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV) : -1 + } + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL { + display "150 Mhz line" + flavor none + no_define + active_if CYGINT_HAL_CORTEXM_KINETIS_150 + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + default_value { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ == 50000000) ? + (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 30000000) ? 30000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4000000) ? 4000000 : + 5000000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL { + display "PLL0 Reference Oscillator select" + flavor data + default_value 0 + legal_values 0 1 + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV { + display "PLL External Reference Divider" + flavor data + legal_values 1 to 8 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV { + display "VCO Divider" + flavor data + legal_values 16 to 47 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ) * 2) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV { + display "PLL output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) / 2) : -1 + } + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV { + display "PLL External Reference Divider" + flavor data + calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ? + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV : + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV { + display "PLL External Reference Divider" + flavor data + calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ? + (CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) : + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV { + display "PLL output frequency actual value" + flavor data + calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ? + CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV : + CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV + } + } + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC { + display "Internal Reference Clock" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI ? 2000000 : 32768 } + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "INT_REFCLK" } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI { + display "Use highh frequency internal osc." + flavor bool + default_value 1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC { + display "External Reference Clock" + flavor data + calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_DIST { + display "Subsystem clocking" + flavor none + no_define + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS { + display "Peripheral bus" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX { + display "Frequency limit" + flavor data + default_value 50000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP { + display "Calculated value" + flavor data + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <= + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ : + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX + } + legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS { + display "Divider" + flavor data + legal_values 1 to 16 + + default_value { !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP + 1) + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH { + display "Flash" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX { + display "Frequency limit" + flavor data + default_value 25000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP { + display "Calculated value" + flavor data + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <= + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ : + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX + } + legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH { + display "Divider" + flavor data + legal_values 1 to 16 + + default_value { + !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP + 1) + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS { + display "Flex bus" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX { + display "Frequency limit" + flavor data + default_value 50000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP { + display "Calculated value" + flavor data + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <= + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ : + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX + } + legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS { + display "Divider" + flavor data + legal_values 1 to 16 + + default_value { + !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP + 1) + } + } + } + + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB { + display "USB clock" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC / + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX { + display "Frequency limit" + flavor data + default_value 48000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC { + display "Fractional Divider" + flavor data + legal_values 1 to 2 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ < + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX ? 1 : + ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN) > + (CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP * 4) ? 1 : + (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP ? 2 : 1)) + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV { + display "Divider" + flavor data + legal_values 1 to 8 + default_value { !((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC) % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) : + ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) +1) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN { + display "USB divider input frequency" + flavor data + calculated { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP { + display "Desired" + flavor data + calculated 48000000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK { + display "Trace clock source" + flavor data + default_value { "CORE" } + legal_values { "CORE" "MCGOUT" } + + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT { + display "Enable Trace Clock out" + flavor bool + default_value 0 + } + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC { + display "System uses Real Time Clock" + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC { + display "Real Time Clock" + flavor bool + default_value CYGINT_HAL_CORTEXM_KINETIS_RTC + + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP { + display "RTC XTAL parallel C \[pF\]" + flavor data + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 + 30 32 } + default_value 0 + description " + The Real Time Clock oscillator has 4 capacitors that + combined produce capacitance in parallel to the crystal." + } + } + + # PLL1 and OSC1 Configuration + # PLL1 + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 { + display "MCG Has PLL1" + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 { + display "MCG Has OSC1" + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 { + display "PLL1 oscillator" + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL + flavor bool + default_value CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP { + display "PLL1 output frequency set point" + flavor data + legal_values 32768 to 220000000 + calculated { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1") ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP : + CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP + } + description "Desired PLL1 output frequency." + } + + cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ { + display "Reference frequency." + flavor data + calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ? + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ : + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC + == "INT_RC_32KHZ" ? 32768 : 2000000 ) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + default_value { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ == 50000000) ? + (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 30000000) ? 30000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 4000000) ? 4000000 : + 5000000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL { + display "PLL10 Reference Oscillator select" + flavor data + default_value 0 + legal_values 0 1 + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV { + display "PLL1 External Reference Divider" + flavor data + legal_values 1 to 8 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV { + display "VCO Divider" + flavor data + legal_values 16 to 47 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ) * 2) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV { + display "PLL1 output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV) / 2) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV { + display "PLL1 External Reference Divider" + flavor data + calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV { + display "PLL1 External Reference Divider" + flavor data + calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV { + display "PLL1 output frequency actual value" + flavor data + calculated CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV { + display "Frequency of selected PLL" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL + calculated {CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV : + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV + } + } + + # EOF kinetis_clocking.cdl diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl new file mode 100644 index 0000000..55cdf99 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl @@ -0,0 +1,259 @@ +##========================================================================== +## +## kinetis_ddram.cdl +## +## Cortex-M Freescale Kinetis DDRAM configuration +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2013-04-28 +## +######DESCRIPTIONEND#### +## +##========================================================================== + + +# cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC { +# display "DDRAM" +# flavor bool +# active_if CYGINT_HAL_CORTEXM_KINETIS_DDRAM +# default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM +# description "DDRAM on Kinetis is mirrored at several address ranges. +# Each mirror has its own caching options that may include: +# non-cached, write-through and write-back. +# By eCos configuration, DDRAM is split in 3 partitions: +# Cached, Non-cached and Code. +# Cached partition is intended for general purpose main memory. +# Non-cached partition is convenient for sharing +# buffers with other bus masters such as Ethernet controller, +# DMA, etc. Code partition is for executable code." +# +# requires CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 +# compile kinetis_ddram.c + + cdl_component CYGHWR_HAL_KINETIS_DDR_SIZE_MIB { + display "DDRAM size \[MiB\]" + flavor data + default_value 128 + + cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE { + display "DDRAM size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 } + } + } + + cdl_component CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB { + display "Non-cached DDRAM data partition \[MiB\]" + requires { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <= + CYGHWR_HAL_KINETIS_DDR_SIZE_MIB } + flavor data + + implements CYGINT_HAL_HAS_NONCACHED + + legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) } + + default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4 + + description " + Non-cached DDRAM partition, intended for sharing + buffers with other bus masters such as Ethernet controller, + DMA, etc." + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE { + display "Non-cached DDRAM size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB + * (1024 * 1024) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE { + display "Non-cached DDRAM base address" + flavor data + + calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR + + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR { + display "Non-cached DDRAM mirror base" + flavor data + no_define + calculated { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR == 0x70000000 ? + 0x80000000 : 0x70000000 } + } + } + + cdl_component CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB { + display "DDRAM code partition \[MiB\]" + requires { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB <= + CYGHWR_HAL_KINETIS_DDR_SIZE_MIB } + flavor data + + legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) } + + default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4 + + description " + DDRAM code partition - for use as program memory. + On systems with cache this partition is cached in PC cache. + Caching is always write-through" + + cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_SIZE { + display "DDRAM code partition size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB + * (1024 * 1024) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_BASE { + display "DDRAM code partition base address" + flavor data + + calculated { 0x08000000 } + } + } + + cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB { + display "Cached DDRAM data partition \[MiB\]" + flavor data + requires { CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB >= 8 } + calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - + CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB - + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB } + + description " + Cached DDRAM data partition - for general use as main data memory. + On systems with cache this partition is cached in PS cache. + Caching can be either copy-back or write-through and is determined by + general cache mode setting." + + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE { + display "Cached DDRAM size \[Bytes\]" + flavor data + calculated { (CYGHWR_HAL_KINETIS_DDR_SIZE - + CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE - + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_BASE { + display "Cached DDRAM base address" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR + + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE { + display "DDRAM cache type" + flavor data + calculated CYGSEM_HAL_DCACHE_STARTUP_MODE + description "DDRAM cache type is determined by general cache setting" + } + + cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR { + display "Cached DDRAM mirror base" + flavor data + no_define + legal_values { 0x70000000 0x80000000 } + default_value { 0x70000000 } + description " + According to Kinetis Reference Manual rev. 2, the DDRAM mirror + mapped at 0x80000000 (supporting write-thru caching only) + is not accesible by ENET, SDH and some other bus masters, + and that the mirror at 0x70000000 (supporting copy-back caching) + is accessible by them. + The practical tests prove that it is the opposite, actually as + it should be. + Until this discrepancy is resolved, this option selects the + default (non)cached mirror and provides the user with possibilty for + manual override. + Note: The behavior may change in future." + } + } + + cdl_option CYGHWR_HAL_DDR_SYNC_MODE { + display "Use synchronous mode" + flavor bool + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" } + default_value { 1 } + } + + cdl_option CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS { + display "DDRAM bus configuration" + flavor data + legal_values 0 1 2 3 6 + default_value 6 + description " + DDRAM configuration: 0 - LPDDR Half Strength, + 1 - LPDDR Full Strength, 2 - DDR2 Half Strength, + 3 - DDR1, 6 - DDR2 Full Strength" + } + + cdl_component CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL { + display "Pad control" + flavor data + + calculated { + (CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT << 24) | + CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL | + 0x00000200 + } + + cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT { + display "On Die Termination" + flavor data + legal_values { 0 1 2 3 } + default_value 1 + + description "On Die Termination \[Ohm\]: 0 - Off, 1 - 75, + 2 - 150, 3 - 50" + } + + cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL { + display "Delay chains in spare logic" + flavor data + legal_values { 0 1 2 3 } + default_value 3 + + description "Delay chains in spare logic: 0 - No buffer, 1 - 4 buffers, + 2 - 7 buffers, 11 - 10 buffers" + } + } +# } + +# EOF kinetis_ddram.cdl diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl new file mode 100644 index 0000000..ea97ad8 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl @@ -0,0 +1,205 @@ +##========================================================================== +## +## kinetis_fbram.cdl +## +## Cortex-M Freescale Kinetis FBRAM configuration +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2013-04-28 +## +######DESCRIPTIONEND#### +## +##========================================================================== + + +# cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM { +# display "FlexBus RAM" +# flavor bool +# active_if CYGINT_HAL_CORTEXM_KINETIS_DBRAM +# default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM +# description "FlexBus RAM on Kinetis is mirrored at several address ranges. +# Each mirror has its own caching options that may include: +# non-cached, write-through and write-back. +# By eCos configuration, FlexBus RAM is split in 3 partitions: +# Cached, Non-cached and Code. +# Cached partition is intended for general purpose main memory. +# Non-cached partition is convenient for sharing +# buffers with other bus masters such as Ethernet controller, +# DMA, etc. Code partition is for executable code." +# + + cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE { + display "FlexBus RAM size \[Bytes\]" + flavor data + default_value CYGHWR_HAL_KINETIS_FB_CS0_SIZE ? CYGHWR_HAL_KINETIS_FB_CS0_SIZE * 1 : 0 + } + + cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE_KIB { + display "FlexBus RAM size \[KiB\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_FBR_SIZE / 1024 } + } + + cdl_component CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB { + display "Non-cached FlexBus data RAM partition \[KiB\]" + requires { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB <= + CYGHWR_HAL_KINETIS_FBR_SIZE_KIB } + flavor data + + implements CYGINT_HAL_HAS_NONCACHED + + legal_values { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) } + + default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 } + + description " + Non-cached FlexBus RAM partition, intended for sharing + buffers with other bus masters such as Ethernet controller, + DMA, etc." + + cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE { + display "Non-cached FlexBus RAM size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB + * 1024 * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE { + display "Non-cached FlexBus RAM base address" + flavor data + + calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR + + CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + + CYGHWR_HAL_KINETIS_FBR_CODE_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR { + display "Non-cached FlexBus RAM mirror base" + flavor data + no_define + legal_values { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 } + default_value { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : + 0x60000000 } + } + + } + + cdl_component CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB { + display "FlexBus RAM code partition \[KiB\]" + requires { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB <= + CYGHWR_HAL_KINETIS_FBR_SIZE_KIB } + flavor data + + legal_values { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) } + + default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 } + + description " + FlexBus RAM code partition - for use as program memory. + On systems with cache this partition is cached in PC cache + and is always write-through" + + cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_SIZE { + display "FlexBus RAM code partition size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB + * 1024 * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_BASE { + display "FlexBus RAM code partition base address" + flavor data + + legal_values { 0x60000000 + CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 : + 0x60000000 } + default_value { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 : + 0x60000000 } + } + } + + cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB { + display "Cached FlexBus RAM data partition \[KiB\]" + flavor data + requires { CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB >= 64 } + calculated { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - + CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB - + CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB } + + description " + Cached FlexBus RAM data partition - for general use as main data memory. + On systems with cache this partition is cached in PS cache. + Caching can be either copy-back or write-through and is determined + by general cache mode setting." + + cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE { + display "Cached FlexBus RAM size \[Bytes\]" + flavor data + calculated { (CYGHWR_HAL_KINETIS_FBR_SIZE - + CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE - + CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_BASE { + display "Cached FlexBus RAM base address" + flavor data + calculated { CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR + + CYGHWR_HAL_KINETIS_FBR_CODE_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_FBR_CACHE_TYPE { + display "FlexBus RAM cache type" + flavor data + calculated CYGSEM_HAL_DCACHE_STARTUP_MODE + description "FlexBus RAM cache type is determined by general + cache setting" + } + + cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR { + display "Cached FlexBus RAM mirror base" + flavor data + no_define + legal_values { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 } + default_value { 0x60000000 } + description "Cached DDRAM base " + } + } + +# } + +# EOF kinetis_fbram.cdl diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl new file mode 100644 index 0000000..96c49a4 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl @@ -0,0 +1,84 @@ +##========================================================================== +## +## kinetis_flexbus.cdl +## +## Cortex-M Freescale Kinetis FlexBus +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-12-11 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +# cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS { +# display "FlexBus" + +for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } { + + cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] { + display "Platform uses Chip select [set ::chipsel]" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides chip select [set ::chipsel], and if + that chip select is used on target hardware." + } + + cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] { + display "Chip select [set ::chipsel]" + flavor bool + active_if CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] + default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] + description " + This option includes initialization data for + chip select [set ::chipsel]." + + cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS { + display "Port size (encoded)" + flavor data + calculated ( \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8 ? 1 : \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3) + } + } +} + + +# EOF kinetis_flexbus.cdl diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl new file mode 100644 index 0000000..bfc3c04 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl @@ -0,0 +1,202 @@ +##========================================================================== +## +## kinetis_irq_scheme.cdl +## +## Cortex-M Freescale Kinetis IRQ configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2010-12-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + + +# cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR { +# display "Variant IRQ priority defaults" +# no_define +# flavor none +# parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME +# description " +# Interrupt priorities defined by Kinetis variant" + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP { + display "Clock IRQ priority" + flavor data + no_define + default_value 0xE0 + description "Set clock ISR priority. Default setting is lowest priority." + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + + } + + cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_INTPRIO_SP { + display "Ethernet IRQ priority" + flavor data + no_define + active_if CYGPKG_DEVS_ETH_FREESCALE_ENET + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0xE0 + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART { + display "UART IRQ priorities" + flavor none + no_define + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP { + display "UART0 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART0 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP { + display "UART1 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART1 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP { + display "UART2 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART2 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP { + display "UART3 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART3 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP { + display "UART4 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART4 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP { + display "UART5 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART5 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_DSPI { + display "DSPI IRQ priorities" + flavor none + no_define + + cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI_SP { + display "DSPI bus 0 interrupt priority" + flavor data + no_define + active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI0 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0xD0 + } + + cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI_SP { + display "DSPI bus 1 interrupt priority" + flavor data + no_define + active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI1 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0xD0 + } + + cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI_SP { + display "DSPI bus 2 interrupt priority" + flavor data + no_define + active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI2 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0xD0 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C { + display "I2C interrupt priorities" + flavor none + no_define + + for { set ::bus 0 } { $::bus < 2 } { incr ::bus } { + + cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_IRQ_PRIORITY { + display "I2C bus [set ::bus] interrupt priority" + flavor data + active_if CYGHWR_DEVS_FREESCALE_I2C[set ::bus] + default_value 0x90 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + } + } + } + +# } + + +# EOF kinetis_irq_scheme.cdl diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml new file mode 100644 index 0000000..9afa24e --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml @@ -0,0 +1,308 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- kinetis.sgml --> +<!-- --> +<!-- KINETIS documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!-- <part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title> --> + +<refentry id="hal-cortexm-kinetis-var"> + <refmeta> + <refentrytitle>Freescale Kinetis Variant</refentrytitle> + </refmeta> + <refnamediv> + <refname><literal>CYGPKG_HAL_CORTEXM_KINETIS</literal></refname> + <refpurpose>eCos Support for Freescale Kinetis Micro-controllers</refpurpose> + </refnamediv> + + <refsect1 id="hal-cortexm-kinetis-var-description"><title>Description</title> + <para> + Kinetis is a Freescale microcontroller family based on the ARM Cortex-M4 core. The + family consists of subfamilies: K10, K20, K30, K40, K50, K60 and K70 + that gradually add-on performance and features. + </para> + <para> + The Kinetis variant HAL provides generic support for hardware found on some + or all Kinetis members. The variant package <literal>CYGPKG_HAL_CORTEXM_KINETIS</literal> + provides configurable components that aim to support the complete set of options + found in the Kinetis family. + </para> + </refsect1> + <refsect1 id="kinetis-var-sup"><title>What's supported</title> + <para> + The current Kinetis software includes a Kinetis variant HAL, some Platform BSPs, + as well as DMA, UART, Wallclock, Ethernet and SPI support. + </para> + </refsect1> + <refsect1 id="kinetis-var-config"><title>Configuration</title> + <para> Kinetis is a set of families of micro-controllers packed with highly configurable components. + In order to facilitate system configuration for the user, the CDL configuration items are organized as a set of + expert components. Typically, for a given peripheral, the user chooses the required hardware + options and desirable parameters, and the respective CDL configuration options and settings are calculated from these. + If it is not possible to achieve exact values, the configurator attempts to provide + approximate settings, then the user can manually do the fine tuning.</para> + <refsect2 id="kinetis-var-cpu-select"><title>Kinetis Part Selection</title> + <para> + Within a family and/or across families the chips are further differentiated by their features + such as: optional FPU, amount of memory, etc. The family member options are reflected in the + controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)). + The Kinetis part builder <literal>CYGHWR_HAL_CORTEXM_KINETIS</literal>, respects this naming scheme and + enables the user to interactively configure eCos for the desired part by selecting + the requested part name segments. + Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation + of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and + Ethernet. + </para> + </refsect2> + <refsect2 id="kinetis-var-clocking"><title>Clocking</title> + <para> + Kinetis is packed with a rich set of clocking options provided by the Multipurpose Clock Generator - MCG. + Dependent on the part, MCG can have outlets for one or two external frequency reference sources + <emphasis>OSC</emphasis> and <emphasis>OSC1</emphasis> and one + or two PLL oscillators <emphasis>PLL</emphasis> and <emphasis>PLL1</emphasis>. + Each of the external frequency reference sources can be either a crystal or external + oscillator and associated with either or both PLL oscillators. <emphasis>OSC</emphasis> can also be a + reference source for the FLL oscillator. + Besides <emphasis>OSC</emphasis> and <emphasis>OSC1</emphasis>, there are additional clock sources + including two RC oscillators and a (battery backed) RTC clock with it's own 32768 Hz crystal oscillator. + MCG gives the user a wide choice of system and peripheral clock source(s) that can be + external clock(s), internal clocks, a PLL or the FLL. An external or on-chip + oscillator can be used as a system clock or as a reference for PLL/FLL oscillator(s). + </para> + <note><para> In the documentation of Kinetis parts with two oscillators, <emphasis>OSC</emphasis> + and <emphasis>PLL</emphasis> are described as <emphasis>OSC0</emphasis> and <emphasis>PLL0</emphasis> respectively. + </para></note> + <para> + Clocking component <literal>CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING</literal> provides some expert + functionality in order to facilitate clock system configuration. Normally, the user sets requirements: + clock source, clock reference, desired core frequency and upper limits for peripheral + clock frequencies. The component automatically calculates MCG and other peripheral register + settings in order to achieve the required clock frequencies. This setting is not always perfect but + fits (exactly or close) for commonly used frequencies. If necessary, the user can fine tune the + clock settings interactively using the eCos Configuration Tool. + The two clock sources are named: + </para> + <variablelist> + <varlistentry> + <term>System clock</term> + <listitem><para>The clock source that provides the clock for the Cortex-M core. + It may also provide the clock for some peripherals. + </para></listitem></varlistentry> + <varlistentry> + <term>Auxiliary clock</term> + <listitem><para>This is optional and may provide a clock for peripherals but not for the Cortex-M core. + </para></listitem></varlistentry> + </variablelist> + <para> + The user can select which source is the system clock. The choices for system clock are: <emphasis>PLL</emphasis>, + <emphasis>FLL</emphasis>, <emphasis>External reference clock</emphasis> and, when available, <emphasis>PLL1</emphasis>. + The auxiliary clock, when available is: <emphasis>PLL</emphasis> if <emphasis>PLL1</emphasis> is selected + for system the clock or <emphasis>PLL1</emphasis> if any other source is selected for the system clock. + </para> + </refsect2> + <refsect2 id="kinetis-var-memory"><title>Memory layouts</title> + <para> + The memory layouts and startup types which don't employ external memory should be applicable to all + Kinetis platforms so they are defined and maintained at the variant level. + This is somewhat different than common eCos practice but has some advantages brought by universal, + single copy linker scripts for single chip configurations. The linker scripts are further enhanced/generalized + by utilization of macros provided by CDL and calculated on the basis of the + <link linkend="kinetis-var-cpu-select">selected Kinetis part</link>. + </para> + <refsect3 id="kinetis-var-memory-ldscript-location"><title>Variant Linker + Script Location</title> + <para> + Variant linker scripts are found at: + <filename class="directory">hal/kinetis/var/<version>/include/pkgconf</filename> + </para> + </refsect3> + <refsect3 id="kinetis-var-memory-ldscript-naming"><title>Linker Script Naming</title> + <para> + Linker script file names are composed of segments + <filename>mlt_kinetis_<NVM>_<SRAM>_<STARTUP>[_<PLF>].ldi</filename> + where <filename>PLF</filename> is an optional extension for platform specific scripts and + other segments have meanings as described in the following table. + </para> + <table frame="all" id="kinetis-var-table-ldscript-naming"><title>Linker script name segments</title> + <tgroup cols="3" align="center"> + <colspec colnum="1" colname="segment" colwidth="1*" > + <colspec colnum="2" colname="desc" colwidth="2*" > + <colspec colnum="3" colname="values" colwidth="1*" > + <thead> + <row> + <entry>Segment</entry> + <entry>Description</entry> + <entry>Values</entry> + </row> + </thead> + <tbody> + <row> + <entry><filename>NVM</filename></entry> + <entry>Kinetis non-volatile memory configuration</entry> + <entry> + <filename>flash</filename>, + <filename>flexnvm</filename> + </entry> + </row> + <row> + <entry><filename>SRAM</filename></entry> + <entry>SRAM memory sectioning</entry> + <entry> + <filename>unisram</filename>, + <filename>sram2s</filename> + </entry> + </row> + <row> + <entry><filename>STARTUP</filename></entry> + <entry>Startup type</entry> + <entry> + <filename>rom</filename>, + <filename>sram</filename> + </entry> + </row> + </tbody> + </tgroup> + </table> + <para> + <note><para>Never attempt to flash Kinetis with an image for SRAM startup. SRAM startup images + do not contain a <literal>.flash_conf</literal> section so random contents may be written in + flash protection area and lock your Kinetis device. This lock-out can be permanent. + </para></note> + </para> + </refsect3> + <refsect3 id="kinetis-var-memory-plf-spec"><title>Platform Specific Memory Layouts</title> + <para> + Platforms, if needed, can provide their own layouts in addition to the variant ones. Typically + they will cover systems with external memory. The <link linkend="kinetis-var-startup"> + startup type</link> implicitly determines whether variant and platform defined + layout shall be used. + </para> + </refsect3> + <refsect3 id="kinetis-var-memory-sram"><title>On-chip SRAM</title> + <para> + Kinetis on chip SRAM memory consists of two equal banks that occupy consecutive locations anchored + below and above <literal>0x20000000</literal>. This fact is reflected in memory layout scripts. + There are linker scripts that treat SRAM as a single section (<filename>unisram</filename>) or as + 2 separate sections (<filename>sram2s</filename>). + </para> + </refsect3> + <refsect3 id="kinetis-var-memory-flash"><title>On-chip FLASH</title> + <para> + Kinetis on-chip flash contains a special area <literal>[0x400-0x40F]</literal> + that holds the flash security configuration. In order to preserve this area from + accidental writing and at the same time provide regular access, + a custom linker section <literal>.flash_conf</literal> is created. In addition, in order + to utilize the FLASH pool below <literal>0x400</literal> the <emphasis>USER_SECTION</emphasis> + <literal>.kinetis_misc</literal> is defined. This section typically contains + code parts from <filename>kinetis_misc.c</filename>. + </para> + </refsect3> + <refsect3 id="kinetis-var-memory-cache"><title>Cache</title> + <para> + Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory. + Due to the Harvard architecture, there are two cache memories connected to code + - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively. + Although both modules can cache both instructions and data (unified caches), with the provided + memory they act as instruction (<emphasis>PC</emphasis>) and data (<emphasis>PS</emphasis>) caches. + </para> + <para> + A common caching issue is sharing memory resources with bus masters such as DMA, Ethernet controller, etc. + In order to keep shared data such as buffers and transfer control descriptors consistent, + cached data have to be flushed and/or invalidated. An alternative approach, used here is usage of + non-cachable memory for shared data. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for + the configuration of non-cachable memory. If some bus masters have provision for non-cache able memory, + such configuration options can be parenthed by <literal>CYGHWR_HAL_NON_CACHABLE</literal>. + </para> + </refsect3> + </refsect2> + <refsect2 id="kinetis-var-startup"><title>Startup types</title> + <para> + There are <emphasis>two levels</emphasis> of startup type: + </para> + <variablelist> + <varlistentry> + <term>Variant <literal>CYG_HAL_STARTUP_VAR</literal></term> + <listitem><para>This is always present and provides startup + types for systems without external memory. + </para></listitem></varlistentry> + <varlistentry> + <term>Platform <literal>CYG_HAL_STARTUP_PLF</literal></term> + <listitem><para>This is optional and is + provided by a platform package. Typically it provides startup types for systems + that employ external memory. + </para></listitem></varlistentry> + </variablelist> + <para> + </para> + <para> + When present, the platform startup overloads the variant startup and has precedence over it. + User can activate the variant startup by setting platform startup to + <literal>ByVariant</literal>. + </para> + <refsect3 id="kinetis-var-startup-byvariant"><title>Startup types provided variant</title> + <para> + The following startup types are provided for Kinetis at the variant level: + </para> + <variablelist> + <varlistentry> + <term><literal>ROM</literal></term> + <listitem><para>Normal startup for stand-alone operation. eCos image has to be flashed + in internal flash; + </para></listitem></varlistentry> + <varlistentry> + <term><literal>SRAM</literal></term> + <listitem><para>Image is loaded in internal SRAM by means of JTAG/SWD and executed + under debugger control. + </para></listitem></varlistentry> + </variablelist> + <note><para>(IMPORTANT) Never, ever attempt to flash Kinetis with an image for SRAM startup. + SRAM startup images do not contain a <literal>.flash_conf</literal> section so random contents + may be written to the flash protection area and lock your Kinetis device. This lock-out can be permanent. + </para></note> + </refsect3> + </refsect2> + <refsect2 id="kinetis-interrupt-priority-scheme"><title>Interrupt priority scheme</title> + <para> + In case of multiple simultaneous interrupts, interrupt service request resolution is based + on a relative comparison of interrupt priorities, rather than on individual interrupt priority values. + <emphasis>Interrupt priority scheme</emphasis> gives a consolidated overview and control + of priorities of all interrupt sources. Interrupt priorities can be provided by either variant + <literal>CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR</literal> + or platform <literal>CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME</literal>. + </para> + </refsect2> + </refsect1> + + </refentry> + + <!--</part>--> diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml new file mode 100644 index 0000000..9fd6e90 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml @@ -0,0 +1,37 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- kinetis_begin.sgml --> +<!-- --> +<!-- Kinetis documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title> diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml new file mode 100644 index 0000000..0d70d93 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml @@ -0,0 +1,37 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- kinetis_end.sgml --> +<!-- --> +<!-- Kinetis documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +</part> diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h new file mode 100644 index 0000000..8c5445b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h @@ -0,0 +1,282 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour, ilijak +// Contributors: +// Date: 2012-05-02 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions +#ifdef CYGINT_HAL_CACHE + +// Data cache +#define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 8192 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +#include <cyg/hal/var_io.h> +#include <cyg/hal/var_io_lmem.h> + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_INVALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PS_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED(); \ + CYG_MACRO_END + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base_, _size_) + +// Write dirty cache lines to memory and invalidate the cache entries +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ + HAL_CORTEXM_KINETIS_CACHE_PS_CLR(_base_, _size_) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() + +// Purge contents of data cache +#define HAL_ICACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED(); \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) \ + HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base_, _size_) + +#else // CYGINT_HAL_CACHE + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +#endif // CYGINT_HAL_CACHE + +// End of hal_cache.h +#endif // CYGONCE_HAL_CACHE_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h new file mode 100644 index 0000000..77bd8f5 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h @@ -0,0 +1,92 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributor(s): ilijak +// Date: 2011-02-05 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_plf_diag_init(void); +__externC void hal_plf_diag_putc(char); +__externC cyg_uint8 hal_plf_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_plf_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc() +# endif + +#endif + + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h new file mode 100644 index 0000000..734bb2f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi new file mode 100644 index 0000000..3e53672 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi @@ -0,0 +1,45 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + ram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h new file mode 100644 index 0000000..ebb5c73 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h @@ -0,0 +1,22 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram_u (0x20000000) +#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi new file mode 100644 index 0000000..818c241 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram_l, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram_u, 0x20000000, LMA_EQ_VMA) + SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h new file mode 100644 index 0000000..3924c2c --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h @@ -0,0 +1,22 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi new file mode 100644 index 0000000..360fc30 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h new file mode 100644 index 0000000..688f12a --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h @@ -0,0 +1,18 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi new file mode 100644 index 0000000..f928d42 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi @@ -0,0 +1,34 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h new file mode 100644 index 0000000..2452f06 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h @@ -0,0 +1,45 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +# define CYGMEM_REGION_flexnvm (0x10000000) +# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE) +# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R) +#endif + +#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE +# define CYGMEM_REGION_eeeprom0 (0x14000000) +# define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE) +# define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 +# define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE ) +# define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE) +# define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R) +# endif +#else +# define CYGMEM_REGION_flexram (0x14000000) +# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE) +# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi new file mode 100644 index 0000000..8897d2d --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi @@ -0,0 +1,67 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + ram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE +# endif +#else + flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE +#endif +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA) +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA) +# endif +#else + USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA) +#endif + SECTION_data (ram, 0x20000000, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h new file mode 100644 index 0000000..ebb5c73 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h @@ -0,0 +1,22 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram_u (0x20000000) +#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi new file mode 100644 index 0000000..ee32874 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, LMA_EQ_VMA) + SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram_u, 0x20000000 , LMA_EQ_VMA) + SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h new file mode 100644 index 0000000..67d4559 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h @@ -0,0 +1,42 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif + +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +# define CYGMEM_REGION_flexnvm (0x10000000) +# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE) +# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R) +#endif + +#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE +# define CYGMEM_REGION_eeeprom0 (0x14000000) +# define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE) +# define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 +# define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE ) +# define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE) +# define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R) +# endif +#else +# define CYGMEM_REGION_flexram (0x14000000) +# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE) +# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi new file mode 100644 index 0000000..acd8375 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi @@ -0,0 +1,65 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE +# endif +#else + flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE +#endif +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA) +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA) +# endif +#else + USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA) +#endif + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h new file mode 100644 index 0000000..688f12a --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h @@ -0,0 +1,18 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi new file mode 100644 index 0000000..f928d42 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi @@ -0,0 +1,34 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h new file mode 100644 index 0000000..61f02de --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, +// 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:jskov, gthomas, jlarmour +// Date: 2008-07-30 +// Purpose: Platform HAL stub support for Kinetis variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/cortexm_stub.h> // architecture stub support + +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_arch.h new file mode 100644 index 0000000..8e99007 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Kinetis variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, ilijak +// Date: 2011-02-05 +// Purpose: Kinetis variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_arch.h> + + +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_intr.h new file mode 100644 index 0000000..5aedc18 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_intr.h @@ -0,0 +1,244 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for Kinetis variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for Freescale Kinetis variants are +// defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + +typedef enum { + CYGNUM_HAL_INTERRUPT_DMA0 + = CYGNUM_HAL_INTERRUPT_EXTERNAL, // DMA Channel 0 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA1, // DMA Channel 1 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA2, // DMA Channel 2 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA3, // DMA Channel 3 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA4, // DMA Channel 4 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA5, // DMA Channel 5 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA6, // DMA Channel 6 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA7, // DMA Channel 7 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA8, // DMA Channel 8 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA9, // DMA Channel 9 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA10, // DMA Channel 10 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA11, // DMA Channel 11 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA12, // DMA Channel 12 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA13, // DMA Channel 13 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA14, // DMA Channel 14 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA15, // DMA Channel 15 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA_ERROR, // DMA Error Int + CYGNUM_HAL_INTERRUPT_MCM, // Normal Int + CYGNUM_HAL_INTERRUPT_FTFL, // FTFL Int + CYGNUM_HAL_INTERRUPT_READ_COLLISION, // Read Collision Int + CYGNUM_HAL_INTERRUPT_LVD_LVW, // Low Volt Detect, Low Volt Warn + CYGNUM_HAL_INTERRUPT_LLW, // Low Leakage Wakeup + CYGNUM_HAL_INTERRUPT_WDOG, // WDOG Int + CYGNUM_HAL_INTERRUPT_RNGB, // RNGB Int + CYGNUM_HAL_INTERRUPT_I2C0, // I2C0 int + CYGNUM_HAL_INTERRUPT_I2C1, // I2C1 int + CYGNUM_HAL_INTERRUPT_SPI0, // SPI0 Int + CYGNUM_HAL_INTERRUPT_SPI1, // SPI1 Int + CYGNUM_HAL_INTERRUPT_SPI2, // SPI2 Int + CYGNUM_HAL_INTERRUPT_CAN0_ORED_MESSAGE_BUFFER,// CAN0 OR'd Msg Buffs Int + CYGNUM_HAL_INTERRUPT_CAN0_BUS_OFF, // CAN0 Bus Off Int + CYGNUM_HAL_INTERRUPT_CAN0_ERROR, // CAN0 Error Int + CYGNUM_HAL_INTERRUPT_CAN0_TX_WARNING, // CAN0 Tx Warning Int + CYGNUM_HAL_INTERRUPT_CAN0_RX_WARNING, // CAN0 Rx Warning Int + CYGNUM_HAL_INTERRUPT_CAN0_WAKE_UP, // CAN0 Wake Up Int + CYGNUM_HAL_INTERRUPT_CAN0_IMEU, // CAN0 Ind. Match El Update (IMEU) Int + CYGNUM_HAL_INTERRUPT_CAN0_LOST_RX, // CAN0 Lost Receive Int + CYGNUM_HAL_INTERRUPT_CAN1_ORED_MESSAGE_BUFFER, // CAN1 OR'd Msg Buffs Int + CYGNUM_HAL_INTERRUPT_CAN1_BUS_OFF, // CAN1 Bus Off Int + CYGNUM_HAL_INTERRUPT_CAN1_ERROR, // CAN1 Error Int + CYGNUM_HAL_INTERRUPT_CAN1_TX_WARNING, // CAN1 Tx Warning Int + CYGNUM_HAL_INTERRUPT_CAN1_RX_WARNING, // CAN1 Rx Warning Int + CYGNUM_HAL_INTERRUPT_CAN1_WAKE_UP, // CAN1 Wake Up Int + CYGNUM_HAL_INTERRUPT_CAN1_IMEU, // CAN1 Ind. Match El Update (IMEU) Int + CYGNUM_HAL_INTERRUPT_CAN1_LOST_RX, // CAN1 Lost Receive Int + CYGNUM_HAL_INTERRUPT_UART0_RX_TX, // UART0 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART0_ERR, // UART0 Error int + CYGNUM_HAL_INTERRUPT_UART1_RX_TX, // UART1 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART1_ERR, // UART1 Error int + CYGNUM_HAL_INTERRUPT_UART2_RX_TX, // UART2 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART2_ERR, // UART2 Error int + CYGNUM_HAL_INTERRUPT_UART3_RX_TX, // UART3 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART3_ERR, // UART3 Error int + CYGNUM_HAL_INTERRUPT_UART4_RX_TX, // UART4 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART4_ERR, // UART4 Error int + CYGNUM_HAL_INTERRUPT_UART5_RX_TX, // UART5 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART5_ERR, // UART5 Error int + CYGNUM_HAL_INTERRUPT_ADC0, // ADC0 int + CYGNUM_HAL_INTERRUPT_ADC1, // ADC1 int + CYGNUM_HAL_INTERRUPT_CMP0, // CMP0 int + CYGNUM_HAL_INTERRUPT_CMP1, // CMP1 int + CYGNUM_HAL_INTERRUPT_CMP2, // CMP2 int + CYGNUM_HAL_INTERRUPT_FTM0, // FTM0 fault, overflow and channels int + CYGNUM_HAL_INTERRUPT_FTM1, // FTM1 fault, overflow and channels int + CYGNUM_HAL_INTERRUPT_FTM2, // FTM2 fault, overflow and channels int + CYGNUM_HAL_INTERRUPT_CMT, // CMT int + CYGNUM_HAL_INTERRUPT_RTC_RTC, // RTC int + CYGNUM_HAL_INTERRUPT_RTC_SECONDS, // RTC seconds interrupt + CYGNUM_HAL_INTERRUPT_PIT0, // PIT timer channel 0 int + CYGNUM_HAL_INTERRUPT_PIT1, // PIT timer channel 1 int + CYGNUM_HAL_INTERRUPT_PIT2, // PIT timer channel 2 int + CYGNUM_HAL_INTERRUPT_PIT3, // PIT timer channel 3 int + CYGNUM_HAL_INTERRUPT_PDB0, // PDB0 Int + CYGNUM_HAL_INTERRUPT_USB0, // USB0 int + CYGNUM_HAL_INTERRUPT_USBDCD, // USBDCD Int + CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER, // ENET MAC IEEE 1588 Timer Int + CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT, // ENET MAC Transmit Int + CYGNUM_HAL_INTERRUPT_ENET_RECEIVE, // ENET MAC Receive Int + CYGNUM_HAL_INTERRUPT_ENET_ERROR, // ENET MAC Error and miscelaneous Int + CYGNUM_HAL_INTERRUPT_I2S0, // I2S0 Int + CYGNUM_HAL_INTERRUPT_SDHC, // SDHC Int + CYGNUM_HAL_INTERRUPT_DAC0, // DAC0 int + CYGNUM_HAL_INTERRUPT_DAC1, // DAC1 int + CYGNUM_HAL_INTERRUPT_TSI0, // TSI0 Int + CYGNUM_HAL_INTERRUPT_MCG, // MCG Int + CYGNUM_HAL_INTERRUPT_LPTIMER, // LPTimer int + CYGNUM_HAL_INTERRUPT_LCD, // Segment LCD int + CYGNUM_HAL_INTERRUPT_PORTA, // Port A int + CYGNUM_HAL_INTERRUPT_PORTB, // Port B int + CYGNUM_HAL_INTERRUPT_PORTC, // Port C int + CYGNUM_HAL_INTERRUPT_PORTD, // Port D int + CYGNUM_HAL_INTERRUPT_PORTE, // Port E int + CYGNUM_HAL_INTERRUPT_PORTF, // Port F interrupt + CYGNUM_HAL_INTERRUPT_DDR, // DDR interrupt + CYGNUM_HAL_INTERRUPT_SWI, // Software interrupt + CYGNUM_HAL_INTERRUPT_NFC, // NAND flash controller interrupt + CYGNUM_HAL_INTERRUPT_USBHS, // USB high speed OTG interrupt + CYGNUM_HAL_INTERRUPT_GLCD, // Graphical LCD interrupt + CYGNUM_HAL_INTERRUPT_CMP3, // CMP3 interrupt + CYGNUM_HAL_INTERRUPT_TAMPER, // Tamper detect interrupt + CYGNUM_HAL_INTERRUPT_Reserved116, // Reserved interrupt 116 + CYGNUM_HAL_INTERRUPT_FTM3, // FTM3 fault, overflow and channels interrupt + CYGNUM_HAL_INTERRUPT_ADC2, // ADC2 interrupt + CYGNUM_HAL_INTERRUPT_ADC3, // ADC3 interrupt + CYGNUM_HAL_INTERRUPT_I2S1_TX, // I2S1 transmit interrupt + CYGNUM_HAL_INTERRUPT_I2S1_RX // I2S1 receive interrupt +} KinetisExtInterrupt_e; + +// DMA16..31 share interrupt vectors with DMA0..15 respectively. + +#define CYGNUM_HAL_INTERRUPT_DMA16 CYGNUM_HAL_INTERRUPT_DMA0 +#define CYGNUM_HAL_INTERRUPT_DMA17 CYGNUM_HAL_INTERRUPT_DMA1 +#define CYGNUM_HAL_INTERRUPT_DMA18 CYGNUM_HAL_INTERRUPT_DMA2 +#define CYGNUM_HAL_INTERRUPT_DMA19 CYGNUM_HAL_INTERRUPT_DMA3 +#define CYGNUM_HAL_INTERRUPT_DMA20 CYGNUM_HAL_INTERRUPT_DMA4 +#define CYGNUM_HAL_INTERRUPT_DMA21 CYGNUM_HAL_INTERRUPT_DMA5 +#define CYGNUM_HAL_INTERRUPT_DMA22 CYGNUM_HAL_INTERRUPT_DMA6 +#define CYGNUM_HAL_INTERRUPT_DMA23 CYGNUM_HAL_INTERRUPT_DMA7 +#define CYGNUM_HAL_INTERRUPT_DMA34 CYGNUM_HAL_INTERRUPT_DMA8 +#define CYGNUM_HAL_INTERRUPT_DMA25 CYGNUM_HAL_INTERRUPT_DMA9 +#define CYGNUM_HAL_INTERRUPT_DMA26 CYGNUM_HAL_INTERRUPT_DMA10 +#define CYGNUM_HAL_INTERRUPT_DMA27 CYGNUM_HAL_INTERRUPT_DMA11 +#define CYGNUM_HAL_INTERRUPT_DMA28 CYGNUM_HAL_INTERRUPT_DMA12 +#define CYGNUM_HAL_INTERRUPT_DMA29 CYGNUM_HAL_INTERRUPT_DMA13 +#define CYGNUM_HAL_INTERRUPT_DMA30 CYGNUM_HAL_INTERRUPT_DMA14 +#define CYGNUM_HAL_INTERRUPT_DMA31 CYGNUM_HAL_INTERRUPT_DMA15 + +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_I2S1_RX) + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_I2S1_RX +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+ \ + CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif + +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +//========================================================================== +// Interrupt mask and config for variant-specific devices + +// PORT Pin interrupts + +#define CYGHWR_HAL_KINETIS_PIN_IRQ_VECTOR(__pin) \ + (CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_KINETIS_PIN_PORT(__pin)) + +//=========================================================================== +// Interrupt resources exported by HAL to device drivers + +// Export Interrupt vectors to serial driver. + +#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART0_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART1_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART2_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART3_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART4_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART5_RX_TX + +// Export Interrupt vectors to ENET driver. + +#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER +#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT +#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_RECEIVE +#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_ERROR + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io.h new file mode 100644 index 0000000..18df202 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io.h @@ -0,0 +1,1206 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//=========================================================================== +// +// var_io.h +// +// Variant specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +#include <pkgconf/hal_cortexm_kinetis.h> + +#include <cyg/hal/plf_io.h> + +//=========================================================================== +// Cortex-M architecture +//--------------------------------------------------------------------------- +//-------------------------------------------------------------------------- +// Cortex-M architecture overrides +//--------------------------------------------------------------------------- +// VTOR - Vector Table Offset Register +#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM +#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM (BIT_(29) - \ + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#endif + +//============================================================================= +// Kinetis system configuration +//--------------------------------------------------------------------------- +// Utilize Freescale Kinetis flash between startup vectors and 0x400 +// for misc funtions. +#ifdef CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION +# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR \ + CYGBLD_ATTRIB_SECTION(".kinetis_misc") +#else +# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +#endif + +//=========================================================================== +// KINETIS FLASH configuration field +//=========================================================================== + +// Note: KINETIS FLASH configuration field must be present in Kinetis flash +// image and ocupy addresses 0x00000400 to 0x0000040f. + +typedef struct cyghwr_hal_kinetis_flash_conf_s { + cyg_uint8 backdoor_key[8]; // 0x400 .. 0x407 + cyg_uint8 fprot[4]; // 0x408 .. 0x40b + cyg_uint8 fsec; // 0x40c + cyg_uint8 fopt; // 0x40d + cyg_uint8 feprot; // 0x40e + cyg_uint8 fdprot; // 0x40f +} cyghwr_hal_kinetis_flash_conf_t; + +__externC const cyghwr_hal_kinetis_flash_conf_t *hal_kinetis_flash_conf_p( void ); + +//=========================================================================== +// Kinetis Peripherals +//--------------------------------------------------------------------------- +// Internal Flash + +typedef volatile struct cyghwr_hal_kinetis_flash_s { + cyg_uint8 fstat; // Flash status register + cyg_uint8 fcnfg; // Flash configuration register + cyg_uint8 fsec; // Flash security register + cyg_uint8 fopt; // Flash option register + cyg_uint8 fccob3; // Flash common command object registers + cyg_uint8 fccob2; + cyg_uint8 fccob1; + cyg_uint8 fccob0; + cyg_uint8 fccob7; + cyg_uint8 fccob6; + cyg_uint8 fccob5; + cyg_uint8 fccob4; + cyg_uint8 fccobB; + cyg_uint8 fccobA; + cyg_uint8 fccob9; + cyg_uint8 fccob8; + cyg_uint8 fprot3; // Program flash protection registers + cyg_uint8 fprot2; + cyg_uint8 fprot1; + cyg_uint8 fprot0; + cyg_uint8 reserved[2]; + cyg_uint8 feprot; // EEPROM Protection register + cyg_uint8 fdprot; // Data flash protection register +} cyghwr_hal_kinetis_flash_t; + +#define CYGHWR_HAL_KINETIS_FLASH_P ((cyghwr_hal_kinetis_flash_t *) 0x40020000) + +#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M 0x80 +#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_RDCOLERR_M 0x40 +#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_ACCERR_M 0x20 +#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_FPVIOL_M 0x10 +#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_MGSTAT0_M 0x01 + +//--------------------------------------------------------------------------- +// Oscillator + +#define CYGHWR_HAL_KINETIS_OSC_CR (0x40065000) +#define CYGHWR_HAL_KINETIS_OSC_CR_P ((volatile cyg_uint8*) 0x40065000) + +#define CYGHWR_HAL_KINETIS_OSC1_CR (0x400E5000) +#define CYGHWR_HAL_KINETIS_OSC1_CR_P ((volatile cyg_uint8*) 0x400E5000) + +#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_M 0x01 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_S 0 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_M 0x02 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_S 1 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_M 0x04 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_S 2 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_M 0x08 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_S 3 +#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M 0x20 +#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_S 5 +#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M 0x80 +#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_S 7 + +//--------------------------------------------------------------------------- +// MCG + +typedef volatile struct cyghwr_hal_kinetis_mcg_s { + cyg_uint8 c1; // MCG Control 1 Register + cyg_uint8 c2; // MCG Control 2 Register + cyg_uint8 c3; // MCG Control 3 Register + cyg_uint8 c4; // MCG Control 4 Register + cyg_uint8 c5; // MCG Control 5 Register + cyg_uint8 c6; // MCG Control 6 Register + cyg_uint8 status; // MCG Status Register + cyg_uint8 mcg_res0; +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1 + cyg_uint8 atc; // MCG Auto Trim Control Register +#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + cyg_uint8 sc; // MCG Status and Control Register +#endif + cyg_uint8 mcg_res1; + cyg_uint8 atcvh; // MCG Auto Trim Compare Value High Register + cyg_uint8 atcvl; // MCG Auto Trim Compare Value Low Register +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + cyg_uint8 c7; // MCG Control 7 Register + cyg_uint8 c8; // MCG Control 8 Register +#endif +#if CYGINT_HAL_CORTEXM_KINETIS_150 + cyg_uint8 c10; // MCG Control 10 Register + cyg_uint8 mcg_res2; + cyg_uint8 c11; // MCG Control 11 Register + cyg_uint8 c12; // MCG Control 12 Register + cyg_uint8 s2; // MCG Status 2 Register +#endif //CYGINT_HAL_CORTEXM_KINETIS_150 +} cyghwr_hal_kinetis_mcg_t; + +#define CYGHWR_HAL_KINETIS_MCG_P ((cyghwr_hal_kinetis_mcg_t *)0x40064000) + +// C1 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_S 1 +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_M 0x4 +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_S 2 +#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_M 0x38 +#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S 3 +#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(_div_) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S, _div_) +#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M 0xC0 +#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS(_clks_) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S, _clks_) +enum { + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_FLL_PLL, + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_INT_REF, + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF, + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_RESERVED +}; +// C2 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C2_LP_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_C2_LP_S 1 +#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M 0x04 +#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_S 2 +#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_M 0x08 +#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_S 3 +#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_M 0x30 +#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S 4 +#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S, __v) + +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_S 7 +#endif +// C3 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_M 0xFF +#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S, __v) +// C4 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_M 0x1E +#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S 1 +#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_M 0x60 +#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_S 7 +// C5 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M 0x1F +#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_S 6 +#if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 +# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M 0x80 +# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_S 7 +#endif +// C6 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M 0x1F +#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C6_CME_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C6_CME_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_S 7 +// S Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_S 0 +#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_S 1 +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_M 0x0C +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_S 2 +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_S_CLKST_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL CYGHWR_HAL_KINETIS_MCG_S_CLKST(0) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_INT CYGHWR_HAL_KINETIS_MCG_S_CLKST(1) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT CYGHWR_HAL_KINETIS_MCG_S_CLKST(2) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL CYGHWR_HAL_KINETIS_MCG_S_CLKST(3) +#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_S 4 +#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_S 5 +#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_S 6 +#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_S 7 + +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1 +// ATC Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_S 5 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_S 7 +#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +// SC Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_S 0 +#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_M 0x0E +#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S 1 +#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_S 4 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_S 5 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_S 7 +#endif // CYGHWR_HAL_CORTEXM_KINETIS_REV +// ATCVH Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_M 0xFF +#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S 0 +#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S, __v) +// ATCVL Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_M 0xFF +#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S 0 +#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL(__v) \ +VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S, __v) + +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +// C7 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M 0x1 +#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_S 0 +// C8 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_M 0x1 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_S 6 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_S 7 +#endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + +#if CYGINT_HAL_CORTEXM_KINETIS_150 + +// C10 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_M 0x04 +#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_S 2 +#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_M 0x08 +#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_S 3 +#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_M 0x30 +#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S 4 +#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_S 7 +// C11 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M 0x7 +#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_S 4 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_S 6 +# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M 0x80 +# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_S 7 +// C12 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M 0x1F +#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_S 7 +// S2 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_S 0 +#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_S 1 +#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_S 4 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_S 6 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_S 7 + +#endif //CYGINT_HAL_CORTEXM_KINETIS_150 + + +//--------------------------------------------------------------------------- +// Real Time Clock + +typedef volatile struct cyghwr_hal_kinetis_rtc_s { + cyg_uint32 tsr; // Time Seconds Register + cyg_uint32 tpr; // Time Prescaler Register + cyg_uint32 tar; // Time Alarm Register + cyg_uint32 tcr; // Time Compensation Register + cyg_uint32 cr; // Control Register + cyg_uint32 sr; // Status Register + cyg_uint32 lr; // Lock Register + cyg_uint32 ier; // Enterrupt Enable Register + cyg_uint32 ttsr; // Tamper Times Seconds Register + cyg_uint32 mer; // Monotonic Enable Register + cyg_uint32 mclr; // Monotonic Counter Low Register + cyg_uint32 mchr; // Monotonic Counter High Register + cyg_uint32 ter; // Tamper Enable Register + cyg_uint32 tdr; // Tamper Detect Register + cyg_uint32 ttr; // Tamper Trim Register + cyg_uint32 tir; // Tamper Interrupt Register + cyg_uint8 reserved[1984]; + cyg_uint32 war; // Write Access Register + cyg_uint32 rar; // Read Access Register +} cyghwr_hal_kinetis_rtc_t; + +#define CYGHWR_HAL_KINETIS_RTC_P ((cyghwr_hal_kinetis_rtc_t *)0x4003D000) + +#define CYGHWR_HAL_KINETIS_RTC_TCR_TCR_M (0x000000FF) +#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S 8 +#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S, _div_) +#define CYGHWR_HAL_KINETIS_RTC_TCR_CIC_S 16 +#define CYGHWR_HAL_KINETIS_RTC_TCR_TCV_S 24 + +#define CYGHWR_HAL_KINETIS_RTC_CR_SWR BIT_(0) +#define CYGHWR_HAL_KINETIS_RTC_CR_WPE BIT_(1) +#define CYGHWR_HAL_KINETIS_RTC_CR_SUP BIT_(2) +#define CYGHWR_HAL_KINETIS_RTC_CR_UM BIT_(3) +#define CYGHWR_HAL_KINETIS_RTC_CR_OSCE BIT_(8) +#define CYGHWR_HAL_KINETIS_RTC_CR_CLKO BIT_(9) +#define CYGHWR_HAL_KINETIS_RTC_CR_SCP \ + VALUE_(10, (CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP/2)) + +#define CYGHWR_HAL_KINETIS_RTC_SR_TCE BIT_(4) +#define CYGHWR_HAL_KINETIS_RTC_SR_TAF BIT_(2) +#define CYGHWR_HAL_KINETIS_RTC_SR_TOF BIT_(1) +#define CYGHWR_HAL_KINETIS_RTC_SR_TIF BIT_(0) + +//--------------------------------------------------------------------------- +// Watch dog + +// WDOG - Peripheral register structure +typedef volatile struct CygHwr_HAL_Kinetis_wdog_s { + cyg_uint16 StCtrlH; // Status and Control Register High + cyg_uint16 StCtrlL; // Status and Control Register Low + cyg_uint16 ToValH; // Time-out Value Register High + cyg_uint16 ToValL; // Time-out Value Register Low + cyg_uint16 WinH; // Window Register High + cyg_uint16 WinL; // Window Register Low + cyg_uint16 Refresh; // Refresh Register + cyg_uint16 Unlock; // Unlock Register + cyg_uint16 TmrOutH; // Timer Output Register High + cyg_uint16 TmrOutL; // Timer Output Register Low + cyg_uint16 RstCnt; // Reset Count Register + cyg_uint16 Presc; // Prescaler Register +} CygHwr_HAL_Kinetis_wdog_t; + +#define CYGHWR_HAL_KINETIS_WDOG_P ((CygHwr_HAL_Kinetis_wdog_t *)0x40052000) + +// STCTRLH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_M 0x0001 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_M 0x0002 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_S 1 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_M 0x0004 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_S 2 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_M 0x0008 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_S 3 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M 0x0010 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_S 4 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_M 0x0020 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_S 5 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_M 0x0040 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_S 6 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_M 0x0080 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_S 7 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_M 0x0100 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_S 8 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_M 0x0400 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_S 10 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_M 0x0800 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_S 11 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_M 0x3000 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S 12 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S, __v) +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_M 0x4000 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_S 14 +// STCTRLL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_M 0x8000 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_S 15 +// TOVALH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S, __v) +// TOVALL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S, __v) +// WINH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S, __v) +// WINL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S, __v) +// REFRESH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S, __v) +// UNLOCK Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S, __v) +// TMROUTH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S, __v) +// TMROUTL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S, __v) +// RSTCNT Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S, __v) +// PRESC Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_M 0x700 +#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S 8 +#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S, __v) + +#ifndef __ASSEMBLER__ + +__externC void hal_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p); +__externC void hal_wdog_disable(void); + +#endif // __ASSEMBLER__ + +//--------------------------------------------------------------------------- +// SIM - System Integration Module + +// SIM - Peripheral register structure +typedef volatile struct cyghwr_hal_kinetis_sim_s { + cyg_uint32 sopt1; // System Options Register 1 + cyg_uint8 reserved_0[4096]; + cyg_uint32 sopt2; // System Options Register 2 + cyg_uint8 reserved_1[4]; + cyg_uint32 sopt4; // System Options Register 4 + cyg_uint32 sopt5; // System Options Register 5 + cyg_uint32 sopt6; // System Options Register 6 + cyg_uint32 sopt7; // System Options Register 7 + cyg_uint8 Reserved_2[8]; + cyg_uint32 sdid; // System Device Identification Register + cyg_uint32 scgc1; // System Clock Gating Control Register 1 + cyg_uint32 scgc2; // System Clock Gating Control Register 2 + cyg_uint32 scgc3; // System Clock Gating Control Register 3 + cyg_uint32 scgc4; // System Clock Gating Control Register 4 + cyg_uint32 scgc5; // System Clock Gating Control Register 5 + cyg_uint32 scgc6; // System Clock Gating Control Register 6 + cyg_uint32 scgc7; // System Clock Gating Control Register 7 + cyg_uint32 clk_div1; // System Clock Divider Register 1 + cyg_uint32 clk_div2; // System Clock Divider Register 2 + cyg_uint32 fcfg1; // Flash Configuration Register 1 + cyg_uint32 fcfg2; // Flash Configuration Register 2 + cyg_uint32 uidh; // Unique Identification Register High + cyg_uint32 uidmh; // Unique Identification Register Mid-High + cyg_uint32 uidml; // Unique Identification Register Mid Low + cyg_uint32 uidl; // Unique Identification Register Low + + cyg_uint32 clkdiv3; // System Clock Divider Register 3 + cyg_uint32 clkdiv4; // System Clock Divider Register 4 + cyg_uint32 mcr; // Misc control register +} cyghwr_hal_kinetis_sim_t; + +#define CYGHWR_HAL_KINETIS_SIM_P ((cyghwr_hal_kinetis_sim_t *) 0x40047000) + +// SOPT1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_M 0xF000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_M 0x80000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_S 19 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_S 23 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_M 0x40000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_S 30 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_M 0x80000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_S 31 +// SOPT2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_M 0x300 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M 0x10000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_S 16 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_M 0x300000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_M 0x3000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_M 0x30000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S 28 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S, __val) +// SOPT4 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_M 0x100 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_M 0xC0000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_M 0x300000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_M 0x4000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_S 26 +// SOPT5 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_M 0x3 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_M 0xC +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_M 0x30 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_M 0xC0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S 6 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S, __val) +// SOPT6 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_M 0x1F000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_M 0xE0000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S 29 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S, __val) +// SOPT7 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_M 0xF +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_M 0x80 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_S 7 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_M 0xF00 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_S 15 +// SDID Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_M 0xF +#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_M 0x70 +#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_M 0xF000 +#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S, __val) + +//--------------------------------------------------------------------------- +// Clock distribution +// The following encodes the control register and clock bit number +// into clock configuration descriptor (CLKCD). +#define CYGHWR_HAL_KINETIS_SIM_SCGC(__reg,__bit) ((((__reg) - 1 ) & 0xF) + \ + (((__bit) << 8) & 0x1F00)) + +// Macros to extract encoded values. +#define CYGHWR_HAL_KINETIS_SIM_SCGC_REG(__clkcd) (((__clkcd) & 0xF)) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(__clkcd) (((__clkcd) >> 8) & 0x1F) + +// Functions and macros to enable/disable clocks. +#define CYGHWR_HAL_SCGC_NONE (0xFFFFFFFF) +__externC void hal_clock_enable(cyg_uint32 clkcd); +__externC void hal_clock_disable(cyg_uint32 clkcd); + +#define CYGHWR_HAL_CLOCK_ENABLE(__clkcd) hal_clock_enable(__clkcd) +#define CYGHWR_HAL_CLOCK_DISABLE(__clkcd) hal_clock_disable(__clkcd) + +#include <cyg/hal/var_io_clkgat.h> + +// CLKDIV1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_M 0xF0000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S 16 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_M 0xF00000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S 20 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_M 0xF000000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S 24 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_M 0xF0000000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S 28 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S, __val) +// CLKDIV2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_S 0 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_M 0xE +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S 1 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_M 0xFF00 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S 8 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_M 0xFFF00000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S 20 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S, __val) +// FCFG1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_M 0xF00 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S 8 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_M 0xF0000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S 16 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_M 0xFF000000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S 24 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S, __val) +// FCFG2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_M 0x3F0000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S 16 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_S 23 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_M 0x3F000000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S 24 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_M 0x80000000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_S 31 +// UIDH Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S, __val) +// UIDMH Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S, __val) +// UIDML Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S, __val) +// UIDL Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S, __val) +// MCR Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_M 0xE000 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S 5 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M 0x8 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_S 3 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_S 2 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_S 1 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_S 0 + + + +//-------------------------------------------------------------------------- +// AXBS - Crossbar switch + +#define CYGHWR_HAL_KINETIS_AXBS_SLAVES_K 7 +#define CYGHWR_HAL_KINETIS_AXBS_MASTERS_K 8 + +typedef volatile struct cyghwr_hal_kinetis_axbs_s { + volatile struct cyghwr_hal_kinetis_axbs_slave_s { + cyg_uint32 prs; + cyg_uint32 res0[3]; + cyg_uint32 crs; + cyg_uint32 res1[59]; + } slave[8]; + volatile struct cyghwr_hal_kinetis_axbs_master_s { + cyg_uint32 res0[64]; + cyg_uint32 mgprc; + } master[8]; +} cyghwr_hal_kinetis_axbs_t; + +#define CYGHWR_HAL_KINETIS_AXBS_P ((cyghwr_hal_kinetis_axbs_t *) 0x40004000) + +// PRS Fields +#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_) ((_master_) * 4) +#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_) \ + (0x7 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_)) + +#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(_master_,_prs) \ + (((_prs) & CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_)) >> \ + CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_)) +// CRS Fields +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PARK_M 0x7 + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M 0x30 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S 4 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL(_x_) (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S) & \ + CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M) +#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M 0x300 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S 8 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_x_) (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S) & \ + CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M) +#define CYGHWR_HAL_KINETIS_AXBS_CRS_HLP_M 0x40000000 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_RO_M 0x80000000 + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB(_slave_i,_arb) \ +CYG_MACRO_START \ + cyg_uint32 regval; \ + cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P; \ + regval = _axbs_p->slave[_slave_i].crs; \ + regval &= ~CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M; \ + regval |= CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_arb); \ + _axbs_p->slave[_slave_i].crs = regval; \ +CYG_MACRO_END + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_RR(_slave_i) \ + CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 1) + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_FIX(_slave_i) \ + CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 0) + +// MGPCR Bit Fields +#define CYGHWR_HAL_KINETIS_AXBS_CRS_AXBS_MGPCR_AULB_M 0x7 + +//--------------------------------------------------------------------------- +// PORT - Peripheral register structure + +typedef volatile struct cyghwr_hal_kinetis_port_s { + cyg_uint32 pcr[32]; // Pin Control Register n, array + cyg_uint32 gpclr; // Global Pin Control Low Register + cyg_uint32 gpchr; // Global Pin Control High Register + cyg_uint8 reserved0[24]; + cyg_uint32 isfr; // Interrupt Status Flag Register + cyg_uint8 reserved1[28]; + cyg_uint32 dfer; // Digital Filter Enable Register + cyg_uint32 dfcr; // Digital Filter Clock Register + cyg_uint32 dfwr; // Digital Filter Width Register +} cyghwr_hal_kinetis_port_t; + +// PORT - Peripheral instance base addresses +#define CYGHWR_HAL_KINETIS_PORTA_P ((cyghwr_hal_kinetis_port_t *)0x40049000) +#define CYGHWR_HAL_KINETIS_PORTB_P ((cyghwr_hal_kinetis_port_t *)0x4004A000) +#define CYGHWR_HAL_KINETIS_PORTC_P ((cyghwr_hal_kinetis_port_t *)0x4004B000) +#define CYGHWR_HAL_KINETIS_PORTD_P ((cyghwr_hal_kinetis_port_t *)0x4004C000) +#define CYGHWR_HAL_KINETIS_PORTE_P ((cyghwr_hal_kinetis_port_t *)0x4004D000) +#define CYGHWR_HAL_KINETIS_PORTF_P ((cyghwr_hal_kinetis_port_t *)0x4004E000) + +enum { + CYGHWR_HAL_KINETIS_PORTA, CYGHWR_HAL_KINETIS_PORTB, + CYGHWR_HAL_KINETIS_PORTC, CYGHWR_HAL_KINETIS_PORTD, + CYGHWR_HAL_KINETIS_PORTE, CYGHWR_HAL_KINETIS_PORTF +}; + +#define CYGHWR_HAL_KINETIS_PORT(__port, __reg) \ + (CYGHWR_HAL_KINETIS_PORT##__port##_P)->__reg + +// PCR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_M 0x1 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_S 0 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_M 0x2 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_S 1 +#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M 0x4 +#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_S 2 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_M 0x10 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_S 4 +#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_M 0x20 +#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_S 5 +#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M 0x40 +#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_S 6 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_M 0x700 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S 8 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_M 0x8000 +#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_S 15 +#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_M 0xF0000 +#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S 16 +#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_M 0x1000000 +#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_S 24 + +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_ANALOG 0 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_DIS 0 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO 1 + +#define CYGHWR_HAL_KINETIS_PORT_PCR_ISFR_CLEAR(__port, __pin) \ + CYGHWR_HAL_KINETIS_PORT(__port, pcr[__pin]) |= BIT_(24) + +#define CYGHWR_HAL_KINETIS_PORT_ISFR_CLEAR(__port, __pin) \ + CYGHWR_HAL_KINETIS_PORT(__port, isfr) |= BIT_(__pin) + +#define CYGHWR_HAL_KINETIS_PIN_CFG(__port, __bit, __mux, __irqc, __cnf) \ + ((CYGHWR_HAL_KINETIS_PORT##__port << 20) | ((__bit) << 27) \ + | CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__irqc) \ + | CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__mux) | (__cnf)) + +#define CYGHWR_HAL_KINETIS_PIN(__port, __bit, __mux, __cnf) \ + CYGHWR_HAL_KINETIS_PIN_CFG(__port, __bit, __mux, 0, __cnf) + +#define CYGHWR_HAL_KINETIS_PIN_PORT(__pin) (((__pin) >> 20) & 0x7) +#define CYGHWR_HAL_KINETIS_PIN_BIT(__pin) (((__pin) >> 27 ) & 0x1f) +#define CYGHWR_HAL_KINETIS_PIN_FUNC(__pin) ((__pin) & 0x010f8777) +#define CYGHWR_HAL_KINETIS_PIN_NONE (0xffffffff) + +// GPCLR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_M 0xFFFF +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S 0 +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_M 0xFFFF0000 +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S 16 +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S, __val) +// GPCHR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_M 0xFFFF +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S 0 +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_M 0xFFFF0000 +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S 16 +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S, __val) +// ISFR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S 0 +#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S, __val) +// DFER Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S 0 +#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S, __val) +// DFCR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_M 0x1 +#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_S 0 +// DFWR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_M 0x1F +#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S 0 +#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S, __val) + +#ifndef __ASSEMBLER__ + +// Pin configuration related functions +__externC void hal_set_pin_function(cyg_uint32 pin); +__externC void hal_dump_pin_function(cyg_uint32 pin); +__externC void hal_dump_pin_setting(cyg_uint32 pin); + +#endif + +#define HAL_SET_PINS(_pin_array) \ +CYG_MACRO_START \ + const cyg_uint32 *_pin_p; \ + for(_pin_p = &_pin_array[0]; \ + _pin_p < &_pin_array[0] + sizeof(_pin_array)/sizeof(_pin_array[0]); \ + hal_set_pin_function(*_pin_p++)); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// PMC Power Management Controller + +typedef volatile struct cyghwr_hal_kinetis_pmc_s { + cyg_uint8 lvdsc1; // Low Voltage Detect Status and Control 1 Register + cyg_uint8 lvdsc2; // Low Voltage Detect Status and Control 2 Register + cyg_uint8 regsc; // Regulator Status and Control Register +} cyghwr_hal_kinetis_pmc_t; + +// PMC base address +#define CYGHWR_HAL_KINETIS_PMC_P ((cyghwr_hal_kinetis_pmc_t *)0x4007D000) + +// LVDSC1 Bit Fields +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M 0x3 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV(__val) \ + ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M) +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_M 0x10 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_S 4 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_M 0x20 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_S 5 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_M 0x40 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_S 6 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_M 0x80 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_S 7 +// LVDSC2 Bit Fields +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M 0x3 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV(__val) \ + ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M) +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_M 0x20 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_S 5 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_M 0x40 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_S 6 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_M 0x80 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_S 7 +// REGSC Bit Fields +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_M 0x1 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_S 0 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_M 0x4 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_S 2 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M 0x8 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_S 3 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_M 0x10 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_S 4 + +//--------------------------------------------------------------------------- +// FMC Flash Memory Controller + +#define CYGHWR_HAL_KINETIS_FMC_BASE (0x4001F000) +#define CYGHWR_HAL_KINETIS_FMC_PFAPR (CYGHWR_HAL_KINETIS_FMC_BASE) +#define CYGHWR_HAL_KINETIS_FMC_PFB0CR (CYGHWR_HAL_KINETIS_FMC_BASE + 4) +#define CYGHWR_HAL_KINETIS_FMC_PFB1CR (CYGHWR_HAL_KINETIS_FMC_BASE + 8) + +enum { + CYGHWR_HAL_KINETIS_FMC_CACHE_W0, + CYGHWR_HAL_KINETIS_FMC_CACHE_W1, + CYGHWR_HAL_KINETIS_FMC_CACHE_W2, + CYGHWR_HAL_KINETIS_FMC_CACHE_W3, + CYGHWR_HAL_KINETIS_FMC_CACHE_WAYS +}; + +enum { + CYGHWR_HAL_KINETIS_FMC_CACHE_S0, + CYGHWR_HAL_KINETIS_FMC_CACHE_S1, + CYGHWR_HAL_KINETIS_FMC_CACHE_S2, + CYGHWR_HAL_KINETIS_FMC_CACHE_S3, + CYGHWR_HAL_KINETIS_FMC_CACHE_S4, + CYGHWR_HAL_KINETIS_FMC_CACHE_S5, + CYGHWR_HAL_KINETIS_FMC_CACHE_S6, + CYGHWR_HAL_KINETIS_FMC_CACHE_S7, + CYGHWR_HAL_KINETIS_FMC_CACHE_SIDES +}; + +#define CYGHWR_HAL_KINETIS_FMC_TAG(__way,__side) \ + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x100 + (__way)*0x20 + (__side)*4) +#define CYGHWR_HAL_KINETIS_FMC_DATA_U(__way,side) \ + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x200 + (__way)*0x20 + (__side)*8) +#define CYGHWR_HAL_KINETIS_FMC_DATA_L(__way,side) \ + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x204 + (__way)*0x40 + (__side)*8) + +#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MPFD_M(__master) (1 << ((__master) + 16)) +enum { + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_NO_ACCESS, + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RO, + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_WO, + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RW +}; +#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP(__master, __access) \ + ((__access) <<(2 * (__master))) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_RWSC_M (0xf0000000) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(__way) ((1 << (__way)) << 24) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_ALL \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(__way) ((1 << (__way)) << 20) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_ALL \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_SBINV (1 << 19) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BMW (7 << 17) + +enum{ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_LRU, + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_res0, + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW01IF23D, + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW02ID3D +}; +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC (__cache_repl_con) \ + ((__cache_repl_con) << 5) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE (0x10) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE (0x08) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE (0x04) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE (0x02) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE (0x01) + +//--------------------------------------------------------------------------- +// MPU Memory Protection unit + +typedef volatile struct cyghwr_hal_kinetis_mpu_s { + cyg_uint32 cesr; // Control/Error Status Register + cyg_uint8 reserved0[12]; + struct { + cyg_uint32 ear; // Error Address Register, Slave Port n + cyg_uint32 edr; // Error Detail Register, Slave Port n + } slave_port[5]; + cyg_uint8 reserved1[968]; + struct { // Region Descriptors, Word 0..Region Descriptor n, Word 3 + cyg_uint32 word[4]; + }reg_desc[12]; + cyg_uint8 reserved2[832]; + cyg_uint32 reg_daac[12]; // Region Descriptor Alternate Access Control n +} cyghwr_hal_kinetis_mpu_t; + +#define CYGHWR_HAL_KINETIS_MPU_P (cyghwr_hal_kinetis_mpu_t *)0x4000d000 + +//--------------------------------------------------------------------------- +// FlexBus +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS +# include <cyg/hal/var_io_flexbus.h> +#endif + +//---------------------------------------------------------------------------- +// DDRMC - SDRAM controller +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC +# include <cyg/hal/var_io_ddrmc.h> +#endif + +//--------------------------------------------------------------------------- +// GPIO +#include <cyg/hal/var_io_gpio.h> + +//============================================================================= +// DEVS: +// Following macros may also be, and usually are borrwed by some device drivers. +//----------------------------------------------------------------------------- +#include <cyg/hal/var_io_devs.h> + +// End Peripherals + +// Some miscelaneous function prototypes +// Clock related functions are in kinetis_clocking.c +__externC void hal_start_clocks(void); +__externC void hal_update_clock_var(void); + +//----------------------------------------------------------------------------- +// end of var_io.h + +#endif // CYGONCE_HAL_VAR_IO_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h new file mode 100644 index 0000000..9374971 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h @@ -0,0 +1,336 @@ +#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H +#define CYGONCE_HAL_VAR_IOCLKGAT_H +//=========================================================================== +// +// var_io_clkgat.h +// +// Kinetis clock gating +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2013-03-17 +// Purpose: Kinetis clock distribution macros +// Description: +// Usage: This file is included by <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//--------------------------------------------------------------------------- +// Clock distribution + +// SCGC1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M 0x20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S 5 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S 11 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_OSC1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S) + +// SCGC2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S 13 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ENET \ + CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S) + +// SCGC3 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_M 0x100 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M 0x4000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S 14 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M 0x20000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S 17 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S 22 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M 0x8000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S 27 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S 28 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGA \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGB \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_NFC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DDR \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SDHC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_LCDC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC3 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S) + +// SCGC4 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M 0x40 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S 6 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M 0x80 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S 7 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M 0x80000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S 19 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M 0x100000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S 28 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_EWM \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMT \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART3 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBOTG \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMP \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_VREF \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_LLWU \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S) + +// SCGC5 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_M 0x8 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S 3 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M 0x20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S 5 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M 0x200 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S 9 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M 0x4000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S 14 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_LPTIMER \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_REGFILE \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICE \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICESR \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_TSI \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTA \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTB \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTD \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTE \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTF \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S) + +// SCGC6 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_M 0x100000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M 0x200000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S 21 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M 0x400000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S 22 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S 23 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M 0x8000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S 27 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S 28 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M 0x20000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S 29 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTFL \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2S \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_CRC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBHS \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBDCD \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PDB \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PIT \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_RTC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S) + +// SCGC7 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S 2 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS \ + CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMA \ + CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_MPU \ + CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S) + +//----------------------------------------------------------------------------- +// end of var_io_clkgat.h + +#endif // CYGONCE_HAL_VAR_IOCLKGAT_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h new file mode 100644 index 0000000..8090a53 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h @@ -0,0 +1,111 @@ +#ifndef CYGONCE_HAL_VAR_IO_DDRMC_H +#define CYGONCE_HAL_VAR_IO_DDRMC_H +//=========================================================================== +// +// var_io_ddrmc.h +// +// Kinetis DDRam controller specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2012-03-08 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io_ddrmc.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//---------------------------------------------------------------------------- +// DDRMC - SDRAM controller + +# define CYGNUM_HAL_KINETIS_DDRMC_CR_N 64 // Number of DDRMC control registers + +typedef volatile struct cyghwr_hal_kinetis_ddrmc_s { + cyg_uint32 cr[CYGNUM_HAL_KINETIS_DDRMC_CR_N]; // Control registers + cyg_uint32 reserved1[32]; + cyg_uint32 rcr; // RCR control register + cyg_uint32 reserved2[10]; + cyg_uint32 pad_ctrl; // I/O Pad control register +} cyghwr_hal_kinetis_ddrmc_t; + +# define CYGHWR_HAL_KINETIS_DDRMC_P ((cyghwr_hal_kinetis_ddrmc_t *)0x400ae000) + +// RCR +# define CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M 0x40000000 +// PAD CTRL +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_M 0x03000000 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S 20 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT(_x_) \ + VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S, _x_) +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_DIS 0 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_50 3 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_75 1 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_150 2 + +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_M 0x0000000f +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S 0 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY(_x_) \ + VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S, _x_) +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_0BUF 0 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_4BUF 1 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_7BUF 2 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_10BUF 3 + +# define CYGHWR_HAL_KINETIS_DDRMC_CR00_START 0x1 +# define CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL 0x400 + +# define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M 0x0000ffff + +# ifndef CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP +# define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS)| \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M * 0) | \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M * 1) | \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M * 0) | \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M * 0 )) +# endif + +__externC void hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 src[]); +# define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \ + hal_cortexm_kinetis_ddrmc_init(__inidat) +__externC void hal_cortexm_kinetis_ddrmc_diag(void); + +//----------------------------------------------------------------------------- +// end of var_io_ddrmc.h +#endif // CYGONCE_HAL_VAR_IO_DDRMC_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h new file mode 100644 index 0000000..a9acaab --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h @@ -0,0 +1,415 @@ +#ifndef CYGONCE_HAL_VAR_IO_DEVS_H +#define CYGONCE_HAL_VAR_IO_DEVS_H +//=========================================================================== +// +// var_io_devs.h +// +// Variant specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Purpose: Kinetis variant IO provided to various device drivers +// Description: +// Usage: #include <cyg/hal/var_io.h> //var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//============================================================================= +// DEVS: +// Following macros may be, and usually are borrwed by some device drivers. + +// Peripheral clock [Hz]; +__externC cyg_uint32 hal_get_peripheral_clock(void); + +//----------------------------------------------------------------------------- +// Freescale UART +// Borrow some HAL resources to Freescale UART driver +// UART macros are used by both: +// src/hal_diag.c +// devs/serial/<version>/src/ser_freescale_uart.c + +#define CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE 0x4006A000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE 0x4006B000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE 0x4006C000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE 0x4006D000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE 0x400EA000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE 0x400EB000 + +// UART Clock gating + +#define CYGHWR_IO_FREESCALE_UART0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART0 +#define CYGHWR_IO_FREESCALE_UART1_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART1 +#define CYGHWR_IO_FREESCALE_UART2_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART2 +#define CYGHWR_IO_FREESCALE_UART3_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART3 +#define CYGHWR_IO_FREESCALE_UART4_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 +#define CYGHWR_IO_FREESCALE_UART5_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 + +// UART PIN configuration +// Note: May be overriden by plf_io.h + +#define CYGHWR_HAL_KINETIS_PORT_PIN_NONE CYGHWR_HAL_KINETIS_PIN_NONE + +#ifndef CYGHWR_IO_FREESCALE_UART0_PIN_RX +# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART1_PIN_RX +# define CYGHWR_IO_FREESCALE_UART1_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART2_PIN_RX +# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART4_PIN_RX +# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX +# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +// Lend some HAL dependent functions to the UART serial device driver + +#ifndef __ASSEMBLER__ + +# define CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) \ + hal_freescale_uart_setbaud(__uart_p, _baud_) + +# define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \ + hal_set_pin_function(__pin) + + +// Set baud rate +__externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud ); + +#endif + +//--------------------------------------------------------------------------- +// ENET +// Lend some HAL dependent functions to the Ethernet device driver +#define CYGADDR_IO_ETH_FREESCALE_ENET0_BASE (0x400C0000) +// Clock gating +#define CYGHWR_IO_FREESCALE_ENET0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_ENET + +#ifndef __ASSEMBLER__ + +# define CYGHWR_IO_FREESCALE_ENET_PIN(__pin) \ + hal_set_pin_function(__pin) + +#endif + +//---------------------------------------------------------------------------- +// DSPI +// Lend some HAL dependent macros to DSPI device driver + +// DSPI - Peripheral instance base addresses +#define CYGADDR_IO_SPI_FREESCALE_DSPI0_P ((cyghwr_devs_freescale_dspi_t*)0x4002C000) +#define CYGADDR_IO_SPI_FREESCALE_DSPI1_P ((cyghwr_devs_freescale_dspi_t*)0x4002D000) +#define CYGADDR_IO_SPI_FREESCALE_DSPI2_P ((cyghwr_devs_freescale_dspi_t*)0x400AC000) + +#define CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK hal_get_peripheral_clock(); + +#define CYGHWR_IO_FREESCALE_DSPI0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0 +#define CYGHWR_IO_FREESCALE_DSPI1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1 +#define CYGHWR_IO_FREESCALE_DSPI2_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2 + +# define CYGHWR_IO_FREESCALE_DSPI_PIN(__pin) hal_set_pin_function(__pin) + +#ifndef KINETIS_PIN_SPI0_OUT_OPT +#define KINETIS_PIN_SPI0_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M) +#endif +#ifndef KINETIS_PIN_SPI0_CS_OPT +#define KINETIS_PIN_SPI0_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M) +#endif +#ifndef KINETIS_PIN_SPI0_IN_OPT +#define KINETIS_PIN_SPI0_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) +#endif + +#ifndef KINETIS_PIN_SPI1_OUT_OPT +#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M) +#endif +#ifndef KINETIS_PIN_SPI1_CS_OPT +#define KINETIS_PIN_SPI1_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M) +#endif +#ifndef KINETIS_PIN_SPI1_IN_OPT +#define KINETIS_PIN_SPI1_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) +#endif +#ifndef KINETIS_PIN_SPI2_OUT_OPT +#define KINETIS_PIN_SPI2_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M) +#endif +#ifndef KINETIS_PIN_SPI2_CS_OPT +#define KINETIS_PIN_SPI2_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M) +#endif +#ifndef KINETIS_PIN_SPI2_IN_OPT +#define KINETIS_PIN_SPI2_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) +#endif + +//--------------------------------------------------------------------------- +// I2C +// Lend some HAL dependent macros to I2C device driver +// Base pointers +#define CYGADDR_IO_I2C_FREESCALE_I2C0_BASE (0x40066000) +#define CYGADDR_IO_I2C_FREESCALE_I2C1_BASE (0x40067000) +// Clocking +#define CYGHWR_IO_I2C_FREESCALE_I2C_CLOCK hal_get_peripheral_clock() +#define CYGHWR_IO_FREESCALE_I2C0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0 +#define CYGHWR_IO_FREESCALE_I2C1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1 +// Pins +# define CYGHWR_IO_FREESCALE_I2C_PIN(__pin) hal_set_pin_function(__pin) + +# ifndef CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE +// Fix an error in Kinetis I2C Manual. There is an unconfirmed +// error in Kinetis I2C divider and hold value table. +#if 0 // Values as are in Kinetis Reference Manuals +#define I2C_FREQ_TABLE_ENTRY_8 28 +#define I2C_FREQ_TABLE_ENTRY_9 32 +#else // Values that give correct result according to measurements +#define I2C_FREQ_TABLE_ENTRY_8 30 +#define I2C_FREQ_TABLE_ENTRY_9 34 +#endif +typedef cyg_uint16 dev_i2c_freescale_frequency_entry_t; +# define CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE \ + 20, 22, 24, 26, 28, 30, 34, 40, I2C_FREQ_TABLE_ENTRY_8, I2C_FREQ_TABLE_ENTRY_9, \ + 36, 40, 44, 48, 56, 68, 48, 56, 64, \ + 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, 160, 192, 224, \ + 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768, \ + 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840 + + +# endif // CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE + +// DMA MUX ------------------------------------------------------------------ +// DMAMUX DMA request sources +#define FREESCALE_DMAMUX_SRC_KINETIS_DISABLE 0 +#define FREESCALE_DMAMUX_SRC_KINETIS_RESERVE 1 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART0R 2 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART0T 3 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART1R 4 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART1T 5 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART2R 6 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART2T 7 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART3R 8 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART3T 9 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART4R 10 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART4T 11 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART5R 12 +#define FREESCALE_DMAMUX_SRC_KINETIS_UART5T 13 +#define FREESCALE_DMAMUX_SRC_KINETIS_I2S0R 14 +#define FREESCALE_DMAMUX_SRC_KINETIS_I3S0T 15 +#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0R 16 +#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0T 17 +#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1R 18 +#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1T 19 +#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2R 20 +#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2T 21 +#define FREESCALE_DMAMUX_SRC_KINETIS_I2C0 22 +#define FREESCALE_DMAMUX_SRC_KINETIS_I2C1 23 // Either I2C1 +#define FREESCALE_DMAMUX_SRC_KINETIS_I2C2 23 // or I2C2 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C0 24 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C1 25 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C2 26 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C3 27 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C4 28 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C5 29 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C6 30 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C7 31 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C0 32 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C1 33 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C0 34 +#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C1 35 +#define FREESCALE_DMAMUX_SRC_KINETIS_1588T0 36 +#define FREESCALE_DMAMUX_SRC_KINETIS_1588T1 37 +#define FREESCALE_DMAMUX_SRC_KINETIS_1588T2 38 +#define FREESCALE_DMAMUX_SRC_KINETIS_1588T3 39 +#define FREESCALE_DMAMUX_SRC_KINETIS_ADC0 40 +#define FREESCALE_DMAMUX_SRC_KINETIS_ADC1 41 +#define FREESCALE_DMAMUX_SRC_KINETIS_CMP0 42 +#define FREESCALE_DMAMUX_SRC_KINETIS_CMP1 43 +#define FREESCALE_DMAMUX_SRC_KINETIS_CMP2 44 +#define FREESCALE_DMAMUX_SRC_KINETIS_DAC0 45 +#define FREESCALE_DMAMUX_SRC_KINETIS_DAC1 46 +#define FREESCALE_DMAMUX_SRC_KINETIS_CMT 47 +#define FREESCALE_DMAMUX_SRC_KINETIS_PDB 48 +#define FREESCALE_DMAMUX_SRC_KINETIS_PORTA 49 +#define FREESCALE_DMAMUX_SRC_KINETIS_PORTB 50 +#define FREESCALE_DMAMUX_SRC_KINETIS_PORTC 51 +#define FREESCALE_DMAMUX_SRC_KINETIS_PORTD 52 +#define FREESCALE_DMAMUX_SRC_KINETIS_PORTE 53 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX0 54 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX1 55 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX2 56 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX3 57 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX4 58 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX5 59 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX6 60 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX7 61 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX8 62 +#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX9 63 + +// DMAMUX1 DMA request sources +#define FREESCALE_DMAMUX1_SRC_KINETIS_DISABLE 0 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE 1 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0R 2 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0T 3 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1R 4 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1T 5 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2R 6 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2T 7 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3R 8 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3T 9 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4R 10 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4T 11 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5R 12 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5T 13 +#define FREESCALE_DMAMUX1_SRC_KINETIS_I2S0R 14 +#define FREESCALE_DMAMUX1_SRC_KINETIS_I3S0T 15 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0R 16 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0T 17 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1R 18 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1T 19 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2R 20 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2T 21 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_22 22 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_23 23 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C0 24 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C1 25 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C2 26 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C3 27 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C4 28 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C5 29 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C6 30 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C7 31 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_32 32 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_33 33 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_34 34 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_35 35 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T0 36 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T1 37 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T2 38 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T3 39 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC0 40 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC1 41 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC2 42 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC3 43 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_44 44 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC0 45 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC1 46 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP0 47 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP1 48 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP2 49 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP3 50 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_51 51 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_52 52 +#define FREESCALE_DMAMUX1_SRC_KINETIS_PORTF 53 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX0 54 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX1 55 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX2 56 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX3 57 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX4 58 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX5 59 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX6 60 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX7 61 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX8 62 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX9 63 + +#define FREESCALE_DMAMUX_SRC_SPI0_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI0R +#define FREESCALE_DMAMUX_SRC_SPI0_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI0T +#define FREESCALE_DMAMUX_SRC_SPI1_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI1R +#define FREESCALE_DMAMUX_SRC_SPI1_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI1T +#define FREESCALE_DMAMUX_SRC_SPI2_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI2R +#define FREESCALE_DMAMUX_SRC_SPI2_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI2T + +//---------------------------------------------------------------------------- +// eDMA +// Lend some eDMA macros to device driver that use DMA + +// Base address +#define CYGHWR_HAL_FREESCALE_EDMA0_P ((cyghwr_hal_freescale_edma_t *)0x40008000) +// DMAMUX base addresses +#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000) +#define CYGHWR_HAL_FREESCALE_DMAMUX1_P ((cyghwr_hal_freescale_dmamux_t *) 0x40022000) + +#define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P +#define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P +#define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P + +//Clock distribution +#define CYGHWR_IO_CLOCK_ENABLE(__scgc) hal_clock_enable(__scgc) + +#define CYGHWR_IO_FREESCALE_EDMA0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMA +#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 +#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 +#define CYGHWR_IO_FREESCALE_DMAMUX1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1 +//----------------------------------------------------------------------------- +// end of var_io_devs.h +#endif // CYGONCE_HAL_VAR_IO_DEVS_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h new file mode 100644 index 0000000..6c303af --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h @@ -0,0 +1,173 @@ +#ifndef CYGONCE_HAL_VAR_IO_FLEXBUS_H +#define CYGONCE_HAL_VAR_IO_FLEXBUS_H +//=========================================================================== +// +// var_io_flexbus.h +// +// Kinetis FlexBus specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//--------------------------------------------------------------------------- +// FlexBus + +// FlexBus chip select control registers +typedef struct cyghwr_hal_kinetis_fbcs_s{ + cyg_uint32 csar; // Chip select address register + cyg_uint32 csmr; // Chip select mask register + cyg_uint32 cscr; // Chip select control register +} cyghwr_hal_kinetis_fbcs_t; + +#define CYGNUM_HAL_KINETIS_FBCS_N 6 // Kinetis has up to 6 chip selects + +// FlexBus control +typedef volatile struct cyghwr_hal_kinetis_fb_s { + cyghwr_hal_kinetis_fbcs_t csel[CYGNUM_HAL_KINETIS_FBCS_N]; //Chip Selects + cyg_uint8 reserved[24]; + cyg_uint32 cspmcr; //Chip select port multiplexing control register +} cyghwr_hal_kinetis_fb_t; + +#define CYGHWR_HAL_KINETIS_FB_P ((cyghwr_hal_kinetis_fb_t *) 0x4000C000) + +// CSAR - Chip Select Address Register +// CSAR Bit Fields +#define CYGHWR_HAL_FB_CSAR_BA_M 0xFFFF0000 +#define CYGHWR_HAL_FB_CSAR_BA_S 16 +#define CYGHWR_HAL_FB_CS_AR_BA(__val) VALUE_(CYGHWR_HAL_FB_CSAR_BA_S, __val) + +// CSMR - Chup Select Mask Register +// CSMR Bit Fields +#define CYGHWR_HAL_FB_CSMR_V_M 0x1 +#define CYGHWR_HAL_FB_CSMR_V_S 0 +#define CYGHWR_HAL_FB_CSMR_WP_M 0x100 +#define CYGHWR_HAL_FB_CSMR_WP_S 8 +#define CYGHWR_HAL_FB_CSMR_BAM_M 0xFFFF0000 +#define CYGHWR_HAL_FB_CSMR_BAM_S 16 +#define CYGHWR_HAL_FB_CS_MR_BAM(__val) VALUE_(CYGHWR_HAL_FB_CSMR_BAM_S, __val) + +// CSCR - Chip Select Control register +// CSCR Bit Fields +#define CYGHWR_HAL_FB_CSCR_BSTW_M 0x8 +#define CYGHWR_HAL_FB_CSCR_BSTW_S 3 +#define CYGHWR_HAL_FB_CSCR_BSTR_M 0x10 +#define CYGHWR_HAL_FB_CSCR_BSTR_S 4 +#define CYGHWR_HAL_FB_CSCR_BEM_M 0x20 +#define CYGHWR_HAL_FB_CSCR_BEM_S 5 +#define CYGHWR_HAL_FB_CSCR_PS_M 0xC0 +#define CYGHWR_HAL_FB_CSCR_PS_S 6 +#define CYGHWR_HAL_FB_CSCR_AA_M 0x100 +#define CYGHWR_HAL_FB_CSCR_AA_S 8 +#define CYGHWR_HAL_FB_CSCR_BLS_M 0x200 +#define CYGHWR_HAL_FB_CSCR_BLS_S 9 +#define CYGHWR_HAL_FB_CSCR_WS_M 0xFC00 +#define CYGHWR_HAL_FB_CSCR_WS_S 10 +#define CYGHWR_HAL_FB_CSCR_WRAH_M 0x30000 +#define CYGHWR_HAL_FB_CSCR_WRAH_S 16 +#define CYGHWR_HAL_FB_CSCR_RDAH_M 0xC0000 +#define CYGHWR_HAL_FB_CSCR_RDAH_S 18 +#define CYGHWR_HAL_FB_CSCR_ASET_M 0x300000 +#define CYGHWR_HAL_FB_CSCR_ASET_S 20 +#define CYGHWR_HAL_FB_CSCR_EXALE_M 0x400000 +#define CYGHWR_HAL_FB_CSCR_EXALE_S 22 +#define CYGHWR_HAL_FB_CSCR_SWSEN_M 0x800000 +#define CYGHWR_HAL_FB_CSCR_SWSEN_S 23 +#define CYGHWR_HAL_FB_CSCR_SWS_M 0xFC000000 +#define CYGHWR_HAL_FB_CSCR_SWS_S 26 + +// CSPMCR Bit Fields +#define CYGHWR_HAL_FB_CSPMCR_G5_M 0xF000 +#define CYGHWR_HAL_FB_CSPMCR_G5_S 12 +#define CYGHWR_HAL_FB_CSPMCR_G4_M 0xF0000 +#define CYGHWR_HAL_FB_CSPMCR_G4_S 16 +#define CYGHWR_HAL_FB_CSPMCR_G3_M 0xF00000 +#define CYGHWR_HAL_FB_CSPMCR_G3_S 20 +#define CYGHWR_HAL_FB_CSPMCR_G2_M 0xF000000 +#define CYGHWR_HAL_FB_CSPMCR_G2_S 24 +#define CYGHWR_HAL_FB_CSPMCR_G1_M 0xF0000000 +#define CYGHWR_HAL_FB_CSPMCR_G1_S 28 + +// FlexBus control pin multiplexing +#define CYGHWR_HAL_FB_CSPMCR(__group, __val) VALUE_(__group, __val) + +#define CYGHWR_HAL_FB_CSPMCR_G1_ALE \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G1_CS1 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G1_TS \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G2_CS4 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G2_TSIZ0 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G3_CS5 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G3_TSIZ1 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G4_TST \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G4_CS2 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G4_BE_15_8 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G5_TA \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G5_CS3 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G5_BE_7_0 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 2) + +//----------------------------------------------------------------------------- +// end of var_io_flexbus.h +#endif // CYGONCE_HAL_VAR_IO_FLEXBUS_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h new file mode 100644 index 0000000..349e351 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h @@ -0,0 +1,123 @@ +#ifndef CYGONCE_HAL_VAR_IO_GPIO_H +#define CYGONCE_HAL_VAR_IO_GPIO_H +//=========================================================================== +// +// var_io_gpio.h +// +// Kinetis GPIO +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tomas Frydrych <tomas@sleepfive.com> +// Date: 2011-11-14 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//--------------------------------------------------------------------------- +// GPIO +typedef volatile struct cyghwr_hal_kinetis_gpio_s { + cyg_uint32 pdor; + cyg_uint32 psor; + cyg_uint32 pcor; + cyg_uint32 ptor; + cyg_uint32 pdir; + cyg_uint32 pddr; +} cyghwr_hal_kinetis_gpio_t; + +// PTA-PTE base pointers +#define CYGHWR_HAL_KINETIS_GPIO_PORTA_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF000u) +#define CYGHWR_HAL_KINETIS_GPIO_PORTB_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF040u) +#define CYGHWR_HAL_KINETIS_GPIO_PORTC_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF080u) +#define CYGHWR_HAL_KINETIS_GPIO_PORTD_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF0C0u) +#define CYGHWR_HAL_KINETIS_GPIO_PORTE_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF100u) +#define CYGHWR_HAL_KINETIS_GPIO_PORTF_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF140u) + +// GPIO register on a given port (register name is lower case) +#define CYGHWR_HAL_KINETIS_GPIO(__port, __reg) \ + (CYGHWR_HAL_KINETIS_GPIO_PORT##__port##_P)->__reg + +// Get values for entire port +#define CYGHWR_HAL_KINETIS_GPIO_GET(__port) \ + CYGHWR_HAL_KINETIS_GPIO(__port, pdir) + +// Output values for entire port +#define CYGHWR_HAL_KINETIS_GPIO_PUT(__port, __val) \ + CYGHWR_HAL_KINETIS_GPIO(__port, pdor) = __val + +// Set values for entire port based on bitmask +#define CYGHWR_HAL_KINETIS_GPIO_SET(__port, __val) \ + CYGHWR_HAL_KINETIS_GPIO(__port, psor) = __val + +// Clear values for entire port based on bitmask +#define CYGHWR_HAL_KINETIS_GPIO_CLEAR(__port, __val) \ + CYGHWR_HAL_KINETIS_GPIO(__port, pcor) = __val + +// Toggle values for entire port based on bitmask +#define CYGHWR_HAL_KINETIS_GPIO_TOGGLE(__port, __val) \ + CYGHWR_HAL_KINETIS_GPIO(__port, ptor) = __val + +// Get value for a single pin on given port +#define CYGHWR_HAL_KINETIS_GPIO_GET_PIN(__port, __pin) \ + (BIT_(__pin) & CYGHWR_HAL_KINETIS_GPIO_GET(__port)) + +// Set a single pin on a given register +#define CYGHWR_HAL_KINETIS_GPIO_SET_PIN(__port, __pin) \ + CYGHWR_HAL_KINETIS_GPIO_SET(__port, BIT_(__pin)) + +// Clear a single pin on a given register +#define CYGHWR_HAL_KINETIS_GPIO_CLEAR_PIN(__port, __pin) \ + CYGHWR_HAL_KINETIS_GPIO_CLEAR(__port, BIT_(__pin)) + +// Toggle a single pin on a given register +#define CYGHWR_HAL_KINETIS_GPIO_TOGGLE_PIN(__port, __pin) \ + CYGHWR_HAL_KINETIS_GPIO_TOGGLE(__port, BIT_(__pin)) + +// Set pin data direction +#define CYGHWR_HAL_KINETIS_GPIO_PIN_DDR_OUT(__port, __pin) \ + CYGHWR_HAL_KINETIS_GPIO(__port, pddr) |= BIT_(__pin) + +#define CYGHWR_HAL_KINETIS_GPIO_PIN_DDR_IN(__port, __pin) \ + CYGHWR_HAL_KINETIS_GPIO(__port, pddr) &= ~BIT_(__pin) + +//----------------------------------------------------------------------------- +// end of var_io_gpio.h +#endif // CYGONCE_HAL_VAR_IO_GPIO_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h new file mode 100644 index 0000000..cbdd067 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h @@ -0,0 +1,302 @@ +#ifndef CYGONCE_HAL_VAR_IO_LMEM_H +#define CYGONCE_HAL_VAR_IO_LMEM_H +//=========================================================================== +// +// var_io_lmem.h +// +// Kinetis Local memory controller specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2012-04-28 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io_lmem.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//---------------------------------------------------------------------------- +// LMEM - Local memory controller + +typedef volatile struct cyghwr_hal_kinetis_lmem_s { + cyg_uint32 ccr; // Cache control register + cyg_uint32 clcr; // Cache line control register + void *csar; // Cache search address register + cyg_uint32 cvr; // Cache read/write value register + cyg_uint8 reserved[16]; + cyg_uint32 rmr; // Cache regions mode register +} cyghwr_hal_kinetis_lmem_t; + +#define CYGHWR_HAL_KINETIS_LMEM_PC_P ((cyghwr_hal_kinetis_lmem_t *) 0xE0082000) +#define CYGHWR_HAL_KINETIS_LMEM_PS_P ((cyghwr_hal_kinetis_lmem_t *) 0xE0082800) + +// CCR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M 0x1 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M 0x2 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M 0x1000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M 0x2000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M 0x4000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M 0x8000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M 0x80000000 + +//CLCR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M 0x1 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_M 0xFFC +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S 2 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR(_ca_) \ + ((_ca_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S) +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_WSEL_M 0x4000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M 0x10000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIVB_M 0x100000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIMB_M 0x200000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCWAY_M 0x400000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S 24 + +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(_cmd_) \ + ((_cmd_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S) +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_SRCH 0 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL 1 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_PUSH 2 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_CLR 3 + +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M 0x4000000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LACC_M 0x8000000 + +// CSAR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_LGO_M 0x1 +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_M 0xFFFFFFFC +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S 2 +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR(_adr_) \ + ((_adr_) << CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S) + +// CCVR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CCVR_DATA_M 0xFFFFFFFF + +// PCCRMR Bit Fields + +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_M 0x3 +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION(_region_,_mask_) \ + ((_mask_) << ((15 - (_region_)) * 2)) + +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M 0 +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M 2 +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M 3 + +#define CYGHWR_HAL_KINETIS_LMEM_FLASH_0000 0 +#define CYGHWR_HAL_KINETIS_LMEM_DRAM_0800 1 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXNVM_1000 2 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_1800 3 +#define CYGHWR_HAL_KINETIS_LMEM_SRAM_L 4 +#define CYGHWR_HAL_KINETIS_LMEM_SRAM_U 5 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_6000 6 +#define CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 7 +#define CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 8 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_9000 9 + +#define HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() \ + hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE() \ + hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() \ + hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE() \ + hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() \ + hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALL() \ + hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() \ + hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_SYNC() \ + hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() \ + hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR() \ + hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED() \ + hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() \ + hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_SRCH(_base, _size_) \ + hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_SRCH) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base, _size_) \ + hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_PUSH(_base, _size_) \ + hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_PUSH) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_CLR(_base, _size_) \ + hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_CLR) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base, _size_) \ + hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PC_P, _base, _size_, \ + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL) + +#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK && defined CYG_HAL_STARTUP_RAM + +#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p) \ +CYG_MACRO_START \ + cyg_uint32 prs_tmp, prs_save; \ + cyg_uint32 m0, m1; \ + cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P; \ + prs_save = prs_tmp = _axbs_p->slave[5].prs; \ + m0 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(0, prs_tmp); \ + m1 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(1, prs_tmp); \ + if(m1 > m0) { \ + prs_tmp &= ~(CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(0) | \ + CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(1)); \ + prs_tmp |= (m0 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(1)) | m1; \ + _axbs_p->slave[5].prs = prs_tmp; \ + } \ + while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M); \ + _axbs_p->slave[5].prs = prs_save; \ +CYG_MACRO_END + +#else // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK + +#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p) \ + while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M) + +#endif // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_enable(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr = ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_disable(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr = 0; +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_inval(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_store(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_clear(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_sync(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + hal_cortexm_kinetis_cache_store(lmem_p); + hal_cortexm_kinetis_cache_clear(lmem_p); +} + +CYGBLD_FORCE_INLINE bool +hal_cortexm_kinetis_cache_is_enabled(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + return lmem_p->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M; +} + + +CYGBLD_FORCE_INLINE void +hal_cortexm_kinetis_cache_lines(cyghwr_hal_kinetis_lmem_t* lmem_p, + cyg_uint8* addr_p, cyg_uint32 size, + const cyg_uint32 oper) +{ + cyg_uint32 line_k; + line_k = (((cyg_uint32)addr_p & (HAL_DCACHE_LINE_SIZE-1)) + size) / HAL_DCACHE_LINE_SIZE + 1; + + lmem_p->clcr = CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M | + CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M | + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(oper); + + addr_p = (cyg_uint8*)((((cyg_uint32) addr_p) & 0xfffffff0) | + CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M); + do { + lmem_p->csar = addr_p; + while(lmem_p->clcr & CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M); + addr_p += HAL_DCACHE_LINE_SIZE; + } while(--line_k); +} + +//----------------------------------------------------------------------------- +// end of var_io_lmem.h +#endif // CYGONCE_HAL_VAR_IO_LMEM_H diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/variant.inc b/ecos/packages/hal/cortexm/kinetis/var/current/include/variant.inc new file mode 100644 index 0000000..11875f2 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/variant.inc @@ -0,0 +1,53 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, ilijak +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_kinetis.h> + +//========================================================================== +// EOF variant.inc diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c new file mode 100644 index 0000000..caadc51 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c @@ -0,0 +1,410 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-04 +// Purpose: HAL diagnostic input/output +// Description: Implementations of HAL diagnostic input/output support. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + */ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/var_io.h> // +#include <cyg/io/ser_freescale_uart.h> // UART registers + +//----------------------------------------------------------------------------- + +typedef struct { + cyg_uint32 uart; + CYG_ADDRESS base; + cyg_int32 msec_timeout; + cyg_int32 isr_vector; + cyg_uint32 rx_pin; + cyg_uint32 tx_pin; + cyg_uint32 clock_gate; + cyg_int32 baud_rate; + cyg_int32 irq_state; +} channel_data_t; + +channel_data_t plf_ser_channels[] = { +#ifdef CYGINT_HAL_FREESCALE_UART0 + { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART0_RX_TX, + CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX, + CYGHWR_IO_FREESCALE_UART0_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART1 + { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART1_RX_TX, + CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX, + CYGHWR_IO_FREESCALE_UART1_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART2 + { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART2_RX_TX, + CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX, + CYGHWR_IO_FREESCALE_UART2_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART3 + { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART3_RX_TX, + CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX, + CYGHWR_IO_FREESCALE_UART3_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART4 + { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART4_RX_TX, + CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX, + CYGHWR_IO_FREESCALE_UART4_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART5 + { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART5_RX_TX, + CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX, + CYGHWR_IO_FREESCALE_UART5_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } +#endif +}; + +#if defined(CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION) && \ + CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION +# define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR \ + CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +#else +# define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +#endif + +//----------------------------------------------------------------------------- + +void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_putc(void *__ch_data, char c); + + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = chan->base; + + // Bring clock to the device + CYGHWR_IO_CLOCK_ENABLE(chan->clock_gate); + // Configure PORT pins + hal_set_pin_function(chan->rx_pin); + hal_set_pin_function(chan->tx_pin); + + // 8-1-no parity. + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C1, 0); + CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_p, chan->baud_rate); + // Enable RX and TX + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, + (CYGHWR_DEV_FREESCALE_UART_C2_TE | + CYGHWR_DEV_FREESCALE_UART_C2_RE)); +} + +void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_putc(void* __ch_data, char ch_out) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint32 uart_s1; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)); + + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint8 uart_s1; + cyg_uint8 ch_in; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + if (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF)) + return false; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + *p_ch_in = ch_in; + + return true; +} + +cyg_uint8 CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + + +//============================================================================= +// Virtual vector HAL diagnostics + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in) +{ + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + // delay in .1 ms steps + delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10; + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base; + cyg_uint8 ser_port_reg; + int ret = 0; + va_list ap; + + CYGARC_HAL_SAVE_GP(); + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->irq_state; + chan->irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + cyg_hal_plf_serial_init_channel(chan); + ret = 0; + break; + default: + break; + } + + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint8 uart_s1; + int res = 0; + cyg_uint8 ch_in; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + if( cyg_hal_is_break( (char *) &ch_in , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + int chan_i; + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Init channels + for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) { + cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]); + + // Setup procs in the vector table + CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + } + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) + plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; + update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] ); +#endif +} + +void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + cyg_hal_plf_serial_init(); +} + +#else // !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) +//============================================================================= +// Non-Virtual vector HAL diagnostics + +// #if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +void hal_plf_diag_init(void) +{ + cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +void hal_plf_diag_putc(char c) +{ + cyg_hal_plf_serial_putc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c); +} + +cyg_uint8 hal_plf_diag_getc(void) +{ + return cyg_hal_plf_serial_getc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +//----------------------------------------------------------------------------- +// End of hal_diag.c diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c new file mode 100644 index 0000000..65d26e5 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c @@ -0,0 +1,463 @@ +//========================================================================== +// +// kinetis_clocking.c +// +// Cortex-M Kinetis HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija kocho <ilijak@siva.com.mk> +// Date: 2011-10-19 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +#include <cyg/io/ser_freescale_uart.h> + +//=========================================================================== +// Forward declarations +//=========================================================================== + +cyg_uint32 hal_cortexm_systick_clock; +cyg_uint32 hal_kinetis_sysclk; +cyg_uint32 hal_kinetis_busclk; + +cyg_uint32 hal_get_cpu_clock(void); + +void hal_start_main_clock(void); +void hal_set_clock_dividers(void); +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC +void hal_start_rtc_clock(void); +#endif + + +//========================================================================== +// Setup up system clocks +// +// Set up clocks from configuration. In the future this should be extended so +// that clock rates can be changed at runtime. + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_clocks( void ) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT + cyghwr_hal_kinetis_port_t *port_p = CYGHWR_HAL_KINETIS_PORTA_P; +#endif +#if !defined(CYG_HAL_STARTUP_RAM) +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC + // Real Time Clock + hal_start_rtc_clock(); +# endif + hal_set_clock_dividers(); + // Main clock - MCG + hal_start_main_clock(); +#endif + // Trace clock +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK_CORE + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M; +#else + sim_p->sopt2 &= ~CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M; +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT + port_p->pcr[6] = CYGHWR_HAL_KINETIS_PORT_PCR_MUX(0x7); +#endif +} + + +#define MCG_WAIT_WHILE(_condition_) do{}while(_condition_) + +// Setup MCG +// Note: Currently only PBE mode is supported and tested. + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + +// MCG can have 1 or 2 PLL oscillators. +// PLL0 aka PLL is always present. +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_pll0(cyghwr_hal_kinetis_mcg_t *mcg_p) +{ + mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) | + CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 + | CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M +# endif //CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 + ; +# if CYGINT_HAL_CORTEXM_KINETIS_150 + mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-16); +# else + mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24); +# endif + mcg_p->c5 |= CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M; + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M)); +} +#endif //CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + +// PLL1 Oscillator is present on some devices. +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_pll1(cyghwr_hal_kinetis_mcg_t *mcg_p) +{ + mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M; + mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV-1) | + CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 + | CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M +# endif +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1 + | CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M +# endif + ; + mcg_p->c12 = CYGHWR_HAL_KINETIS_MCG_C12_VDIV1( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV-16); + mcg_p->c11 |= CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M; + MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M)); +} +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + +// There are 1 or 2 external oscillators +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_ext_ref(void) +{ + volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P; + +# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || \ + defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_0 +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + // Set the oscillator 0 + *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2; +# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC + // Select external oscillator + *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M | + CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M; +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL +# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || ... + +# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || \ + defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1 +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL + // Set the oscillator 1 + osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_P; + *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP / 2; +# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_OSC + // Select external oscillator + *osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_ERCLKEN_M | + CYGHWR_HAL_KINETIS_OSC1_CR_EREFSTEN_M; +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL +# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || ... +} +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_main_clock(void) +{ + cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; +#if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL ||\ + defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 ||\ + (defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC &&\ + CYGHWR_HAL_CORTEXM_KINETIS_REV == 1) + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; +#endif + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + // Select RTC clock source for MCG reference +# if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1 + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M; +# elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + mcg_p->c7 |= CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M; +# endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + hal_start_ext_ref(); +# endif + +#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + + mcg_p->c2 = CYGHWR_HAL_KINETIS_MCG_C2_RANGE( + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE) +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + | CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M | CYGHWR_HAL_KINETIS_MCG_C2_HGO_M +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + ; + + mcg_p->c1 = CYGHWR_HAL_KINETIS_MCG_C1_FRDIV( + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG) +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + |CYGHWR_HAL_KINETIS_MCG_C1_CLKS(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF) +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL* + ; + +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + // Wait for oscillator start up + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M)); +# endif +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL + // Wait for oscillator 1 start up + MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M)); +# endif +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + // Wait for reference clock to switch to external reference + MCG_WAIT_WHILE(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_IREFST_M); + // Wait for status flags update + MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT +# else + CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL +# endif + ); +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL + // Configure FLL + mcg_p->c4 = (mcg_p->c4 & 0x1f) | + (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 | + CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS( + CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS)); + +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL + +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + hal_start_pll0(mcg_p); +# endif +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + hal_start_pll1(mcg_p); +# endif +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1) + // Switch to PBE mode + mcg_p->c6 |= CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M; + + MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != + CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT); + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_PLLST_M)); +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M)); +# endif +# if defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M)); +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + + // Enter PEE mode + mcg_p->c1 &= ~CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M; + MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != + CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL); +# endif // defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL* + +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M; +# endif + +#endif // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || + // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || + // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || + // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) +} + +cyg_uint32 CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_get_cpu_clock(void) +{ + cyg_uint32 freq; +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL + cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; + +# if CYGINT_HAL_CORTEXM_KINETIS_150 + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) * + ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+16) / 2; +# else + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) * + ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+24); +# endif +#elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 + cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; + + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ((mcg_p->c11 & CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M)+1) * + ((mcg_p->c12 & CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M)+16) / 2; +#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV; +#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + freq = CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC; +#else // ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_none +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_end + + return freq; +} + + +// Clock dividers provide clock sources for various peripherals. + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_set_clock_dividers(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + + sim_p->clk_div1 = CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(0) | + CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2( + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS-1) | + CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3( + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS-1) | + CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4( + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH-1); + + sim_p->clk_div2 = CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV( + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV-1) | + (CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC==2 ? + CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M : 0); +} + +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_rtc_clock(void) +{ + cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P; + + rtc_p->ier=0; // Disable RTC interrupts + + //Start RTC clock if not already started + if(!(rtc_p->cr & CYGHWR_HAL_KINETIS_RTC_CR_OSCE)){ + rtc_p->cr = CYGHWR_HAL_KINETIS_RTC_CR_OSCE | + CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP; +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + { + volatile cyg_uint32 busycnt; + for(busycnt=1000000; busycnt; busycnt--) + __asm__ volatile ("nop\n"); + } +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + } +} +#endif + + +//========================================================================== +// UART baud rate +// +// Set the baud rate divider of a UART based on the requested rate and +// the current clock settings. + + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud) +{ + cyg_uint32 sbr, brfa; + cyg_uint32 regval; + + switch(uart_p) { + case CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE: + sbr = hal_kinetis_sysclk/(16*baud); + break; + case CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE: + sbr = hal_kinetis_busclk/(16*baud); + break; + default: + sbr=0; + break; + } + if(sbr) { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval); + regval &= 0xE0; + regval |= sbr >> 8; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval); + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF)); + brfa = (((32*hal_kinetis_busclk)/(16*baud))-(32*sbr)); + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval); + regval &= 0xE0; + regval |= brfa & 0x1f; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval); + } +} + + +void hal_update_clock_var(void) +{ + hal_kinetis_sysclk=hal_get_cpu_clock(); + hal_kinetis_busclk=hal_kinetis_sysclk / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS; + hal_cortexm_systick_clock=hal_kinetis_sysclk; +} + + +cyg_uint32 hal_get_peripheral_clock(void) +{ + return hal_kinetis_busclk; +} + +//========================================================================== +// EOF kinetis_clocking.c diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c new file mode 100644 index 0000000..2b934cf --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c @@ -0,0 +1,129 @@ +//========================================================================== +// +// kinetis_ddram.c +// +// Cortex-M Kinetis HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija kocho <ilijak@siva.com.mk> +// Date: 2012-03-08 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +// DDRAM Controller +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +// DDRAM controller register indices. +const cyg_uint8 const kinetis_ddr_reg_ix[] = { + 0, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 20, 21, 22, 23, + 25, 26, 27, 28, 29, 30, + 34, + 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, + 52, 53, 54, 55, 56, 57 +}; + +// Initialize DDRAM controller. +// inidat[] is an array of ordered pairs: (register-index, register-value). +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 inidat[]) +{ + cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P; + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + volatile cyg_uint32* cr_p; + cyg_uint32 cr_ix; + cyg_uint32 cr_i; + cyg_uint32 regval; + + CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_DDR); + + regval = sim_p->mcr & ~CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M; + sim_p->mcr = regval | CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP; + + ddrmc_p->rcr |= CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M; + ddrmc_p->pad_ctrl = CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL; + cr_p = ddrmc_p->cr; + for(cr_ix = 0; cr_ix < sizeof(kinetis_ddr_reg_ix); cr_ix++) { + cr_i = kinetis_ddr_reg_ix[cr_ix]; + cr_p[cr_i] = *inidat++; + }; + __asm__ volatile ("nop\n"); + ddrmc_p->cr[0] |= CYGHWR_HAL_KINETIS_DDRMC_CR00_START; + while(!(ddrmc_p->cr[30] & CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL)); +} + +void +hal_cortexm_kinetis_ddrmc_diag(void) +{ + cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P; + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + volatile cyg_uint32* cr_p; + cyg_uint32 cr_i; + + diag_printf("SCGC3 = 0x%08x, MCR = 0x%08x\n", sim_p->scgc3, sim_p->mcr); + diag_printf("RCR= 0x%08x, PAD_CTRL= 0x%08x\n", ddrmc_p->rcr, ddrmc_p->pad_ctrl); + cr_p = ddrmc_p->cr; + for(cr_i=0; cr_i < 64; cr_i++){ + diag_printf(" CR%02d = 0x%08x\n", cr_i, cr_p[cr_i]); + } +} + +#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +//========================================================================== +// EOF kinetis_ddram.c diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c new file mode 100644 index 0000000..391c034 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c @@ -0,0 +1,309 @@ +//========================================================================== +// +// kinetis_misc.c +// +// Cortex-M Kinetis HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +#include <cyg/hal/hal_cache.h> + +void sst25xx_freescale_dspi_reg(void); + +#if defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM + +//=========================================================================== +// KINETIS FLASH configuration field +//=========================================================================== + +// Note: KINETIS FLASH configuration field must be present in Kinetis flash +// image and ocupy addresses 0x00000400 to 0x0000040f. + +// For ".flash_conf" section definition see MLT files. + +const cyghwr_hal_kinetis_flash_conf_t CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD +__attribute__((section(".flash_conf"), used)) = { + .backdoor_key = CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY, + .fprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT, + .fsec = CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC, + .fopt = CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT, + .feprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT, + .fdprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT +}; + +const cyghwr_hal_kinetis_flash_conf_t * +CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_kinetis_flash_conf_p( void ) +{ + return &CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD; +} + +#endif // defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM + +//=== KINETIS FLASH security configuration END. ============================ + +#if defined CYGPKG_HAL_KINETIS_CACHE + +// Function for demotion of caching memory regions +static void +hal_cortexm_kinetis_conf_cache_regions(cyghwr_hal_kinetis_lmem_t* lmem_p, + cyg_uint32 reg_n, const cyg_uint32 *reg_mode_p) +{ + cyg_uint32 region; + cyg_uint32 mode; + cyg_uint32 regval; + cyg_uint32 reg_mode; + + regval = lmem_p->rmr; + for(; reg_n; reg_n--){ + reg_mode = *reg_mode_p++; + region = reg_mode >> 16; + mode = reg_mode & 0x0000ffff; + regval &= ~(0x3 << (15-region)*2); + regval |= mode << (15-region)*2; + } + lmem_p->rmr = regval; +} + +const cyg_uint32 cache_reg_modes_pc[] = { + (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, + + (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M +}; + +const cyg_uint32 cache_reg_modes_ps[] = { + (CYGHWR_HAL_KINETIS_LMEM_FLASH_0000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, + + (CYGHWR_HAL_KINETIS_LMEM_DRAM_0800 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, + + (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) | +#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_WRITETHRU + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M, +#elif defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M, +#else + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, +#endif + + (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M +}; + +#endif // defined CYGPKG_HAL_KINETIS_CACHE + +//========================================================================== +// Setup variant specific hardware +//========================================================================= + +void hal_variant_init( void ) +{ +#if defined CYGPKG_HAL_KINETIS_CACHE +# if defined CYG_HAL_STARTUP_RAM + register CYG_INTERRUPT_STATE oldints; +# endif +#endif + + hal_update_clock_var(); + +#if defined CYGPKG_HAL_KINETIS_CACHE +# if defined CYG_HAL_STARTUP_RAM + HAL_DISABLE_INTERRUPTS(oldints); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + HAL_DCACHE_PURGE_ALL(); + HAL_ICACHE_DISABLE(); + HAL_ICACHE_INVALIDATE_ALL(); +# endif // defined CYG_HAL_STARTUP_RAM + hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P, + sizeof(cache_reg_modes_ps)/sizeof(cache_reg_modes_ps[0]), + cache_reg_modes_ps); + hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P, + sizeof(cache_reg_modes_pc)/sizeof(cache_reg_modes_pc[0]), + cache_reg_modes_pc); +# if defined CYG_HAL_STARTUP_RAM + HAL_RESTORE_INTERRUPTS(oldints); +# endif +# ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP + HAL_ICACHE_ENABLE(); +# endif +# ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP + HAL_DCACHE_ENABLE(); +# endif +#endif // defined CYGPKG_HAL_KINETIS_CACHE + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif +} + +//=========================================================================== +// The WDOG at Freescale Kinetis is enabled after reset. hal_wdog_disable +// provides functionality for disabling it at startup. +//=========================================================================== + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_kinetis_wdog_unlock_simple(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p) +{ + wdog_p->Unlock = 0xC520; + wdog_p->Unlock = 0xD928; +} + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_kinetis_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p) +{ + CYGARC_CPSID( i ); + hal_kinetis_wdog_unlock_simple(wdog_p); + CYGARC_CPSIE( i ); +} + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_wdog_disable(void) +{ + volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p = CYGHWR_HAL_KINETIS_WDOG_P; + hal_kinetis_wdog_unlock_simple(wdog_p); + wdog_p->StCtrlH = CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M; +} + +//========================================================================== +// Pin configuration functions +// + +static cyghwr_hal_kinetis_port_t * const Ports[] = { + CYGHWR_HAL_KINETIS_PORTA_P, CYGHWR_HAL_KINETIS_PORTB_P, + CYGHWR_HAL_KINETIS_PORTC_P, CYGHWR_HAL_KINETIS_PORTD_P, + CYGHWR_HAL_KINETIS_PORTE_P, CYGHWR_HAL_KINETIS_PORTF_P +}; + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_set_pin_function(cyg_uint32 pin) +{ + cyghwr_hal_kinetis_port_t *port_p; + + if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) { + port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)]; + port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)] = + CYGHWR_HAL_KINETIS_PIN_FUNC(pin); + } +} + +void +hal_dump_pin_function(cyg_uint32 pin) +{ + cyghwr_hal_kinetis_port_t *port_p; + + if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) { + port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)]; + diag_printf("Port %d: %p[%d] fun=%x\n", + CYGHWR_HAL_KINETIS_PIN_PORT(pin), + port_p, + CYGHWR_HAL_KINETIS_PIN_BIT(pin), + port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)]); + } +} + +void +hal_dump_pin_setting(cyg_uint32 pin) +{ + if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) { + diag_printf("Pin: 0x%08x Port=%d bit=%d fun=%x\n", + pin, + CYGHWR_HAL_KINETIS_PIN_PORT(pin), + CYGHWR_HAL_KINETIS_PIN_BIT(pin), + CYGHWR_HAL_KINETIS_PIN_FUNC(pin)); + } +} + +//========================================================================== +// Clock distribution +// + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_clock_enable(cyg_uint32 desc) +{ + volatile cyg_uint32 *scgc_p; + + if(desc != CYGHWR_HAL_SCGC_NONE) { + scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + + CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc); + *scgc_p |= 1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc); + } +} + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_clock_disable(cyg_uint32 desc) +{ + volatile cyg_uint32 *scgc_p; + + if(desc != CYGHWR_HAL_SCGC_NONE) { + scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + + CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc); + *scgc_p &= ~(1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc)); + } +} + +//========================================================================== +// EOF kinetis_misc.c |