Added the OS files

6 files changed, 2595 insertions, 0 deletions

diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
new file mode 100644
index 0000000..e8ee8f8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
@@ -0,0 +1,867 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis.cdl
+##
+##      Cortex-M Freescale Kinetis variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
+    display       "Freescale Kinetis Cortex-M4 Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    doc           ref/hal-cortexm-kinetis-var.html
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_kinetis.h
+    description   "
+        This package provides generic support for the Freescale Cortex-M4
+        based Kinetis microcontroller family.
+        It is also necessary to select a variant and platform HAL package."
+
+    compile       hal_diag.c kinetis_misc.c kinetis_clocking.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_kinetis.h>"
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS {
+        display          "Kinetis part"
+        flavor           data
+        calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM .
+            CYGHWR_HAL_CORTEXM_KINETIS_FPU . CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM .
+            CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME }
+        description   "
+            Kinetis family has several sub-families, with various peripheral
+            sets and CPU options. Each sub-family consists of several
+            members differing by sizes of on-chip FLASH and SRAM. This
+            control, enables the user to build Kinetis member part and so
+            tailor HAL for a specific microcontroller by selection of
+            microcontroller's properties such as microcontroller sub-family,
+            memory options, etc."
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM {
+            display        "Sub-family"
+            flavor         data
+            no_define
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT }
+            legal_values   { 10 11 12 20 21 22 30 40 50 51 60 61 70 }
+            description    "
+                Kinetis family consists of several sub-families differing by
+                features and CPU power."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT {
+                display        "Default sub-family"
+                flavor         data
+                no_define
+                default_value  { 60 }
+                legal_values   { 10 11 12 20 21 22 30 40 50 51 60 61 70 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FPU {
+            display       "Floating Point Unit part name option"
+            flavor        data
+            no_define
+            legal_values  { "D" "F" }
+            default_value { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT }
+            description   "
+                Select whether the part has Floating Point Unit. \"F\" - stands for
+                parts with FPU, while \"D\" for ones without. Note:
+                Selection of part with FPU does not imply that the FPU is used -
+                CYGHWR_HAL_CORTEXM_FPU activates the FPU."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT {
+                display       "Default FPU part name option"
+                flavor        data
+                no_define
+                legal_values  { "D" "F" }
+                default_value { "D" }
+            }
+
+            cdl_option CYGIMP_HAL_CORTEXM_KINETIS_FPU {
+                display    "FPU implemented"
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" }
+                active_if  { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" }
+                implements CYGINT_HAL_FPV4_SP_D16
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM {
+            display        "FlexNVM name option"
+            flavor         data
+            no_define
+            legal_values   { "N" "X" }
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT }
+            description    "Select whether the part has FlexNVM."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT {
+                display        "Default FlexNVM name option"
+                flavor         data
+                no_define
+                legal_values   { "N" "X" }
+                default_value  { "N" }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME {
+            display        "Flash name segment"
+            flavor           data
+            no_define
+            legal_values   { 32 64 96 128 256 512 "1M0" }
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT }
+            description    "
+                Flash size is represented in part name encoded as KiB
+                (e.g. 512) or MiB (e.g. 1M0)."
+
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT {
+                display        "Default Flash name segment"
+                flavor           data
+                no_define
+                legal_values   { 32 64 96 128 256 512 "1M0" }
+                default_value  { 512 }
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_REV {
+            display       "Kinetis revision"
+            flavor        data
+            legal_values  { 1 2 }
+            default_value 1
+            description " Revision"
+        }
+
+        cdl_interface CYGINT_HAL_CORTEXM_KINETIS_150 {
+            display       "Is a 150MHz device"
+            description   "
+                150Mhz and 120MHz devices have some properties different than 100MHz
+                devices of same types. This interface shall be implemented if the
+                device is 150Mhz or 120MHz."
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU exception priority level bits"
+        flavor        data
+        default_value 4
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING {
+        display     "Clocking"
+        flavor      data
+        no_define
+        calculated  CYGHWR_HAL_CORTEXM_KINETIS_MCG
+        description "Configure system clock and subsystem clocking."
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP {
+            display      "System frequency clock setpoint"
+            flavor        data
+            legal_values  32768 to 220000000
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP ?
+                CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP : 96000000 }
+            description "Desired system clock frequency"
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP {
+            display       "Auxiliary clock frequency setpoint"
+            flavor        data
+            active_if     CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+            legal_values  32768 to 220000000
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP ?
+                            CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 }
+            description    "Desired auxiliary clock frequency"
+        }
+
+        script kinetis_clocking.cdl
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP
+        description   "Set clock ISR priority. Default setting is lowest priority."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYG_HAL_STARTUP_VAR {
+        display      "By variant"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ?
+                        "ByPlatform" : "ROM" }
+        legal_values  { "ROM" "SRAM" }
+        active_if     ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
+        description   "
+            'ROM' startup builds a stand-alone application which will
+            be placed into flash. SRAM startup builds application
+            intended for loading in on-chip SRAM by means of JTAG/SWD.
+            Note: Variant Startup Type can be overriden/overloaded by
+            Platform Startup Type."
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type calculator"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        calculated    { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
+                        CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR}
+        no_define
+        define        -file system.h CYG_HAL_STARTUP
+        description   "
+            Startup type defines what type of application shall be built.
+            Startup type  can be defined by variant (CYG_HAL_STARTUP_VAR)
+            or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF {
+        display "FlexNVM configuration"
+        flavor none
+        no_define
+        active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" }
+        requires {
+            CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <=
+            CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE {
+            display "Enhanced EEPROM (EEE)"
+            flavor  bool;
+
+            cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE {
+                display      "EEE Size \[Bytes\]"
+                flavor        data
+                legal_values  { 0 32 64 128 256 512 1024 2048 4096
+                    CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 8196 : 0
+                    CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 16384 : 0
+                }
+                default_value CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+            }
+
+            cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT {
+                display       "EEE Split ratio"
+                flavor data
+                legal_values  { 0 2 4 8 }
+                default_value 0
+                description "
+                    Enhanced EEPROM is split in two partitions that are
+                    represented by separate sections in MLT files.
+                    The split, CYGHWR_HAL_KINETIS_EEE_SPLIT, represents
+                    partition size ratio where EEE0 partition size is
+                    1/CYGHWR_HAL_KINETIS_EEE_SPLIT of EEE size, and EEE1
+                    is the rest. As a special arrangement
+                    (CYGHWR_HAL_KINETIS_EEE_SPLIT == 0) is a PHONY, where
+                    split equals 2 but in MLT files whole EEE is counted
+                    as a single section."
+
+                cdl_option CYGHWR_HAL_KINETIS_EEE0_SIZE {
+                    display "e_eeprom0 section size \[Bytes\]"
+                    flavor data
+                    calculated { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 ?
+                        CYGHWR_HAL_KINETIS_EEE_SIZE /
+                        CYGHWR_HAL_KINETIS_EEE_SPLIT :
+                        CYGHWR_HAL_KINETIS_EEE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_EEE1_SIZE {
+                    display "e_eeprom1 section size \[Bytes\]"
+                    flavor data
+                    active_if { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 }
+                    calculated { CYGHWR_HAL_KINETIS_EEE_SIZE -
+                        CYGHWR_HAL_KINETIS_EEE0_SIZE }
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB {
+                display "FlexNVM partition used for EEE \[KiB\]"
+                flavor     data
+                calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512 ?
+                             CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB :
+                             CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB {
+                    display "FlexNVM partition used for EEE \[KiB\]"
+                    flavor data
+                    active_if      CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 256
+                    default_value  32
+                    legal_values { 32 64 128 192 224 256 }
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB {
+                    display "FlexNVM partition used for EEE \[KiB\]"
+                    flavor data
+                    active_if      CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512
+                    default_value  64
+                    legal_values { 64 128 256 384 448 512 }
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE {
+            display "FlexNVM D Flash"
+            flavor data
+            active_if { CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <
+                CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB}
+            calculated {
+                1024 * ( CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB -
+                         CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_RAM {
+            display "Flexram ordinary RAM"
+            flavor data
+            active_if { !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
+            calculated CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_SIZE {
+            display "Flexram size"
+            flavor data
+            legal_values  { 4096 16384 }
+            default_value CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 ? 16384 : 4096
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB {
+            display "FlexNVM size \[KiB\]"
+            flavor data
+            calculated CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        parent CYG_HAL_STARTUP_ENV
+        calculated {
+            (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF :
+            (CYG_HAL_STARTUP == "ROM" ) ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_rom" :
+            (CYG_HAL_STARTUP == "SRAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_sram" :
+            "undefined" }
+        description "
+            Combination of 'Startup type' and 'Kinetis part'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED {
+        display  "Unified on chip SRAM region"
+        flavor    bool
+        default_value    { 1 }
+        description "
+            Kinetis have two equal SRAM banks SRAM_L and SRAM_U that
+            occupy consecutive memory blocks with \(possibility for
+            simultaneous\) access from on separate buses.
+            SRAM_L is placed below 0x20000000 and SRAM_U above 0x20000000.
+            This option provides for selection between memory layout with
+            single (unified) (S)RAM region and layout with two separate
+            (S)RAM regions."
+    }
+
+    cdl_option CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION {
+        display "Utilize \".kinetis_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+            Kinetis use FLASH locations between 0x400 and 0x40F for FLASH
+            security configuration. This leaves FLASH area below 0x400
+            out of standard linker sections. Special section
+            \".kinetis_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
+    cdl_option CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION {
+        display "HAL diag. in \".kinetis_misc\" section"
+        flavor bool
+        active_if CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION
+        default_value 0
+        description "
+        By default only misc. HAL functions are stored in
+        \".kinetis_misc\" section. In addition HAL diagnostc
+        functions may be placed as well."
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES {
+        display "On chip memory resources"
+        flavor none
+        no_define
+        description "
+        View and manage on-chip memory resources.
+        Output is used for naming of 'mlt' files."
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB {
+            display "On chip Flash option \[KiB\]"
+            flavor data
+            calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0")
+                ? 1024 : CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB {
+            display "Kinetis on chip SRAM size \[KiB\]"
+            flavor data
+            calculated {
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 1024 ||
+                 CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 512)   ? 128 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 256)   ? 64 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 128)   ? 32 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 96 ||
+                 CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 64)    ? 16 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 32)    ? 8 :
+                "Unknown"
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT {
+            display "SRAM layout"
+            flavor data
+            no_define
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ?
+                "unisram" :
+                "sram2s"
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT {
+            display "On-chip memory layout"
+            flavor data
+            no_define
+            calculated {(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" ? "flexnvm_": "flash_")
+                . CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_SIZE {
+            display "Kinetis on chip FLASH size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB * 0x400 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SRAM_SIZE {
+            display "Kinetis on chip SRAM size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB * 0x400 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE {
+            display "Kinetis onchip RAM bank size"
+            flavor  data
+            calculated { CYGHWR_HAL_KINETIS_SRAM_SIZE/2 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE {
+            display "Kinetis on chip FlexNVM FLASH size"
+            flavor data
+            active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" }
+            calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB
+                          - CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 }
+            }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE {
+            display   "Kinetis on chip FlexRAM size"
+            flavor    data
+            active_if { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X") &&
+                !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
+            calculated { CYGHWR_HAL_KINETIS_FLEXRAM_SIZE }
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CACHE {
+        display "Platform has cache"
+        flavor bool
+    }
+
+    cdl_interface CYGINT_HAL_HAS_NONCACHED {
+        display "Platform has non-cached regions"
+        flavor bool
+    }
+
+    cdl_component CYGPKG_HAL_KINETIS_CACHE {
+        display "Cache memory"
+        flavor bool
+
+        default_value CYGINT_HAL_CACHE
+        active_if (CYGINT_HAL_CACHE)
+    }
+
+    cdl_component CYGHWR_HAL_NONCACHED {
+        display "Non cached RAM memory regions"
+        flavor        booldata
+        active_if     CYGINT_HAL_HAS_NONCACHED
+        legal_values  { "\".sram\"" "\".noncache\"" }
+        default_value { "\".noncache\"" }
+        description   "
+            Non cached memory sections may be usful for storage that
+            is unsuitable for caching, such as sharing buffers between
+            the CPU and other bus masters such as DMA, ENET, etc.
+            The  \".sram\" section is located in the internal SRAM,
+            which is is always present and never cached.
+            Additionaly, as an option, a partition of external memory:
+            DDRAM or FlexRAM, if one is present, can be configured
+            non-cached and accommodate \".noncache\" section."
+
+        cdl_option CYGHWR_HAL_ENET_TCD_SECTION {
+            display       "Ethernet buffer descriptor memory section"
+            flavor data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".sram\"" }
+
+            description "Ethernet is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_ENET_BUF_SECTION {
+            display       "Ethernet buffer memory section"
+            flavor        data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".noncache\"" }
+
+            description "Ethernet is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_EDMA_TCD_SECTION {
+            display       "eDMA transfer control descriptor memory section"
+            flavor        data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".sram\"" }
+
+            description   "eDMA is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_EDMA_BUF_SECTION {
+            display       "eDMA buffer memory section"
+            flavor data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".noncache\"" }
+
+            description   "eDMA is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_DDRAM {
+        display "Platform uses DDRAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DDRAM and if DDRAM is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC {
+        display       "DDRAM"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        description   "DDRAM on Kinetis is mirrored at several address ranges.
+                Each mirror has its own caching options that may include:
+                non-cached, write-through and write-back.
+                By eCos configuration, DDRAM is split in 3 partitions:
+                Cached, Non-cached and Code.
+                Cached partition is intended for general purpose main memory.
+                Non-cached partition is convenient for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc. Code partition is for executable code."
+
+        requires       CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+        compile        kinetis_ddram.c
+
+        script kinetis_ddram.cdl
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FBRAM {
+        display "Platform uses FlexBus RAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides FlexBus and if FlexBus is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM {
+        display       "FlexBus RAM"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        requires      CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+        description   "FBRAM on Kinetis is mirrored at several address ranges.
+                Each mirror has its own caching options that may include:
+                non-cached, write-through and write-back.
+                By eCos configuration, FlexBus RAM is split in 3 partitions:
+                Cached, Non-cached and Code.
+                Cached partition is intended for general purpose main memory.
+                Non-cached partition is convenient for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc. Code partition is for executable code."
+
+        script kinetis_fbram.cdl
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS {
+        display     "Platform uses FlexBus"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides FlexBus and if FlexBus is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+        display       "FlexBus"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+        default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+        description   "FlexBus provides access for external memory."
+
+        script        kinetis_flexbus.cdl
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF {
+        display "Flash configuration field"
+        flavor   none
+        no_define
+
+        active_if { CYG_HAL_STARTUP == "ROM" }
+
+        description "
+            The program flash memory contains a 16-byte flash
+            configuration field that stores default protection settings
+            (loaded on reset) and security information that allows the MCU to
+            restrict access to the flash module.
+            Note: Changing some values in Flash configuration field may make
+            flash inaccessible and disable further re-programming of the flash
+            permanently. Consult respective Kinetis' documentation before dealing
+            with the Flash configuration field. Default values are equal
+            to the factory values."
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY {
+            display "Backdoor comparison key"
+            flavor data
+            default_value { "\{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff \}" }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT {
+            display "Program flash protection"
+            flavor data
+            default_value { "\{ 0xff, 0xff, 0xff, 0xff \}" }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC {
+            display "Flash security byte"
+            flavor data
+            default_value 0xfe
+
+            description "
+                Note: FSEC default value is deliberately set to
+                0xfe in order to disable chip lockout."
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT {
+            display "Flash nonvolatile option byte"
+            flavor data
+            default_value 0xff
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT {
+            display "Data flash protection byte"
+            flavor data
+            default_value 0xff
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT {
+            display "EEPROM protection byte"
+            flavor data
+            default_value 0xff
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KINETIS_MEM_SEGMENTS {
+        display    "RAM memory segments"
+        flavor     data
+        no_define
+        active_if  is_active(CYGBLD_REDBOOT_MAX_MEM_SEGMENTS)
+        requires   { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS >= CYGNUM_HAL_KINETIS_MEM_SEGMENTS }
+
+        calculated {
+            ((CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? 1 : 2) +
+            (CYGPKG_HAL_CORTEXM_KINETIS_DDRMC        ? 2 : 0) +
+            (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE  ? 1 : 0) +
+            (CYGPKG_HAL_CORTEXM_KINETIS_FBRAM        ? 2 : 0) +
+            (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE  ? 1 : 0))
+        }
+    }
+
+    for { set ::channel 0 } { $::channel < 6 } { incr ::channel } {
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] {
+            display     "Platform provides UART [set ::channel] HAL"
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                controller being used has on-chip UART [set ::channel],
+                and if that UART is accessible on the target hardware."
+        }
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS {
+            display     "Platform provides HAL for UART[set ::channel] hardware flow control."
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                on-chip UART [set ::channel] has RTS/CTS flow control
+                that is accessible on the target hardware."
+        }
+    }
+
+    cdl_interface CYGINT_HAL_DMA {
+        display     "Platform uses DMA"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DMA and if DMA is
+            used on target hardware"
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display     "Variant IRQ priority defaults"
+        no_define
+        flavor      none
+        parent      CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by Kinetis variant"
+        script kinetis_irq_scheme.cdl
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS {
+        display      "Build options"
+        flavor       none
+        no_define
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Kinetis variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Kinetis variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_kinetis.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl
new file mode 100644
index 0000000..0d785d1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl
@@ -0,0 +1,978 @@
+##==========================================================================
+##
+##      kinetis_clocking.cdl
+##
+##      Cortex-M Freescale Kinetis Clocking
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-10-19
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING
+#    display       "Clocking"
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ {
+        display "System frequency actual value"
+        flavor data
+        calculated {
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC   ?
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC   :
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC   ?
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC   :
+            (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL ||
+             CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1)   ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV:
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL      ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV :
+            0
+        }
+        description "Operating system clock frequency."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG {
+        display "MCG"
+        flavor data
+        no_define
+        calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK . " " .
+            ((CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ+500000)/1000000) . "MHz, " . (
+                  (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") ?
+                  CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS :
+                  CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC)
+
+        }
+        description "Multipurpose Clock Generator"
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK {
+            display "System clock source"
+            flavor data
+            default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 ? "PLL1" : "PLL" }
+            legal_values {
+                "PLL" "FLL" "EXT_REFCLK" ( CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 ? "PLL1" : "PLL" )
+            }
+            requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" implies
+                CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 1
+            }
+            requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" implies
+                CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1
+            }
+            description "
+                Select one of 3 options for MCG output clock:
+                PLL or FLL oscillator or External reference clock."
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT {
+            display "EXT_REFCLK source clock settings"
+            flavor none
+            no_define
+            active_if {
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK") ||
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK")
+            }
+            description "Set External Reference Clock frequency and type."
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT0 {
+                display "External freq ref 0"
+                flavor data
+                no_define
+                calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS . " " .
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
+                }
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS {
+                    display "Clock type"
+                    flavor data
+                    default_value { "OSC" }
+                    legal_values { "OSC" "XTAL" "RTC"}
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies
+                        (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000)
+                    }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies
+                        (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) &&
+                          (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) ||
+                          ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) &&
+                           (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000)))
+                    }
+
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
+                    }
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                    }
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768)
+                    }
+
+                    description "
+                    Ext reference can be External oscillator or a crystal
+                    for the on-chip oscillator or Real Time Clock."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ {
+                    display "Clock frequency"
+                    flavor data
+                    legal_values  0 to 50000000
+                    default_value {
+                        is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ?
+                        CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ :
+                        4000000
+                    }
+                    description "External oscillator or crystal reference in Hz."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP {
+                    display "XTAL parallel C \[pF\]"
+                    flavor data
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+                    legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
+                    default_value 0
+                    description "
+                        The oscillator has 4 on-chip capacitors that combined
+                        produce capacitance in parallel to the crystal."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1 {
+                display "External freq ref 1"
+                flavor data
+                no_define
+                active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+                calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS . " " .
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ
+                }
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS {
+                    display "Clock type"
+                    flavor data
+                    default_value { "OSC" }
+                    legal_values { "OSC" "XTAL" }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC") implies
+                        (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 50000000)
+                    }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL") implies
+                        (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 3000000) &&
+                          (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 32000000)) ||
+                          ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 32000) &&
+                           (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 40000)))
+                    }
+
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 0)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 0)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ == 32768)
+                   }
+
+                    description "
+                    Ext reference can be External oscillator or a crystal
+                    for the on-chip oscillator or Real Time Clock."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ {
+                    display "Clock frequency"
+                    flavor data
+                    legal_values  0 to 50000000
+                    default_value {
+                        is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ) ?
+                        CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ :
+                        4000000
+                    }
+                    description "External oscillator or crystal reference in Hz."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP {
+                    display "XTAL parallel C \[pF\]"
+                    flavor data
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+                    legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
+                    default_value 0
+                    description "
+                        The oscillator has 4 on-chip capacitors that combined
+                        produce capacitance in parallel to the crystal."
+                }
+            }
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL {
+            display "FLL / PLL configuration"
+            flavor none
+            no_define
+            description "
+                PLL / FLL parameters are being calculated on a
+                base of required system frequrncy and output as well as
+                reference oscillator/frequency settings."
+
+            cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP {
+                display "PLL/FLL output frequency set point"
+                flavor data
+                legal_values  32768 to 220000000
+                calculated {
+                    ((CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL") ||
+                     (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")) ?
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP :
+                        CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP
+                }
+                description "Desired PLL output frequency."
+            }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC {
+                display "Reference clock source for FLL or PLL"
+                flavor data
+                default_value { "EXT_REFCLK" }
+
+                requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "INT_RC_32KHZ")
+                    implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                }
+
+                legal_values { "INT_RC_32KHZ" "EXT_REFCLK" "EXT_REFCLK1" }
+                description "
+                PLL/FLL oscillators can use one of external reference
+                clock references as well as Low (32768 Hz) or High (2MHz)
+                Frequency Internal oscillator"
+            }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_PLL1_REFSRC {
+                display "Reference clock source for PLL1"
+                active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+                flavor data
+                default_value { "EXT_REFCLK" }
+
+                legal_values { "EXT_REFCLK" "EXT_REFCLK1" }
+                description "
+                    PLL1 oscillator can use one of 2 external reference clock
+                    references."
+            }
+
+            cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ {
+                display "Reference frequency."
+                flavor data
+                calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
+                    (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
+                     == "INT_RC_32KHZ" ? 32768 : 2000000 )
+                }
+            }
+
+            cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL {
+                display "FLL oscillator"
+                flavor none
+                no_define
+                active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE {
+                    display "Reference frequency range"
+                    flavor data
+                    legal_values 0 1 2
+                    calculated {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ > 8000000 ? 2 :
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 1000000 ? 1 :
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 32000) &&
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ <= 40000)) ? 0 :
+                        -1
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV {
+                    display "Calculated FLL divider"
+                    flavor data
+                    calculated {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE >= 1 ?
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+32768*16) / (32768*32)) :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
+                         ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+16384) / 32768) : -1)
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG {
+                    display "FLL divider register value"
+                    flavor data
+                    legal_values 0 1 2 3 4 5 6 7
+                    default_value {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) <= 5 ?
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : 5
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS {
+                    display "DCO Range Select"
+                    flavor data
+                    legal_values 0 1 2 3
+                    default_value {
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 80000000 ? 3 :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 60000000 ? 2 :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 40000000 ? 1 : 0
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 {
+                    display "DCO max. frequency with 32768 reference"
+                    flavor data
+                    legal_values { 0 0x80 }
+                    default_value {
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 9600000)) ?
+                        0x80 : 0x00
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT {
+                    display "FLL factor"
+                    flavor data
+                    calculated {
+                        (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 == 0x80) ?
+                        ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ?  732 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1464 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 2197 : 2929 ) :
+                        ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ?  640 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1280 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 1920 : 2560 )
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN {
+                    display "DCO input frequency"
+                    flavor data
+                    calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                        ( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG == 0 ?
+                         ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 1 : 32 ) :
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG *
+                          ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 2 : 64)))
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN_CHECK {
+                    display "DCO input frequency check"
+                    flavor data
+                    no_define
+                    legal_values { "OK" "NOK" "not applicable" }
+                    calculated {
+                        CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ?
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) ?
+                         "OK" : "NOK" ) :
+                        "NotApplicable"
+                    }
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" }
+                    requires {
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063)
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV {
+                    display "FLL output frequency actual value"
+                    flavor data
+                    calculated {CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN *
+                        CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT }
+                }
+            }
+
+            cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL {
+                display "PLL oscillator"
+                flavor bool
+                default_value 1
+#                { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? 0 : 1 }
+#                active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
+#                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
+#                }
+
+                cdl_component CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL {
+                    display "100 Mhz line"
+                    flavor none
+                    no_define
+                    active_if !CYGINT_HAL_CORTEXM_KINETIS_150
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X {
+                        display "Phase detector proposed input frequency"
+                        no_define
+                        flavor data
+                        calculated {
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ?
+                            3800000 :
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ?
+                            3000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 :
+                            300000
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV {
+                        display "PLL External Reference Divider"
+                        flavor data
+                        legal_values 1 to 25
+                        default_value {
+                            CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ {
+                        display "Phase detector input frequency"
+                        no_define
+                        flavor data
+                        legal_values 2000000 to 4000000
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV) : -1
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV {
+                        display "VCO Divider"
+                        flavor data
+                        legal_values 24 to 55
+                        default_value { CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
+                             CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV {
+                        display "PLL output frequency actual value"
+                        flavor data
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV *
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV) : -1
+                        }
+                    }
+                }
+
+                cdl_component CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL {
+                    display "150 Mhz line"
+                    flavor none
+                    no_define
+                    active_if CYGINT_HAL_CORTEXM_KINETIS_150
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X {
+                        display "Phase detector proposed input frequency"
+                        no_define
+                        flavor data
+                        legal_values 1000000 to 32000000
+                        default_value {
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ == 50000000) ?
+                            (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 30000000) ? 30000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4000000) ? 4000000 :
+                            5000000
+                        }
+                    }
+
+                    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL {
+                        display "PLL0 Reference Oscillator select"
+                        flavor data
+                        default_value 0
+                        legal_values 0 1
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV {
+                        display "PLL External Reference Divider"
+                        flavor data
+                        legal_values 1 to 8
+                        default_value {
+                            CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ {
+                        display "Phase detector input frequency"
+                        no_define
+                        flavor data
+                        legal_values 1000000 to 32000000
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV) : -1
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV {
+                        display "VCO Divider"
+                        flavor data
+                        legal_values 16 to 47
+                        default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ ?
+                            ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
+                             CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ) * 2) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV {
+                        display "PLL output frequency actual value"
+                        flavor data
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ?
+                            ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV *
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) / 2) : -1
+                        }
+                    }
+                }
+
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV {
+                    display "PLL External Reference Divider"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV :
+                        CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV
+                    }
+                }
+
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV {
+                    display "PLL External Reference Divider"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        (CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) :
+                        CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV {
+                    display "PLL output frequency actual value"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV :
+                        CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV
+                    }
+                }
+            }
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC {
+            display "Internal Reference Clock"
+            flavor data
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI ? 2000000 : 32768 }
+            active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK ==  "INT_REFCLK" }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI {
+                display "Use highh frequency internal osc."
+                flavor bool
+                default_value 1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC {
+            display "External Reference Clock"
+            flavor data
+            calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
+            active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK ==  "EXT_REFCLK" }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_DIST {
+        display "Subsystem clocking"
+        flavor none
+        no_define
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS {
+            display "Peripheral bus"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 50000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value { !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                                  CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP + 1)
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH {
+            display "Flash"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 25000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value {
+                    !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP + 1)
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS {
+            display "Flex bus"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 50000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value {
+                    !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP + 1)
+                }
+            }
+        }
+
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB {
+            display "USB clock"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 48000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC {
+                display "Fractional Divider"
+                flavor data
+                legal_values 1 to 2
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX ? 1 :
+                    ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN) >
+                     (CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP * 4) ? 1 :
+                     (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN %
+                      CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP ? 2 : 1))
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV {
+                display "Divider"
+                flavor data
+                legal_values 1 to 8
+                default_value { !((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                                   CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC) %
+                                   CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                     CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP)  :
+                    ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                      CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                      CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) +1)
+                }
+            }
+
+            cdl_option CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN {
+                display "USB divider input frequency"
+                flavor data
+                calculated {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP {
+                display "Desired"
+                flavor data
+                calculated 48000000
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK {
+            display "Trace clock source"
+            flavor data
+            default_value { "CORE" }
+            legal_values { "CORE" "MCGOUT" }
+
+        }
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT {
+            display "Enable Trace Clock out"
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC {
+        display "System uses Real Time Clock"
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC {
+        display "Real Time Clock"
+        flavor bool
+        default_value CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP {
+            display "RTC XTAL parallel C \[pF\]"
+            flavor data
+            legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
+                30 32 }
+            default_value 0
+            description "
+                The Real Time Clock oscillator has 4 capacitors that
+                combined produce capacitance in parallel to the crystal."
+        }
+    }
+
+    #   PLL1 and OSC1 Configuration
+    #   PLL1
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 {
+        display "MCG Has PLL1"
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 {
+        display "MCG Has OSC1"
+    }
+
+    cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 {
+        display "PLL1 oscillator"
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL
+        flavor bool
+        default_value CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+        active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP {
+            display "PLL1 output frequency set point"
+            flavor data
+            legal_values  32768 to 220000000
+            calculated {
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1") ?
+                     CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP :
+                     CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP
+            }
+            description "Desired PLL1 output frequency."
+        }
+
+        cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ {
+            display "Reference frequency."
+            flavor data
+            calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
+                CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
+                 == "INT_RC_32KHZ" ? 32768 : 2000000 )
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X {
+            display "Phase detector proposed input frequency"
+            no_define
+            flavor data
+            legal_values 1000000 to 32000000
+            default_value {
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ == 50000000) ?
+                (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) :
+                !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 30000000) ? 30000000 :
+                !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 4000000) ? 4000000 :
+                5000000
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL {
+            display "PLL10 Reference Oscillator select"
+            flavor data
+            default_value 0
+            legal_values 0 1
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            legal_values 1 to 8
+            default_value {
+                CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ?
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                 CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ) : -1
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ {
+            display "Phase detector input frequency"
+            no_define
+            flavor data
+            legal_values 1000000 to 32000000
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ?
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                 CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV) : -1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV {
+            display "VCO Divider"
+            flavor data
+            legal_values 16 to 47
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ ?
+                ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP /
+                  CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ) * 2) : -1
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV {
+            display "PLL1 output frequency actual value"
+            flavor data
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ?
+                ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                  CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV *
+                  CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV) / 2) : -1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV {
+            display "PLL1 output frequency actual value"
+            flavor data
+            calculated CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV {
+        display "Frequency of selected PLL"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL
+        calculated {CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV :
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV
+        }
+    }
+
+    # EOF kinetis_clocking.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl
new file mode 100644
index 0000000..55cdf99
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl
@@ -0,0 +1,259 @@
+##==========================================================================
+##
+##      kinetis_ddram.cdl
+##
+##      Cortex-M Freescale Kinetis DDRAM configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2013-04-28
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC {
+#        display       "DDRAM"
+#        flavor bool
+#        active_if     CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+#        default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+#        description   "DDRAM on Kinetis is mirrored at several address ranges.
+#                Each mirror has its own caching options that may include:
+#                non-cached, write-through and write-back.
+#                By eCos configuration, DDRAM is split in 3 partitions:
+#                Cached, Non-cached and Code.
+#                Cached partition is intended for general purpose main memory.
+#                Non-cached partition is convenient for sharing
+#                buffers with other bus masters such as Ethernet controller,
+#                DMA, etc. Code partition is for executable code."
+#
+#        requires       CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+#        compile        kinetis_ddram.c
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_SIZE_MIB {
+            display       "DDRAM size \[MiB\]"
+            flavor        data
+            default_value 128
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE {
+                display    "DDRAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB {
+            display      "Non-cached DDRAM data partition \[MiB\]"
+            requires     { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <=
+                           CYGHWR_HAL_KINETIS_DDR_SIZE_MIB }
+            flavor       data
+
+            implements   CYGINT_HAL_HAS_NONCACHED
+
+            legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) }
+
+            default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4
+
+            description "
+                Non-cached DDRAM partition, intended for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc."
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE {
+                display    "Non-cached DDRAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB
+                             * (1024 * 1024) * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE {
+                display    "Non-cached DDRAM base address"
+                flavor     data
+
+                calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR +
+                             CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE +
+                             CYGHWR_HAL_KINETIS_DDR_CODE_SIZE }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR {
+                display       "Non-cached DDRAM mirror base"
+                flavor        data
+                no_define
+                calculated    { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR == 0x70000000 ?
+                    0x80000000 : 0x70000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB {
+            display       "DDRAM code partition \[MiB\]"
+            requires      { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB <=
+                            CYGHWR_HAL_KINETIS_DDR_SIZE_MIB }
+            flavor        data
+
+            legal_values  { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) }
+
+            default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4
+
+            description "
+                DDRAM code partition - for use as program memory.
+                On systems with cache this partition is cached in PC cache.
+                Caching is always write-through"
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_SIZE {
+                display    "DDRAM code partition size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB
+                             * (1024 * 1024) * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_BASE {
+                display    "DDRAM code partition base address"
+                flavor     data
+
+                calculated { 0x08000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB {
+            display    "Cached DDRAM data partition \[MiB\]"
+            flavor     data
+            requires   { CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB >= 8 }
+            calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB -
+                         CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB -
+                         CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB }
+
+            description "
+                Cached DDRAM data partition - for general use as main data memory.
+                On systems with cache this partition is cached in PS cache.
+                Caching can be either copy-back or write-through and is determined by
+                general cache mode setting."
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE {
+                display    "Cached DDRAM size \[Bytes\]"
+                flavor      data
+                calculated  { (CYGHWR_HAL_KINETIS_DDR_SIZE -
+                              CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE -
+                              CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) * 0x1 }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_BASE {
+                    display       "Cached DDRAM base address"
+                    flavor        data
+                    calculated    { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR +
+                                    CYGHWR_HAL_KINETIS_DDR_CODE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE {
+                    display     "DDRAM cache type"
+                    flavor       data
+                    calculated  CYGSEM_HAL_DCACHE_STARTUP_MODE
+                    description "DDRAM cache type is determined by general cache setting"
+                }
+
+                cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR {
+                    display         "Cached DDRAM mirror base"
+                    flavor data
+                    no_define
+                    legal_values     { 0x70000000 0x80000000 }
+                    default_value    { 0x70000000 }
+                    description   "
+                        According to Kinetis Reference Manual rev. 2, the DDRAM mirror
+                        mapped at 0x80000000 (supporting write-thru caching only)
+                        is not accesible by ENET, SDH and some other bus masters,
+                        and that the mirror at 0x70000000 (supporting copy-back caching)
+                        is accessible by them.
+                        The practical tests prove that it is the opposite, actually as
+                        it should be.
+                        Until this discrepancy is resolved, this option selects the
+                        default (non)cached mirror and provides the user with possibilty for
+                        manual override.
+                        Note: The behavior may change in future."
+                }
+        }
+
+        cdl_option CYGHWR_HAL_DDR_SYNC_MODE {
+            display       "Use synchronous mode"
+            flavor        bool
+            requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" }
+            default_value { 1 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS {
+            display      "DDRAM bus configuration"
+            flavor        data
+            legal_values  0 1 2 3 6
+            default_value 6
+            description "
+                DDRAM configuration: 0 - LPDDR Half Strength,
+                1 - LPDDR Full Strength, 2 - DDR2 Half Strength,
+                3 - DDR1, 6 - DDR2 Full Strength"
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL {
+            display    "Pad control"
+            flavor     data
+
+            calculated {
+                (CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT << 24) |
+                CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL |
+                0x00000200
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT {
+                display       "On Die Termination"
+                flavor        data
+                legal_values  { 0 1 2 3 }
+                default_value 1
+
+                description   "On Die Termination \[Ohm\]: 0 - Off, 1 - 75,
+                    2 - 150, 3 - 50"
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL {
+                display       "Delay chains in spare logic"
+                flavor        data
+                legal_values  { 0 1 2 3 }
+                default_value 3
+
+                description "Delay chains in spare logic: 0 - No buffer, 1 - 4 buffers,
+                    2 - 7 buffers, 11 - 10 buffers"
+            }
+        }
+#    }
+
+# EOF kinetis_ddram.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl
new file mode 100644
index 0000000..ea97ad8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl
@@ -0,0 +1,205 @@
+##==========================================================================
+##
+##      kinetis_fbram.cdl
+##
+##      Cortex-M Freescale Kinetis FBRAM configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2013-04-28
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM {
+#        display       "FlexBus RAM"
+#        flavor bool
+#        active_if     CYGINT_HAL_CORTEXM_KINETIS_DBRAM
+#        default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+#        description   "FlexBus RAM on Kinetis is mirrored at several address ranges.
+#                Each mirror has its own caching options that may include:
+#                non-cached, write-through and write-back.
+#                By eCos configuration, FlexBus RAM is split in 3 partitions:
+#                Cached, Non-cached and Code.
+#                Cached partition is intended for general purpose main memory.
+#                Non-cached partition is convenient for sharing
+#                buffers with other bus masters such as Ethernet controller,
+#                DMA, etc. Code partition is for executable code."
+#
+
+        cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE {
+            display       "FlexBus RAM size \[Bytes\]"
+            flavor        data
+            default_value CYGHWR_HAL_KINETIS_FB_CS0_SIZE ? CYGHWR_HAL_KINETIS_FB_CS0_SIZE * 1 : 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE_KIB {
+            display       "FlexBus RAM size \[KiB\]"
+            flavor        data
+            calculated    { CYGHWR_HAL_KINETIS_FBR_SIZE / 1024 }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB {
+            display      "Non-cached FlexBus data RAM partition \[KiB\]"
+            requires     { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB <=
+                           CYGHWR_HAL_KINETIS_FBR_SIZE_KIB }
+            flavor       data
+
+            implements   CYGINT_HAL_HAS_NONCACHED
+
+            legal_values { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) }
+
+            default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 }
+
+            description "
+                Non-cached FlexBus RAM partition, intended for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc."
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE {
+                display    "Non-cached FlexBus RAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB
+                             * 1024 * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE {
+                display    "Non-cached FlexBus RAM base address"
+                flavor     data
+
+                calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR +
+                             CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE +
+                             CYGHWR_HAL_KINETIS_FBR_CODE_SIZE }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR {
+                display       "Non-cached FlexBus RAM mirror base"
+                flavor        data
+                no_define
+                legal_values     { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 }
+                default_value    { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 :
+                                                                    0x60000000 }
+            }
+
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB {
+            display       "FlexBus RAM code partition \[KiB\]"
+            requires      { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB <=
+                            CYGHWR_HAL_KINETIS_FBR_SIZE_KIB }
+            flavor        data
+
+            legal_values  { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) }
+
+            default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 }
+
+            description "
+               FlexBus RAM code partition - for use as program memory.
+               On systems with cache this partition is cached in PC cache
+               and is always write-through"
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_SIZE {
+                display    "FlexBus RAM code partition size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB
+                             * 1024 * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_BASE {
+                display    "FlexBus RAM code partition base address"
+                flavor     data
+
+                legal_values     { 0x60000000
+                                   CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 :
+                                                                    0x60000000 }
+                default_value { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 :
+                                                                 0x60000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB {
+            display    "Cached FlexBus RAM data partition \[KiB\]"
+            flavor     data
+            requires   { CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB >= 64 }
+            calculated { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB -
+                         CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB -
+                         CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB }
+
+            description "
+               Cached FlexBus RAM data partition - for general use as main data memory.
+               On systems with cache this partition is cached in PS cache.
+               Caching can be either copy-back or write-through and is determined
+               by general cache mode setting."
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE {
+                display    "Cached FlexBus RAM size \[Bytes\]"
+                flavor      data
+                calculated  { (CYGHWR_HAL_KINETIS_FBR_SIZE -
+                              CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE -
+                              CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) * 0x1 }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_BASE {
+                    display       "Cached FlexBus RAM base address"
+                    flavor        data
+                    calculated    { CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR +
+                                    CYGHWR_HAL_KINETIS_FBR_CODE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_FBR_CACHE_TYPE {
+                    display     "FlexBus RAM cache type"
+                    flavor       data
+                    calculated  CYGSEM_HAL_DCACHE_STARTUP_MODE
+                    description "FlexBus RAM cache type is determined by general
+                        cache setting"
+                }
+
+                cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR {
+                    display         "Cached FlexBus RAM mirror base"
+                    flavor data
+                    no_define
+                    legal_values     { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 }
+                    default_value    { 0x60000000 }
+                    description      "Cached DDRAM base "
+                }
+        }
+
+#    }
+
+# EOF kinetis_fbram.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
new file mode 100644
index 0000000..96c49a4
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
@@ -0,0 +1,84 @@
+##==========================================================================
+##
+##      kinetis_flexbus.cdl
+##
+##      Cortex-M Freescale Kinetis FlexBus
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-11
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+#        cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+#        display       "FlexBus"
+
+for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } {
+
+    cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display     "Platform uses Chip select [set ::chipsel]"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides chip select [set ::chipsel], and if
+            that chip select is used on target hardware."
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display       "Chip select [set ::chipsel]"
+        flavor        bool
+        active_if     CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        description   "
+            This option includes initialization data for
+            chip select [set ::chipsel]."
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS {
+            display "Port size (encoded)"
+            flavor data
+            calculated ( \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8  ? 1 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
+        }
+    }
+}
+
+
+# EOF kinetis_flexbus.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
new file mode 100644
index 0000000..bfc3c04
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
@@ -0,0 +1,202 @@
+##==========================================================================
+##
+##      kinetis_irq_scheme.cdl
+##
+##      Cortex-M Freescale Kinetis IRQ configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+#        display "Variant IRQ priority defaults"
+#        no_define
+#        flavor none
+#        parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+#        description "
+#            Interrupt priorities defined by Kinetis variant"
+
+        cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP {
+            display       "Clock IRQ priority"
+            flavor        data
+            no_define
+            default_value 0xE0
+            description   "Set clock ISR priority. Default setting is lowest priority."
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_INTPRIO_SP {
+            display "Ethernet IRQ priority"
+            flavor data
+            no_define
+            active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+            default_value 0xE0
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART {
+            display "UART IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP {
+                display "UART0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP {
+                display "UART1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP {
+                display "UART2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP {
+                display "UART3 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART3
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP {
+                display "UART4 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART4
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP {
+                display "UART5 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART5
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_DSPI {
+            display "DSPI IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI_SP {
+                display "DSPI bus 0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI_SP {
+                display "DSPI bus 1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI_SP {
+                display "DSPI bus 2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+        }
+        
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C {
+            display "I2C interrupt priorities"
+            flavor none
+            no_define
+            
+            for { set ::bus 0 } { $::bus < 2 } { incr ::bus } {
+                
+                cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_IRQ_PRIORITY {
+                    display       "I2C bus [set ::bus] interrupt priority"
+                    flavor        data
+                    active_if     CYGHWR_DEVS_FREESCALE_I2C[set ::bus]
+                    default_value 0x90
+                    legal_values  { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 
+                        0x90  0xA0 0xB0 0xC0 0xD0 0xE0 }
+                }
+            }
+        }
+
+#    }
+
+
+# EOF kinetis_irq_scheme.cdl