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imx-atf.git
imx_4.14.78_1.0.0_ga
imx_4.9.51_imx8_beta1
imx_5.4.24_2.1.0
toradex_imx_5.4.24_2.1.0
toradex_imx_5.4.70_2.3.0
Reference implementation of ARM secure world software for i.MX
Marcel Ziswiler
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bl31
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aarch64
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bl31_entrypoint.S
Age
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Author
2019-12-13
imx: initialize register value before writting MU_SR register
Anson Huang
2019-12-13
imx8qm: turn off A53 cluster for cpu hotplug
Anson Huang
2019-09-13
Refactor ARMv8.3 Pointer Authentication support code
Alexei Fedorov
2019-05-24
Add support for Branch Target Identification
Alexei Fedorov
2019-03-25
PIE: Fix reloc at the beginning of bl31 entrypoint
Louis Mayencourt
2019-03-07
BL31: Enable pointer authentication support in warm boot path
Alexei Fedorov
2019-02-27
BL31: Enable pointer authentication support
Antonio Nino Diaz
2019-01-04
Sanitise includes across codebase
Antonio Nino Diaz
2018-10-29
PIE: Position Independant Executable support for BL31
Soby Mathew
2018-10-04
Remove some MISRA defects in common code
Antonio Nino Diaz
2018-06-27
DynamIQ: Enable MMU without using stack
Jeenu Viswambharan
2018-02-28
Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch
davidcunado-arm
2018-02-27
Add comments about mismatched TCR_ELx and xlat tables
Antonio Nino Diaz
2018-02-26
Introduce the new BL handover interface
Soby Mathew
2017-06-21
Fully initialise essential control registers
David Cunado
2017-05-03
Use SPDX license identifiers
dp-arm
2017-04-19
PSCI: Build option to enable D-Caches early in warmboot
Soby Mathew
2017-03-17
Merge pull request #860 from jeenu-arm/hw-asstd-coh
davidcunado-arm
2017-03-08
Simplify translation tables headers dependencies
Antonio Nino Diaz
2017-03-02
Enable data caches early with hardware-assisted coherency
Jeenu Viswambharan
2016-10-12
Add PMF instrumentation points in TF
dp-arm
2016-07-19
Introduce PSCI Library Interface
Soby Mathew
2015-12-14
Remove dashes from image names: 'BL3-x' --> 'BL3x'
Juan Castillo
2015-11-26
Introduce COLD_BOOT_SINGLE_CPU build option
Sandrine Bailleux
2015-09-14
Make generic code work in presence of system caches
Achin Gupta
2015-06-04
Introduce PROGRAMMABLE_RESET_ADDRESS build option
Sandrine Bailleux
2015-06-04
Rationalize reset handling code
Sandrine Bailleux
2015-04-08
Add support to indicate size and end of assembly functions
Kévin Petit
2015-03-13
Initialise cpu ops after enabling data cache
Vikram Kanigiri
2015-01-26
Call reset handlers upon BL3-1 entry.
Yatharth Kochar
2015-01-22
Remove coherent memory from the BL memory maps
Soby Mathew
2014-08-27
Miscellaneous documentation fixes
Sandrine Bailleux
2014-08-20
Add CPU specific power management operations
Soby Mathew
2014-08-20
Introduce framework for CPU specific operations
Soby Mathew
2014-08-15
Unmask SError interrupt and clear SCR_EL3.EA bit
Achin Gupta
2014-08-01
Call platform_is_primary_cpu() only from reset handler
Juan Castillo
2014-07-28
Merge pull request #172 from soby-mathew/sm/asm_assert
danh-arm
2014-07-28
Rework the crash reporting in BL3-1 to use less stack
Soby Mathew
2014-07-28
Simplify management of SCTLR_EL3 and SCTLR_EL1
Achin Gupta
2014-07-19
Remove coherent stack usage from the cold boot path
Achin Gupta
2014-06-27
Merge pull request #151 from vikramkanigiri/vk/t133-code-readability
Andrew Thoelke
2014-06-24
Simplify entry point information generation code on FVP
Vikram Kanigiri
2014-06-17
Remove early_exceptions from BL3-1
Andrew Thoelke
2014-06-16
Per-cpu data cache restructuring
Andrew Thoelke
2014-05-22
Introduce interrupt handling framework in BL3-1
Achin Gupta
2014-05-22
Add support for BL3-1 as a reset vector
Vikram Kanigiri
2014-05-22
Populate BL31 input parameters as per new spec
Vikram Kanigiri
2014-05-22
Rework handover interface between BL stages
Vikram Kanigiri
2014-05-08
Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu...
danh-arm
2014-05-08
Preserve x19-x29 across world switch for exception handling
Soby Mathew
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