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path: root/arch/riscv/dts/ae350_32.dts
AgeCommit message (Expand)Author
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin
2021-06-17riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng
2021-06-17riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng
2021-06-17riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng
2021-06-17riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng
2021-06-17riscv: ae350: dts: Add SPDX license headerBin Meng
2021-05-19riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng
2019-12-10riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen
2019-12-10riscv: dts: Support four cores SMPRick Chen
2019-09-03riscv: dts: move out AE350 L2 node from cpus nodeRick Chen
2019-04-12dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong
2019-04-08riscv: dts: ae350 support SMPRick Chen
2018-11-26riscv: dts: Add ae350_32.dts for RV32IRick Chen