u-boot-toradex.git - U-Boot bootloader for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2016-09-21	MIPS: Ensure cache ops complete in mips_cache_reset	Paul Burton
2016-09-21	MIPS: Clear hazard between TagLo writes & cache ops	Paul Burton
2016-09-21	MIPS: Join the coherent domain when a CM is present	Paul Burton
2016-09-21	MIPS: L2 cache support	Paul Burton
2016-09-21	MIPS: Define register names for cache init	Paul Burton
2016-09-21	MIPS: Enable use of the instruction cache earlier	Paul Burton
2016-05-31	MIPS: Split I & D cache line size config	Paul Burton
2016-05-31	MIPS: Move cache sizes to Kconfig	Paul Burton
2016-05-21	MIPS: Use unchecked immediate addition/subtraction	Paul Burton
2016-01-16	MIPS: sync processor and register definitions with linux-4.4	Daniel Schwierzeck
2015-01-29	MIPS: clear TagLo select 2 during cache init	Paul Burton
2015-01-29	MIPS: allow systems to skip loads during cache init	Paul Burton
2015-01-29	MIPS: inline mips_init_[id]cache functions	Paul Burton
2015-01-29	MIPS: refactor cache loops to a macro	Paul Burton
2015-01-29	MIPS: refactor L1 cache config reads to a macro	Paul Burton
2015-01-29	MIPS: unify cache initialization code	Paul Burton