| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-09-21 | MIPS: L2 cache support | Paul Burton |
| 2016-09-21 | MIPS: Probe cache line sizes once during boot | Paul Burton |
| 2016-06-10 | MIPS: Fix invalidate_dcache_range to operate on L1 Dcache | Paul Burton |
| 2016-05-31 | MIPS: Abstract cache op loops with a macro | Paul Burton |
| 2016-05-31 | MIPS: Split I & D cache line size config | Paul Burton |
| 2016-05-31 | MIPS: Move cache sizes to Kconfig | Paul Burton |
| 2016-02-01 | mips: cache: Bulletproof the code against cornercases | Marek Vasut |
| 2016-01-16 | MIPS: sync processor and register definitions with linux-4.4 | Daniel Schwierzeck |
| 2015-01-29 | MIPS: unify cache maintenance functions | Paul Burton |
 |
index : u-boot-toradex.git | |
| U-Boot bootloader for Apalis and Colibri modules | Marcel Ziswiler |
| summaryrefslogtreecommitdiff |