diff options
| author | Tom Rini <trini@konsulko.com> | 2022-06-20 14:40:59 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-20 14:40:59 -0400 |
| commit | 52af0101be55da74a32e9b169864508101f886fe (patch) | |
| tree | 0027962a3a4e43a1e29fa7411934501b75fe811b /drivers/ddr | |
| parent | 78533a1ce87786d2ba9be70e657b09cded1267e1 (diff) | |
| parent | 568a226f87655fd5339514f66413c2ad72f65d6f (diff) | |
Merge branch 'master' into next
Merge in v2022.07-rc5.
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/altera/sdram_n5x.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_s10.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.c | 5 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 2 |
4 files changed, 8 insertions, 7 deletions
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index ac13ac4319..737a4e2ff1 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* - * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> * */ diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index d3a6d21860..4d36fb4533 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> * */ @@ -277,7 +277,7 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_SCH_DEVTODEV); /* assigning the SDRAM size */ - unsigned long long size = sdram_calculate_size(plat); + phys_size_t size = sdram_calculate_size(plat); /* If the size is invalid, use default Config size */ if (size <= 0) hw_size = PHYS_SDRAM_1_SIZE; diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index d6baac2410..9b1710c135 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> * */ @@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7460f8c220..07a0f9f2ae 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -53,7 +53,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0xF #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f |