From 166e5b82a3f49239f67ac5f0d6df8abeb6ca0bdd Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Fri, 10 Jun 2022 19:18:00 +0800 Subject: intel: n5x: ddr: update license All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_n5x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/ddr') diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index ac13ac4319..737a4e2ff1 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* - * Copyright (C) 2020-2021 Intel Corporation + * Copyright (C) 2020-2022 Intel Corporation * */ -- cgit v1.2.3 From ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Wed, 27 Apr 2022 12:27:21 +0800 Subject: ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/ddr') diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7460f8c220..07a0f9f2ae 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -53,7 +53,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0xF #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f -- cgit v1.2.3 From 39bbcc341bda435899cb623a19d20727ca98c67a Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Wed, 27 Apr 2022 12:52:42 +0800 Subject: ddr: altera: Stratix10: Use phys_size_t for memory size Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_s10.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/ddr') diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index d3a6d21860..4d36fb4533 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2022 Intel Corporation * */ @@ -277,7 +277,7 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_SCH_DEVTODEV); /* assigning the SDRAM size */ - unsigned long long size = sdram_calculate_size(plat); + phys_size_t size = sdram_calculate_size(plat); /* If the size is invalid, use default Config size */ if (size <= 0) hw_size = PHYS_SDRAM_1_SIZE; -- cgit v1.2.3 From 32e0379143b433e29d76404f5f4c279067e48853 Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Wed, 1 Jun 2022 18:49:02 +0800 Subject: ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/ddr') diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index d6baac2410..9b1710c135 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2021 Intel Corporation + * Copyright (C) 2016-2022 Intel Corporation * */ @@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + -- cgit v1.2.3