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authorWolfgang Denk <wd@denx.de>2008-10-12 23:12:44 +0200
committerWolfgang Denk <wd@denx.de>2008-10-12 23:12:44 +0200
commit1f7bab0832cfd04fe534eba10e67a8b9def0dc4f (patch)
treeb21eed0da543e1f90dd57be02d86d71847fbcfaa /cpu
parent20d635142b0a0bfebe8687ffa22d366fc71ade34 (diff)
parentf3bf9273939ffe1a60a32a2eef909097f15df56b (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/cpu.c3
-rw-r--r--cpu/mpc85xx/fdt.c3
-rw-r--r--cpu/mpc85xx/speed.c7
3 files changed, 6 insertions, 7 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 67e81c0574d..f15b0a8c9e5 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -85,7 +85,8 @@ int checkcpu (void)
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index bc1550d7c26..037a60fba9a 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob)
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
- fdt_setprop_cell(blob, off, "cache-line-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
@@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob)
dnum_sets = dsize / (dline_size * dnum_ways);
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
- fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
@@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob)
inum_sets = isize / (iline_size * inum_ways);
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
- fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-size", isize);
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 1cda1e34ebf..70dfad0321e 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_DDR_CLK_FREQ
{
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
@@ -101,9 +102,9 @@ int get_clocks (void)
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->i2c1_clk = sys_info.freqSystemBus / 3;
- else
gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ else
+ gd->i2c1_clk = sys_info.freqSystemBus / 3;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
gd->i2c1_clk = sys_info.freqSystemBus / 2;