From bac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 7 Oct 2008 10:28:46 -0500 Subject: 85xx: Remove setting of *cache-line-size in device trees ePAPR says if the *cache-block-size is the same as *cache-line-size than we don't need the *cache-line-size property. Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bc1550d7c2..037a60fba9 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob) } fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); - fdt_setprop_cell(blob, off, "cache-line-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); @@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob) dnum_sets = dsize / (dline_size * dnum_ways); fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); - fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); @@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob) inum_sets = isize / (iline_size * inum_ways); fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); - fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); fdt_setprop_cell(blob, off, "i-cache-size", isize); fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); -- cgit v1.2.3 From c0391111c33c22fabeddf8f4ca801ec7645b4f5c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Sat, 27 Sep 2008 14:40:57 +0800 Subject: Fix the incorrect DDR clk freq reporting on 8536DS On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin --- cpu/mpc85xx/cpu.c | 3 ++- cpu/mpc85xx/speed.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 67e81c0574..f15b0a8c9e 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -85,7 +85,8 @@ int checkcpu (void) struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 1cda1e34eb..485ba20fd7 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_DDR_CLK_FREQ { - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } -- cgit v1.2.3 From dffd2446fb041f38ef034b0fcf41e51e5e489159 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Tue, 30 Sep 2008 10:55:57 +0200 Subject: 85xx: Using proper I2C source clock divider for MPC8544 Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 485ba20fd7..70dfad0321 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 3; - else gd->i2c1_clk = sys_info.freqSystemBus / 2; + else + gd->i2c1_clk = sys_info.freqSystemBus / 3; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; -- cgit v1.2.3