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authorSudhakar Rajashekara <x0096290@linux-psp-server.(none)>2009-03-18 05:32:39 -0400
committerJustin Waters <justin.waters@timesys.com>2009-09-09 14:03:19 -0400
commite14ced58a6b692309c5e074e7e1f34385fb3eca8 (patch)
tree19f5c841faa9ca9a0b50b7478aca5cab12fd126d /cpu/arm926ejs
parente3efef4a083b1ef5779cd8a3441415e73245e68a (diff)
Support for multiple instance of PLL and reading from PLL1.
Signed-off-by: Sudhakar Rajashekara <sudhakar.raj@ti.com>
Diffstat (limited to 'cpu/arm926ejs')
-rw-r--r--cpu/arm926ejs/da8xx/clock.c26
-rw-r--r--cpu/arm926ejs/da8xx/lowlevel_init.S6
2 files changed, 21 insertions, 11 deletions
diff --git a/cpu/arm926ejs/da8xx/clock.c b/cpu/arm926ejs/da8xx/clock.c
index 7cb979bc00..ff8e36ce5a 100644
--- a/cpu/arm926ejs/da8xx/clock.c
+++ b/cpu/arm926ejs/da8xx/clock.c
@@ -22,16 +22,26 @@
#include <common.h>
#include <asm/arch/hardware.h>
-dv_reg_p sysdiv[9] = {
- PLL0_DIV1, PLL0_DIV2, PLL0_DIV3, PLL0_DIV4, PLL0_DIV5, PLL0_DIV6,
- PLL0_DIV7, PLL0_DIV8, PLL0_DIV9 };
+unsigned int sysdiv[9] = {
+ PLL_DIV1, PLL_DIV2, PLL_DIV3, PLL_DIV4, PLL_DIV5, PLL_DIV6,
+ PLL_DIV7, PLL_DIV8, PLL_DIV9 };
int clk_get(unsigned int id)
{
- int pre_div = (REG(PLL0_PREDIV) & 0xff) + 1;
- int pllm = REG(PLL0_PLLM) + 1;
- int post_div = (REG(PLL0_POSTDIV) & 0xff) + 1;
int pll_out = CFG_OSCIN_FREQ;
+ int pre_div;
+ int pllm;
+ int post_div;
+ volatile unsigned int pll_base;
+
+ if ((id >> 8) == 1)
+ pll_base = DAVINCI_PLL_CNTRL1_BASE;
+ else
+ pll_base = DAVINCI_PLL_CNTRL0_BASE;
+
+ pre_div = (REG(pll_base + PLL_PREDIV) & 0xff) + 1;
+ pllm = REG(pll_base + PLL_PLLM) + 1;
+ post_div = (REG(pll_base + PLL_POSTDIV) & 0xff) + 1;
if(id == DAVINCI_AUXCLK_CLKID)
goto out;
@@ -49,8 +59,8 @@ int clk_get(unsigned int id)
if(id == DAVINCI_PLLC_CLKID)
goto out;
-
- pll_out /= (REG(sysdiv[id - 1]) & 0xff) + 1;
+
+ pll_out /= (REG(pll_base + sysdiv[(id & 0xff) - 1]) & 0xff) + 1;
out:
return pll_out;
diff --git a/cpu/arm926ejs/da8xx/lowlevel_init.S b/cpu/arm926ejs/da8xx/lowlevel_init.S
index c36993e16e..a89102261d 100644
--- a/cpu/arm926ejs/da8xx/lowlevel_init.S
+++ b/cpu/arm926ejs/da8xx/lowlevel_init.S
@@ -492,11 +492,11 @@ PLL_LOCK_COUNT:
/* PLL0 MMRs */
PLL0_PLLCTL_ADDR:
- .word PLL0_PLLCTL
+ .word DAVINCI_PLL_CNTRL0_BASE + PLL_PLLCTL
PLL0_PLLM_ADDR:
- .word PLL0_PLLM
+ .word DAVINCI_PLL_CNTRL0_BASE + PLL_PLLM
PLL0_POSTDIV_ADDR:
- .word PLL0_POSTDIV
+ .word DAVINCI_PLL_CNTRL0_BASE + PLL_POSTDIV
DDR2_START_ADDR:
.word 0xc0000000