From e14ced58a6b692309c5e074e7e1f34385fb3eca8 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekara Date: Wed, 18 Mar 2009 05:32:39 -0400 Subject: Support for multiple instance of PLL and reading from PLL1. Signed-off-by: Sudhakar Rajashekara --- cpu/arm926ejs/da8xx/clock.c | 26 ++++++++++++++++++-------- cpu/arm926ejs/da8xx/lowlevel_init.S | 6 +++--- 2 files changed, 21 insertions(+), 11 deletions(-) (limited to 'cpu/arm926ejs') diff --git a/cpu/arm926ejs/da8xx/clock.c b/cpu/arm926ejs/da8xx/clock.c index 7cb979bc005..ff8e36ce5ae 100644 --- a/cpu/arm926ejs/da8xx/clock.c +++ b/cpu/arm926ejs/da8xx/clock.c @@ -22,16 +22,26 @@ #include #include -dv_reg_p sysdiv[9] = { - PLL0_DIV1, PLL0_DIV2, PLL0_DIV3, PLL0_DIV4, PLL0_DIV5, PLL0_DIV6, - PLL0_DIV7, PLL0_DIV8, PLL0_DIV9 }; +unsigned int sysdiv[9] = { + PLL_DIV1, PLL_DIV2, PLL_DIV3, PLL_DIV4, PLL_DIV5, PLL_DIV6, + PLL_DIV7, PLL_DIV8, PLL_DIV9 }; int clk_get(unsigned int id) { - int pre_div = (REG(PLL0_PREDIV) & 0xff) + 1; - int pllm = REG(PLL0_PLLM) + 1; - int post_div = (REG(PLL0_POSTDIV) & 0xff) + 1; int pll_out = CFG_OSCIN_FREQ; + int pre_div; + int pllm; + int post_div; + volatile unsigned int pll_base; + + if ((id >> 8) == 1) + pll_base = DAVINCI_PLL_CNTRL1_BASE; + else + pll_base = DAVINCI_PLL_CNTRL0_BASE; + + pre_div = (REG(pll_base + PLL_PREDIV) & 0xff) + 1; + pllm = REG(pll_base + PLL_PLLM) + 1; + post_div = (REG(pll_base + PLL_POSTDIV) & 0xff) + 1; if(id == DAVINCI_AUXCLK_CLKID) goto out; @@ -49,8 +59,8 @@ int clk_get(unsigned int id) if(id == DAVINCI_PLLC_CLKID) goto out; - - pll_out /= (REG(sysdiv[id - 1]) & 0xff) + 1; + + pll_out /= (REG(pll_base + sysdiv[(id & 0xff) - 1]) & 0xff) + 1; out: return pll_out; diff --git a/cpu/arm926ejs/da8xx/lowlevel_init.S b/cpu/arm926ejs/da8xx/lowlevel_init.S index c36993e16ef..a89102261db 100644 --- a/cpu/arm926ejs/da8xx/lowlevel_init.S +++ b/cpu/arm926ejs/da8xx/lowlevel_init.S @@ -492,11 +492,11 @@ PLL_LOCK_COUNT: /* PLL0 MMRs */ PLL0_PLLCTL_ADDR: - .word PLL0_PLLCTL + .word DAVINCI_PLL_CNTRL0_BASE + PLL_PLLCTL PLL0_PLLM_ADDR: - .word PLL0_PLLM + .word DAVINCI_PLL_CNTRL0_BASE + PLL_PLLM PLL0_POSTDIV_ADDR: - .word PLL0_POSTDIV + .word DAVINCI_PLL_CNTRL0_BASE + PLL_POSTDIV DDR2_START_ADDR: .word 0xc0000000 -- cgit v1.2.3