diff options
| author | Peng Fan <peng.fan@nxp.com> | 2022-09-20 12:24:34 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-09-28 21:04:04 +0800 |
| commit | fab973fe1dfcb514793e0653a897e022add4f33a (patch) | |
| tree | 2d7559a63c34af6f4b481d13b671c61bae516887 /arch/arm/mach-imx/imx8m/clock_imx8mm.c | |
| parent | 4881ba99fa4efa2edd8a7b8f95f85ea48d9858ba (diff) | |
LFU-397 imx8m: clock: not configure reserved SRC register
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 78d7ccda83f729d7f7b5f4b731a6d35764cdc402)
Diffstat (limited to 'arch/arm/mach-imx/imx8m/clock_imx8mm.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d6be307e6e..203c52d1d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -83,7 +83,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; |