From fab973fe1dfcb514793e0653a897e022add4f33a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 20 Sep 2022 12:24:34 +0800 Subject: LFU-397 imx8m: clock: not configure reserved SRC register i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it. Reviewed-by: Ye Li Signed-off-by: Peng Fan (cherry picked from commit 78d7ccda83f729d7f7b5f4b731a6d35764cdc402) --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-imx/imx8m/clock_imx8mm.c') diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d6be307e6e..203c52d1d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -83,7 +83,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; -- cgit v1.2.3