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authorTom Rini <trini@konsulko.com>2019-04-24 09:04:23 -0400
committerTom Rini <trini@konsulko.com>2019-04-24 09:04:23 -0400
commit3fbd2dce351ab5d40d3244f26bd713caa4f826e2 (patch)
tree4a8e5c2fd2dee4abed674da4ce0312af06f97bc1 /arch/arm/include
parent8a94262435ca559a5e2dad79f2dc3c130e9047a8 (diff)
parent74a7e0018a97a0e7318c4c7a3b473fd9ebbb5ad1 (diff)
Merge branch '2019-04-22-master-imports'
- Add and enable brcmnand driver on a number of relevant platforms. Also add and enable LED drivers on more bcm platforms. - Various ARMv8 fixes/improvements, including extending PSCI functionality. - fs_loader improvments - Various FIT/SPL improvements - PCI bugfixes - Poplar platform ethernet support - MediaTek MMC improvements - Android boot improvements
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/io.h21
-rw-r--r--arch/arm/include/asm/secure.h31
2 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 12bc7fbe06..e6d27b69f9 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -123,6 +123,27 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.
+ */
+#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+ __raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+ __raw_readl(c)); __r; })
+#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
+ __raw_readq(c)); __r; })
+
+#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
+#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
+ cpu_to_le16(v), (c)))
+#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
+ cpu_to_le32(v), (c)))
+#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
+ cpu_to_le64(v), (c)))
+
+/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index d23044a1c3..50582c972b 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,6 +6,37 @@
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
+#ifndef __ASSEMBLY__
+
+typedef struct secure_svc_tbl {
+ u32 id;
+#ifdef CONFIG_ARMV8_PSCI
+ u8 pad[4];
+#endif
+ void *func;
+} secure_svc_tbl_t;
+
+/*
+ * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section
+ */
+#define DECLARE_SECURE_SVC(_name, _id, _fn) \
+ static const secure_svc_tbl_t __secure_svc_ ## _name \
+ __attribute__((used, section("._secure_svc_tbl_entries"))) \
+ = { \
+ .id = _id, \
+ .func = _fn }
+
+#else
+
+#ifdef CONFIG_ARMV8_PSCI
+#define SECURE_SVC_TBL_OFFSET 16
+#else
+#define SECURE_SVC_TBL_OFFSET 8
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.