From 6478848d165b63293f7021db9b70ce25a1e1062c Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:33 +0100 Subject: arm: asm: io.h: define readX_relaxed and writeX_relaxed This patch port the function readX_relaxed and writeX_relaxed from kernel 4.18. Signed-off-by: Philippe Reynes --- arch/arm/include/asm/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 12bc7fbe06e..e6d27b69f93 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -122,6 +122,27 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) #define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ + __raw_readw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ + __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) +#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ + cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ + cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ + cpu_to_le64(v), (c))) + /* * The compiler seems to be incapable of optimising constants * properly. Spell it out to the compiler in some cases. -- cgit v1.2.3 From f6b0115a966cc0f0eb816a1570ccd99dd5611b3f Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Tue, 12 Feb 2019 00:27:02 -0800 Subject: ARMv8: Allow SiP service extensions on top of PSCI code Allow PSCI layer to handle any SiP service functions added by platform vendors. PSCI layer will look for SiP service function in the SiP function table located in '._secure_svc_tbl_entries' section if the SMC function identifier is not found in the PSCI standard functions table. Use DECLARE_SECURE_SVC macro to declare and add platform specific SiP service function. This new section '._secure_svc_tbl_entries' is located next to '._secure.text' section. Refer to arch/arm/cpu/armv8/u-boot.lds. Signed-off-by: Chee Hong Ang --- arch/arm/include/asm/secure.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index d23044a1c36..50582c972b7 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -6,6 +6,37 @@ #define __secure __attribute__ ((section ("._secure.text"))) #define __secure_data __attribute__ ((section ("._secure.data"))) +#ifndef __ASSEMBLY__ + +typedef struct secure_svc_tbl { + u32 id; +#ifdef CONFIG_ARMV8_PSCI + u8 pad[4]; +#endif + void *func; +} secure_svc_tbl_t; + +/* + * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section + */ +#define DECLARE_SECURE_SVC(_name, _id, _fn) \ + static const secure_svc_tbl_t __secure_svc_ ## _name \ + __attribute__((used, section("._secure_svc_tbl_entries"))) \ + = { \ + .id = _id, \ + .func = _fn } + +#else + +#ifdef CONFIG_ARMV8_PSCI +#define SECURE_SVC_TBL_OFFSET 16 +#else +#define SECURE_SVC_TBL_OFFSET 8 + +#endif + +#endif /* __ASSEMBLY__ */ + #if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE) /* * Warning, horror ahead. -- cgit v1.2.3