diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-02-12 01:33:45 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-02-15 14:37:59 -0500 |
| commit | 1b0d82a273e0b1e35af8c33dfc25322ab7242bca (patch) | |
| tree | eeeefe53dbc26250a9f72330f1b537210b28d359 /arch/arm/include/asm/omap_common.h | |
| parent | 2aea02d038d8c9a810d6d09f53a6f7695de370ce (diff) | |
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/omap_common.h')
| -rw-r--r-- | arch/arm/include/asm/omap_common.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec9383..0af0c3376c4 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs { /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; |