From 1b0d82a273e0b1e35af8c33dfc25322ab7242bca Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 01:33:45 +0000 Subject: ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Cc: Tom Rini --- arch/arm/include/asm/omap_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec9383..0af0c3376c4 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs { /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; -- cgit v1.2.3