diff options
Diffstat (limited to 'ecos/packages/hal/cortexm/stm32/var/current/include')
11 files changed, 4248 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h new file mode 100644 index 0000000..0a19bc9 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h @@ -0,0 +1,194 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2004-07-23 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// +// For the STM32, these are empty macros as there +// is no cache. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h new file mode 100644 index 0000000..207930b --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h @@ -0,0 +1,91 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_stm32_diag_init(void); +__externC void hal_stm32_diag_putc(char); +__externC cyg_uint8 hal_stm32_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_stm32_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_stm32_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_stm32_diag_getc() +# endif + +#endif + + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h new file mode 100644 index 0000000..d1d9db3 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:jskov, gthomas, jlarmour +// Date: 2008-07-30 +// Purpose: Platform HAL stub support for STM32 variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/cortexm_stub.h> // architecture stub support + +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h new file mode 100644 index 0000000..1bc50a2 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// STM32 variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32 variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_arch.h> + +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h new file mode 100644 index 0000000..dc4089f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h @@ -0,0 +1,146 @@ +#ifndef CYGONCE_HAL_VAR_DMA_H +#define CYGONCE_HAL_VAR_DMA_H +//============================================================================= +// +// var_dma.h +// +// STM32 DMA support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2011-12-07 +// Purpose: STM32 DMA support +// Description: +// Usage: #include <cyg/hal/var_dma.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_cortexm_stm32.h> + +#include <cyg/hal/drv_api.h> + +//============================================================================= +// DMA stream descriptors + +#define CYGHWR_HAL_STM32_DMA_MODE_P2M 0 +#define CYGHWR_HAL_STM32_DMA_MODE_M2P 1 +#define CYGHWR_HAL_STM32_DMA_MODE_M2M 2 + + +// DMA descriptor. Packs interrupt vector, controller, stream and +// channel IDs together with the mode into a 32 bit descriptor. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode ) \ + (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_CH##__stream)<<16) | \ + ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) | \ + ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0)) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode ) \ + (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_STR##__stream)<<16) | \ + ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) | \ + ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0)) +#else +#error "Undefined STM32 family" +#endif + +#define CYGHWR_HAL_STM32_DMA_INTERRUPT( __desc ) (((__desc)>>16)&0xFFFF) +#define CYGHWR_HAL_STM32_DMA_MODE( __desc ) (((__desc)>>12)&0xF) +#define CYGHWR_HAL_STM32_DMA_CHANNEL( __desc ) (((__desc)>>8)&0xF) +#define CYGHWR_HAL_STM32_DMA_STREAM( __desc ) (((__desc)>>4)&0xF) +#define CYGHWR_HAL_STM32_DMA_CONTROLLER( __desc ) (((__desc)>>0)&0xF) + +//============================================================================= +// API + +#ifndef __ASSEMBLER__ + +typedef struct hal_stm32_dma_stream hal_stm32_dma_stream; + +typedef void hal_stm32_dma_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data ); + +struct hal_stm32_dma_stream +{ + // These fields need to be initialized before calling + // hal_stm32_dma_init(). This can usually be done statically, when + // defining an containing data structure. + + cyg_uint32 desc; // stream descriptor + hal_stm32_dma_callback *callback; // Callback function + CYG_ADDRWORD data; // Client private data + + + // Runtime data + + CYG_ADDRWORD ctlr; // Controller base address + CYG_ADDRWORD stream; // Stream/channel index + + cyg_uint32 ccr; // Channel control register value + cyg_bool active; // Channel active + cyg_uint32 count; // Bytes left to transfer + + cyg_interrupt interrupt; // DMA interrupt object + cyg_handle_t handle; // Interrupt handle +}; + + +__externC void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri ); + +__externC void hal_stm32_dma_delete( hal_stm32_dma_stream *stream ); + +__externC void hal_stm32_dma_disable( hal_stm32_dma_stream *stream ); + +__externC void hal_stm32_dma_poll( hal_stm32_dma_stream *stream ); + +__externC void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size, + cyg_bool no_minc, cyg_bool polled ); + +__externC void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream, + cyg_bool enable); + +__externC void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory, + CYG_ADDRESS peripheral, cyg_uint32 size ); + +__externC void hal_stm32_dma_show( hal_stm32_dma_stream *stream ); + +#endif // __ASSEMBLER__ + +#endif // CYGONCE_HAL_VAR_DMA_H +//----------------------------------------------------------------------------- +// end of var_dma.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h new file mode 100644 index 0000000..05835f9 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h @@ -0,0 +1,427 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for STM32 variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-10-06 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for ST STM32 variants are +// defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + + +#define CYGNUM_HAL_INTERRUPT_WWDG ( 0+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_PVD ( 1+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TAMPER ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TAMP_STAMP ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name - also timestamps +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_RTC_GLOBAL ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_RTC_WKUP ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_FLASH ( 4+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RCC ( 5+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI0 ( 6+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI1 ( 7+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI2 ( 8+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI3 ( 9+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#define CYGNUM_HAL_INTERRUPT_EXTI4 (10+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA1_CH1 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR0 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH2 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR1 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH3 (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR2 (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH4 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR3 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH5 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR4 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH6 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR5 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH7 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR6 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_ADC1_2 (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 only has ADC1+2 +#define CYGNUM_HAL_INTERRUPT_ADC1_2_3 (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has ADC1+2+3 +#define CYGNUM_HAL_INTERRUPT_ADC (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // More generic name +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_HP (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_CAN1_TX (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_LP (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_CAN1_RX0 (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN1_RX1 (21+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN1_SCE (22+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI9_5 (23+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_BRK (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_BRK_TIM9 (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM9 +#define CYGNUM_HAL_INTERRUPT_TIM1_UP (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_UP_TIM10 (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM10 +#define CYGNUM_HAL_INTERRUPT_TIM1_TRG (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_TRG_COM_TIM11 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM11 +#define CYGNUM_HAL_INTERRUPT_TIM1_CC (27+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM2 (28+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM3 (29+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#define CYGNUM_HAL_INTERRUPT_TIM4 (30+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_EV (31+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_EE (32+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C2_EV (33+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C2_EE (34+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI1 (35+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI2 (36+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART1 (37+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART2 (38+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART3 (39+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#define CYGNUM_HAL_INTERRUPT_EXTI15_10 (40+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RTC_ALARM (41+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_WAKEUP (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGNUM_HAL_INTERRUPT_TIM8_BRK (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM8_UP (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM8_TRG (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM8_CC (46+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_ADC3 (47+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_FSMC (48+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SDIO (49+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#else +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_TIM8_BRK_TIM12 (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM12 +#define CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13 (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13 +#define CYGNUM_HAL_INTERRUPT_TIM8_TRG_COM_TIM14 (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13 +#define CYGNUM_HAL_INTERRUPT_TIM8_CC (46+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA1_STR7 (47+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_FSMC (48+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SDIO (49+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#endif + +#define CYGNUM_HAL_INTERRUPT_TIM5 (50+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI3 (51+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART4 (52+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART5 (53+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM6 (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM6_DAC (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because also DAC1+2 underrun +#define CYGNUM_HAL_INTERRUPT_TIM7 (55+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_CH1 (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR0 (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA2_CH2 (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR1 (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA2_CH3 (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR2 (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams + +#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +# error Support does not yet exist for F2 or F4 without connectivity +#endif + +#define CYGNUM_HAL_INTERRUPT_DMA2_CH4 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_CH5 (CYGNUM_HAL_INTERRUPT_DMA2_CH4) // As per RM0008 datasheet 3.3.6 note + +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#else + +#define CYGNUM_HAL_INTERRUPT_DMA2_CH4 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR3 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams + +#define CYGNUM_HAL_INTERRUPT_DMA2_CH5 (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR4 (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_ETH (61+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ETH_WAKEUP (62+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_TX (63+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_RX0 (64+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_RX1 (65+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_SCE (66+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_FS (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_OTG_FS (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_STR5 (68+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_STR6 (69+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_STR7 (70+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART6 (71+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C3_EV (72+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C3_ER (73+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_OUT (74+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_IN (75+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP (76+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS (77+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DCMI (78+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CRYP (79+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_HASH_RNG (80+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +# define CYGNUM_HAL_INTERRUPT_HASH_FPU (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +# define CYGNUM_HAL_INTERRUPT_NVIC_MAX (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +# define CYGNUM_HAL_INTERRUPT_NVIC_MAX (80+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#else +# error "Support does not yet exist for this FAMILY_HIPERFORMANCE configuration" +#endif +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#endif // ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#define CYGNUM_HAL_INTERRUPT_EXTI5 ( 1+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI6 ( 2+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI7 ( 3+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI8 ( 4+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI9 ( 5+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI10 ( 6+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI11 ( 7+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI12 ( 8+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI13 ( 9+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI14 (10+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI15 (11+CYGNUM_HAL_INTERRUPT_NVIC_MAX) + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTI15 +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +#define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +//========================================================================== +// Interrupt mask and config for variant-specific devices + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ + break; \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + case CYGNUM_HAL_INTERRUPT_USB_WAKEUP: \ + __v = 18; \ + break; + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ + break; \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + case CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP: \ + __v = 18; \ + break; \ + case CYGNUM_HAL_INTERRUPT_ETH_WAKEUP: \ + __v = 19; \ + break; \ + case CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP: \ + __v = 20; \ + break; \ + case CYGNUM_HAL_INTERRUPT_TAMP_STAMP: \ + __v = 21; \ + break; \ + case CYGNUM_HAL_INTERRUPT_RTC_WKUP: \ + __v = 22; \ + break; + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define HAL_VAR_INTERRUPT_MASK( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __imr; \ + HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + __imr &= ~CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + } \ +} + +#define HAL_VAR_INTERRUPT_UNMASK( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL), \ + CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL), \ + CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __imr; \ + HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + __imr |= CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + } \ +} + +#define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT + +#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_PR, __bit ); \ + } \ +} + +#define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if(( __v >= 0 ) && !(__level) ) \ + { \ + cyg_uint32 __base = CYGHWR_HAL_STM32_EXTI; \ + cyg_uint32 __rtsr, __ftsr; \ + cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr ); \ + HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr ); \ + if( __up ) __rtsr |= __bit, __ftsr &= ~__bit; \ + else __ftsr |= __bit, __rtsr &= ~__bit; \ + HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr ); \ + HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr ); \ + } \ +} + + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h new file mode 100644 index 0000000..b947bf5 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h @@ -0,0 +1,1931 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32 variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_cortexm_stm32.h> + +#include <cyg/hal/plf_io.h> + +//============================================================================= +// Peripherals + +#define CYGHWR_HAL_STM32_TIM2 0x40000000 +#define CYGHWR_HAL_STM32_TIM3 0x40000400 +#define CYGHWR_HAL_STM32_TIM4 0x40000800 +#define CYGHWR_HAL_STM32_TIM5 0x40000C00 +#define CYGHWR_HAL_STM32_TIM6 0x40001000 +#define CYGHWR_HAL_STM32_TIM7 0x40001400 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_TIM12 0x40001800 +#define CYGHWR_HAL_STM32_TIM13 0x40001C00 +#define CYGHWR_HAL_STM32_TIM14 0x40002000 +#endif +#define CYGHWR_HAL_STM32_RTC 0x40002800 +#define CYGHWR_HAL_STM32_WWDG 0x40002C00 +#define CYGHWR_HAL_STM32_IWDG 0x40003000 +#define CYGHWR_HAL_STM32_SPI2 0x40003800 +#define CYGHWR_HAL_STM32_SPI3 0x40003C00 +#define CYGHWR_HAL_STM32_UART2 0x40004400 +#define CYGHWR_HAL_STM32_UART3 0x40004800 +#define CYGHWR_HAL_STM32_UART4 0x40004C00 +#define CYGHWR_HAL_STM32_UART5 0x40005000 +#define CYGHWR_HAL_STM32_I2C1 0x40005400 +#define CYGHWR_HAL_STM32_I2C2 0x40005800 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_USB 0x40005C00 +#define CYGHWR_HAL_STM32_USB_CAN_SRAM 0x40006000 +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_I2C3 0x40005C00 +#endif +#define CYGHWR_HAL_STM32_BXCAN1 0x40006400 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_BXCAN2 0x40006800 +#endif +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_BKP 0x40006C00 +#endif +#define CYGHWR_HAL_STM32_PWR 0x40007000 +#define CYGHWR_HAL_STM32_DAC 0x40007400 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_AFIO 0x40010000 +#define CYGHWR_HAL_STM32_EXTI 0x40010400 +#define CYGHWR_HAL_STM32_GPIOA 0x40010800 +#define CYGHWR_HAL_STM32_GPIOB 0x40010C00 +#define CYGHWR_HAL_STM32_GPIOC 0x40011000 +#define CYGHWR_HAL_STM32_GPIOD 0x40011400 +#define CYGHWR_HAL_STM32_GPIOE 0x40011800 +#define CYGHWR_HAL_STM32_GPIOF 0x40011C00 +#define CYGHWR_HAL_STM32_GPIOG 0x40012000 +#define CYGHWR_HAL_STM32_ADC1 0x40012400 +#define CYGHWR_HAL_STM32_ADC2 0x40012800 +#define CYGHWR_HAL_STM32_TIM1 0x40012C00 +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_TIM1 0x40010000 +#define CYGHWR_HAL_STM32_PWM1 0x40010000 +#define CYGHWR_HAL_STM32_TIM8 0x40010400 +#define CYGHWR_HAL_STM32_PWM2 0x40010400 +#define CYGHWR_HAL_STM32_UART1 0x40011000 +#define CYGHWR_HAL_STM32_UART6 0x40011400 +#define CYGHWR_HAL_STM32_ADC1 0x40012000 +#define CYGHWR_HAL_STM32_ADC2 CYGHWR_HAL_STM32_ADC1 + 0x0100 +#define CYGHWR_HAL_STM32_ADC3 CYGHWR_HAL_STM32_ADC1 + 0x0200 +#define CYGHWR_HAL_STM32_ADC_COMMON CYGHWR_HAL_STM32_ADC1 + 0x0300 +#define CYGHWR_HAL_STM32_SDIO 0x40012C00 +#endif +#define CYGHWR_HAL_STM32_SPI1 0x40013000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_TIM8 0x40013400 +#define CYGHWR_HAL_STM32_UART1 0x40013800 +#define CYGHWR_HAL_STM32_ADC3 0x40013C00 +#define CYGHWR_HAL_STM32_SDIO 0x40018000 +#define CYGHWR_HAL_STM32_DMA1 0x40020000 +#define CYGHWR_HAL_STM32_DMA2 0x40020400 +#define CYGHWR_HAL_STM32_RCC 0x40021000 +#define CYGHWR_HAL_STM32_FLASH 0x40022000 +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_SYSCFG 0x40013800 +#define CYGHWR_HAL_STM32_EXTI 0x40013C00 +#define CYGHWR_HAL_STM32_TIM9 0x40014000 +#define CYGHWR_HAL_STM32_TIM10 0x40014400 +#define CYGHWR_HAL_STM32_TIM11 0x40014800 +#define CYGHWR_HAL_STM32_GPIOA 0x40020000 +#define CYGHWR_HAL_STM32_GPIOB 0x40020400 +#define CYGHWR_HAL_STM32_GPIOC 0x40020800 +#define CYGHWR_HAL_STM32_GPIOD 0x40020C00 +#define CYGHWR_HAL_STM32_GPIOE 0x40021000 +#define CYGHWR_HAL_STM32_GPIOF 0x40021400 +#define CYGHWR_HAL_STM32_GPIOG 0x40021800 +#define CYGHWR_HAL_STM32_GPIOH 0x40021C00 +#define CYGHWR_HAL_STM32_GPIOI 0x40022000 +#endif +#define CYGHWR_HAL_STM32_CRC 0x40023000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC 0x40023800 +#define CYGHWR_HAL_STM32_FLASH 0x40023C00 +#define CYGHWR_HAL_STM32_BKPSRAM 0x40024000 +#define CYGHWR_HAL_STM32_DMA1 0x40026000 +#define CYGHWR_HAL_STM32_DMA2 0x40026400 +#endif +#define CYGHWR_HAL_STM32_ETH 0x40028000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_USB_OTG_HS 0x40040000 +#endif +#define CYGHWR_HAL_STM32_USB_OTG_FS 0x50000000 +#define CYGHWR_HAL_STM32_OTG CYGHWR_HAL_STM32_USB_OTG_FS // compatibility define. Deprecated. +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_DCMI 0x50050000 +#define CYGHWR_HAL_STM32_CRYP 0x50060000 +#define CYGHWR_HAL_STM32_HASH 0x50060400 +#define CYGHWR_HAL_STM32_RNG 0x50060800 +#endif +#define CYGHWR_HAL_STM32_FSMC 0xA0000000 + +//============================================================================= +// Device signature and ID registers + +#define CYGHWR_HAL_STM32_DEV_SIG 0x1FFFF7E0 +#define CYGHWR_HAL_STM32_DEV_SIG_RSIZE(__s) (((__s)>>16)&0xFFFF) +#define CYGHWR_HAL_STM32_DEV_SIG_FSIZE(__s) ((__s)&0xFFFF) + +#define CYGHWR_HAL_STM32_MCU_ID 0xe0042000 +#define CYGHWR_HAL_STM32_MCU_ID_DEV(__x) ((__x)&0xFFF) +#define CYGHWR_HAL_STM32_MCU_ID_DEV_MEDIUM 0x410 +#define CYGHWR_HAL_STM32_MCU_ID_DEV_HIGH 0x414 +#define CYGHWR_HAL_STM32_MCU_ID_REV(__x) (((__x)>>16)&0xFFFF) + +//============================================================================= +// RCC +// +// Not all registers are described here + +#define CYGHWR_HAL_STM32_RCC_CR 0x00 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RCC_CFGR 0x04 +#define CYGHWR_HAL_STM32_RCC_CIR 0x08 +#define CYGHWR_HAL_STM32_RCC_APB2RSTR 0x0C +#define CYGHWR_HAL_STM32_RCC_APB1RSTR 0x10 +#define CYGHWR_HAL_STM32_RCC_AHBENR 0x14 +#define CYGHWR_HAL_STM32_RCC_APB2ENR 0x18 +#define CYGHWR_HAL_STM32_RCC_APB1ENR 0x1C +#define CYGHWR_HAL_STM32_RCC_BDCR 0x20 +#define CYGHWR_HAL_STM32_RCC_CSR 0x24 +# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_AHBRSTR 0x28 +#define CYGHWR_HAL_STM32_RCC_CFGR2 0x2C +# endif +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR 0x04 +#define CYGHWR_HAL_STM32_RCC_CFGR 0x08 +#define CYGHWR_HAL_STM32_RCC_CIR 0x0C +#define CYGHWR_HAL_STM32_RCC_AHB1RSTR 0x10 +#define CYGHWR_HAL_STM32_RCC_AHB2RSTR 0x14 +#define CYGHWR_HAL_STM32_RCC_AHB3RSTR 0x18 +#define CYGHWR_HAL_STM32_RCC_APB1RSTR 0x20 +#define CYGHWR_HAL_STM32_RCC_APB2RSTR 0x24 +#define CYGHWR_HAL_STM32_RCC_AHB1ENR 0x30 +#define CYGHWR_HAL_STM32_RCC_AHB2ENR 0x34 +#define CYGHWR_HAL_STM32_RCC_AHB3ENR 0x38 +#define CYGHWR_HAL_STM32_RCC_APB1ENR 0x40 +#define CYGHWR_HAL_STM32_RCC_APB2ENR 0x44 +#define CYGHWR_HAL_STM32_RCC_AHB1LPENR 0x50 +#define CYGHWR_HAL_STM32_RCC_AHB2LPENR 0x54 +#define CYGHWR_HAL_STM32_RCC_AHB3LPENR 0x58 +#define CYGHWR_HAL_STM32_RCC_APB1LPENR 0x60 +#define CYGHWR_HAL_STM32_RCC_APB2LPENR 0x64 +#define CYGHWR_HAL_STM32_RCC_BDCR 0x70 +#define CYGHWR_HAL_STM32_RCC_CSR 0x74 +#endif + +#define CYGHWR_HAL_STM32_RCC_CR_HSION BIT_(0) +#define CYGHWR_HAL_STM32_RCC_CR_HSIRDY BIT_(1) +#define CYGHWR_HAL_STM32_RCC_CR_HSITRIM MASK_(3,5) +#define CYGHWR_HAL_STM32_RCC_CR_HSICAL MASK_(8,8) +#define CYGHWR_HAL_STM32_RCC_CR_HSEON BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CR_HSERDY BIT_(17) +#define CYGHWR_HAL_STM32_RCC_CR_HSEBYP BIT_(18) +#define CYGHWR_HAL_STM32_RCC_CR_CSSON BIT_(19) +#define CYGHWR_HAL_STM32_RCC_CR_PLLON BIT_(24) +#define CYGHWR_HAL_STM32_RCC_CR_PLLRDY BIT_(25) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SON BIT_(26) +#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SRDY BIT_(27) +#endif + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(__m) VALUE_(0,__m) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM_MASK MASK_(0,6) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(__n) VALUE_(6,__n) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN_MASK MASK_(6,9) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(__p) VALUE_(16,((__p)>>1)-1 ) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_2 VALUE_(16,0) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_4 VALUE_(16,1) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_6 VALUE_(16,2) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_8 VALUE_(16,3) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSI VALUE_(22,0) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE VALUE_(22,1) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(__q) VALUE_(24,__q) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ_MASK MASK_(24,4) +#endif + +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSI VALUE_(0,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSE VALUE_(0,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_PLL VALUE_(0,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_XXX VALUE_(0,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_HSI VALUE_(2,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_HSE VALUE_(2,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_PLL VALUE_(2,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_XXX VALUE_(2,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_1 VALUE_(4,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_2 VALUE_(4,8) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_4 VALUE_(4,9) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_8 VALUE_(4,10) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_16 VALUE_(4,11) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_64 VALUE_(4,12) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_128 VALUE_(4,13) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_256 VALUE_(4,14) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_512 VALUE_(4,15) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1 VALUE_(8,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2 VALUE_(8,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4 VALUE_(8,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8 VALUE_(8,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16 VALUE_(8,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1 VALUE_(11,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2 VALUE_(11,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4 VALUE_(11,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8 VALUE_(11,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16 VALUE_(11,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_2 VALUE_(14,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_4 VALUE_(14,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_6 VALUE_(14,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_8 VALUE_(14,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_XXX VALUE_(14,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSI 0 +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_PREDIV1 BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE BIT_(17) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(__x) VALUE_(18,(__x)-2) +#define CYGHWR_HAL_STM32_RCC_CFGR_USBPRE BIT_(22) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_NONE VALUE_(24,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_SYSCLK VALUE_(24,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSI VALUE_(24,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSE VALUE_(24,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL VALUE_(24,7) +# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL2 VALUE_(24,8) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3_HALF VALUE_(24,9) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_XT1 VALUE_(24,10) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3 VALUE_(24,11) +#define CYGHWR_HAL_STM32_RCC_CR_PLL2ON BIT_(26) +#define CYGHWR_HAL_STM32_RCC_CR_PLL2RDY BIT_(27) +# endif +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1 VALUE_(10,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2 VALUE_(10,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4 VALUE_(10,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8 VALUE_(10,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16 VALUE_(10,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1 VALUE_(13,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2 VALUE_(13,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4 VALUE_(13,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8 VALUE_(13,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16 VALUE_(13,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE(__x) VALUE_(16,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE_MASK MASK_(16,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK MASK_(21,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSI VALUE_(21,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_LSE VALUE_(21,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE VALUE_(21,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_PLL VALUE_(21,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_PLLI2S VALUE_(23,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_EXT VALUE_(23,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK MASK_(24,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1 VALUE_(24,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_2 VALUE_(24,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_3 VALUE_(24,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_4 VALUE_(24,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_5 VALUE_(24,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_MASK MASK_(27,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_1 VALUE_(27,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_2 VALUE_(27,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_3 VALUE_(27,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_4 VALUE_(27,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_5 VALUE_(27,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_MASK MASK_(30,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_SYSCLK VALUE_(30,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLLI2S VALUE_(30,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_HSE VALUE_(30,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLL VALUE_(30,3) +#endif + +#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA1 (0) +#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA2 (1) +#define CYGHWR_HAL_STM32_RCC_AHBENR_SRAM (2) +#define CYGHWR_HAL_STM32_RCC_AHBENR_FLITF (4) +#define CYGHWR_HAL_STM32_RCC_AHBENR_CRC (6) +#define CYGHWR_HAL_STM32_RCC_AHBENR_FSMC (8) +#define CYGHWR_HAL_STM32_RCC_AHBENR_SDIO (10) +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_AHBENR_OTGFS (12) +#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMAC (14) +#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACTX (15) +#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACRX (16) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RCC_AHBRSTR_OTGFSRST BIT_(12) +#define CYGHWR_HAL_STM32_RCC_AHBRSTR_ETHMACRST BIT_(14) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_AHB1RSTR_ETHMACRST BIT_(25) +#endif +#endif + +// Note that the following are bit numbers, not masks. They should +// either be used with the CYGHWR_HAL_STM32_CLOCK() macro or used to +// shift a 1, perhaps using the BIT_() macro. +// +// Note that in the F2/F4 families, the bit positions in the LP registers are +// the same. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO (0) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA (2) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB (3) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC (4) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD (5) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE (6) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF (7) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG (8) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1 (9) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2 (10) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1 (11) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1 (12) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8 (13) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1 (14) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3 (15) + + +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2 (0) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3 (1) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4 (2) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5 (3) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6 (4) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7 (5) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG (11) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2 (14) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3 (15) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2 (17) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3 (18) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4 (19) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5 (20) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1 (21) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2 (22) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB (23) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1 (25) +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2 (26) +#endif +#define CYGHWR_HAL_STM32_RCC_APB1ENR_BKP (27) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR (28) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC (29) + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV2(__x) VALUE_(4,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL2MUL(__x) VALUE_(8,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL3MUL(__x) VALUE_(12,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_HSE 0 +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_PLL2 BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_SYSCLK 0 +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_PLL3 BIT_(17) +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_SYSCLK 0 +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_PLL3 BIT_(18) +#endif + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA (0) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB (1) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC (2) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD (3) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE (4) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF (5) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG (6) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH (7) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI (8) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CRC (12) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_BKPSRAM (18) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN (20) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA1 (21) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA2 (22) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMAC (25) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACTX (26) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACRX (27) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACPTP (28) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHS (29) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHSULPI (30) + +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_DCMI (0) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_CRYP (4) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_HASH (5) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_RNG (6) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_OTGFS (7) + +#define CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC (0) + +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2 (0) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3 (1) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4 (2) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5 (3) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6 (4) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7 (5) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM12 (6) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM13 (7) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM14 (8) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG (11) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2 (14) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3 (15) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2 (17) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3 (18) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4 (19) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5 (20) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1 (21) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2 (22) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C3 (23) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1 (25) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2 (26) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR (28) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC (29) + +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1 (0) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8 (1) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1 (4) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART6 (5) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1 (8) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2 (9) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3 (10) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SDIO (11) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1 (12) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SYSCFG (14) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM9 (16) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM10 (17) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM11 (18) + +#endif + +// The following encodes the control register and clock bit number +// into a 32 bit descriptor. +#define CYGHWR_HAL_STM32_CLOCK( __reg, __pin ) \ + ((CYGHWR_HAL_STM32_RCC_##__reg##ENR) | \ + ((CYGHWR_HAL_STM32_RCC_##__reg##ENR_##__pin)<<16)) + +// Macros to extract encoded values. +#define CYGHWR_HAL_STM32_CLOCK_REG( __desc ) ((__desc)&0xFF) +#define CYGHWR_HAL_STM32_CLOCK_PIN( __desc ) (((__desc)>>16)&0xFF) + +// Functions and macros to enable/disable clocks. + +__externC void hal_stm32_clock_enable( cyg_uint32 desc ); +__externC void hal_stm32_clock_disable( cyg_uint32 desc ); + +#define CYGHWR_HAL_STM32_CLOCK_ENABLE( __desc ) hal_stm32_clock_enable( __desc ) +#define CYGHWR_HAL_STM32_CLOCK_DISABLE( __desc ) hal_stm32_clock_disable( __desc ) + + +#define CYGHWR_HAL_STM32_RCC_BDCR_LSEON BIT_(0) +#define CYGHWR_HAL_STM32_RCC_BDCR_LSERDY BIT_(1) +#define CYGHWR_HAL_STM32_RCC_BDCR_LSEBYP BIT_(2) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_NO VALUE_(8,0) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSE VALUE_(8,1) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSI VALUE_(8,2) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_HSE VALUE_(8,3) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_XXX VALUE_(8,3) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCEN BIT_(15) +#define CYGHWR_HAL_STM32_RCC_BDCR_BDRST BIT_(16) + +#define CYGHWR_HAL_STM32_RCC_CSR_LSION BIT_(0) +#define CYGHWR_HAL_STM32_RCC_CSR_LSIRDY BIT_(1) +#define CYGHWR_HAL_STM32_RCC_CSR_RMVF BIT_(24) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_CSR_BORRSTF BIT_(25) +#endif +#define CYGHWR_HAL_STM32_RCC_CSR_PINRSTF BIT_(26) +#define CYGHWR_HAL_STM32_RCC_CSR_PORRSTF BIT_(27) +#define CYGHWR_HAL_STM32_RCC_CSR_SFTRSTF BIT_(28) +#define CYGHWR_HAL_STM32_RCC_CSR_IWDGRSTF BIT_(29) +#define CYGHWR_HAL_STM32_RCC_CSR_WWDGRSTF BIT_(30) +#define CYGHWR_HAL_STM32_RCC_CSR_LPWRRSTF BIT_(31) + + +// Miscellaneous clock control bits + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_CLOCK_BKP CYGHWR_HAL_STM32_CLOCK( APB1, BKP ) +#endif + +#define CYGHWR_HAL_STM32_CLOCK_PWR CYGHWR_HAL_STM32_CLOCK( APB1, PWR ) + +//============================================================================= +// Realtime Clock + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RTC_CRH 0x00 +#define CYGHWR_HAL_STM32_RTC_CRL 0x04 +#define CYGHWR_HAL_STM32_RTC_PRLH 0x08 +#define CYGHWR_HAL_STM32_RTC_PRLL 0x0C +#define CYGHWR_HAL_STM32_RTC_DIVH 0x10 +#define CYGHWR_HAL_STM32_RTC_DIVL 0x14 +#define CYGHWR_HAL_STM32_RTC_CNTH 0x18 +#define CYGHWR_HAL_STM32_RTC_CNTL 0x1C +#define CYGHWR_HAL_STM32_RTC_ALRH 0x20 +#define CYGHWR_HAL_STM32_RTC_ALRL 0x24 + +// CRH fields + +#define CYGHWR_HAL_STM32_RTC_CRH_SECIE BIT_(0) +#define CYGHWR_HAL_STM32_RTC_CRH_ALRIE BIT_(1) +#define CYGHWR_HAL_STM32_RTC_CRH_OWIE BIT_(2) + +// CRL fields + +#define CYGHWR_HAL_STM32_RTC_CRL_SECF BIT_(0) +#define CYGHWR_HAL_STM32_RTC_CRL_ALRF BIT_(1) +#define CYGHWR_HAL_STM32_RTC_CRL_OWF BIT_(2) +#define CYGHWR_HAL_STM32_RTC_CRL_RSF BIT_(3) +#define CYGHWR_HAL_STM32_RTC_CRL_CNF BIT_(4) +#define CYGHWR_HAL_STM32_RTC_CRL_RTOFF BIT_(5) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_RTC_TR 0x00 +#define CYGHWR_HAL_STM32_RTC_DR 0x04 +#define CYGHWR_HAL_STM32_RTC_CR 0x08 +#define CYGHWR_HAL_STM32_RTC_ISR 0x0C +#define CYGHWR_HAL_STM32_RTC_PRER 0x10 +#define CYGHWR_HAL_STM32_RTC_WUTR 0x14 +#define CYGHWR_HAL_STM32_RTC_CALIBR 0x18 +#define CYGHWR_HAL_STM32_RTC_ALRMAR 0x1C +#define CYGHWR_HAL_STM32_RTC_ALRMBR 0x20 +#define CYGHWR_HAL_STM32_RTC_WPR 0x24 +#define CYGHWR_HAL_STM32_RTC_TSTR 0x30 +#define CYGHWR_HAL_STM32_RTC_TSDR 0x34 +#define CYGHWR_HAL_STM32_RTC_TAFCR 0x40 +#define CYGHWR_HAL_STM32_RTC_BKxR(_x) (0x50 + 4*(_x)) + +#define CYGHWR_HAL_STM32_RTC_TR_SU MASK_(0,4) +#define CYGHWR_HAL_STM32_RTC_TR_SU_SHIFT 0 +#define CYGHWR_HAL_STM32_RTC_TR_ST MASK_(4,3) +#define CYGHWR_HAL_STM32_RTC_TR_ST_SHIFT 4 +#define CYGHWR_HAL_STM32_RTC_TR_MNU MASK_(8,4) +#define CYGHWR_HAL_STM32_RTC_TR_MNU_SHIFT 8 +#define CYGHWR_HAL_STM32_RTC_TR_MNT MASK_(12,3) +#define CYGHWR_HAL_STM32_RTC_TR_MNT_SHIFT 12 +#define CYGHWR_HAL_STM32_RTC_TR_HU MASK_(16,4) +#define CYGHWR_HAL_STM32_RTC_TR_HU_SHIFT 16 +#define CYGHWR_HAL_STM32_RTC_TR_HT MASK_(20,2) +#define CYGHWR_HAL_STM32_RTC_TR_HT_SHIFT 20 +#define CYGHWR_HAL_STM32_RTC_TR_AM VALUE_(22, 0) +#define CYGHWR_HAL_STM32_RTC_TR_PM VALUE_(22, 1) + +#define CYGHWR_HAL_STM32_RTC_DR_DU MASK_(0,4) +#define CYGHWR_HAL_STM32_RTC_DR_DU_SHIFT 0 +#define CYGHWR_HAL_STM32_RTC_DR_DT MASK_(4,2) +#define CYGHWR_HAL_STM32_RTC_DR_DT_SHIFT 4 +#define CYGHWR_HAL_STM32_RTC_DR_MU MASK_(8,4) +#define CYGHWR_HAL_STM32_RTC_DR_MU_SHIFT 8 +#define CYGHWR_HAL_STM32_RTC_DR_MT BIT_(12) +#define CYGHWR_HAL_STM32_RTC_DR_MT_SHIFT 12 +#define CYGHWR_HAL_STM32_RTC_DR_WDU_MON VALUE_(13,1) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_TUE VALUE_(13,2) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_WED VALUE_(13,3) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_THU VALUE_(13,4) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_FRI VALUE_(13,5) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_SAT VALUE_(13,6) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_SUN VALUE_(13,7) +#define CYGHWR_HAL_STM32_RTC_DR_YU MASK_(16,4) +#define CYGHWR_HAL_STM32_RTC_DR_YU_SHIFT 16 +#define CYGHWR_HAL_STM32_RTC_DR_YT MASK_(20,4) +#define CYGHWR_HAL_STM32_RTC_DR_YT_SHIFT 20 + +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_16 VALUE_(0,0) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_8 VALUE_(0,1) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_4 VALUE_(0,2) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_2 VALUE_(0,3) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE VALUE_(0,4) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE_PLUS_216 VALUE_(0,6) +#define CYGHWR_HAL_STM32_RTC_CR_TSEDGE BIT_(3) +#define CYGHWR_HAL_STM32_RTC_CR_REFCKON BIT_(4) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RTC_CR_BYPSHAD BIT_(5) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGHWR_HAL_STM32_RTC_CR_FMT BIT_(6) +#define CYGHWR_HAL_STM32_RTC_CR_DCE BIT_(7) +#define CYGHWR_HAL_STM32_RTC_CR_ALRAE BIT_(8) +#define CYGHWR_HAL_STM32_RTC_CR_ALRBE BIT_(9) +#define CYGHWR_HAL_STM32_RTC_CR_WUTE BIT_(10) +#define CYGHWR_HAL_STM32_RTC_CR_TSE BIT_(11) +#define CYGHWR_HAL_STM32_RTC_CR_ALRAIE BIT_(12) +#define CYGHWR_HAL_STM32_RTC_CR_ALRBIE BIT_(13) +#define CYGHWR_HAL_STM32_RTC_CR_WUTIE BIT_(14) +#define CYGHWR_HAL_STM32_RTC_CR_TSIE BIT_(15) +#define CYGHWR_HAL_STM32_RTC_CR_ADD1H BIT_(16) +#define CYGHWR_HAL_STM32_RTC_CR_SUB1H BIT_(17) +#define CYGHWR_HAL_STM32_RTC_CR_BKP BIT_(18) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RTC_CR_COSEL BIT_(19) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGHWR_HAL_STM32_RTC_CR_POL BIT_(20) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_DISABLE VALUE_(21, 0) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRAOE VALUE_(21, 1) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRBOE VALUE_(21, 2) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_WUOE VALUE_(21, 3) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_COE BIT_(23) + +#define CYGHWR_HAL_STM32_RTC_ISR_ALRAWF BIT_(0) +#define CYGHWR_HAL_STM32_RTC_ISR_ALRBWF BIT_(1) +#define CYGHWR_HAL_STM32_RTC_ISR_WUTWF BIT_(2) +#define CYGHWR_HAL_STM32_RTC_ISR_INITS BIT_(4) +#define CYGHWR_HAL_STM32_RTC_ISR_RSF BIT_(5) +#define CYGHWR_HAL_STM32_RTC_ISR_INITF BIT_(6) +#define CYGHWR_HAL_STM32_RTC_ISR_INIT BIT_(7) +#define CYGHWR_HAL_STM32_RTC_ISR_ALRAF BIT_(8) +#define CYGHWR_HAL_STM32_RTC_ISR_ALRBF BIT_(9) +#define CYGHWR_HAL_STM32_RTC_ISR_WUTF BIT_(10) +#define CYGHWR_HAL_STM32_RTC_ISR_TSF BIT_(11) +#define CYGHWR_HAL_STM32_RTC_ISR_TSOVF BIT_(12) +#define CYGHWR_HAL_STM32_RTC_ISR_TAMP1F BIT_(13) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S MASK_(0,13) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RTC_ISR_SHPF BIT_(3) +#define CYGHWR_HAL_STM32_RTC_ISR_TAMP2F BIT_(14) +#define CYGHWR_HAL_STM32_RTC_ISR_RECALPF BIT_(16) +#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S MASK_(0,15) +#endif +#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_A MASK_(16,7) + +// RTC_WUTR defines omitted +// RTC_CALIBR defines omitted +// RTC_ALRMAR defines omitted +// RTC_ALRMBR defines omitted + +#define CYGHWR_HAL_STM32_RTC_WPR_KEY MASK_(0,8) +#define CYGHWR_HAL_STM32_RTC_WPR_KEY1 0xCA +#define CYGHWR_HAL_STM32_RTC_WPR_KEY2 0x53 + +// RTC_TSTR defines omitted, but layout identical to RTC_TR +// RTC_TSDR defines omitted, but layout identical to RTC_DR except for omission of year fields +// RTC_TAFCR defines omitted +// No relevant RTC_BKPxR defines. + +// RCC clock is selected within wallclock driver, so no define here. + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +//============================================================================= +// System configuration controller - F2 and F4 only + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +// Register offsets +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP 0x00 +#define CYGHWR_HAL_STM32_SYSCFG_PMC 0x04 +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR1 0x08 +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR2 0x0C +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR3 0x10 +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR4 0x14 +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR 0x20 + +// Register definitions + +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_MAINFLASH VALUE_(0,0) +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SYSFLASH VALUE_(0,1) +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_FSMC1 VALUE_(0,2) +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SRAM VALUE_(0,3) + +#define CYGHWR_HAL_STM32_SYSCFG_PMC_MII VALUE_(23,0) +#define CYGHWR_HAL_STM32_SYSCFG_PMC_RMII VALUE_(23,1) + +// FIXME: The below EXTI bits should be merged with the F1 defines in +// var_io_pins.h to provide a common interface + +// The following macro allows the four EXTICR registers to be indexed +// as CYGHWR_HAL_STM32_SYSCFG_EXTICR(1) to CYGHWR_HAL_STM32_SYSCFG_EXTICR(4) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR(__x) (4*((__x)-1)+0x08) + +// The following macros are used to generate the bitfields for setting up +// external interrupts. For example, CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(12) +// will generate the bitfield which when ORed into the EXTICR4 register will +// set up C12 as the external interrupt pin for the EXTI12 interrupt. +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTH(__x) VALUE_(4*((__x)&3),7) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_MASK(__x) VALUE_(4*((__x)&3),0xF) + +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_DIS VALUE_(0,0) +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_ENA VALUE_(0,1) +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_READY BIT_(8) + +// SYSCFG clock control + +#define CYGHWR_HAL_STM32_SYSCFG_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, SYSCFG ) + +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +//============================================================================= +// External interrupt controller + +#define CYGHWR_HAL_STM32_EXTI_IMR 0x00 +#define CYGHWR_HAL_STM32_EXTI_EMR 0x04 +#define CYGHWR_HAL_STM32_EXTI_RTSR 0x08 +#define CYGHWR_HAL_STM32_EXTI_FTSR 0x0C +#define CYGHWR_HAL_STM32_EXTI_SWIER 0x10 +#define CYGHWR_HAL_STM32_EXTI_PR 0x14 + +#define CYGHWR_HAL_STM32_EXTI_BIT(__b) BIT_(__b) + +//============================================================================= +// GPIO ports and pin configuration. Include separate header file for this +// to avoid this header getting unmanageable. +#include <cyg/hal/var_io_pins.h> + +//============================================================================= +// DMA controller register definitions. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_DMA_ISR 0x00 +#define CYGHWR_HAL_STM32_DMA_IFCR 0x04 + +#define CYGHWR_HAL_STM32_DMA_ISR_REG(__chan) CYGHWR_HAL_STM32_DMA_ISR +#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__chan) CYGHWR_HAL_STM32_DMA_IFCR + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_DMA_LISR 0x00 +#define CYGHWR_HAL_STM32_DMA_HISR 0x04 +#define CYGHWR_HAL_STM32_DMA_LIFCR 0x08 +#define CYGHWR_HAL_STM32_DMA_HIFCR 0x0C + +#define CYGHWR_HAL_STM32_DMA_ISR_REG(__stream) ((__stream)>3 ? \ + CYGHWR_HAL_STM32_DMA_HISR : \ + CYGHWR_HAL_STM32_DMA_LISR) +#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__stream) ((__stream)>3 ? \ + CYGHWR_HAL_STM32_DMA_HIFCR : \ + CYGHWR_HAL_STM32_DMA_LIFCR) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +// The following macros allow access to the per-channel DMA registers, indexed +// by channel number. For F1 parts there is no concept of a stream - each entry +// has a fixed relationship to the corresponding channel. +// Valid channel/stream numbers are 1 to 7 for DMA1 and 1 to 5 for DMA2 on F1 +// parts, 1 to 7 for DMA2 streams on F2/F4 parts. +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_DMA_CCR(__x) (0x14*(__x)-0x0C) +#define CYGHWR_HAL_STM32_DMA_CNDTR(__x) (0x14*(__x)-0x08) +#define CYGHWR_HAL_STM32_DMA_CPAR(__x) (0x14*(__x)-0x04) +#define CYGHWR_HAL_STM32_DMA_CMAR(__x) (0x14*(__x)) + +#define CYGHWR_HAL_STM32_DMA_ISR_GIF(__x) BIT_(4*(__x)-4) +#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x) BIT_(4*(__x)-3) +#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x) BIT_(4*(__x)-2) +#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x) BIT_(4*(__x)-1) +#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x) VALUE_(4*(__x)-4,0xF) + +#define CYGHWR_HAL_STM32_DMA_IFCR_CGIF(__x) BIT_(4*(__x)-4) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x) BIT_(4*(__x)-3) +#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x) BIT_(4*(__x)-2) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x) BIT_(4*(__x)-1) +#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x) VALUE_(4*(__x)-4,0xF) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_DMA_SCR(__x) (0x18*(__x)+0x10) +#define CYGHWR_HAL_STM32_DMA_SNDTR(__x) (0x18*(__x)+0x14) +#define CYGHWR_HAL_STM32_DMA_SPAR(__x) (0x18*(__x)+0x18) +#define CYGHWR_HAL_STM32_DMA_SM0AR(__x) (0x18*(__x)+0x1C) +#define CYGHWR_HAL_STM32_DMA_SM1AR(__x) (0x18*(__x)+0x20) +#define CYGHWR_HAL_STM32_DMA_SFCR(__x) (0x18*(__x)+0x24) + +// For now at least we implement an identity mapping between +// streams and channels. +#define CYGHWR_HAL_STM32_DMA_CCR(__x) CYGHWR_HAL_STM32_DMA_SCR(__x) +#define CYGHWR_HAL_STM32_DMA_CNDTR(__x) CYGHWR_HAL_STM32_DMA_SNDTR(__x) +#define CYGHWR_HAL_STM32_DMA_CPAR(__x) CYGHWR_HAL_STM32_DMA_SPAR(__x) +#define CYGHWR_HAL_STM32_DMA_CMAR(__x) CYGHWR_HAL_STM32_DMA_SM0AR(__x) +#define CYGHWR_HAL_STM32_DMA_CM0AR(__x) CYGHWR_HAL_STM32_DMA_SM0AR(__x) +#define CYGHWR_HAL_STM32_DMA_CM1AR(__x) CYGHWR_HAL_STM32_DMA_SM1AR(__x) + +// This selects which region of an isr register to use for a stream +#define CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) ( ((__x)&0x3) == 3 ? 22 : \ + ((__x)&0x3) == 2 ? 16 : \ + ((__x)&0x3) == 1 ? 6 : 0 ) + +#define CYGHWR_HAL_STM32_DMA_ISR_FEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) ) +#define CYGHWR_HAL_STM32_DMA_ISR_DMEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 2 ) +#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 3 ) +#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 4 ) +#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 5 ) + +#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x) VALUE_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x), 0x3f ) + +// This selects which region of an ifcr register to use for a stream. +// Happens to be laid out the same as the isr, so reuse. +#define CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + +#define CYGHWR_HAL_STM32_DMA_IFCR_CFEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CDMEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 2 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 3 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 4 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 5 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x) VALUE_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x), 0x3f ) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_DMA_CCR_EN BIT_(0) +#define CYGHWR_HAL_STM32_DMA_CCR_TCIE BIT_(1) +#define CYGHWR_HAL_STM32_DMA_CCR_HTIE BIT_(2) +#define CYGHWR_HAL_STM32_DMA_CCR_TEIE BIT_(3) +#define CYGHWR_HAL_STM32_DMA_CCR_DIR BIT_(4) +#define CYGHWR_HAL_STM32_DMA_CCR_CIRC BIT_(5) +#define CYGHWR_HAL_STM32_DMA_CCR_PINC BIT_(6) +#define CYGHWR_HAL_STM32_DMA_CCR_MINC BIT_(7) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 VALUE_(8,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 VALUE_(8,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 VALUE_(8,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8 VALUE_(10,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16 VALUE_(10,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32 VALUE_(10,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x) VALUE_(12,__x) +#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW VALUE_(12,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM VALUE_(12,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH VALUE_(12,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX VALUE_(12,3) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM BIT_(14) + +// F2/F4 compatibility combinations to control transfer source/dest +#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM 0 +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P CYGHWR_HAL_STM32_DMA_CCR_DIR + +// Clock enable bits + +#define CYGHWR_HAL_STM32_DMA1_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, DMA1 ) +#define CYGHWR_HAL_STM32_DMA2_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, DMA2 ) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_DMA_CCR_EN BIT_(0) +#define CYGHWR_HAL_STM32_DMA_CCR_DMEIE BIT_(1) +#define CYGHWR_HAL_STM32_DMA_CCR_TEIE BIT_(2) +#define CYGHWR_HAL_STM32_DMA_CCR_HTIE BIT_(3) +#define CYGHWR_HAL_STM32_DMA_CCR_TCIE BIT_(4) +#define CYGHWR_HAL_STM32_DMA_CCR_PFCTRL BIT_(5) +#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM VALUE_(6,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P VALUE_(6,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM VALUE_(6,2) + +#define CYGHWR_HAL_STM32_DMA_CCR_CIRC BIT_(8) +#define CYGHWR_HAL_STM32_DMA_CCR_PINC BIT_(9) +#define CYGHWR_HAL_STM32_DMA_CCR_MINC BIT_(10) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 VALUE_(11,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 VALUE_(11,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 VALUE_(11,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8 VALUE_(13,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16 VALUE_(13,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32 VALUE_(13,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PINCOS BIT_(15) +#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x) VALUE_(16,__x) +#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW VALUE_(16,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM VALUE_(16,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH VALUE_(16,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX VALUE_(16,3) +#define CYGHWR_HAL_STM32_DMA_CCR_DBM BIT_(18) +#define CYGHWR_HAL_STM32_DMA_CCR_CT BIT_(19) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST1 VALUE_(21,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST4 VALUE_(21,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST8 VALUE_(21,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST16 VALUE_(21,3) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST1 VALUE_(23,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST4 VALUE_(23,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST8 VALUE_(23,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST16 VALUE_(23,3) +#define CYGHWR_HAL_STM32_DMA_CCR_CHSEL(__x) VALUE_(25,__x) + +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_QUARTER VALUE_(0,0) // FIFO threshold selection +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_HALF VALUE_(0,1) +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_3QUARTER VALUE_(0,2) +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_FULL VALUE_(0,3) +#define CYGHWR_HAL_STM32_DMA_FCR_DMDIS BIT_(2) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTQUARTER VALUE_(3,0) // LT==less than +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTHALF VALUE_(3,1) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LT3QUARTER VALUE_(3,2) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTFULL VALUE_(3,3) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_EMPTY VALUE_(3,4) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_FULL VALUE_(3,5) +#define CYGHWR_HAL_STM32_DMA_FCR_FEIE BIT_(7) + +// Clock enable bits + +#define CYGHWR_HAL_STM32_DMA1_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, DMA1 ) +#define CYGHWR_HAL_STM32_DMA2_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, DMA2 ) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +//============================================================================= +// UARTs +// Include separate header file for this to avoid this header getting unmanageable. + +#include <cyg/hal/var_io_usart.h> + +//============================================================================= +// ADCs + +#define CYGHWR_HAL_STM32_ADC_SR 0x00 +#define CYGHWR_HAL_STM32_ADC_CR1 0x04 +#define CYGHWR_HAL_STM32_ADC_CR2 0x08 +#define CYGHWR_HAL_STM32_ADC_SMPR1 0x0C +#define CYGHWR_HAL_STM32_ADC_SMPR2 0x10 +#define CYGHWR_HAL_STM32_ADC_JOFR(__x) 0x14 + ((__x) << 2) +#define CYGHWR_HAL_STM32_ADC_HTR 0x24 +#define CYGHWR_HAL_STM32_ADC_LTR 0x28 +#define CYGHWR_HAL_STM32_ADC_SQR1 0x2C +#define CYGHWR_HAL_STM32_ADC_SQR2 0x30 +#define CYGHWR_HAL_STM32_ADC_SQR3 0x34 +#define CYGHWR_HAL_STM32_ADC_JSQR 0x38 +#define CYGHWR_HAL_STM32_ADC_JDR(__x) 0x3C + ((__x) << 2) +#define CYGHWR_HAL_STM32_ADC_DR 0x4C + +// SR fields + +#define CYGHWR_HAL_STM32_ADC_SR_AWD BIT_(0) +#define CYGHWR_HAL_STM32_ADC_SR_EOC BIT_(1) +#define CYGHWR_HAL_STM32_ADC_SR_JEOC BIT_(2) +#define CYGHWR_HAL_STM32_ADC_SR_JSTRT BIT_(3) +#define CYGHWR_HAL_STM32_ADC_SR_STRT BIT_(4) + +// CR1 fields + +#define CYGHWR_HAL_STM32_ADC_CR1_AWDCH(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR1_EOCIE BIT_(5) +#define CYGHWR_HAL_STM32_ADC_CR1_AWDIE BIT_(6) +#define CYGHWR_HAL_STM32_ADC_CR1_JEOCIE BIT_(7) +#define CYGHWR_HAL_STM32_ADC_CR1_SCAN BIT_(8) +#define CYGHWR_HAL_STM32_ADC_CR1_AWDSGL BIT_(9) +#define CYGHWR_HAL_STM32_ADC_CR1_JAUTO BIT_(10) +#define CYGHWR_HAL_STM32_ADC_CR1_DISCEN BIT_(11) +#define CYGHWR_HAL_STM32_ADC_CR1_JDISCEN BIT_(12) +#define CYGHWR_HAL_STM32_ADC_CR1_DISCNUM(__x) VALUE_(13,(__x)) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_ADC_CR1_DUALMODE(__x) VALUE_(16,(__x)) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#define CYGHWR_HAL_STM32_ADC_CR1_JAWDEN BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CR1_AWDEN BIT_(23) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CR1_OVRIE BIT_(26) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + + + +// CR2 fields + +#define CYGHWR_HAL_STM32_ADC_CR2_ADON BIT_(0) +#define CYGHWR_HAL_STM32_ADC_CR2_CONT BIT_(1) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_ADC_CR2_CAL BIT_(2) +#define CYGHWR_HAL_STM32_ADC_CR2_RSTCAL BIT_(3) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#define CYGHWR_HAL_STM32_ADC_CR2_DMA BIT_(8) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CR2_DDS BIT_(9) +#define CYGHWR_HAL_STM32_ADC_CR2_EOCS BIT_(10) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +#define CYGHWR_HAL_STM32_ADC_CR2_ALIGN BIT_(11) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x) VALUE_(12,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTTRIG BIT_(15) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x) VALUE_(17,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTTRIG BIT_(20) +#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART BIT_(21) +#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CR2_TSVREFE BIT_(23) +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x) VALUE_(16,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTEN(__x) VALUE_(20,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x) VALUE_(24,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTEN(__x) VALUE_(28,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART BIT_(30) +#endif + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +// On F1 devices ADC1 and ADC3 have different external event sets for regular groups +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC1 (0) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC2 (1) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC3 (2) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM2_CC2 (3) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM3_TRGO (4) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM4_CC4 (5) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM8_TRGO (6) // For high- and XL-density devices +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_SWSTART (7) + +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM3_CC1 (0) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM2_CC3 (1) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM1_CC3 (2) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_CC1 (3) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_TRGO (4) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC1 (5) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC3 (6) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_SWSTART (7) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC1 (0) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC2 (1) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC3 (2) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC2 (3) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC3 (4) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC4 (5) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_TRGO (6) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_CC1 (7) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_TRGO (8) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM4_CC4 (9) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC1 (10) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC2 (11) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC3 (12) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_CC1 (13) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_TRGO (14) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_EXTI (15) // line 11 + +#define CYGHWR_HAL_STM32_ADC_EXTEN_DISABLED (0) +#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_RISE (1) +#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_FALL (2) +#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_BOTH (3) + +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +// SMPRx fields + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +// F1 : SMPR1 17..10 : SMPR2 9..0 +#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (8) +#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +// F2/F4 : SMPR1 18..10 : SMPR2 9..0 +#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (9) +#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +#define CYGHWR_HAL_STM32_ADC_SMPRx_SMP(__x, __y) VALUE_((__x) * 3, (__y)) + +// SQRx fields + +#define CYGHWR_HAL_STM32_ADC_SQR1_L(__x) VALUE_(20, (__x)) +#define CYGHWR_HAL_STM32_ADC_SQRx_SQ(__x, __y) VALUE_((__x) * 5, (__y)) + +// JSQR fields + +#define CYGHWR_HAL_STM32_ADC_JSQR_SQ(__x, __y) VALUE_((__x) * 5, (__y)) + +// ADC GPIO pins + +// F1/F2/F4 GPIO inputs have 16 channels (0..15). +// ADC1 has extra internal sources, which for F1 and HIPERFORMANCE (F2/F4) +// devices respectively have 18 (0..17) and 19 (0..18) available sources. + +// Internal (non-GPIO) channels (ADC1 only): +// - ADC1_IN16 temperature F1/F2/F4 +// - ADC1_IN17 Vrefint F1/F2/F4 +// - ADC1_IN18 Vbat F2/F4 + +#define CYGHWR_HAL_STM32_ADC123_IN0 CYGHWR_HAL_STM32_PIN_ANALOG( A, 0 ) +#define CYGHWR_HAL_STM32_ADC123_IN1 CYGHWR_HAL_STM32_PIN_ANALOG( A, 1 ) +#define CYGHWR_HAL_STM32_ADC123_IN2 CYGHWR_HAL_STM32_PIN_ANALOG( A, 2 ) +#define CYGHWR_HAL_STM32_ADC123_IN3 CYGHWR_HAL_STM32_PIN_ANALOG( A, 3 ) + +#define CYGHWR_HAL_STM32_ADC12_IN4 CYGHWR_HAL_STM32_PIN_ANALOG( A, 4 ) +#define CYGHWR_HAL_STM32_ADC12_IN5 CYGHWR_HAL_STM32_PIN_ANALOG( A, 5 ) +#define CYGHWR_HAL_STM32_ADC12_IN6 CYGHWR_HAL_STM32_PIN_ANALOG( A, 6 ) +#define CYGHWR_HAL_STM32_ADC12_IN7 CYGHWR_HAL_STM32_PIN_ANALOG( A, 7 ) + +#define CYGHWR_HAL_STM32_ADC12_IN8 CYGHWR_HAL_STM32_PIN_ANALOG( B, 0 ) +#define CYGHWR_HAL_STM32_ADC12_IN9 CYGHWR_HAL_STM32_PIN_ANALOG( B, 1 ) + +#define CYGHWR_HAL_STM32_ADC3_IN4 CYGHWR_HAL_STM32_PIN_ANALOG( F, 6 ) +#define CYGHWR_HAL_STM32_ADC3_IN5 CYGHWR_HAL_STM32_PIN_ANALOG( F, 7 ) +#define CYGHWR_HAL_STM32_ADC3_IN6 CYGHWR_HAL_STM32_PIN_ANALOG( F, 8 ) +#define CYGHWR_HAL_STM32_ADC3_IN7 CYGHWR_HAL_STM32_PIN_ANALOG( F, 9 ) +#define CYGHWR_HAL_STM32_ADC3_IN8 CYGHWR_HAL_STM32_PIN_ANALOG( F, 10 ) + +#define CYGHWR_HAL_STM32_ADC123_IN10 CYGHWR_HAL_STM32_PIN_ANALOG( C, 0 ) +#define CYGHWR_HAL_STM32_ADC123_IN11 CYGHWR_HAL_STM32_PIN_ANALOG( C, 1 ) +#define CYGHWR_HAL_STM32_ADC123_IN12 CYGHWR_HAL_STM32_PIN_ANALOG( C, 2 ) +#define CYGHWR_HAL_STM32_ADC123_IN13 CYGHWR_HAL_STM32_PIN_ANALOG( C, 3 ) + +#define CYGHWR_HAL_STM32_ADC12_IN14 CYGHWR_HAL_STM32_PIN_ANALOG( C, 4 ) +#define CYGHWR_HAL_STM32_ADC12_IN15 CYGHWR_HAL_STM32_PIN_ANALOG( C, 5) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +// Following ADC3 channels not-mapped on F1 devices +#define CYGHWR_HAL_STM32_ADC3_IN9 CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_ADC3_IN14 CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_ADC3_IN15 CYGHWR_HAL_STM32_GPIO_NONE +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC3_IN9 CYGHWR_HAL_STM32_PIN_ANALOG( F, 3 ) +#define CYGHWR_HAL_STM32_ADC3_IN14 CYGHWR_HAL_STM32_PIN_ANALOG( F, 4 ) +#define CYGHWR_HAL_STM32_ADC3_IN15 CYGHWR_HAL_STM32_PIN_ANALOG( F, 5 ) +#endif + +// ADC1 GPIO pin aliases + +#define CYGHWR_HAL_STM32_ADC1_IN0 CYGHWR_HAL_STM32_ADC123_IN0 +#define CYGHWR_HAL_STM32_ADC1_IN1 CYGHWR_HAL_STM32_ADC123_IN1 +#define CYGHWR_HAL_STM32_ADC1_IN2 CYGHWR_HAL_STM32_ADC123_IN2 +#define CYGHWR_HAL_STM32_ADC1_IN3 CYGHWR_HAL_STM32_ADC123_IN3 +#define CYGHWR_HAL_STM32_ADC1_IN4 CYGHWR_HAL_STM32_ADC12_IN4 +#define CYGHWR_HAL_STM32_ADC1_IN5 CYGHWR_HAL_STM32_ADC12_IN5 +#define CYGHWR_HAL_STM32_ADC1_IN6 CYGHWR_HAL_STM32_ADC12_IN6 +#define CYGHWR_HAL_STM32_ADC1_IN7 CYGHWR_HAL_STM32_ADC12_IN7 +#define CYGHWR_HAL_STM32_ADC1_IN8 CYGHWR_HAL_STM32_ADC12_IN8 +#define CYGHWR_HAL_STM32_ADC1_IN9 CYGHWR_HAL_STM32_ADC12_IN9 +#define CYGHWR_HAL_STM32_ADC1_IN10 CYGHWR_HAL_STM32_ADC123_IN10 +#define CYGHWR_HAL_STM32_ADC1_IN11 CYGHWR_HAL_STM32_ADC123_IN11 +#define CYGHWR_HAL_STM32_ADC1_IN12 CYGHWR_HAL_STM32_ADC123_IN12 +#define CYGHWR_HAL_STM32_ADC1_IN13 CYGHWR_HAL_STM32_ADC123_IN13 +#define CYGHWR_HAL_STM32_ADC1_IN14 CYGHWR_HAL_STM32_ADC12_IN14 +#define CYGHWR_HAL_STM32_ADC1_IN15 CYGHWR_HAL_STM32_ADC12_IN15 + +// ADC2 GPIO pin aliases + +#define CYGHWR_HAL_STM32_ADC2_IN0 CYGHWR_HAL_STM32_ADC123_IN0 +#define CYGHWR_HAL_STM32_ADC2_IN1 CYGHWR_HAL_STM32_ADC123_IN1 +#define CYGHWR_HAL_STM32_ADC2_IN2 CYGHWR_HAL_STM32_ADC123_IN2 +#define CYGHWR_HAL_STM32_ADC2_IN3 CYGHWR_HAL_STM32_ADC123_IN3 +#define CYGHWR_HAL_STM32_ADC2_IN4 CYGHWR_HAL_STM32_ADC12_IN4 +#define CYGHWR_HAL_STM32_ADC2_IN5 CYGHWR_HAL_STM32_ADC12_IN5 +#define CYGHWR_HAL_STM32_ADC2_IN6 CYGHWR_HAL_STM32_ADC12_IN6 +#define CYGHWR_HAL_STM32_ADC2_IN7 CYGHWR_HAL_STM32_ADC12_IN7 +#define CYGHWR_HAL_STM32_ADC2_IN8 CYGHWR_HAL_STM32_ADC12_IN8 +#define CYGHWR_HAL_STM32_ADC2_IN9 CYGHWR_HAL_STM32_ADC12_IN9 +#define CYGHWR_HAL_STM32_ADC2_IN10 CYGHWR_HAL_STM32_ADC123_IN10 +#define CYGHWR_HAL_STM32_ADC2_IN11 CYGHWR_HAL_STM32_ADC123_IN11 +#define CYGHWR_HAL_STM32_ADC2_IN12 CYGHWR_HAL_STM32_ADC123_IN12 +#define CYGHWR_HAL_STM32_ADC2_IN13 CYGHWR_HAL_STM32_ADC123_IN13 +#define CYGHWR_HAL_STM32_ADC2_IN14 CYGHWR_HAL_STM32_ADC12_IN14 +#define CYGHWR_HAL_STM32_ADC2_IN15 CYGHWR_HAL_STM32_ADC12_IN15 + +// ADC3 GPIO pin aliases + +#define CYGHWR_HAL_STM32_ADC3_IN0 CYGHWR_HAL_STM32_ADC123_IN0 +#define CYGHWR_HAL_STM32_ADC3_IN1 CYGHWR_HAL_STM32_ADC123_IN1 +#define CYGHWR_HAL_STM32_ADC3_IN2 CYGHWR_HAL_STM32_ADC123_IN2 +#define CYGHWR_HAL_STM32_ADC3_IN3 CYGHWR_HAL_STM32_ADC123_IN3 +// Inputs 4 - 9 are already defined +#define CYGHWR_HAL_STM32_ADC3_IN10 CYGHWR_HAL_STM32_ADC123_IN10 +#define CYGHWR_HAL_STM32_ADC3_IN11 CYGHWR_HAL_STM32_ADC123_IN11 +#define CYGHWR_HAL_STM32_ADC3_IN12 CYGHWR_HAL_STM32_ADC123_IN12 +#define CYGHWR_HAL_STM32_ADC3_IN13 CYGHWR_HAL_STM32_ADC123_IN13 +// Inputs 14 - 15 are already defined + +// ADC Clock control pins + +#define CYGHWR_HAL_STM32_ADC1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, ADC1 ) +#define CYGHWR_HAL_STM32_ADC2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, ADC2 ) +#define CYGHWR_HAL_STM32_ADC3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, ADC3 ) + +// F2/F4 only: Common configuration registers based from CYGHWR_HAL_STM32_ADC_COMMON +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CSR 0x00 +#define CYGHWR_HAL_STM32_ADC_CCR 0x04 +#define CYGHWR_HAL_STM32_ADC_CDR 0x08 + +// CSR +#define CYGHWR_HAL_STM32_ADC_CSR_AWD BIT_(0) +#define CYGHWR_HAL_STM32_ADC_CSR_EOC BIT_(1) +#define CYGHWR_HAL_STM32_ADC_CSR_JEOC BIT_(2) +#define CYGHWR_HAL_STM32_ADC_CSR_JSTRT BIT_(3) +#define CYGHWR_HAL_STM32_ADC_CSR_STRT BIT_(4) +#define CYGHWR_HAL_STM32_ADC_CSR_OVR BIT_(5) + +#define CYGHWR_HAL_STM32_ADC1_CSR_AWD CYGHWR_HAL_STM32_ADC_CSR_AWD +#define CYGHWR_HAL_STM32_ADC1_CSR_EOC CYGHWR_HAL_STM32_ADC_CSR_EOC +#define CYGHWR_HAL_STM32_ADC1_CSR_JEOC CYGHWR_HAL_STM32_ADC_CSR_JEOC +#define CYGHWR_HAL_STM32_ADC1_CSR_JSTRT CYGHWR_HAL_STM32_ADC_CSR_JSTRT +#define CYGHWR_HAL_STM32_ADC1_CSR_STRT CYGHWR_HAL_STM32_ADC_CSR_STRT +#define CYGHWR_HAL_STM32_ADC1_CSR_OVR CYGHWR_HAL_STM32_ADC_CSR_OVR + +#define CYGHWR_HAL_STM32_ADC2_CSR_AWD (CYGHWR_HAL_STM32_ADC_CSR_AWD << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_EOC (CYGHWR_HAL_STM32_ADC_CSR_EOC << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_JEOC (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_JSTRT (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_STRT (CYGHWR_HAL_STM32_ADC_CSR_STRT << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_OVR (CYGHWR_HAL_STM32_ADC_CSR_OVR << 8) + +#define CYGHWR_HAL_STM32_ADC3_CSR_AWD (CYGHWR_HAL_STM32_ADC_CSR_AWD << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_EOC (CYGHWR_HAL_STM32_ADC_CSR_EOC << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_JEOC (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_JSTRT (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_STRT (CYGHWR_HAL_STM32_ADC_CSR_STRT << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_OVR (CYGHWR_HAL_STM32_ADC_CSR_OVR << 16) + +#define CYGHWR_HAL_STM32_ADC_CSR_ADC1(__csr) ((__csr) >> 0) +#define CYGHWR_HAL_STM32_ADC_CSR_ADC2(__csr) ((__csr) >> 8) +#define CYGHWR_HAL_STM32_ADC_CSR_ADC3(__csr) ((__csr) >> 16) + +// CCR +#define CYGHWR_HAL_STM32_ADC_CCR_MULTI_XXX VALUE_(0,0x1F) +#define CYGHWR_HAL_STM32_ADC_CCR_DELAY_XXX VALUE_(8,0xF) +#define CYGHWR_HAL_STM32_ADC_CCR_DDS BIT_(13) +#define CYGHWR_HAL_STM32_ADC_CCR_DMA_XXX VALUE_(14,0x3) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_2 VALUE_(16,0x0) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_4 VALUE_(16,0x1) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_6 VALUE_(16,0x2) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_8 VALUE_(16,0x3) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_XXX VALUE_(16,0x3) +#define CYGHWR_HAL_STM32_ADC_CCR_VBATE BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CCR_TSVREFE BIT_(23) + +// CDR +#define CYGHWR_HAL_STM32_ADC_CDR_DATA1_XXX VALUE_(0,0xFFFF) +#define CYGHWR_HAL_STM32_ADC_CDR_DATA2_XXX VALUE_(16,0xFFFF) +#endif + +//============================================================================= +// SPI interface register definitions. + +#define CYGHWR_HAL_STM32_SPI_CR1 0x00 +#define CYGHWR_HAL_STM32_SPI_CR2 0x04 +#define CYGHWR_HAL_STM32_SPI_SR 0x08 +#define CYGHWR_HAL_STM32_SPI_DR 0x0C +#define CYGHWR_HAL_STM32_SPI_CRCPR 0x10 +#define CYGHWR_HAL_STM32_SPI_RXCRCR 0x14 +#define CYGHWR_HAL_STM32_SPI_TXCRCR 0x18 +#define CYGHWR_HAL_STM32_SPI_I2SCFGR 0x1C +#define CYGHWR_HAL_STM32_SPI_I2SPR 0x20 + +#define CYGHWR_HAL_STM32_SPI_CR1_CPHA BIT_(0) +#define CYGHWR_HAL_STM32_SPI_CR1_CPOL BIT_(1) +#define CYGHWR_HAL_STM32_SPI_CR1_MSTR BIT_(2) +#define CYGHWR_HAL_STM32_SPI_CR1_BR(__x) VALUE_(3,(__x)) +#define CYGHWR_HAL_STM32_SPI_CR1_SPE BIT_(6) +#define CYGHWR_HAL_STM32_SPI_CR1_LSBFIRST BIT_(7) +#define CYGHWR_HAL_STM32_SPI_CR1_SSI BIT_(8) +#define CYGHWR_HAL_STM32_SPI_CR1_SSM BIT_(9) +#define CYGHWR_HAL_STM32_SPI_CR1_RXONLY BIT_(10) +#define CYGHWR_HAL_STM32_SPI_CR1_DFF BIT_(11) +#define CYGHWR_HAL_STM32_SPI_CR1_CRCNEXT BIT_(12) +#define CYGHWR_HAL_STM32_SPI_CR1_CRCEN BIT_(13) +#define CYGHWR_HAL_STM32_SPI_CR1_BIDIOE BIT_(14) +#define CYGHWR_HAL_STM32_SPI_CR1_BIDIMODE BIT_(15) + +#define CYGHWR_HAL_STM32_SPI_CR2_RXDMAEN BIT_(0) +#define CYGHWR_HAL_STM32_SPI_CR2_TXDMAEN BIT_(1) +#define CYGHWR_HAL_STM32_SPI_CR2_SSOE BIT_(2) +#define CYGHWR_HAL_STM32_SPI_CR2_ERRIE BIT_(5) +#define CYGHWR_HAL_STM32_SPI_CR2_RXNEIE BIT_(6) +#define CYGHWR_HAL_STM32_SPI_CR2_TXEIE BIT_(7) + +#define CYGHWR_HAL_STM32_SPI_SR_RXNE BIT_(0) +#define CYGHWR_HAL_STM32_SPI_SR_TXE BIT_(1) +#define CYGHWR_HAL_STM32_SPI_SR_CHSIDE BIT_(2) +#define CYGHWR_HAL_STM32_SPI_SR_UDR BIT_(3) +#define CYGHWR_HAL_STM32_SPI_SR_CRCERR BIT_(4) +#define CYGHWR_HAL_STM32_SPI_SR_MODF BIT_(5) +#define CYGHWR_HAL_STM32_SPI_SR_OVR BIT_(6) +#define CYGHWR_HAL_STM32_SPI_SR_BSY BIT_(7) + +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CHLEN BIT_(0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN16 VALUE_(1,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN24 VALUE_(1,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN32 VALUE_(1,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CKPOL BIT_(3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPHL VALUE_(4,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDMSB VALUE_(4,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDLSB VALUE_(4,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPCM VALUE_(4,3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_PCMSYNC BIT_(7) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGST VALUE_(8,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGSR VALUE_(8,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMT VALUE_(8,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMR VALUE_(8,3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SE BIT_(10) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2MOD BIT_(11) + +#define CYGHWR_HAL_STM32_SPI_I2SPR_I2SDIV(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_SPI_I2SPR_ODD BIT_(8) +#define CYGHWR_HAL_STM32_SPI_I2SPR_MCKOE BIT_(9) + +// Clock control definitions for each SPI bus + +#define CYGHWR_HAL_STM32_SPI1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, SPI1 ) +#define CYGHWR_HAL_STM32_SPI2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, SPI2 ) +#define CYGHWR_HAL_STM32_SPI3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, SPI3 ) + +//============================================================================= +// I2C busses + +#define CYGHWR_HAL_STM32_I2C_CR1 0x00 +#define CYGHWR_HAL_STM32_I2C_CR2 0x04 +#define CYGHWR_HAL_STM32_I2C_OAR1 0x08 +#define CYGHWR_HAL_STM32_I2C_OAR2 0x0C +#define CYGHWR_HAL_STM32_I2C_DR 0x10 +#define CYGHWR_HAL_STM32_I2C_SR1 0x14 +#define CYGHWR_HAL_STM32_I2C_SR2 0x18 +#define CYGHWR_HAL_STM32_I2C_CCR 0x1C +#define CYGHWR_HAL_STM32_I2C_TRISE 0x20 + +#define CYGHWR_HAL_STM32_I2C_CR1_PE BIT_(0) +#define CYGHWR_HAL_STM32_I2C_CR1_SMBUS BIT_(1) +#define CYGHWR_HAL_STM32_I2C_CR1_SMBTYPE BIT_(3) +#define CYGHWR_HAL_STM32_I2C_CR1_ENARP BIT_(4) +#define CYGHWR_HAL_STM32_I2C_CR1_ENPEC BIT_(5) +#define CYGHWR_HAL_STM32_I2C_CR1_ENGC BIT_(6) +#define CYGHWR_HAL_STM32_I2C_CR1_NOSTRETCH BIT_(7) +#define CYGHWR_HAL_STM32_I2C_CR1_START BIT_(8) +#define CYGHWR_HAL_STM32_I2C_CR1_STOP BIT_(9) +#define CYGHWR_HAL_STM32_I2C_CR1_ACK BIT_(10) +#define CYGHWR_HAL_STM32_I2C_CR1_POS BIT_(11) +#define CYGHWR_HAL_STM32_I2C_CR1_PEC BIT_(12) +#define CYGHWR_HAL_STM32_I2C_CR1_ALERT BIT_(13) +#define CYGHWR_HAL_STM32_I2C_CR1_SWRST BIT_(15) + + +#define CYGHWR_HAL_STM32_I2C_CR2_FREQ(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_I2C_CR2_FREQ_MASK MASK_(0,6) +#define CYGHWR_HAL_STM32_I2C_CR2_ITERREN BIT_(8) +#define CYGHWR_HAL_STM32_I2C_CR2_ITEVTEN BIT_(9) +#define CYGHWR_HAL_STM32_I2C_CR2_ITBUFEN BIT_(10) +#define CYGHWR_HAL_STM32_I2C_CR2_DMAEN BIT_(11) +#define CYGHWR_HAL_STM32_I2C_CR2_LAST BIT_(12) + +// OAR1 and OAR2 omitted, we only support master mode + +#define CYGHWR_HAL_STM32_I2C_SR1_SB BIT_(0) +#define CYGHWR_HAL_STM32_I2C_SR1_ADDR BIT_(1) +#define CYGHWR_HAL_STM32_I2C_SR1_BTF BIT_(2) +#define CYGHWR_HAL_STM32_I2C_SR1_ADD10 BIT_(3) +#define CYGHWR_HAL_STM32_I2C_SR1_STOPF BIT_(4) +#define CYGHWR_HAL_STM32_I2C_SR1_RxNE BIT_(6) +#define CYGHWR_HAL_STM32_I2C_SR1_TxE BIT_(7) +#define CYGHWR_HAL_STM32_I2C_SR1_BERR BIT_(8) +#define CYGHWR_HAL_STM32_I2C_SR1_ARLO BIT_(9) +#define CYGHWR_HAL_STM32_I2C_SR1_AF BIT_(10) +#define CYGHWR_HAL_STM32_I2C_SR1_OVR BIT_(11) +#define CYGHWR_HAL_STM32_I2C_SR1_PECERR BIT_(12) +#define CYGHWR_HAL_STM32_I2C_SR1_TIMEOUT BIT_(14) +#define CYGHWR_HAL_STM32_I2C_SR1_SMBALERT BIT_(15) + + +#define CYGHWR_HAL_STM32_I2C_SR2_MSL BIT_(0) +#define CYGHWR_HAL_STM32_I2C_SR2_BUSY BIT_(1) +#define CYGHWR_HAL_STM32_I2C_SR2_TRA BIT_(2) +#define CYGHWR_HAL_STM32_I2C_SR2_GENCALL BIT_(4) +#define CYGHWR_HAL_STM32_I2C_SR2_SMBDEFAULT BIT_(5) +#define CYGHWR_HAL_STM32_I2C_SR2_SMBHOST BIT_(6) +#define CYGHWR_HAL_STM32_I2C_SR2_DUALF BIT_(7) +#define CYGHWR_HAL_STM32_I2C_SR2_PEC MASK_(7,8) + +#define CYGHWR_HAL_STM32_I2C_CCR_CCR(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_I2C_CCR_CCR_MASK MASK_(0,12) +#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_2 0 +#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_16_9 BIT_(14) +#define CYGHWR_HAL_STM32_I2C_CCR_STD 0 +#define CYGHWR_HAL_STM32_I2C_CCR_FAST BIT_(15) + +#define CYGHWR_HAL_STM32_I2C_TRISE_VAL(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_I2C_TRISE_MASK MASK_(0,6) + +// Clock control definitions for each I2C bus + +#define CYGHWR_HAL_STM32_I2C1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, I2C1 ) +#define CYGHWR_HAL_STM32_I2C2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, I2C2 ) + + +//============================================================================= +// USB interface register definitions. + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_USB_EP0R 0x00 +#define CYGHWR_HAL_STM32_USB_EP1R 0x04 +#define CYGHWR_HAL_STM32_USB_EP2R 0x08 +#define CYGHWR_HAL_STM32_USB_EP3R 0x0C +#define CYGHWR_HAL_STM32_USB_EP4R 0x10 +#define CYGHWR_HAL_STM32_USB_EP5R 0x14 +#define CYGHWR_HAL_STM32_USB_EP6R 0x18 +#define CYGHWR_HAL_STM32_USB_EP7R 0x1C + +#define CYGHWR_HAL_STM32_USB_CNTR 0x40 +#define CYGHWR_HAL_STM32_USB_ISTR 0x44 +#define CYGHWR_HAL_STM32_USB_FNR 0x48 +#define CYGHWR_HAL_STM32_USB_DADDR 0x4C +#define CYGHWR_HAL_STM32_USB_BTABLE 0x50 + +// The following macro allows the USB endpoint registers to be indexed as +// CYGHWR_HAL_STM32_USB_EPXR(0) to CYGHWR_HAL_STM32_USB_EPXR(7). +#define CYGHWR_HAL_STM32_USB_EPXR(__x) ((__x)*4) + +#define CYGHWR_HAL_STM32_USB_EPXR_EA(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS VALUE_(4,0) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL VALUE_(4,1) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK VALUE_(4,2) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID VALUE_(4,3) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK VALUE_(4,3) +#define CYGHWR_HAL_STM32_USB_EPXR_DTOGTX BIT_(6) +#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX BIT_(6) +#define CYGHWR_HAL_STM32_USB_EPXR_CTRTX BIT_(7) +#define CYGHWR_HAL_STM32_USB_EPXR_EPKIND BIT_(8) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_BULK VALUE_(9,0) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_CTRL VALUE_(9,1) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_ISO VALUE_(9,2) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_INTR VALUE_(9,3) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_MASK VALUE_(9,3) +#define CYGHWR_HAL_STM32_USB_EPXR_SETUP BIT_(11) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS VALUE_(12,0) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL VALUE_(12,1) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK VALUE_(12,2) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID VALUE_(12,3) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK VALUE_(12,3) +#define CYGHWR_HAL_STM32_USB_EPXR_DTOGRX BIT_(14) +#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX BIT_(14) +#define CYGHWR_HAL_STM32_USB_EPXR_CTRRX BIT_(15) + +#define CYGHWR_HAL_STM32_USB_CNTR_FRES BIT_(0) +#define CYGHWR_HAL_STM32_USB_CNTR_PDWN BIT_(1) +#define CYGHWR_HAL_STM32_USB_CNTR_LPMODE BIT_(2) +#define CYGHWR_HAL_STM32_USB_CNTR_FSUSP BIT_(3) +#define CYGHWR_HAL_STM32_USB_CNTR_RESUME BIT_(4) +#define CYGHWR_HAL_STM32_USB_CNTR_ESOFM BIT_(8) +#define CYGHWR_HAL_STM32_USB_CNTR_SOFM BIT_(9) +#define CYGHWR_HAL_STM32_USB_CNTR_RESETM BIT_(10) +#define CYGHWR_HAL_STM32_USB_CNTR_SUSPM BIT_(11) +#define CYGHWR_HAL_STM32_USB_CNTR_WKUPM BIT_(12) +#define CYGHWR_HAL_STM32_USB_CNTR_ERRM BIT_(13) +#define CYGHWR_HAL_STM32_USB_CNTR_PMAOVRM BIT_(14) +#define CYGHWR_HAL_STM32_USB_CNTR_CTRM BIT_(15) + +#define CYGHWR_HAL_STM32_USB_ISTR_EPID(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_ISTR_EPID_MASK MASK_(0,4) +#define CYGHWR_HAL_STM32_USB_ISTR_DIR BIT_(4) +#define CYGHWR_HAL_STM32_USB_ISTR_ESOF BIT_(8) +#define CYGHWR_HAL_STM32_USB_ISTR_SOF BIT_(9) +#define CYGHWR_HAL_STM32_USB_ISTR_RESET BIT_(10) +#define CYGHWR_HAL_STM32_USB_ISTR_SUSP BIT_(11) +#define CYGHWR_HAL_STM32_USB_ISTR_WKUP BIT_(12) +#define CYGHWR_HAL_STM32_USB_ISTR_ERR BIT_(13) +#define CYGHWR_HAL_STM32_USB_ISTR_PMAOVR BIT_(14) +#define CYGHWR_HAL_STM32_USB_ISTR_CTR BIT_(15) + +#define CYGHWR_HAL_STM32_USB_FNR_FN_MASK MASK_(0,11) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF0 VALUE_(11,0) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF1 VALUE_(11,1) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF2 VALUE_(11,2) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOFN VALUE_(11,3) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_MASK MASK_(11,2) +#define CYGHWR_HAL_STM32_USB_FNR_LCK BIT_(13) +#define CYGHWR_HAL_STM32_USB_FNR_RXDM BIT_(14) +#define CYGHWR_HAL_STM32_USB_FNR_RXDP BIT_(15) + +#define CYGHWR_HAL_STM32_USB_DADDR_ADD(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_DADDR_EF BIT_(7) + +#define CYGHWR_HAL_STM32_USB_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, USB ) + +#endif // if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +// USB in F2/F4 parts is completely different. Definitions will be provided when implemented. + +//============================================================================= +// Timers +// +// This currently only defines the basic registers and functionality +// common to all timers. + +#define CYGHWR_HAL_STM32_TIM_CR1 0x00 +#define CYGHWR_HAL_STM32_TIM_CR2 0x04 +#define CYGHWR_HAL_STM32_TIM_DIER 0x0C +#define CYGHWR_HAL_STM32_TIM_SR 0x10 +#define CYGHWR_HAL_STM32_TIM_EGR 0x14 +#define CYGHWR_HAL_STM32_TIM_CCMR1 0x18 +#define CYGHWR_HAL_STM32_TIM_CCMR2 0x1C +#define CYGHWR_HAL_STM32_TIM_CCER 0x20 +#define CYGHWR_HAL_STM32_TIM_CNT 0x24 +#define CYGHWR_HAL_STM32_TIM_PSC 0x28 +#define CYGHWR_HAL_STM32_TIM_ARR 0x2C +#define CYGHWR_HAL_STM32_TIM_CCR1 0x34 +#define CYGHWR_HAL_STM32_TIM_CCR2 0x38 +#define CYGHWR_HAL_STM32_TIM_CCR3 0x3C +#define CYGHWR_HAL_STM32_TIM_CCR4 0x40 + +#define CYGHWR_HAL_STM32_TIM_CR1_CEN BIT_(0) +#define CYGHWR_HAL_STM32_TIM_CR1_UDIS BIT_(1) +#define CYGHWR_HAL_STM32_TIM_CR1_URS BIT_(2) +#define CYGHWR_HAL_STM32_TIM_CR1_OPM BIT_(3) +#define CYGHWR_HAL_STM32_TIM_CR1_DIR BIT_(4) +#define CYGHWR_HAL_STM32_TIM_CR1_ARPE BIT_(7) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_1 VALUE_(8,0) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_2 VALUE_(8,1) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_4 VALUE_(8,2) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_XXX VALUE_(8,3) + +#define CYGHWR_HAL_STM32_TIM_CR2_MMS_RESET VALUE_(4,0) +#define CYGHWR_HAL_STM32_TIM_CR2_MMS_ENABLE VALUE_(4,1) +#define CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE VALUE_(4,2) + +#define CYGHWR_HAL_STM32_TIM_DIER_UIE BIT_(0) +#define CYGHWR_HAL_STM32_TIM_DIER_UDE BIT_(8) + +#define CYGHWR_HAL_STM32_TIM_SR_UIF BIT_(0) + +#define CYGHWR_HAL_STM32_TIM_EGR_UG BIT_(0) + +// Clock control pins +#define CYGHWR_HAL_STM32_TIM1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM1 ) +#define CYGHWR_HAL_STM32_TIM2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM2 ) +#define CYGHWR_HAL_STM32_TIM3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM3 ) +#define CYGHWR_HAL_STM32_TIM4_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM4 ) +#define CYGHWR_HAL_STM32_TIM5_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM5 ) +#define CYGHWR_HAL_STM32_TIM6_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM6 ) +#define CYGHWR_HAL_STM32_TIM7_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM7 ) +#define CYGHWR_HAL_STM32_TIM8_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM8 ) +#if 0 +#define CYGHWR_HAL_STM32_TIM9_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM9 ) +#define CYGHWR_HAL_STM32_TIM10_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM10 ) +#define CYGHWR_HAL_STM32_TIM11_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM11 ) +#define CYGHWR_HAL_STM32_TIM12_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM12 ) +#define CYGHWR_HAL_STM32_TIM13_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM13 ) +#define CYGHWR_HAL_STM32_TIM14_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM14 ) +#endif + +#ifndef __ASSEMBLER__ + +__externC cyg_uint32 hal_stm32_timer_clock( CYG_ADDRESS base ); + +#endif + +//============================================================================= +// Independent Watchdog + +#define CYGHWR_HAL_STM32_IWDG_KR 0x00 +#define CYGHWR_HAL_STM32_IWDG_PR 0x04 +#define CYGHWR_HAL_STM32_IWDG_RLR 0x08 +#define CYGHWR_HAL_STM32_IWDG_SR 0x0C + +#define CYGHWR_HAL_STM32_IWDG_KR_RESET 0xAAAA +#define CYGHWR_HAL_STM32_IWDG_KR_ACCESS 0x5555 +#define CYGHWR_HAL_STM32_IWDG_KR_START 0xCCCC + +#define CYGHWR_HAL_STM32_IWDG_PR_4 0 +#define CYGHWR_HAL_STM32_IWDG_PR_8 1 +#define CYGHWR_HAL_STM32_IWDG_PR_16 2 +#define CYGHWR_HAL_STM32_IWDG_PR_32 3 +#define CYGHWR_HAL_STM32_IWDG_PR_64 4 +#define CYGHWR_HAL_STM32_IWDG_PR_128 5 +#define CYGHWR_HAL_STM32_IWDG_PR_256 6 + +#define CYGHWR_HAL_STM32_IWDG_SR_PVU BIT_(0) +#define CYGHWR_HAL_STM32_IWDG_SR_RVU BIT_(1) + +// Clock control + +//#define CYGHWR_HAL_STM32_IWDG_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, IWDG ) + + +//============================================================================= +// Flash controller + +#define CYGHWR_HAL_STM32_FLASH_ACR 0x00 +#define CYGHWR_HAL_STM32_FLASH_KEYR 0x04 +#define CYGHWR_HAL_STM32_FLASH_OPTKEYR 0x08 +#define CYGHWR_HAL_STM32_FLASH_SR 0x0C +#define CYGHWR_HAL_STM32_FLASH_CR 0x10 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_FLASH_AR 0x14 +#define CYGHWR_HAL_STM32_FLASH_OBR 0x1C +#define CYGHWR_HAL_STM32_FLASH_WRPR 0x20 +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_FLASH_OPTCR 0x14 +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// Key values + +#define CYGHWR_HAL_STM32_FLASH_KEYR_KEY1 0x45670123 +#define CYGHWR_HAL_STM32_FLASH_KEYR_KEY2 0xCDEF89AB + +// ACR fields + +#define CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(__x) VALUE_(0,__x) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_FLASH_ACR_HLFCYA BIT_(3) +#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBS BIT_(5) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN BIT_(8) +#define CYGHWR_HAL_STM32_FLASH_ACR_ICEN BIT_(9) +#define CYGHWR_HAL_STM32_FLASH_ACR_DCEN BIT_(10) +#define CYGHWR_HAL_STM32_FLASH_ACR_ICRST BIT_(11) +#define CYGHWR_HAL_STM32_FLASH_ACR_DCRST BIT_(12) + +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// SR fields + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_FLASH_SR_BSY BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_SR_PGERR BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_SR_WRPRTERR BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_SR_EOP BIT_(5) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_FLASH_SR_EOP BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_SR_OPERR BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_SR_WRPERR BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_SR_PGAERR BIT_(5) +#define CYGHWR_HAL_STM32_FLASH_SR_PGPERR BIT_(6) +#define CYGHWR_HAL_STM32_FLASH_SR_PGSERR BIT_(7) +#define CYGHWR_HAL_STM32_FLASH_SR_BSY BIT_(16) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// CR fields + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_FLASH_CR_PG BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_CR_PER BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_CR_MER BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_CR_OPTPG BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_CR_OPTER BIT_(5) +#define CYGHWR_HAL_STM32_FLASH_CR_STRT BIT_(6) +#define CYGHWR_HAL_STM32_FLASH_CR_LOCK BIT_(7) +#define CYGHWR_HAL_STM32_FLASH_CR_OPTWRE BIT_(9) +#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE BIT_(10) +#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE BIT_(12) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_FLASH_CR_PG BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_CR_SER BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_CR_MER BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_CR_SNB(__x) (((__x)&0xf) << 3) +#define CYGHWR_HAL_STM32_FLASH_CR_SNB_MASK MASK_(3,4) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE(__x) ( (__x) == 8 ? VALUE_(8,0) : \ + (__x) == 16 ? VALUE_(8,1) : \ + (__x) == 32 ? VALUE_(8,2) : \ + VALUE_(8,3) ) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_8 VALUE_(8,0) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_16 VALUE_(8,1) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_32 VALUE_(8,2) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_64 VALUE_(8,3) +#define CYGHWR_HAL_STM32_FLASH_CR_STRT BIT_(16) +#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE BIT_(24) +#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE BIT_(25) +#define CYGHWR_HAL_STM32_FLASH_CR_LOCK BIT_(31) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// OBR fields +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_FLASH_OBR_OPTERR BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_OBR_RDPRT BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_OBR_WDG_SW BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STOP BIT_(3) +#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STDBY BIT_(4) +#endif + +// F2/F4 FLASH_OPTCR not defined as our flash driver doesn't use it. + +//============================================================================= +// Power control + +#define CYGHWR_HAL_STM32_PWR_CR 0x00 +#define CYGHWR_HAL_STM32_PWR_CSR 0x04 + +// CR fields + +#define CYGHWR_HAL_STM32_PWR_CR_LPDS BIT_(0) +#define CYGHWR_HAL_STM32_PWR_CR_PDDS BIT_(1) +#define CYGHWR_HAL_STM32_PWR_CR_CWUF BIT_(2) +#define CYGHWR_HAL_STM32_PWR_CR_CSBF BIT_(3) +#define CYGHWR_HAL_STM32_PWR_CR_PVDE BIT_(4) +#define CYGHWR_HAL_STM32_PWR_CR_PLS_XXX VALUE_(5,7) +#define CYGHWR_HAL_STM32_PWR_CR_DBP BIT_(8) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_PWR_CR_FPDS BIT_(9) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_PWR_CR_VOS BIT_(14) +#endif // (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +// CSR fields + +#define CYGHWR_HAL_STM32_PWR_CSR_WUF BIT_(0) +#define CYGHWR_HAL_STM32_PWR_CSR_SBF BIT_(1) +#define CYGHWR_HAL_STM32_PWR_CSR_PVDO BIT_(2) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_PWR_CSR_BRR BIT_(3) +#endif +#define CYGHWR_HAL_STM32_PWR_CSR_EWUP BIT_(8) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_PWR_CSR_BRE BIT_(9) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_PWR_CSR_VOSRDY BIT_(14) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +// Functions and macros to reset the backup domain as well as +// enable/disable backup domain write protection. + +#ifndef __ASSEMBLER__ + +__externC void hal_stm32_bd_protect( int protect ); + +#endif + +#define CYGHWR_HAL_STM32_BD_RESET() \ + CYG_MACRO_START \ + HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, \ + CYGHWR_HAL_STM32_RCC_BDCR_BDRST); \ + HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, 0); \ + CYG_MACRO_END + +#define CYGHWR_HAL_STM32_BD_PROTECT(__protect ) \ + hal_stm32_bd_protect( __protect ) + +//============================================================================= +// FSMC +// +// These registers are usually set up in hal_system_init() using direct +// binary values. Hence we don't define all the fields here (of which +// there are many). + +#define CYGHWR_HAL_STM32_FSMC_BCR1 0x00 +#define CYGHWR_HAL_STM32_FSMC_BTR1 0x04 +#define CYGHWR_HAL_STM32_FSMC_BCR2 0x08 +#define CYGHWR_HAL_STM32_FSMC_BTR2 0x0C +#define CYGHWR_HAL_STM32_FSMC_BCR3 0x10 +#define CYGHWR_HAL_STM32_FSMC_BTR3 0x14 +#define CYGHWR_HAL_STM32_FSMC_BCR4 0x18 +#define CYGHWR_HAL_STM32_FSMC_BTR4 0x1C + +#define CYGHWR_HAL_STM32_FSMC_BWTR1 0x104 +#define CYGHWR_HAL_STM32_FSMC_BWTR2 0x10C +#define CYGHWR_HAL_STM32_FSMC_BWTR3 0x114 +#define CYGHWR_HAL_STM32_FSMC_BWTR4 0x11C + +#define CYGHWR_HAL_STM32_FSMC_PCR2 0x60 +#define CYGHWR_HAL_STM32_FSMC_SR2 0x64 +#define CYGHWR_HAL_STM32_FSMC_PMEM2 0x68 +#define CYGHWR_HAL_STM32_FSMC_PATT2 0x6C +#define CYGHWR_HAL_STM32_FSMC_ECCR2 0x74 + +#define CYGHWR_HAL_STM32_FSMC_PCR3 0x80 +#define CYGHWR_HAL_STM32_FSMC_SR3 0x84 +#define CYGHWR_HAL_STM32_FSMC_PMEM3 0x88 +#define CYGHWR_HAL_STM32_FSMC_PATT3 0x8C +#define CYGHWR_HAL_STM32_FSMC_ECCR3 0x94 + +#define CYGHWR_HAL_STM32_FSMC_PCR4 0xA0 +#define CYGHWR_HAL_STM32_FSMC_SR4 0xA4 +#define CYGHWR_HAL_STM32_FSMC_PMEM4 0xA8 +#define CYGHWR_HAL_STM32_FSMC_PATT4 0xAC + +#define CYGHWR_HAL_STM32_FSMC_PIO4 0xB0 + +#define CYGHWR_HAL_STM32_FSMC_BANK1_BASE 0x60000000 +#define CYGHWR_HAL_STM32_FSMC_BANK2_BASE 0x70000000 +#define CYGHWR_HAL_STM32_FSMC_BANK3_BASE 0x80000000 +#define CYGHWR_HAL_STM32_FSMC_BANK4_BASE 0x90000000 + +#define CYGHWR_HAL_STM32_FSMC_BANK_CMD 0x10000 +#define CYGHWR_HAL_STM32_FSMC_BANK_ADDR 0x20000 + +// PCR fields + +#define CYGHWR_HAL_STM32_FSMC_PCR_PWAITEN BIT_(1) +#define CYGHWR_HAL_STM32_FSMC_PCR_PBKEN BIT_(2) +#define CYGHWR_HAL_STM32_FSMC_PCR_PTYP_NAND BIT_(3) +#define CYGHWR_HAL_STM32_FSMC_PCR_PWID_8 VALUE_(4,0) +#define CYGHWR_HAL_STM32_FSMC_PCR_PWID_16 VALUE_(4,1) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCEN BIT_(6) +// FIXME: I don't see where ADLOW comes from? It's not in F1, F2 or F4. -Jifl +#define CYGHWR_HAL_STM32_FSMC_PCR_ADLOW BIT_(8) +#define CYGHWR_HAL_STM32_FSMC_PCR_TCLR(__x) VALUE_(9,__x) +#define CYGHWR_HAL_STM32_FSMC_PCR_TAR(__x) VALUE_(13,__x) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_256 VALUE_(17,0) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_512 VALUE_(17,1) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_1024 VALUE_(17,2) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_2048 VALUE_(17,3) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_4096 VALUE_(17,4) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_8192 VALUE_(17,5) + +// SR fields + +#define CYGHWR_HAL_STM32_FSMC_SR_IRS BIT_(0) +#define CYGHWR_HAL_STM32_FSMC_SR_ILS BIT_(1) +#define CYGHWR_HAL_STM32_FSMC_SR_IFS BIT_(2) +#define CYGHWR_HAL_STM32_FSMC_SR_IREN BIT_(3) +#define CYGHWR_HAL_STM32_FSMC_SR_ILEN BIT_(4) +#define CYGHWR_HAL_STM32_FSMC_SR_IFEN BIT_(5) +#define CYGHWR_HAL_STM32_FSMC_SR_FEMPT BIT_(6) + +//============================================================================= +// CAN +// + +#define CYGHWR_HAL_STM32_CAN1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, CAN1 ) +#define CYGHWR_HAL_STM32_CAN2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, CAN2 ) + + +//============================================================================= +// Ethernet MAC +// Include separate header file for this to avoid this header getting unmanageable. + +#include <cyg/hal/var_io_eth.h> + +//========================================================================== + +#if (defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RC) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VC) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZC) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RD) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VD) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZD) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RE) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VE) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZE)) +// NOTE: From ST document ES0104 (STM32F101xC/D/E and STM32F103xC/D/E) +// errata section 2.6.9 we cannot use FSMC and I2C1 at the same time. +// For I2C1 support we are limited to on-chip SRAM/Flash execution and +// must ensure that FSMC is disabled. +# if (defined(CYG_HAL_STARTUP_SRAM) || \ + defined(CYG_HAL_STARTUP_ROM) || \ + defined(CYG_HAL_STARTUP_JTAG)) +# define HAL_AARDVARK_CHECK_I2C( _i2cdev_ ) \ + CYG_MACRO_START \ + if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) { \ + CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_CLOCK( AHB, FSMC) ); \ + } \ + CYG_MACRO_END +# else // on this CPU we cannot use I2C1 since FSMC needed for the CYG_HAL_STARTUP type +# define HAL_AARDVARK_CHECK_I2C( _i2cdev_ ) \ + CYG_MACRO_START \ + if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) { \ + CYG_TEST_FAIL_FINISH("Invalid CYG_HAL_STARTUP for I2C1 operations"); \ + } \ + CYG_MACRO_END +# endif +#endif + +//========================================================================== + +#endif // CYGONCE_HAL_VAR_IO_H +//----------------------------------------------------------------------------- +// end of var_io.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h new file mode 100644 index 0000000..a5ab5fa --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h @@ -0,0 +1,490 @@ +#ifndef CYGONCE_HAL_VAR_IO_ETH_H +#define CYGONCE_HAL_VAR_IO_ETH_H +//============================================================================= +// +// var_io_eth.h +// +// Ethernet-specific variant definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jlarmour +// Date: 2008-07-30 +// Purpose: STM32 variant ETH specific registers +// Description: +// Usage: Do not include this header file directly. Instead: +// #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_VAR_IO_H +# error Do not include var_io_eth.h directly, use var_io.h +#endif + + +//============================================================================= +// Ethernet MAC +// +// Connectivity devices only + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#define CYGHWR_HAL_STM32_ETH_MACCR 0x0000 +#define CYGHWR_HAL_STM32_ETH_MACFFR 0x0004 +#define CYGHWR_HAL_STM32_ETH_MACHTHR 0x0008 +#define CYGHWR_HAL_STM32_ETH_MACHTLR 0x000C +#define CYGHWR_HAL_STM32_ETH_MACMIIAR 0x0010 +#define CYGHWR_HAL_STM32_ETH_MACMIIDR 0x0014 +#define CYGHWR_HAL_STM32_ETH_MACFCR 0x0018 +#define CYGHWR_HAL_STM32_ETH_MACVLANTR 0x001C +#define CYGHWR_HAL_STM32_ETH_MACRWUFFR 0x0028 +#define CYGHWR_HAL_STM32_ETH_MACPMTCSR 0x002C +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MACDBGR 0x0034 +#endif +#define CYGHWR_HAL_STM32_ETH_MACSR 0x0038 +#define CYGHWR_HAL_STM32_ETH_MACIMR 0x003C +#define CYGHWR_HAL_STM32_ETH_MACA0HR 0x0040 +#define CYGHWR_HAL_STM32_ETH_MACA0LR 0x0044 +#define CYGHWR_HAL_STM32_ETH_MACA1HR 0x0048 +#define CYGHWR_HAL_STM32_ETH_MACA1LR 0x004C +#define CYGHWR_HAL_STM32_ETH_MACA2HR 0x0050 +#define CYGHWR_HAL_STM32_ETH_MACA2LR 0x0054 +#define CYGHWR_HAL_STM32_ETH_MACA3HR 0x0058 +#define CYGHWR_HAL_STM32_ETH_MACA3LR 0x005C + +#define CYGHWR_HAL_STM32_ETH_MMCCR 0x0100 +#define CYGHWR_HAL_STM32_ETH_MMCRIR 0x0104 +#define CYGHWR_HAL_STM32_ETH_MMCTIR 0x0108 +#define CYGHWR_HAL_STM32_ETH_MMCRIMR 0x010C +#define CYGHWR_HAL_STM32_ETH_MMCTIMR 0x0110 +#define CYGHWR_HAL_STM32_ETH_MMCTGFSCCR 0x014C +#define CYGHWR_HAL_STM32_ETH_MMCTGFMSCCR 0x0150 +#define CYGHWR_HAL_STM32_ETH_MMCTGFCR 0x0168 +#define CYGHWR_HAL_STM32_ETH_MMCRFCECR 0x0194 +#define CYGHWR_HAL_STM32_ETH_MMCRFAECR 0x0198 +#define CYGHWR_HAL_STM32_ETH_MMCRGUFCR 0x01C4 + +#define CYGHWR_HAL_STM32_ETH_PTPTSCR 0x0700 +#define CYGHWR_HAL_STM32_ETH_PTPSSIR 0x0704 +#define CYGHWR_HAL_STM32_ETH_PTPTSHR 0x0708 +#define CYGHWR_HAL_STM32_ETH_PTPTSLR 0x070C +#define CYGHWR_HAL_STM32_ETH_PTPTSHUR 0x0710 +#define CYGHWR_HAL_STM32_ETH_PTPTSLUR 0x0714 +#define CYGHWR_HAL_STM32_ETH_PTPTSAR 0x0718 +#define CYGHWR_HAL_STM32_ETH_PTPTTHR 0x071C +#define CYGHWR_HAL_STM32_ETH_PTPTTLR 0x0720 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_PTPTSSR 0x0728 +#endif + +#define CYGHWR_HAL_STM32_ETH_DMABMR 0x1000 +#define CYGHWR_HAL_STM32_ETH_DMATPDR 0x1004 +#define CYGHWR_HAL_STM32_ETH_DMARPDR 0x1008 +#define CYGHWR_HAL_STM32_ETH_DMARDLAR 0x100C +#define CYGHWR_HAL_STM32_ETH_DMATDLAR 0x1010 +#define CYGHWR_HAL_STM32_ETH_DMASR 0x1014 +#define CYGHWR_HAL_STM32_ETH_DMAOMR 0x1018 +#define CYGHWR_HAL_STM32_ETH_DMAIER 0x101C +#define CYGHWR_HAL_STM32_ETH_DMAMFBOCR 0x1020 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_DMARSWTR 0x1024 +#endif +#define CYGHWR_HAL_STM32_ETH_DMACHTDR 0x1048 +#define CYGHWR_HAL_STM32_ETH_DMACHRDR 0x104C +#define CYGHWR_HAL_STM32_ETH_DMACHTBAR 0x1050 +#define CYGHWR_HAL_STM32_ETH_DMACHRBAR 0x1054 + +// MACCR + +#define CYGHWR_HAL_STM32_ETH_MACCR_RE BIT_(2) +#define CYGHWR_HAL_STM32_ETH_MACCR_TE BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACCR_DC BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MACCR_BL(__x) VALUE_(6, __x) +#define CYGHWR_HAL_STM32_ETH_MACCR_APCS BIT_(7) +#define CYGHWR_HAL_STM32_ETH_MACCR_RD BIT_(9) +#define CYGHWR_HAL_STM32_ETH_MACCR_IPCO BIT_(10) +#define CYGHWR_HAL_STM32_ETH_MACCR_DM BIT_(11) +#define CYGHWR_HAL_STM32_ETH_MACCR_LM BIT_(12) +#define CYGHWR_HAL_STM32_ETH_MACCR_ROD BIT_(13) +#define CYGHWR_HAL_STM32_ETH_MACCR_FES BIT_(14) +#define CYGHWR_HAL_STM32_ETH_MACCR_CSD BIT_(16) +#define CYGHWR_HAL_STM32_ETH_MACCR_IFG(__x) VALUE_(17, (96-(__x))/8 ) +#define CYGHWR_HAL_STM32_ETH_MACCR_JD BIT_(22) +#define CYGHWR_HAL_STM32_ETH_MACCR_WD BIT_(23) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MACCR_CSTF BIT_(25) +#endif + +// MACFFR + +#define CYGHWR_HAL_STM32_ETH_MACFFR_PM BIT_(0) +#define CYGHWR_HAL_STM32_ETH_MACFFR_HU BIT_(1) +#define CYGHWR_HAL_STM32_ETH_MACFFR_HM BIT_(2) +#define CYGHWR_HAL_STM32_ETH_MACFFR_DAIF BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PAM BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MACFFR_BFD BIT_(5) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_BLOCK VALUE_(6,0) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_NOPAUSE VALUE_(6,1) +#endif +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_ALL VALUE_(6,2) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_FILTER VALUE_(6,3) +#define CYGHWR_HAL_STM32_ETH_MACFFR_SAIF BIT_(8) +#define CYGHWR_HAL_STM32_ETH_MACFFR_SAF BIT_(9) +#define CYGHWR_HAL_STM32_ETH_MACFFR_HPF BIT_(10) +#define CYGHWR_HAL_STM32_ETH_MACFFR_RA BIT_(31) + +// MACHT* omitted + +// MACMIIAR + +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MB BIT_(0) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MW BIT_(1) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(__x) VALUE_(2,__x) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MASK MASK_(2,4) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 72) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 120) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 168) +#endif +// This macro is shared between F1/F2/F4 families for now (despite +// irrelevance for >72Mhz speed, but that's checked above) but it's +// foreseeable that this could change for future products. +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ(_mhz) ( \ + ((_mhz) >= 150) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(4) : \ + ((_mhz) >= 100) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(1) : \ + ((_mhz) >= 60) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(0) : \ + ((_mhz) >= 35) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(3) : \ + /*((_mhz) >= 20) ?*/ CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(2)) + +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MR(__x) VALUE_(6,__x) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_PA(__x) VALUE_(11,__x) + +// MACFCR omitted +// MACVLANTR omitted +// MACRWUFFR omitted +// MACPMTCSR omitted +// MACDBGR (F2/F4 only) omitted + +// MACSR + +#define CYGHWR_HAL_STM32_ETH_MACSR_PMTS BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACSR_MMCS BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MACSR_MMCRS BIT_(5) +#define CYGHWR_HAL_STM32_ETH_MACSR_MMCTS BIT_(6) +#define CYGHWR_HAL_STM32_ETH_MACSR_TSTS BIT_(9) + +// MACIMR + +#define CYGHWR_HAL_STM32_ETH_MACIMR_PMTIM BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACIMR_TSTIM BIT_(9) + +// MMCR + +#define CYGHWR_HAL_STM32_ETH_MMCCR_CR BIT_(0) +#define CYGHWR_HAL_STM32_ETH_MMCCR_CSR BIT_(1) +#define CYGHWR_HAL_STM32_ETH_MMCCR_ROR BIT_(2) +#define CYGHWR_HAL_STM32_ETH_MMCCR_MCF BIT_(3) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MMCCR_MCP BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MMCCR_MCFHP BIT_(5) +#endif + +// MMCRIR & MMCRIMR + +#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFCES BIT_(5) +#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFAES BIT_(6) +#define CYGHWR_HAL_STM32_ETH_MMCRIR_RGUFS BIT_(17) + +// MMCTIR & MMCTIMR + +#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFSCS BIT_(14) +#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFMSCS BIT_(15) +#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFS BIT_(21) + +// PTP* omitted + +// DMABMR + +#define CYGHWR_HAL_STM32_ETH_DMABMR_SR BIT_(0) +#define CYGHWR_HAL_STM32_ETH_DMABMR_DA BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMABMR_DSL(__x) VALUE_(2,__x) +#define CYGHWR_HAL_STM32_ETH_DMABMR_PBL(__x) VALUE_(8,__x) +#define CYGHWR_HAL_STM32_ETH_DMABMR_RTPR(__x) VALUE_(14,(__x)-1) +#define CYGHWR_HAL_STM32_ETH_DMABMR_FB BIT_(16) +#define CYGHWR_HAL_STM32_ETH_DMABMR_RDP(__x) VALUE_(17,__x) +#define CYGHWR_HAL_STM32_ETH_DMABMR_USP BIT_(23) +#define CYGHWR_HAL_STM32_ETH_DMABMR_FPM BIT_(24) +#define CYGHWR_HAL_STM32_ETH_DMABMR_AAB BIT_(25) + +//DMASR + +#define CYGHWR_HAL_STM32_ETH_DMASR_TS BIT_(0) +#define CYGHWR_HAL_STM32_ETH_DMASR_TPSS BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMASR_TBUS BIT_(2) +#define CYGHWR_HAL_STM32_ETH_DMASR_TJTS BIT_(3) +#define CYGHWR_HAL_STM32_ETH_DMASR_ROS BIT_(4) +#define CYGHWR_HAL_STM32_ETH_DMASR_TUS BIT_(5) +#define CYGHWR_HAL_STM32_ETH_DMASR_RS BIT_(6) +#define CYGHWR_HAL_STM32_ETH_DMASR_RBUS BIT_(7) +#define CYGHWR_HAL_STM32_ETH_DMASR_RPSS BIT_(8) +#define CYGHWR_HAL_STM32_ETH_DMASR_RWTS BIT_(9) +#define CYGHWR_HAL_STM32_ETH_DMASR_ETS BIT_(10) +#define CYGHWR_HAL_STM32_ETH_DMASR_FBES BIT_(13) +#define CYGHWR_HAL_STM32_ETH_DMASR_ERS BIT_(14) +#define CYGHWR_HAL_STM32_ETH_DMASR_AIS BIT_(15) +#define CYGHWR_HAL_STM32_ETH_DMASR_NIS BIT_(16) +#define CYGHWR_HAL_STM32_ETH_DMASR_RPS MASK_(17,3) +#define CYGHWR_HAL_STM32_ETH_DMASR_TPS MASK_(20,3) +#define CYGHWR_HAL_STM32_ETH_DMASR_EBS MASK_(23,3) +#define CYGHWR_HAL_STM32_ETH_DMASR_MMCS BIT_(27) +#define CYGHWR_HAL_STM32_ETH_DMASR_PMTS BIT_(28) +#define CYGHWR_HAL_STM32_ETH_DMASR_TSTS BIT_(29) + +// DMAOMR + +#define CYGHWR_HAL_STM32_ETH_DMAOMR_SR BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_OSF BIT_(2) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_RTC(__x) VALUE_(3,__x) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_FUGF BIT_(6) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_FEF BIT_(7) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_ST BIT_(13) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_TTC(__x) VALUE_(14,__x) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_FTF BIT_(20) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_TSF BIT_(21) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_DFRF BIT_(24) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_RSF BIT_(25) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_DTCEFD BIT_(26) + +// DMAIER + +#define CYGHWR_HAL_STM32_ETH_DMAIER_TIE BIT_(0) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TPSIE BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TBUIE BIT_(2) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TJTIE BIT_(3) +#define CYGHWR_HAL_STM32_ETH_DMAIER_ROIE BIT_(4) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TUIE BIT_(5) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RIE BIT_(6) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RBUIE BIT_(7) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RPSIE BIT_(8) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RWTIE BIT_(9) +#define CYGHWR_HAL_STM32_ETH_DMAIER_ETIE BIT_(10) +#define CYGHWR_HAL_STM32_ETH_DMAIER_FBEIE BIT_(13) +#define CYGHWR_HAL_STM32_ETH_DMAIER_ERIE BIT_(14) +#define CYGHWR_HAL_STM32_ETH_DMAIER_AISE BIT_(15) +#define CYGHWR_HAL_STM32_ETH_DMAIER_NISE BIT_(16) + +// DMAFBOCR omitted + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK MASK_(0,8) +#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC(__x) ((__x)& CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK) +#endif + +// Transmit descriptor fields + +/* +----------------------------------------------------------------------- +TDES0|OWN(31)|CTRL[30:26]|Res[25:24]|CTRL[23:20]|Res[19:17]|Stat[16:0]| +----------------------------------------------------------------------- +TDES1|Res[31:29]| Buffer2 Len[28:16] | Res[15:13] | Buffer1 Len[12:0] | +----------------------------------------------------------------------- +TDES2| Buffer1 Address [31:0] | +----------------------------------------------------------------------- +TDES3| Buffer2 Address [31:0] | +----------------------------------------------------------------------- +*/ + +// TDES0 register: DMA Tx descriptor status + +#define CYGHWR_HAL_STM32_ETH_TDES0_DB BIT_(0) +#define CYGHWR_HAL_STM32_ETH_TDES0_UF BIT_(1) +#define CYGHWR_HAL_STM32_ETH_TDES0_ED BIT_(2) +#define CYGHWR_HAL_STM32_ETH_TDES0_CC MASK_(3,4) +#define CYGHWR_HAL_STM32_ETH_TDES0_VF BIT_(7) +#define CYGHWR_HAL_STM32_ETH_TDES0_EC BIT_(8) +#define CYGHWR_HAL_STM32_ETH_TDES0_LCO BIT_(9) +#define CYGHWR_HAL_STM32_ETH_TDES0_NC BIT_(10) +#define CYGHWR_HAL_STM32_ETH_TDES0_LCA BIT_(11) +#define CYGHWR_HAL_STM32_ETH_TDES0_IPE BIT_(12) +#define CYGHWR_HAL_STM32_ETH_TDES0_FF BIT_(13) +#define CYGHWR_HAL_STM32_ETH_TDES0_JT BIT_(14) +#define CYGHWR_HAL_STM32_ETH_TDES0_ES BIT_(15) +#define CYGHWR_HAL_STM32_ETH_TDES0_IHE BIT_(16) +#define CYGHWR_HAL_STM32_ETH_TDES0_TTSS BIT_(17) +#define CYGHWR_HAL_STM32_ETH_TDES0_TCH BIT_(20) +#define CYGHWR_HAL_STM32_ETH_TDES0_TER BIT_(21) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_DISA VALUE_(22,0) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_H VALUE_(22,1) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HP VALUE_(22,2) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HPP VALUE_(22,3) +#define CYGHWR_HAL_STM32_ETH_TDES0_TTSE BIT_(25) +#define CYGHWR_HAL_STM32_ETH_TDES0_DP BIT_(26) +#define CYGHWR_HAL_STM32_ETH_TDES0_DC BIT_(27) +#define CYGHWR_HAL_STM32_ETH_TDES0_FS BIT_(28) +#define CYGHWR_HAL_STM32_ETH_TDES0_LS BIT_(29) +#define CYGHWR_HAL_STM32_ETH_TDES0_IC BIT_(30) +#define CYGHWR_HAL_STM32_ETH_TDES0_OWN BIT_(31) + +#define CYGHWR_HAL_STM32_ETH_TDES1_TBS1(__x) (VALUE_(0,__x)&0x00001FFF) +#define CYGHWR_HAL_STM32_ETH_TDES1_TBS2(__x) (VALUE_(16,__x)&0x1FFF0000) + +// Receive descriptor fields + +/* +----------------------------------------------------------------------- +RDES0| OWN(31) | Status [30:0] | +----------------------------------------------------------------------- +RDES1|DIC(31)|Res[30:29]|Not Used|CTRL[15:14]|Res(13)|Buffer Len[12:0]| +----------------------------------------------------------------------- +RDES2| Buffer1 Address [31:0] | +----------------------------------------------------------------------- +RDES3| Not Used | +----------------------------------------------------------------------- +*/ + +// RDES0 register: DMA Rx descriptor status + +#define CYGHWR_HAL_STM32_ETH_RDES0_PCE BIT_(0) +#define CYGHWR_HAL_STM32_ETH_RDES0_CE BIT_(1) +#define CYGHWR_HAL_STM32_ETH_RDES0_DE BIT_(2) +#define CYGHWR_HAL_STM32_ETH_RDES0_RE BIT_(3) +#define CYGHWR_HAL_STM32_ETH_RDES0_RWT BIT_(4) +#define CYGHWR_HAL_STM32_ETH_RDES0_FT BIT_(5) +#define CYGHWR_HAL_STM32_ETH_RDES0_LCO BIT_(6) +#define CYGHWR_HAL_STM32_ETH_RDES0_IPHCE BIT_(7) +#define CYGHWR_HAL_STM32_ETH_RDES0_LS BIT_(8) +#define CYGHWR_HAL_STM32_ETH_RDES0_FS BIT_(9) +#define CYGHWR_HAL_STM32_ETH_RDES0_VLAN BIT_(10) +#define CYGHWR_HAL_STM32_ETH_RDES0_OE BIT_(11) +#define CYGHWR_HAL_STM32_ETH_RDES0_LE BIT_(12) +#define CYGHWR_HAL_STM32_ETH_RDES0_SAF BIT_(13) +#define CYGHWR_HAL_STM32_ETH_RDES0_DESCE BIT_(14) +#define CYGHWR_HAL_STM32_ETH_RDES0_ES BIT_(15) +#define CYGHWR_HAL_STM32_ETH_RDES0_FL(__x) (((__x)>>16)&0x3FFF) +#define CYGHWR_HAL_STM32_ETH_RDES0_AFM BIT_(30) +#define CYGHWR_HAL_STM32_ETH_RDES0_OWN BIT_(31) + +// RDES1 register : DMA Rx descriptor control and buffer length + +#define CYGHWR_HAL_STM32_ETH_RDES1_RBS1(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_ETH_RDES1_RCH BIT_(14) +#define CYGHWR_HAL_STM32_ETH_RDES1_RER BIT_(15) +#define CYGHWR_HAL_STM32_ETH_RDES1_RBS2(__x) VALUE_(16,__x) + + +// GPIO pins + +// NOTE: The platform specific (re-)mapping of pins is provided in the relevant +// target specific "plf_io.h" header file. These definitions just cover the +// fixed mappings. + +// MCO1 clock to PHY +#define CYGHWR_HAL_STM32_ETH_MCO CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 8, 0, PUSHPULL, NONE, AT_LEAST(50) ) + +// MII interface +#define CYGHWR_HAL_STM32_ETH_MII_MDC CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 1, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD2 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 2, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_MDIO CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 2, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TX_CLK CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 3, 11, OPENDRAIN, FLOATING ) +#define CYGHWR_HAL_STM32_ETH_MII_RX_CLK CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 1, 11, OPENDRAIN, FLOATING ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +// MII interface +#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS CYGHWR_HAL_STM32_PIN_IN( A, 0, FLOATING ) +#define CYGHWR_HAL_STM32_ETH_MII_COL CYGHWR_HAL_STM32_PIN_IN( A, 3, FLOATING ) +#define CYGHWR_HAL_STM32_ETH_MII_RX_ER CYGHWR_HAL_STM32_PIN_IN( B, 10, FLOATING ) + +#define CYGHWR_HAL_STM32_ETH_MII_TX_EN CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD0 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 12, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD1 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_PPS_OUT CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD3 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 8, 11, PUSHPULL, NONE, AT_LEAST(50) ) + +// RMII interface +#define CYGHWR_HAL_STM32_ETH_RMII_MDC CYGHWR_HAL_STM32_ETH_MII_MDC +#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK CYGHWR_HAL_STM32_ETH_MII_RX_CLK +#define CYGHWR_HAL_STM32_ETH_RMII_MDIO CYGHWR_HAL_STM32_ETH_MII_MDIO +#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN CYGHWR_HAL_STM32_ETH_MII_TX_EN +#define CYGHWR_HAL_STM32_ETH_RMII_TXD0 CYGHWR_HAL_STM32_ETH_MII_TXD0 +#define CYGHWR_HAL_STM32_ETH_RMII_TXD1 CYGHWR_HAL_STM32_ETH_MII_TXD1 +#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT CYGHWR_HAL_STM32_ETH_MII_PPS_OUT + +// Clock controls + +#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, ETHMAC ) +#define CYGHWR_HAL_STM32_ETH_TX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACTX ) +#define CYGHWR_HAL_STM32_ETH_RX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACRX ) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// MII interface +#define CYGHWR_HAL_STM32_ETH_MII_RX_DV CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 7, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD0 CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 4, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD1 CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 5, 11, OPENDRAIN, NONE ) + +// RMII interface +#define CYGHWR_HAL_STM32_ETH_RMII_MDC CYGHWR_HAL_STM32_ETH_MII_MDC +#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK CYGHWR_HAL_STM32_ETH_MII_RX_CLK +#define CYGHWR_HAL_STM32_ETH_RMII_MDIO CYGHWR_HAL_STM32_ETH_MII_MDIO +#define CYGHWR_HAL_STM32_ETH_RMII_CRS_DV CYGHWR_HAL_STM32_ETH_MII_RX_DV +#define CYGHWR_HAL_STM32_ETH_RMII_RXD0 CYGHWR_HAL_STM32_ETH_MII_RXD0 +#define CYGHWR_HAL_STM32_ETH_RMII_RXD1 CYGHWR_HAL_STM32_ETH_MII_RXD1 +#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN CYGHWR_HAL_STM32_ETH_MII_TX_EN +#define CYGHWR_HAL_STM32_ETH_RMII_TXD0 CYGHWR_HAL_STM32_ETH_MII_TXD0 +#define CYGHWR_HAL_STM32_ETH_RMII_TXD1 CYGHWR_HAL_STM32_ETH_MII_TXD1 +#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT CYGHWR_HAL_STM32_ETH_MII_PPS_OUT + +// Clock controls + +#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMAC ) +#define CYGHWR_HAL_STM32_ETH_TX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACTX ) +#define CYGHWR_HAL_STM32_ETH_RX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACRX ) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#endif // CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#endif // CYGONCE_HAL_VAR_IO_ETH_H +//----------------------------------------------------------------------------- +// end of var_io_eth.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h new file mode 100644 index 0000000..5ec9986 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h @@ -0,0 +1,502 @@ +#ifndef CYGONCE_HAL_VAR_IO_PINS_H +#define CYGONCE_HAL_VAR_IO_PINS_H +//============================================================================= +// +// var_io_pins.h +// +// Pin configuration and GPIO definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jlarmour +// Date: 2011-11-29 +// Purpose: STM32 variant GPIO and pin configuration specific registers +// Description: +// Usage: Do not include this header file directly. Instead: +// #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_VAR_IO_H +# error Do not include var_io_pins.h directly, use var_io.h +#endif + +//============================================================================= +// GPIO ports - common manifests + +#define CYGHWR_HAL_STM32_GPIO_OSPEED_NA (0) // Convenience define for ease of pin definitions (for F1 actually marks MODE as INPUT) + +//============================================================================= +// GPIO ports - F1 family + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_GPIO_CRL 0x00 +#define CYGHWR_HAL_STM32_GPIO_CRH 0x04 +#define CYGHWR_HAL_STM32_GPIO_IDR 0x08 +#define CYGHWR_HAL_STM32_GPIO_ODR 0x0C +#define CYGHWR_HAL_STM32_GPIO_BSRR 0x10 +#define CYGHWR_HAL_STM32_GPIO_BRR 0x14 +#define CYGHWR_HAL_STM32_GPIO_LCKR 0x18 + +#define CYGHWR_HAL_STM32_GPIO_MODE_IN VALUE_(0,0) // Input mode +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ VALUE_(0,1) // Output mode, max 10MHz +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ VALUE_(0,2) // Output mode, max 2MHz +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ VALUE_(0,3) // Output mode, max 50MHz + +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_LOW (CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ) +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_MED (CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ) +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST (CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ) +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH (CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST) // F1 limited to 50MHz + +// The following allows compatible specification of speed with other parts +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_LEAST(__mhz) ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ : \ + ((__mhz) <= 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ : \ + ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH ) + +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_MOST(__mhz) ( ((__mhz) < 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ : \ + ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ : \ + ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH ) + +#define CYGHWR_HAL_STM32_GPIO_CNF_AIN VALUE_(2,0) // Analog input +#define CYGHWR_HAL_STM32_GPIO_CNF_FIN VALUE_(2,1) // Floating input +#define CYGHWR_HAL_STM32_GPIO_CNF_PULL VALUE_(2,2) // Input with pull up/down +#define CYGHWR_HAL_STM32_GPIO_CNF_RESV VALUE_(2,3) // Reserved + +#define CYGHWR_HAL_STM32_GPIO_CNF_GPOPP VALUE_(2,0) // GP output push/pull +#define CYGHWR_HAL_STM32_GPIO_CNF_GPOOD VALUE_(2,1) // GP output open drain +#define CYGHWR_HAL_STM32_GPIO_CNF_AOPP VALUE_(2,2) // Alt output push/pull +#define CYGHWR_HAL_STM32_GPIO_CNF_AOOD VALUE_(2,3) // Alt output open drain + + +// Alternative, more readable, config names +// Inputs +#define CYGHWR_HAL_STM32_GPIO_CNF_ANALOG CYGHWR_HAL_STM32_GPIO_CNF_AIN +#define CYGHWR_HAL_STM32_GPIO_CNF_FLOATING CYGHWR_HAL_STM32_GPIO_CNF_FIN +#define CYGHWR_HAL_STM32_GPIO_CNF_PULLDOWN (CYGHWR_HAL_STM32_GPIO_CNF_PULL) +#define CYGHWR_HAL_STM32_GPIO_CNF_PULLUP (CYGHWR_HAL_STM32_GPIO_CNF_PULL|CYGHWR_HAL_STM32_GPIO_PULLUP) +// Outputs +#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_GPOOD +#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_PUSHPULL CYGHWR_HAL_STM32_GPIO_CNF_GPOPP +#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_AOOD +#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_PUSHPULL CYGHWR_HAL_STM32_GPIO_CNF_AOPP + + +// This macro packs the port number, bit number, mode and +// configuration for a GPIO pin into a single word. The packing puts +// the mode and config in the ls 5 bits, the bit number in 16:20 and +// the offset of the GPIO port from GPIOA in bits 8:15. The port, mode +// and config are only specified using the last component of the names +// to keep definitions short. + +#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __cnf ) \ + ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) | \ + (__bit<<16) | \ + (CYGHWR_HAL_STM32_GPIO_MODE_##__mode) | \ + (CYGHWR_HAL_STM32_GPIO_CNF_##__cnf)) + +// We treat the CNF and MODE fields as a single field to simplify the hardware register access. The CNFMODE fields are split across +// two registers (CRL/CRH) so the passed __pin needs to be in the range 0..7 +#define CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode) ((__cnfmode) << ((__pin)<<2)) +#define CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(__pin, __cnfmode, __reg) ((__reg) &= ~MASK_((__pin<<2),4), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode)) + +// Macros to extract encoded values +#define CYGHWR_HAL_STM32_GPIO_PORT(__pin) (CYGHWR_HAL_STM32_GPIOA+((__pin)&0x0000FF00)) +#define CYGHWR_HAL_STM32_GPIO_BIT(__pin) (((__pin)>>16)&0x1F) +#define CYGHWR_HAL_STM32_GPIO_CFG(__pin) ((__pin)&0xF) +#define CYGHWR_HAL_STM32_GPIO_PULLUP BIT_(4) + +//============================================================================= +// Alternate I/O configuration registers. + +#define CYGHWR_HAL_STM32_AFIO_EVCR 0x00 +#define CYGHWR_HAL_STM32_AFIO_MAPR 0x04 +#define CYGHWR_HAL_STM32_AFIO_EXTICR1 0x08 +#define CYGHWR_HAL_STM32_AFIO_EXTICR2 0x0C +#define CYGHWR_HAL_STM32_AFIO_EXTICR3 0x10 +#define CYGHWR_HAL_STM32_AFIO_EXTICR4 0x14 + +// The following macro allows the four EXTICR registers to be indexed +// as CYGHWR_HAL_STM32_AFIO_EXTICR(1) to CYGHWR_HAL_STM32_AFIO_EXTICR(4) +#define CYGHWR_HAL_STM32_AFIO_EXTICR(__x) (4*((__x)-1)+0x08) + +#define CYGHWR_HAL_STM32_AFIO_EVCR_PIN(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTA VALUE_(4,0) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTB VALUE_(4,1) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTC VALUE_(4,2) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTD VALUE_(4,3) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTE VALUE_(4,4) +#define CYGHWR_HAL_STM32_AFIO_EVCR_EVOE BIT_(7) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP BIT_(0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_I2C1_RMP BIT_(1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP BIT_(2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP BIT_(3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP VALUE_(4,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP VALUE_(4,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP VALUE_(4,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_NO_RMP VALUE_(6,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_P1_RMP VALUE_(6,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_FL_RMP VALUE_(6,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_NO_RMP VALUE_(8,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P1_RMP VALUE_(8,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P2_RMP VALUE_(8,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_FL_RMP VALUE_(8,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_NO_RMP VALUE_(10,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_P2_RMP VALUE_(10,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_FL_RMP VALUE_(10,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM4_RMP BIT_(12) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_NO_RMP VALUE_(13,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL1_RMP VALUE_(13,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL2_RMP VALUE_(13,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_PD01_RMP BIT_(15) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM5CH4_RMP BIT_(16) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EINJ_RMP BIT_(17) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EREG_RMP BIT_(18) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EINJ_RMP BIT_(19) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EREG_RMP BIT_(20) + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMP BIT_(21) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN2_RMP BIT_(22) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMII BIT_(23) +#endif + +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL VALUE_(24,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST VALUE_(24,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN VALUE_(24,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS VALUE_(24,4) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK VALUE_(24,7) + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP BIT_(28) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2ITR1_RMP BIT_(29) +#define CYGHWR_HAL_STM32_AFIO_MAPR_PTP_PPS_RMP BIT_(30) +#endif + +// The following macros are used to generate the bitfields for setting up +// external interrupts. For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12) +// will generate the bitfield which when ORed into the EXTICR4 register will +// set up C12 as the external interrupt pin for the EXTI12 interrupt. +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_MASK(__x) VALUE_(4*((__x)&3),0xF) + +// AFIO clock control + +#define CYGHWR_HAL_STM32_AFIO_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, AFIO ) + +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +//============================================================================= +// GPIO ports - F2/F4 family + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// GPIO Register offsets. +#define CYGHWR_HAL_STM32_GPIO_MODER 0x00 +#define CYGHWR_HAL_STM32_GPIO_OTYPER 0x04 +#define CYGHWR_HAL_STM32_GPIO_OSPEEDR 0x08 +#define CYGHWR_HAL_STM32_GPIO_PUPDR 0x0C +#define CYGHWR_HAL_STM32_GPIO_IDR 0x10 +#define CYGHWR_HAL_STM32_GPIO_ODR 0x14 +#define CYGHWR_HAL_STM32_GPIO_BSRR 0x18 +#define CYGHWR_HAL_STM32_GPIO_LCKR 0x1C +#define CYGHWR_HAL_STM32_GPIO_AFRL 0x20 +#define CYGHWR_HAL_STM32_GPIO_AFRH 0x24 + +// A helper macro just to allow access to a particular register +#define CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, __offset) ((volatile cyg_uint32 *)( ((char*)__portbaseaddr) + __offset )) + +// GPIO port mode register. +#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_IN (0) +#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_OUT (1) +#define CYGHWR_HAL_STM32_GPIO_MODE_ALTFN (2) +#define CYGHWR_HAL_STM32_GPIO_MODE_ANALOG (3) +#define CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode) ((__mode) << ((__pin)<<1)) +#define CYGHWR_HAL_STM32_GPIO_MODE_SET(__pin, __mode, __reg) ((__reg) &= ~MASK_((__pin<<1),2), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode)) + +// GPIO port output type register. +#define CYGHWR_HAL_STM32_GPIO_OTYPE_PUSHPULL (0) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_OPENDRAIN (1) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype) VALUE_(__pin,__otype) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_SET(__pin, __otype, __reg) ((__reg) &= ~BIT_(__pin), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype)) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_NA (0) // Convenience define for ease of pin definitions + +// GPIO port output speed register. +#define CYGHWR_HAL_STM32_GPIO_OSPEED_LOW (0) // 2MHz +#define CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ (0) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_MED (1) // 25MHz +#define CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ (1) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_FAST (2) // 50MHz +#define CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ (2) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH (3) // 100MHZ on 30pF, 80MHz on 15pF +#define CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed) ((__speed) << ((__pin)<<1)) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_SET(__pin, __speed, __reg) ((__reg) &= ~MASK_((__pin<<1),2), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed)) + +// The following allows compatible specification of speed with other parts +// which have different speed ranges e.g. F1 +#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_LEAST(__mhz) ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ : \ + ((__mhz) <= 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ : \ + ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH ) + +#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_MOST(__mhz) ( ((__mhz) < 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ : \ + ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ : \ + ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH ) + +// GPIO port pull-up/pull-down register. +#define CYGHWR_HAL_STM32_GPIO_PUPD_NONE (0) +#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLUP (1) +#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLDOWN (2) +#define CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd) ((__pupd) << ((__pin)<<1)) +#define CYGHWR_HAL_STM32_GPIO_PUPD_SET(__pin, __pupd, __reg) ((__reg) &= ~MASK_(((__pin)<<1),2), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd)) + +// GPIO port input data register. +#define CYGHWR_HAL_STM32_GPIO_IDR_GET(__portbaseaddr, __pin, __val) \ + ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_IDR) >> (__pin)) & 1) + +// GPIO port output data register. +// Don't encourage setting it here. Use GPIO_BSRR instead for that. +#define CYGHWR_HAL_STM32_GPIO_ODR_GET(__portbaseaddr, __pin, __val) \ + ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_ODR) >> (__pin)) & 1) + +// GPIO port bit set/reset register. +#define CYGHWR_HAL_STM32_GPIO_BSRR_SET(__portbaseaddr, __pin, __val) \ + ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_BSRR) = (__val)?(1<<(__pin)):(1<<((__pin)+16))) + +// GPIO port configuration lock register. +#define CYGHWR_HAL_STM32_GPIO_LCKR_LCKK BIT_(16) +#define CYGHWR_HAL_STM32_GPIO_LCKR_LCK(__pin) BIT_((__pin)) + +// GPIO alternate function low register. +#define CYGHWR_HAL_STM32_GPIO_AFRL0 MASK_(0,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL1 MASK_(4,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL2 MASK_(8,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL3 MASK_(12,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL4 MASK_(16,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL5 MASK_(20,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL6 MASK_(24,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL7 MASK_(28,4) +// GPIO alternate function high register. +#define CYGHWR_HAL_STM32_GPIO_AFRH8 MASK_(0,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH9 MASK_(4,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH10 MASK_(8,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH11 MASK_(12,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH12 MASK_(16,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH13 MASK_(20,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH14 MASK_(24,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH15 MASK_(28,4) + +// Set alternate function. We try to keep this as a macro as most times the +// arguments will be constant so can easily be collapsed substantially by the +// compiler. +// Note, this is not interrupt-safe, unavoidably. Provide your own protection +// if that's needed, although in general this will happen at startup time. +#define CYGHWR_HAL_STM32_GPIO_AFR_SET(__portbaseaddr, __pin, __func) \ + CYG_MACRO_START \ + cyg_uint32 __cur_afr, __mask; \ + volatile cyg_uint32 *__reg; \ + cyg_uint8 __reg_pin = (__pin); \ + if (__pin < 8) { \ + __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRL); \ + } else { \ + __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRH); \ + __reg_pin -= 8; \ + } \ + HAL_READ_UINT32( __reg, __cur_afr ); \ + __mask = 0xf << (__reg_pin<<2); \ + __cur_afr &= ~__mask; \ + __mask = (__func) << (__reg_pin<<2); \ + __cur_afr |= __mask; \ + HAL_WRITE_UINT32( __reg, __cur_afr ); \ + CYG_MACRO_END + + +// This macro packs the port number, bit number, mode and +// configuration for a GPIO pin into a single word. The packing puts +// the GPIO bank at bits 16:19, the pin at bits 12:15, the mode (i.e. function) +// at bits 10:11, for ALTFN mode the specific mapping at bits 6:9, pushpull(0) +// or open drain(1) at bit 5, pull-up(1) pull-down (2) or neither(0) at +// bits 3:4, and speed at bits 0:2 (low, med, fast, high). +// To keep definitions short, we simplify most of the arguments so they +// can be passed in with only their last components. + +// FIXME: This should be renamed to something like CYGHWR_HAL_STM32_PIN(... when +// bringing F1 into line with this way of declaring pins. + +#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __af, __ppod, __pupd, __speed) \ + ( ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) << 6 ) | \ + (__bit << 12) | \ + (CYGHWR_HAL_STM32_GPIO_MODE_##__mode << 10) | \ + (__af << 6) | \ + (CYGHWR_HAL_STM32_GPIO_OTYPE_##__ppod << 5) | \ + (CYGHWR_HAL_STM32_GPIO_PUPD_##__pupd << 3) | \ + (CYGHWR_HAL_STM32_GPIO_OSPEED_##__speed) ) + +// Macros to extract encoded values +#define CYGHWR_HAL_STM32_GPIO_PORT(__pin) (CYGHWR_HAL_STM32_GPIOA+(((__pin)&0xF0000)>>6)) +#define CYGHWR_HAL_STM32_GPIO_BIT(__pin) (((__pin)>>12)&0xF) +#define CYGHWR_HAL_STM32_GPIO_MODE(__pin) (((__pin)>>10)&0x3) +#define CYGHWR_HAL_STM32_GPIO_AF(__pin) (((__pin)>>6)&0xF) +#define CYGHWR_HAL_STM32_GPIO_OPENDRAIN(__pin) (((__pin)>>5)&0x1) +#define CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(__pin) (((__pin)>>3)&0x3) +#define CYGHWR_HAL_STM32_GPIO_SPEED(__pin) ((__pin)&0x7) + +#endif //if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +//============================================================================= + +#define CYGHWR_HAL_STM32_GPIO_NONE (0xFFFFFFFF) + +// Functions and macros to configure GPIO ports. + +__externC void hal_stm32_gpio_set( cyg_uint32 pin ); +__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val ); +__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val ); + +#define CYGHWR_HAL_STM32_GPIO_SET(__pin ) hal_stm32_gpio_set( __pin ) +#define CYGHWR_HAL_STM32_GPIO_OUT(__pin, __val ) hal_stm32_gpio_out( __pin, __val ) +#define CYGHWR_HAL_STM32_GPIO_IN(__pin, __val ) hal_stm32_gpio_in( __pin, __val ) + +//----------------------------------------------------------------------------- + +// For the following pin definition macros where __speed is a parameter the +// actual rates available depend on the target family. The generic LOW, MED, +// FAST and HIGH manifests can be used instead of explicit values, or more +// usefully the AT_LEAST(__mhz) and AT_MOST(__mhz) macros can be used to specify +// an acceptable limit instead. + +// The CYGHWR_HAL_STM32_PIN_OUT() macro defines a GPIO output pin. The __ppod +// parameter can be one of PUSHPULL or OPENDRAIN. The __pupd parameter can be +// one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is +// not-relevant and is ignored. +// e.g. +// CYGHWR_HAL_STM32_PIN_OUT(B,8,OPENDRAIN,NONE,FAST); +// CYGHWR_HAL_STM32_PIN_OUT(B,9,OPENDRAIN,NONE.AT_LEAST(50)); + +// The CYGHWR_HAL_STM32_PIN_ALTFN_OUT() macro defines an alternative function +// output pin. For F1 family devices the __af field is not-relevant and is +// ignored. The __ppod should be PUSHPULL or OPENDRAIN. The __pupd parameter can +// be one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is +// not-relevant and is ignored. +// e.g. +// CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,6,4,OPENDRAIN,NONE,MED); +// CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,10,4,OPENDRAIN,NONE,AT_LEAST(10)); + +// The CYGHWR_HAL_STM32_PIN_IN() macro is used to define GPIO input pins. The +// __pupd should be one of NONE. FLOATING, PULLUP or PULLDOWN. +// e.g. +// CYGHWR_HAL_STM32_PIN_IN(B,4,PULLUP); + +// The CYGHWR_HAL_STM32_PIN_ALTFN_IN() macro is used to define alternate +// function input pins. The __ppod parameter can be one of PUSHPULL, +// OPENDRAIN or NA. The __pupd should be one of NONE. FLOATING, PULLUP or +// PULLDOWN. For F1 family devices the __af and _ppod fields are not relevant +// and are ignored, and in reality this macro peforms the same function as +// CYGHWR_HAL_STM32_PIN_IN() for F1 family devices since extra AFIO +// configuration is needed. +// e.g. +// CYGHWR_HAL_STM32_PIN_ALTFN_IN(B,4,6,OPENDRAIN,PULLUP); + +// The CYGHWR_HAL_STM32_PIN_ANALOG() macro defines an analog mode pin. For F1 +// family devices this is for input only, e.g. ADC. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_GPIO_CNF_NONE (CYGHWR_HAL_STM32_GPIO_CNF_FLOATING) // Should not be needed for F1 family but ensure HIPERFORMANCE compatible name NONE exists + +#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,OUT_##__ppod) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,ALT_##__ppod) + +#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd) // NOTE: Identical to CYGHWR_HAL_STM32_PIN_IN() at the moment + +#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,ANALOG) + +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_GPIO_PUPD_FLOATING (CYGHWR_HAL_STM32_GPIO_PUPD_NONE) // Should not be needed for HIPERFORMANCE family but ensure F1 compatible name FLOATING exists + +#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_OUT,0,__ppod,__pupd,__speed) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,__speed) + +#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_IN,0,NA,__pupd,NA) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,NA) + +#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,ANALOG,0,NA,NONE,NA) + +#else +#error "Unknown STM32 family for GPIO PIN macros" +#endif + +//----------------------------------------------------------------------------- +// end of var_io_pins.h +#endif // CYGONCE_HAL_VAR_IO_PINS_H diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h new file mode 100644 index 0000000..2f00053 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h @@ -0,0 +1,264 @@ +#ifndef CYGONCE_HAL_VAR_IO_USART_H +#define CYGONCE_HAL_VAR_IO_USART_H +//============================================================================= +// +// var_io_usart.h +// +// USART-specific variant definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jlarmour +// Date: 2008-07-30 +// Purpose: STM32 variant USART specific registers +// Description: +// Usage: Do not include this header file directly. Instead: +// #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_VAR_IO_H +# error Do not include var_io_usart.h directly, use var_io.h +#endif + +//============================================================================= +// UARTs + +#define CYGHWR_HAL_STM32_UART_SR 0x00 +#define CYGHWR_HAL_STM32_UART_DR 0x04 +#define CYGHWR_HAL_STM32_UART_BRR 0x08 +#define CYGHWR_HAL_STM32_UART_CR1 0x0C +#define CYGHWR_HAL_STM32_UART_CR2 0x10 +#define CYGHWR_HAL_STM32_UART_CR3 0x14 +#define CYGHWR_HAL_STM32_UART_GTPR 0x18 + +// SR Bits + +#define CYGHWR_HAL_STM32_UART_SR_PE BIT_(0) +#define CYGHWR_HAL_STM32_UART_SR_FE BIT_(1) +#define CYGHWR_HAL_STM32_UART_SR_NE BIT_(2) +#define CYGHWR_HAL_STM32_UART_SR_NF BIT_(2) +#define CYGHWR_HAL_STM32_UART_SR_ORE BIT_(3) +#define CYGHWR_HAL_STM32_UART_SR_IDLE BIT_(4) +#define CYGHWR_HAL_STM32_UART_SR_RXNE BIT_(5) +#define CYGHWR_HAL_STM32_UART_SR_TC BIT_(6) +#define CYGHWR_HAL_STM32_UART_SR_TXE BIT_(7) +#define CYGHWR_HAL_STM32_UART_SR_LBD BIT_(8) +#define CYGHWR_HAL_STM32_UART_SR_CTS BIT_(9) + +// BRR bits + +#define CYGHWR_HAL_STM32_UART_BRR_DIVF(__f) VALUE_(0,__f) +#define CYGHWR_HAL_STM32_UART_BRR_DIVM(__m) VALUE_(4,__m) + +// CR1 bits + +#define CYGHWR_HAL_STM32_UART_CR1_SBK BIT_(0) +#define CYGHWR_HAL_STM32_UART_CR1_RWU BIT_(1) +#define CYGHWR_HAL_STM32_UART_CR1_RE BIT_(2) +#define CYGHWR_HAL_STM32_UART_CR1_TE BIT_(3) +#define CYGHWR_HAL_STM32_UART_CR1_IDLEIE BIT_(4) +#define CYGHWR_HAL_STM32_UART_CR1_RXNEIE BIT_(5) +#define CYGHWR_HAL_STM32_UART_CR1_TCIE BIT_(6) +#define CYGHWR_HAL_STM32_UART_CR1_TXEIE BIT_(7) +#define CYGHWR_HAL_STM32_UART_CR1_PEIE BIT_(8) +#define CYGHWR_HAL_STM32_UART_CR1_PS_EVEN 0 +#define CYGHWR_HAL_STM32_UART_CR1_PS_ODD BIT_(9) +#define CYGHWR_HAL_STM32_UART_CR1_PCE BIT_(10) +#define CYGHWR_HAL_STM32_UART_CR1_WAKE BIT_(11) +#define CYGHWR_HAL_STM32_UART_CR1_M_8 0 +#define CYGHWR_HAL_STM32_UART_CR1_M_9 BIT_(12) +#define CYGHWR_HAL_STM32_UART_CR1_UE BIT_(13) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_UART_CR1_OVER8 BIT_(15) +#endif + +// CR2 bits + +#define CYGHWR_HAL_STM32_UART_CR2_ADD(__a) VALUE_(0,__a) +#define CYGHWR_HAL_STM32_UART_CR2_LBDL BIT_(5) +#define CYGHWR_HAL_STM32_UART_CR2_LBDIE BIT_(6) +#define CYGHWR_HAL_STM32_UART_CR2_LBCL BIT_(8) +#define CYGHWR_HAL_STM32_UART_CR2_CPHA BIT_(9) +#define CYGHWR_HAL_STM32_UART_CR2_CPOL BIT_(10) +#define CYGHWR_HAL_STM32_UART_CR2_CLKEN BIT_(11) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_1 VALUE_(12,0) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_0_5 VALUE_(12,1) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_2 VALUE_(12,2) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_1_5 VALUE_(12,3) +#define CYGHWR_HAL_STM32_UART_CR2_LINEN BIT_(14) + +// CR3 bits + +#define CYGHWR_HAL_STM32_UART_CR3_EIE BIT_(0) +#define CYGHWR_HAL_STM32_UART_CR3_IREN BIT_(1) +#define CYGHWR_HAL_STM32_UART_CR3_IRLP BIT_(2) +#define CYGHWR_HAL_STM32_UART_CR3_HDSEL BIT_(3) +#define CYGHWR_HAL_STM32_UART_CR3_NACK BIT_(4) +#define CYGHWR_HAL_STM32_UART_CR3_SCEN BIT_(5) +#define CYGHWR_HAL_STM32_UART_CR3_DMAR BIT_(6) +#define CYGHWR_HAL_STM32_UART_CR3_DMAT BIT_(7) +#define CYGHWR_HAL_STM32_UART_CR3_RTSE BIT_(8) +#define CYGHWR_HAL_STM32_UART_CR3_CTSE BIT_(9) +#define CYGHWR_HAL_STM32_UART_CR3_CTSIE BIT_(10) + +// GTPR fields + +#define CYGHWR_HAL_STM32_UART_GTPR_PSC(__p) VALUE_(0,__p) +#define CYGHWR_HAL_STM32_UART_GTPR_GT(__g) VALUE_(8,__g) + +// UART GPIO pins + +// NOTE: For those UARTS providing a RTS pin the driver uses HW CTS control but +// manually controls the RTS as a GPIO. + +#ifndef CYGHWR_HAL_STM32_UART0_REMAP +#define CYGHWR_HAL_STM32_UART1_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 10, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART1_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 9, 7, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#else // CYGHWR_HAL_STM32_UART0_REMAP +#define CYGHWR_HAL_STM32_UART1_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 7, 7, NA , FLOATING ) +#define CYGHWR_HAL_STM32_UART1_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 6, 7, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#endif // else CYGHWR_HAL_STM32_UART0_REMAP + +#define CYGHWR_HAL_STM32_UART1_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART1_RTS CYGHWR_HAL_STM32_PIN_OUT( A, 12, PUSHPULL, NONE, 50MHZ ) + +#define CYGHWR_HAL_STM32_UART1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, UART1 ) + +#ifndef CYGHWR_HAL_STM32_UART1_REMAP +#define CYGHWR_HAL_STM32_UART2_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 3, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 2, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART2_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 0, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_RTS CYGHWR_HAL_STM32_PIN_OUT( A, 1, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#else +#define CYGHWR_HAL_STM32_UART2_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 6, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D, 5, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART2_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 3, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_RTS CYGHWR_HAL_STM32_PIN_OUT( D, 4, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#endif + +#define CYGHWR_HAL_STM32_UART2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART2 ) + +#if defined(CYGHWR_HAL_STM32_UART2_REMAP_PARTIAL) + +#define CYGHWR_HAL_STM32_UART3_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART3_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 13, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_RTS CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#elif defined(CYGHWR_HAL_STM32_UART2_REMAP_FULL) + +#define CYGHWR_HAL_STM32_UART3_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 9, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D, 8, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART3_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_RTS CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, 50MHZ ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#else + +#define CYGHWR_HAL_STM32_UART3_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART3_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 13, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_RTS CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#endif + +#define CYGHWR_HAL_STM32_UART3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART3 ) + +#define CYGHWR_HAL_STM32_UART4_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, 8, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART4_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART4_CTS CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_UART4_RTS CYGHWR_HAL_STM32_GPIO_NONE +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#define CYGHWR_HAL_STM32_UART4_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART4 ) + +#define CYGHWR_HAL_STM32_UART5_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 2, 8, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART5_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART5_CTS CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_UART5_RTS CYGHWR_HAL_STM32_GPIO_NONE +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#define CYGHWR_HAL_STM32_UART5_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART5 ) + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_UART6_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 7, 8, NA, NONE ) +#define CYGHWR_HAL_STM32_UART6_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 6, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART6_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( G, 15, 8, NA, NONE ) +#define CYGHWR_HAL_STM32_UART6_RTS CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 8, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART6_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, UART6 ) + +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +#ifndef __ASSEMBLER__ + +__externC void hal_stm32_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud ); + +#endif + +#endif // CYGONCE_HAL_VAR_IO_USART_H +//----------------------------------------------------------------------------- +// end of var_io_usart.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc b/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc new file mode 100644 index 0000000..4c72d2e --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc @@ -0,0 +1,54 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_stm32.h> + +//========================================================================== +// EOF variant.inc + |