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-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h21
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi36
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h15
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi37
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h21
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi36
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h24
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi38
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h21
-rw-r--r--ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi36
10 files changed, 285 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h
new file mode 100644
index 0000000..cb67af0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi
new file mode 100644
index 0000000..a1e5775
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ sram : ORIGIN = 0x20000000, LENGTH = 0x00010000
+ flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+ rom : ORIGIN = 0x64000000, LENGTH = 0x01000000
+ ram : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, 0x68008000+CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM, LMA_EQ_VMA)
+ SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x68100000;
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h
new file mode 100644
index 0000000..62aa297
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h
@@ -0,0 +1,15 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi
new file mode 100644
index 0000000..d72db27
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi
@@ -0,0 +1,37 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+ rom : ORIGIN = 0x64000000, LENGTH = 0x01000000
+ ram : ORIGIN = 0x68000000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, 0x68000000, LMA_EQ_VMA)
+ SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h
new file mode 100644
index 0000000..cb67af0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi
new file mode 100644
index 0000000..11b1ab9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ sram : ORIGIN = 0x20000000, LENGTH = 0x00010000
+ flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+ rom : ORIGIN = 0x64000000, LENGTH = 0x01000000
+ ram : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, 0x68008000, LMA_EQ_VMA)
+ SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x68100000;
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h
new file mode 100644
index 0000000..93f4f59
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h
@@ -0,0 +1,24 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00080000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x64000000)
+#define CYGMEM_REGION_rom_SIZE (0x01000000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi
new file mode 100644
index 0000000..0a17ecc
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi
@@ -0,0 +1,38 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+ rom : ORIGIN = 0x64000000, LENGTH = 0x01000000
+ ram : ORIGIN = 0x68000000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+ SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
+ SECTION_data (ram, 0x68000000, FOLLOWING (.sram))
+ SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h
new file mode 100644
index 0000000..1ed517d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi
new file mode 100644
index 0000000..c533b38
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+ rom : ORIGIN = 0x64000000, LENGTH = 0x01000000
+ ram : ORIGIN = 0x68000000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (sram, 0x20000400, LMA_EQ_VMA)
+ SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA)
+ SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20010000;