diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2018-08-21 11:31:39 +0800 |
|---|---|---|
| committer | Haibo Chen <haibo.chen@nxp.com> | 2018-08-21 14:41:33 +0800 |
| commit | ece4a31cdcce239cd35a49929935a8c20312b1aa (patch) | |
| tree | 3796624d59c9a7aa0b9f011e1e473c5f8268802a /board | |
| parent | b918c85c45f81e4759ed45a0ff40ec9642130388 (diff) | |
MLK-19223 arm: imx8mm: add MXC_XXX_CLK clock map for imx common code
Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.
e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT
This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
Conflicts:
arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/imx8mm_evk/spl.c | 4 | ||||
| -rw-r--r-- | board/freescale/imx8mm_val/spl.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index d52a2e0850..fd4726e86c 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -103,7 +103,7 @@ int board_mmc_init(bd_t *bis) for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); @@ -112,7 +112,7 @@ int board_mmc_init(bd_t *bis) gpio_direction_output(USDHC2_PWR_GPIO, 1); break; case 1: - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC3_CLK_ROOT); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); break; diff --git a/board/freescale/imx8mm_val/spl.c b/board/freescale/imx8mm_val/spl.c index 7ab32109ab..c419ea1670 100644 --- a/board/freescale/imx8mm_val/spl.c +++ b/board/freescale/imx8mm_val/spl.c @@ -103,7 +103,7 @@ int board_mmc_init(bd_t *bis) for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); @@ -112,7 +112,7 @@ int board_mmc_init(bd_t *bis) gpio_direction_output(USDHC2_PWR_GPIO, 1); break; case 1: - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC3_CLK_ROOT); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); break; |