diff options
| author | Dipen Dudhat <dipen.dudhat@freescale.com> | 2010-03-18 17:38:07 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:25 -0500 |
| commit | 3d0bc92072df6641d9491858653c2d864421d202 (patch) | |
| tree | 6fc3df5b435a3a1ef186fb64bb6129da3a2b11f0 | |
| parent | 86393b1b88199d55eb1ab739d05ab744750cdb67 (diff) | |
fix wrong clock mask for eSDHC Driver
This patch is derived from P2020DS BSP Release.
Signed-off-by: Jin Qing <B24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
| -rw-r--r-- | include/fsl_esdhc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 72ad84de1d..a061bcdfd5 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 |