diff options
123 files changed, 7281 insertions, 2689 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 624bd80f..0a1cb304 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +23,7 @@ void bl1_arch_setup(void) ******************************************************************************/ void bl1_arch_next_el_setup(void) { - unsigned long next_sctlr; + u_register_t next_sctlr; /* Use the same endianness than the current BL */ next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index d222b9c5..48f08d2c 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -483,7 +483,7 @@ static int bl1_fwu_image_auth(unsigned int image_id, * Flush image_info to memory so that other * secure world images can see changes. */ - flush_dcache_range((unsigned long)&image_desc->image_info, + flush_dcache_range((uintptr_t)&image_desc->image_info, sizeof(image_info_t)); INFO("BL1-FWU: Authentication was successful\n"); diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index df01dbae..2bb85114 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -49,7 +49,7 @@ void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, bl2_mem_layout->total_base = bl1_mem_layout->total_base; bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; - flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); + flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); } /******************************************************************************* diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index 8843404d..99d0eee9 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -29,6 +29,33 @@ static int append_psci_compatible(void *fdt, int offs, const char *str) return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); } +/* + * Those defines are for PSCI v0.1 legacy clients, which we expect to use + * the same execution state (AArch32/AArch64) as TF-A. + * Kernels running in AArch32 on an AArch64 TF-A should use PSCI v0.2. + */ +#ifdef __aarch64__ +#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH64 +#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH64 +#else +#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH32 +#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH32 +#endif + +/******************************************************************************* + * dt_add_psci_node() - Add a PSCI node into an existing device tree + * @fdt: pointer to the device tree blob in memory + * + * Add a device tree node describing PSCI into the root level of an existing + * device tree blob in memory. + * This will add v0.1, v0.2 and v1.0 compatible strings and the standard + * function IDs for v0.1 compatibility. + * An existing PSCI node will not be touched, the function will return success + * in this case. This function will not touch the /cpus enable methods, use + * dt_add_psci_cpu_enable_methods() for that. + * + * Return: 0 on success, -1 otherwise. + ******************************************************************************/ int dt_add_psci_node(void *fdt) { int offs; @@ -52,15 +79,11 @@ int dt_add_psci_node(void *fdt) return -1; if (fdt_setprop_string(fdt, offs, "method", "smc")) return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_AARCH64)) + if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_FNID)) return -1; if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF)) return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_AARCH64)) - return -1; - if (fdt_setprop_u32(fdt, offs, "sys_poweroff", PSCI_SYSTEM_OFF)) - return -1; - if (fdt_setprop_u32(fdt, offs, "sys_reset", PSCI_SYSTEM_RESET)) + if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_FNID)) return -1; return 0; } @@ -113,6 +136,17 @@ static int dt_update_one_cpu_node(void *fdt, int offset) return offs; } +/******************************************************************************* + * dt_add_psci_cpu_enable_methods() - switch CPU nodes in DT to use PSCI + * @fdt: pointer to the device tree blob in memory + * + * Iterate over all CPU device tree nodes (/cpus/cpu@x) in memory to change + * the enable-method to PSCI. This will add the enable-method properties, if + * required, or will change existing properties to read "psci". + * + * Return: 0 on success, or a negative error value otherwise. + ******************************************************************************/ + int dt_add_psci_cpu_enable_methods(void *fdt) { int offs, ret; @@ -130,6 +164,25 @@ int dt_add_psci_cpu_enable_methods(void *fdt) #define HIGH_BITS(x) ((sizeof(x) > 4) ? ((x) >> 32) : (typeof(x))0) +/******************************************************************************* + * fdt_add_reserved_memory() - reserve (secure) memory regions in DT + * @dtb: pointer to the device tree blob in memory + * @node_name: name of the subnode to be used + * @base: physical base address of the reserved region + * @size: size of the reserved region + * + * Add a region of memory to the /reserved-memory node in a device tree in + * memory, creating that node if required. Each region goes into a subnode + * of that node and has a @node_name, a @base address and a @size. + * This will prevent any device tree consumer from using that memory. It + * can be used to announce secure memory regions, as it adds the "no-map" + * property to prevent mapping and speculative operations on that region. + * + * See reserved-memory/reserved-memory.txt in the (Linux kernel) DT binding + * documentation for details. + * + * Return: 0 on success, a negative error value otherwise. + ******************************************************************************/ int fdt_add_reserved_memory(void *dtb, const char *node_name, uintptr_t base, size_t size) { diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 5786dd38..9eb7c17e 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -546,6 +546,13 @@ optionally be defined: PLAT_PARTITION_MAX_ENTRIES := 12 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) +- **PLAT_PARTITION_BLOCK_SIZE** + The size of partition block. It could be either 512 bytes or 4096 bytes. + The default value is 512. + `For example, define the build flag in platform.mk`_: + PLAT_PARTITION_BLOCK_SIZE := 4096 + $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) + The following constant is optional. It should be defined to override the default behaviour of the ``assert()`` function (for example, to save memory). @@ -2202,6 +2209,19 @@ immediately before the CPU was turned on. It indicates which power domains above the CPU might require initialization due to having previously been in low power states. The generic code expects the handler to succeed. +plat_psci_ops.pwr_domain_on_finish_late() [optional] +........................................................... + +This optional function is called by the PSCI implementation after the calling +CPU is fully powered on with respective data caches enabled. The calling CPU and +the associated cluster are guaranteed to be participating in coherency. This +function gives the flexibility to perform any platform-specific actions safely, +such as initialization or modification of shared data structures, without the +overhead of explicit cache maintainace operations. + +The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` +operation. The generic code expects the handler to succeed. + plat_psci_ops.pwr_domain_suspend_finish() ......................................... diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 59514137..eaeee84f 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -12,6 +12,7 @@ Platform Ports imx8m intel-stratix10 ls1043a + marvell/index meson-gxbb meson-gxl mt8183 diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst new file mode 100644 index 00000000..c8923e43 --- /dev/null +++ b/docs/plat/marvell/build.rst @@ -0,0 +1,254 @@ +TF-A Build Instructions for Marvell Platforms +============================================= + +This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms. + +Build Instructions +------------------ +(1) Set the cross compiler + + .. code:: shell + + > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- + +(2) Set path for FIP images: + +Set U-Boot image path (relatively to TF-A root or absolute path) + + .. code:: shell + + > export BL33=path/to/u-boot.bin + +For example: if U-Boot project (and its images) is located at ``~/project/u-boot``, +BL33 should be ``~/project/u-boot/u-boot.bin`` + + .. note:: + + *u-boot.bin* should be used and not *u-boot-spl.bin* + +Set MSS/SCP image path (mandatory only for Armada80x0) + + .. code:: shell + + > export SCP_BL2=path/to/mrvl_scp_bl2*.img + +(3) Armada-37x0 build requires WTP tools installation. + +See below in the section "Tools and external components installation". +Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3 + + .. code:: shell + + > sudo apt-get install gcc-arm-linux-gnueabi + +(4) Clean previous build residuals (if any) + + .. code:: shell + + > make distclean + +(5) Build TF-A + +There are several build options: + +- DEBUG + + Default is without debug information (=0). in order to enable it use ``DEBUG=1``. + Must be disabled when building UART recovery images due to current console driver + implementation that is not compatible with Xmodem protocol used for boot image download. + +- LOG_LEVEL + + Defines the level of logging which will be purged to the default output port. + + LOG_LEVEL_NONE 0 + LOG_LEVEL_ERROR 10 + LOG_LEVEL_NOTICE 20 + LOG_LEVEL_WARNING 30 + LOG_LEVEL_INFO 40 + LOG_LEVEL_VERBOSE 50 + +- USE_COHERENT_MEM + + This flag determines whether to include the coherent memory region in the + BL memory map or not. + +- LLC_ENABLE + + Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). + +- MARVELL_SECURE_BOOT + + Build trusted(=1)/non trusted(=0) image, default is non trusted. + +- BLE_PATH + + Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. + The parameter is optional, its default value is ``plat/marvell/a8k/common/ble``. + +- MV_DDR_PATH + + For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, + it is used for ddr_tool build. + + Usage example: MV_DDR_PATH=path/to/mv_ddr + + The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr + sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter + is necessary for A37x0. + + For the mv_ddr source location, check the section "Tools and external components installation" + +- DDR_TOPOLOGY + + For Armada37x0 only, the DDR topology map index/name, default is 0. + + Supported Options: + - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) + - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) + - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) + - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) + - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) + - DDR4 1CS (5): EspressoBin V7 (1GB) + - DDR4 2CS (6): EspressoBin V7 (2GB) + - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB + +- CLOCKSPRESET + + For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, + default is CPU_800_DDR_800. + + - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz + - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz + - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz + - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz + +- BOOTDEV + + For Armada37x0 only, the flash boot device, default is ``SPINOR``. + + Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``: + + - SPINOR - SPI NOR flash boot + - SPINAND - SPI NAND flash boot + - EMMCNORM - eMMC Download Mode + + Download boot loader or program code from eMMC flash into CM3 or CA53 + Requires full initialization and command sequence + + - SATA - SATA device boot + +- PARTNUM + + For Armada37x0 only, the boot partition number, default is 0. + + To boot from eMMC, the value should be aligned with the parameter in + U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is + 1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot + build instructions. + +- WTMI_IMG + + For Armada37x0 only, the path of the WTMI image can point to an image which + does nothing, an image which supports EFUSE or a customized CM3 firmware + binary. The default image is wtmi.bin that built from sources in WTP + folder, which is the next option. If the default image is OK, then this + option should be skipped. + +- WTP + + For Armada37x0 only, use this parameter to point to wtptools source code + directory, which can be found as a3700_utils.zip in the release. Usage + example: ``WTP=/path/to/a3700_utils`` + + For example, in order to build the image in debug mode with log level up to 'notice' level run + + .. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip + + And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, + the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, + the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command + line is as following + + .. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ + MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip + + Supported MARVELL_PLATFORM are: + - a3700 (for both A3720 DB and EspressoBin) + - a70x0 + - a70x0_amc (for AMC board) + - a80x0 + - a80x0_mcbin (for MacciatoBin) + +Special Build Flags +-------------------- + +- PLAT_RECOVERY_IMAGE_ENABLE + When set this option to enable secondary recovery function when build atf. + In order to build UART recovery image this operation should be disabled for + a70x0 and a80x0 because of hardware limitation (boot from secondary image + can interrupt UART recovery process). This MACRO definition is set in + ``plat/marvell/a8k/common/include/platform_def.h`` file. + +For more information about build options, please refer to section +'Summary of build options' in the :ref:`User Guide`. + + +Build output +------------ +Marvell's TF-A compilation generates 7 files: + + - ble.bin - BLe image + - bl1.bin - BL1 image + - bl2.bin - BL2 image + - bl31.bin - BL31 image + - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) + - boot-image.bin - TF-A image (contains BL1 and FIP images) + - flash-image.bin - Image which contains boot-image.bin and SPL image. + Should be placed on the boot flash/device. + + +Tools and external components installation +------------------------------------------ + +Armada37x0 Builds require installation of 3 components +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) ARM cross compiler capable of building images for the service CPU (CM3). + This component is usually included in the Linux host packages. + On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed + using the following command + + .. code:: shell + + > sudo apt-get install gcc-arm-linux-gnueabi + + Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be + overwritten using the environment variable ``CROSS_CM3``. + Example for BASH shell + + .. code:: shell + + > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi + +(2) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch): + + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + +(3) Armada3700 tools available at the following repository (use the latest release branch): + + https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git + +Armada70x0 and Armada80x0 Builds require installation of an additional component +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch): + + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + diff --git a/docs/plat/marvell/build.txt b/docs/plat/marvell/build.txt deleted file mode 100644 index 7b75196f..00000000 --- a/docs/plat/marvell/build.txt +++ /dev/null @@ -1,194 +0,0 @@ -TF-A Build Instructions -====================== - -This section describes how to compile the ARM Trusted Firmware (TF-A) project for Marvell's platforms. - -Build Instructions ------------------- -(1) Set the cross compiler:: - - > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- - -(2) Set path for FIP images: - - Set U-Boot image path (relatively to TF-A root or absolute path):: - - > export BL33=path/to/u-boot.bin - - For example: if U-Boot project (and its images) is located at ~/project/u-boot, - BL33 should be ~/project/u-boot/u-boot.bin - - .. note:: - - u-boot.bin should be used and not u-boot-spl.bin - - Set MSS/SCP image path (mandatory only for Armada80x0):: - - > export SCP_BL2=path/to/mrvl_scp_bl2*.img - -(3) Armada-37x0 build requires WTP tools installation. - - See below in the section "Tools and external components installation". - Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3:: - - > sudo apt-get install gcc-arm-linux-gnueabi - -(4) Clean previous build residuals (if any):: - - > make distclean - -(5) Build TF-A: - - There are several build options: - - - DEBUG: default is without debug information (=0). in order to enable it use DEBUG=1 - Must be disabled when building UART recovery images due to current console driver - implementation that is not compatible with Xmodem protocol used for boot image download. - - - LOG_LEVEL: defines the level of logging which will be purged to the default output port. - - LOG_LEVEL_NONE 0 - LOG_LEVEL_ERROR 10 - LOG_LEVEL_NOTICE 20 - LOG_LEVEL_WARNING 30 - LOG_LEVEL_INFO 40 - LOG_LEVEL_VERBOSE 50 - - - USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the - BL memory map or not. - - - LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1). - - - MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted. - - - BLE_PATH: - Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. - The parameter is optional, its default value is "plat/marvell/a8k/common/ble". - - - MV_DDR_PATH: - For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, - it is used for ddr_tool build. - Usage example: MV_DDR_PATH=path/to/mv_ddr - The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr - sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter - is necessary for A37x0. - For the mv_ddr source location, check the section "Tools and external components installation" - - - DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0. - Supported Options: - - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) - - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) - - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) - - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) - - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) - - DDR4 1CS (5): EspressoBin V7 (1GB) - - DDR4 2CS (6): EspressoBin V7 (2GB) - - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB - - - CLOCKSPRESET: For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, - default is CPU_800_DDR_800. - - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz - - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz - - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz - - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz - - - BOOTDEV: For Armada37x0 only, the flash boot device, default is SPINOR, - Currently, Armada37x0 only supports SPINOR, SPINAND, EMMCNORM and SATA: - - - SPINOR - SPI NOR flash boot - - SPINAND - SPI NAND flash boot - - EMMCNORM - eMMC Download Mode - Download boot loader or program code from eMMC flash into CM3 or CA53 - Requires full initialization and command sequence - - SATA - SATA device boot - - - PARTNUM: For Armada37x0 only, the boot partition number, default is 0. To boot from eMMC, the value - should be aligned with the parameter in U-Boot with name of CONFIG_SYS_MMC_ENV_PART, whose - value by default is 1. - For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot build instructions. - - - WTMI_IMG: For Armada37x0 only, the path of the WTMI image can point to an image which does - nothing, an image which supports EFUSE or a customized CM3 firmware binary. The default image - is wtmi.bin that built from sources in WTP folder, which is the next option. If the default - image is OK, then this option should be skipped. - - - WTP: For Armada37x0 only, use this parameter to point to wtptools source code directory, which - can be found as a3700_utils.zip in the release. - Usage example: WTP=/path/to/a3700_utils - - For example, in order to build the image in debug mode with log level up to 'notice' level run:: - - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip - - And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, - the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, - the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command - line is as following:: - - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ - MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip - - Supported MARVELL_PLATFORM are: - - a3700 (for both A3720 DB and EspressoBin) - - a70x0 - - a70x0_amc (for AMC board) - - a80x0 - - a80x0_mcbin (for MacciatoBin) - -Special Build Flags --------------------- - - PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build - atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0 - because of hardware limitation (boot from secondary image can interrupt UART recovery process). - This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file - -(for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide: - https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/user-guide.md) - - -Build output -------------- -Marvell's TF-A compilation generates 7 files: - - ble.bin - BLe image - - bl1.bin - BL1 image - - bl2.bin - BL2 image - - bl31.bin - BL31 image - - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) - - boot-image.bin - TF-A image (contains BL1 and FIP images) - - flash-image.bin - Image which contains boot-image.bin and SPL image; - should be placed on the boot flash/device. - - -Tools and external components installation -========================================== - -Armada37x0 Builds require installation of 3 components -------------------------------------------------------- - -(1) ARM cross compiler capable of building images for the service CPU (CM3). - This component is usually included in the Linux host packages. - On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed - using the following command:: - - > sudo apt-get install gcc-arm-linux-gnueabi - - Only if required, the default tool chain prefix "arm-linux-gnueabi-" can be - overwritten using the environment variable CROSS_CM3. - Example for BASH shell:: - - > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi - -(2) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch):: - https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git - -(3) Armada3700 tools available at the following repository (use the latest release branch):: - https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git - -Armada70x0 and Armada80x0 Builds require installation of an additional component --------------------------------------------------------------------------------- - -(1) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch):: - https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git - diff --git a/docs/plat/marvell/index.rst b/docs/plat/marvell/index.rst new file mode 100644 index 00000000..89ebdc0a --- /dev/null +++ b/docs/plat/marvell/index.rst @@ -0,0 +1,14 @@ +Marvell +======= + +.. toctree:: + :maxdepth: 1 + :caption: Contents + + build + porting + misc/mvebu-a8k-addr-map + misc/mvebu-amb + misc/mvebu-ccu + misc/mvebu-io-win + misc/mvebu-iob diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst new file mode 100644 index 00000000..e88a4582 --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst @@ -0,0 +1,49 @@ +Address decoding flow and address translation units of Marvell Armada 8K SoC family +=================================================================================== + +:: + + +--------------------------------------------------------------------------------------------------+ + | +-------------+ +--------------+ | + | | Memory +----- DRAM CS | | + |+------------+ +-----------+ +-----------+ | Controller | +--------------+ | + || AP DMA | | | | | +-------------+ | + || SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | + || MCI-0/1 | | | | | | Memory | | + |+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | + | | | | | +----- Translaton | |AP | | + | | | | | | +-------------+ |Configuration| | + | | | +-----+ +-------------------------Space | | + | | | +-------------+ | CCU | +-------------+ | + | | | | MMU +---------+ Windows | +-----------+ +-------------+ | + | | +-| translation | | Lookup +---- +--------- AP SPI | | + | | +-------------+ | | | | +-------------+ | + | | +-------------+ | | | IO | +-------------+ | + | +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | + | | translation | +------------+ | Lookup | +-------------+ | + | +---------+---+ | | +-------------+ | + | - | | +--------- AP STM | | + | +----------------- | | +-------------+ | + | AP | | +-+---------+ | + +---------------------------------------------------------------|----------------------------------+ + +-------------|-------------------------------------------------|----------------------------------+ + | CP | +-------------+ +------+-----+ +-------------------+ | + | | | | | +------- SB CFG Space | | + | | | DIOB | | | +-------------------+ | + | | | Windows ----------------- IOB | +-------------------+ | + | | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | + | | | | | Lookup | +-------------------+ | + | | +------+------+ | | +-------------------+ | + | | | | +------+ SB NAND | | + | | | +------+-----+ +-------------------+ | + | | | | | + | | | | | + | +------------------+ +------------+ +------+-----+ +-------------------+ | + | | Network Engine | | | | +------- SB SPI-0/SPI-1 | | + | | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | + | | SATA, USB | | DMA | | Windows | +-------------------+ | + | | SD/eMMC | | | | Lookup +------- SB Device Bus | | + | | TDM, I2C | | | | | +-------------------+ | + | +------------------+ +------------+ +------------+ | + | | + +--------------------------------------------------------------------------------------------------+ diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt b/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt deleted file mode 100644 index 586e8b73..00000000 --- a/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt +++ /dev/null @@ -1,47 +0,0 @@ -Address decoding flow and address translation units of Marvell Armada 8K SoC family - -+--------------------------------------------------------------------------------------------------+ -| +-------------+ +--------------+ | -| | Memory +----- DRAM CS | | -|+------------+ +-----------+ +-----------+ | Controller | +--------------+ | -|| AP DMA | | | | | +-------------+ | -|| SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | -|| MCI-0/1 | | | | | | Memory | | -|+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | -| | | | | +----- Translaton | |AP | | -| | | | | | +-------------+ |Configuration| | -| | | +-----+ +-------------------------Space | | -| | | +-------------+ | CCU | +-------------+ | -| | | | MMU +---------+ Windows | +-----------+ +-------------+ | -| | +-| translation | | Lookup +---- +--------- AP SPI | | -| | +-------------+ | | | | +-------------+ | -| | +-------------+ | | | IO | +-------------+ | -| +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | -| | translation | +------------+ | Lookup | +-------------+ | -| +---------+---+ | | +-------------+ | -| - | | +--------- AP STM | | -| +----------------- | | +-------------+ | -| AP | | +-+---------+ | -+---------------------------------------------------------------|----------------------------------+ -+-------------|-------------------------------------------------|----------------------------------+ -| CP | +-------------+ +------+-----+ +-------------------+ | -| | | | | +------- SB CFG Space | | -| | | DIOB | | | +-------------------+ | -| | | Windows ----------------- IOB | +-------------------+ | -| | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | -| | | | | Lookup | +-------------------+ | -| | +------+------+ | | +-------------------+ | -| | | | +------+ SB NAND | | -| | | +------+-----+ +-------------------+ | -| | | | | -| | | | | -| +------------------+ +------------+ +------+-----+ +-------------------+ | -| | Network Engine | | | | +------- SB SPI-0/SPI-1 | | -| | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | -| | SATA, USB | | DMA | | Windows | +-------------------+ | -| | SD/eMMC | | | | Lookup +------- SB Device Bus | | -| | TDM, I2C | | | | | +-------------------+ | -| +------------------+ +------------+ +------------+ | -| | -+--------------------------------------------------------------------------------------------------+ - diff --git a/docs/plat/marvell/misc/mvebu-amb.rst b/docs/plat/marvell/misc/mvebu-amb.rst new file mode 100644 index 00000000..d734003d --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-amb.rst @@ -0,0 +1,58 @@ +AMB - AXI MBUS address decoding +=============================== + +AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. + +The Runit offers a second level of address windows lookup. It is used to map +transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR). + +The Runit contains eight configurable windows. Each window defines a contiguous, +address space and the properties associated with that address space. + +:: + + Unit Bank ATTR + Device-Bus DEV_BOOT_CS 0x2F + DEV_CS0 0x3E + DEV_CS1 0x3D + DEV_CS2 0x3B + DEV_CS3 0x37 + SPI-0 SPI_A_CS0 0x1E + SPI_A_CS1 0x5E + SPI_A_CS2 0x9E + SPI_A_CS3 0xDE + SPI_A_CS4 0x1F + SPI_A_CS5 0x5F + SPI_A_CS6 0x9F + SPI_A_CS7 0xDF + SPI SPI_B_CS0 0x1A + SPI_B_CS1 0x5A + SPI_B_CS2 0x9A + SPI_B_CS3 0xDA + BOOT_ROM BOOT_ROM 0x1D + UART UART 0x01 + +Mandatory functions +------------------- + +- marvell_get_amb_memory_map + Returns the AMB windows configuration and the number of windows + +Mandatory structures +-------------------- + +- amb_memory_map + Array that include the configuration of the windows. Every window/entry is a + struct which has 2 parameters: + + - Base address of the window + - Attribute of the window + +Examples +-------- + +.. code:: c + + struct addr_map_win amb_memory_map[] = { + {0xf900, AMB_DEV_CS0_ID}, + }; diff --git a/docs/plat/marvell/misc/mvebu-amb.txt b/docs/plat/marvell/misc/mvebu-amb.txt deleted file mode 100644 index 2a7a41ec..00000000 --- a/docs/plat/marvell/misc/mvebu-amb.txt +++ /dev/null @@ -1,45 +0,0 @@ -AMB - AXI MBUS address decoding -------------------------------- - -AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. - -- The Runit offers a second level of address windows lookup. It is used to map transaction towards -the CD BootROM, SPI0, SPI1 and Device bus (NOR). -- The Runit contains eight configurable windows. Each window defines a contiguous, -address space and the properties associated with that address space. - -Unit Bank ATTR -Device-Bus DEV_BOOT_CS 0x2F - DEV_CS0 0x3E - DEV_CS1 0x3D - DEV_CS2 0x3B - DEV_CS3 0x37 -SPI-0 SPI_A_CS0 0x1E - SPI_A_CS1 0x5E - SPI_A_CS2 0x9E - SPI_A_CS3 0xDE - SPI_A_CS4 0x1F - SPI_A_CS5 0x5F - SPI_A_CS6 0x9F - SPI_A_CS7 0xDF -SPI1 SPI_B_CS0 0x1A - SPI_B_CS1 0x5A - SPI_B_CS2 0x9A - SPI_B_CS3 0xDA -BOOT_ROM BOOT_ROM 0x1D -UART UART 0x01 - -Mandatory functions: - - marvell_get_amb_memory_map - returns the AMB windows configuration and the number of windows - -Mandatory structures: - amb_memory_map - Array that include the configuration of the windows - every window/entry is a struct which has 2 parameters: - - base address of the window - - Attribute of the window - -Examples: - struct addr_map_win amb_memory_map[] = { - {0xf900, AMB_DEV_CS0_ID}, - }; diff --git a/docs/plat/marvell/misc/mvebu-ccu.rst b/docs/plat/marvell/misc/mvebu-ccu.rst new file mode 100644 index 00000000..5bac11fa --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-ccu.rst @@ -0,0 +1,33 @@ +Marvell CCU address decoding bindings +===================================== + +CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The CCU node includes a description of the address decoding configuration. + +Mandatory functions +------------------- + +- marvell_get_ccu_memory_map + Return the CCU windows configuration and the number of windows of the + specific AP. + +Mandatory structures +-------------------- + +- ccu_memory_map + Array that includes the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Example +------- + +.. code:: c + + struct addr_map_win ccu_memory_map[] = { + {0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */ + }; diff --git a/docs/plat/marvell/misc/mvebu-ccu.txt b/docs/plat/marvell/misc/mvebu-ccu.txt deleted file mode 100644 index 97640276..00000000 --- a/docs/plat/marvell/misc/mvebu-ccu.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell CCU address decoding bindings -===================================== - -CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The CCU node includes a description of the address decoding configuration. - -Mandatory functions: - - marvell_get_ccu_memory_map - return the CCU windows configuration and the number of windows - of the specific AP. - -Mandatory structures: - ccu_memory_map - Array that includes the configuration of the windows - every window/entry is a struct which has 3 parameters: - - Base address of the window - - Size of the window - - Target-ID of the window - -Example: - struct addr_map_win ccu_memory_map[] = { - {0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */ - }; diff --git a/docs/plat/marvell/misc/mvebu-io-win.txt b/docs/plat/marvell/misc/mvebu-io-win.rst index c83ad1fd..52845ca0 100644 --- a/docs/plat/marvell/misc/mvebu-io-win.txt +++ b/docs/plat/marvell/misc/mvebu-io-win.rst @@ -1,5 +1,5 @@ Marvell IO WIN address decoding bindings -===================================== +======================================== IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. @@ -8,26 +8,37 @@ The IO WIN includes a description of the address decoding configuration. Transactions that are decoded by CCU windows as IO peripheral, have an additional layer of decoding. This additional address decoding layer defines one of the following targets: - 0x0 = BootRom - 0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream) - 0x2 = SPI direct access - 0x3 = PCIe registers - 0x4 = MCI Port - 0x5 = PCIe port - -Mandatory functions: - - marvell_get_io_win_memory_map - returns the IO windows configuration and the number of windows - of the specific AP. - -Mandatory structures: - io_win_memory_map - Array that include the configuration of the windows - every window/entry is a struct which has 3 parameters: + +- **0x0** = BootRom +- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream) +- **0x2** = SPI direct access +- **0x3** = PCIe registers +- **0x4** = MCI Port +- **0x5** = PCIe port + +Mandatory functions +------------------- + +- marvell_get_io_win_memory_map + Returns the IO windows configuration and the number of windows of the + specific AP. + +Mandatory structures +-------------------- + +- io_win_memory_map + Array that include the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + - Base address of the window - Size of the window - Target-ID of the window -Example: +Example +------- + +.. code:: c + struct addr_map_win io_win_memory_map[] = { {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ diff --git a/docs/plat/marvell/misc/mvebu-iob.txt b/docs/plat/marvell/misc/mvebu-iob.rst index 97ec09d0..d02a7e84 100644 --- a/docs/plat/marvell/misc/mvebu-iob.txt +++ b/docs/plat/marvell/misc/mvebu-iob.rst @@ -10,28 +10,40 @@ When a transaction passes through the IOB, its address is compared to each of the enabled windows. If there is a hit and it passes the security checks, it is advanced to the target port. -Mandatory functions: - - marvell_get_iob_memory_map - returns the IOB windows configuration and the number of windows - -Mandatory structures: - iob_memory_map - Array that include the configuration of the windows - every window/entry is a struct which has 3 parameters: - - Base address of the window - - Size of the window - - Target-ID of the window - -Target ID options: - - 0x0 = Internal configuration space - - 0x1 = MCI0 - - 0x2 = PEX1_X1 - - 0x3 = PEX2_X1 - - 0x4 = PEX0_X4 - - 0x5 = NAND flash - - 0x6 = RUNIT (NOR/SPI/BootRoom) - - 0x7 = MCI1 - -Example: +Mandatory functions +------------------- + +- marvell_get_iob_memory_map + Returns the IOB windows configuration and the number of windows + +Mandatory structures +-------------------- + +- iob_memory_map + Array that includes the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Target ID options +----------------- + +- **0x0** = Internal configuration space +- **0x1** = MCI0 +- **0x2** = PEX1_X1 +- **0x3** = PEX2_X1 +- **0x4** = PEX0_X4 +- **0x5** = NAND flash +- **0x6** = RUNIT (NOR/SPI/BootRoom) +- **0x7** = MCI1 + +Example +------- + +.. code:: c + struct addr_map_win iob_memory_map[] = { {0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */ {0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */ diff --git a/docs/plat/marvell/porting.rst b/docs/plat/marvell/porting.rst new file mode 100644 index 00000000..8fc1c1f6 --- /dev/null +++ b/docs/plat/marvell/porting.rst @@ -0,0 +1,163 @@ +TF-A Porting Guide for Marvell Platforms +======================================== + +This section describes how to port TF-A to a customer board, assuming that the +SoC being used is already supported in TF-A. + + +Source Code Structure +--------------------- + +- The customer platform specific code shall reside under ``plat/marvell/<soc family>/<soc>_cust`` + (e.g. 'plat/marvell/a8k/a7040_cust'). +- The platform name for build purposes is called ``<soc>_cust`` (e.g. ``a7040_cust``). +- The build system will reuse all files from within the soc directory, and take only the porting + files from the customer platform directory. + +Files that require porting are located at ``plat/marvell/<soc family>/<soc>_cust`` directory. + + +Armada-70x0/Armada-80x0 Porting +------------------------------- + +SoC Physical Address Map (marvell_plat_config.c) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This file describes the SoC physical memory mapping to be used for the CCU, +IOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for +more details). + +In most cases, using the default address decode windows should work OK. + +In cases where a special physical address map is needed (e.g. Special size for +PCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC +memory map is required. + +.. note:: + For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please + refer to the SoC functional spec, and under + ``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files. + +boot loader recovery (marvell_plat_config.c) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Background: + + Boot rom can skip the current image and choose to boot from next position if a + specific value (``0xDEADB002``) is returned by the ble main function. This + feature is used for boot loader recovery by booting from a valid flash-image + saved in next position on flash (e.g. address 2M in SPI flash). + + Supported options to implement the skip request are: + - GPIO + - I2C + - User defined + +- Porting: + + Under marvell_plat_config.c, implement struct skip_image that includes + specific board parameters. + + .. warning:: + To disable this feature make sure the struct skip_image is not implemented. + +- Example: + +In A7040-DB specific implementation +(``plat/marvell/a8k/a70x0/board/marvell_plat_config.c``), the image skip is +implemented using GPIO: mpp 33 (SW5). + +Before resetting the board make sure there is a valid image on the next flash +address: + + -tftp [valid address] flash-image.bin + -sf update [valid address] 0x2000000 [size] + +Press reset and keep pressing the button connected to the chosen GPIO pin. A +skip image request message is printed on the screen and boot rom boots from the +saved image at the next position. + +DDR Porting (dram_port.c) +~~~~~~~~~~~~~~~~~~~~~~~~~ + +This file defines the dram topology and parameters of the target board. + +The DDR code is part of the BLE component, which is an extension of ARM Trusted +Firmware (TF-A). + +The DDR driver called mv_ddr is released separately apart from TF-A sources. + +The BLE and consequently, the DDR init code is executed at the early stage of +the boot process. + +Each supported platform of the TF-A has its own DDR porting file called +dram_port.c located at ``atf/plat/marvell/a8k/<platform>/board`` directory. + +Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed +porting description. + +The build target directory is "build/<platform>/release/ble". + +Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Background: + Some of the comphy's parameters value depend on the HW connection between + the SoC and the PHY. Every board type has specific HW characteristics like + wire length. Due to those differences some comphy parameters vary between + board types. Therefore each board type can have its own list of values for + all relevant comphy parameters. The PHY porting layer specifies which + parameters need to be suited and the board designer should provide relevant + values. + + .. seealso:: + For XFI/SFI comphy type there is procedure "rx_training" which eases + process of suiting some of the parameters. Please see :ref:`uboot_cmd` + section: rx_training. + + The PHY porting layer simplifies updating static values per board type, + which are now grouped in one place. + + .. note:: + The parameters for the same type of comphy may vary even for the same + board type, it is because the lanes from comphy-x to some PHY may have + different HW characteristic than lanes from comphy-y to the same + (multiplexed) or other PHY. + +- Porting: + The porting layer for PHY was introduced in TF-A. There is one file + ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the + defaults. Those default parameters are used only if there is no appropriate + phy-porting-layer.h file under: ``plat/marvell/<soc + family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h + exists, the phy-default-porting-layer.h is not going to be included. + + .. warning:: + Not all comphy types are already reworked to support the PHY porting + layer, currently the porting layer is supported for XFI/SFI and SATA + comphy types. + + The easiest way to prepare the PHY porting layer for custom board is to copy + existing example to a new platform: + + - cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/<soc family>/<platform>/board/phy-porting-layer.h" + - adjust relevant parameters or + - if different comphy index is used for specific feature, move it to proper table entry and then adjust. + + .. note:: + The final table size with comphy parameters can be different, depending + on the CP module count for given SoC type. + +- Example: + Example porting layer for armada-8040-db is under: + ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` + + .. note:: + If there is no PHY porting layer for new platform (missing + phy-porting-layer.h), the default values are used + (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is + warned: + + .. warning:: + "Using default comphy parameters - it may be required to suit them for + your board". diff --git a/docs/plat/marvell/porting.txt b/docs/plat/marvell/porting.txt deleted file mode 100644 index f9a39a05..00000000 --- a/docs/plat/marvell/porting.txt +++ /dev/null @@ -1,118 +0,0 @@ -.. _porting: - -TF-A Porting Guide -================= - -This section describes how to port TF-A to a customer board, assuming that the SoC being used is already supported -in TF-A. - - -Source Code Structure ---------------------- -- The customer platform specific code shall reside under "plat/marvell/<soc family>/<soc>_cust" - (e.g. 'plat/marvell/a8k/a7040_cust'). -- The platform name for build purposes is called "<soc>_cust" (e.g. a7040_cust). -- The build system will reuse all files from within the soc directory, and take only the porting - files from the customer platform directory. - -Files that require porting are located at "plat/marvell/<soc family>/<soc>_cust" directory. - - -Armada-70x0/Armada-80x0 Porting -------------------------------- - - - SoC Physical Address Map (marvell_plat_config.c): - - This file describes the SoC physical memory mapping to be used for the CCU, IOWIN, AXI-MBUS and IOB - address decode units (Refer to the functional spec for more details). - - In most cases, using the default address decode windows should work OK. - - In cases where a special physical address map is needed (e.g. Special size for PCIe MEM windows, - large memory mapped SPI flash...), then porting of the SoC memory map is required. - - Note: For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please refer to the SoC functional spec, - and under "docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt" files. - - - boot loader recovery (marvell_plat_config.c): - - Background: - boot rom can skip the current image and choose to boot from next position if a specific value - (0xDEADB002) is returned by the ble main function. This feature is used for boot loader recovery - by booting from a valid flash-image saved in next position on flash (e.g. address 2M in SPI flash). - - Supported options to implement the skip request are: - - GPIO - - I2C - - User defined - - - Porting: - Under marvell_plat_config.c, implement struct skip_image that includes specific board parameters. - .. warning:: to disable this feature make sure the struct skip_image is not implemented. - - - Example: - In A7040-DB specific implementation (plat/marvell/a8k/a70x0/board/marvell_plat_config.c), - the image skip is implemented using GPIO: mpp 33 (SW5). - - Before resetting the board make sure there is a valid image on the next flash address: - -tftp [valid address] flash-image.bin - -sf update [valid address] 0x2000000 [size] - - Press reset and keep pressing the button connected to the chosen GPIO pin. A skip image request - message is printed on the screen and boot rom boots from the saved image at the next position. - - - DDR Porting (dram_port.c): - - This file defines the dram topology and parameters of the target board. - - The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (TF-A). - - The DDR driver called mv_ddr is released separately apart from TF-A sources. - - The BLE and consequently, the DDR init code is executed at the early stage of the boot process. - - Each supported platform of the TF-A has its own DDR porting file called dram_port.c located at - ``atf/plat/marvell/a8k/<platform>/board`` directory. - - Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed porting description. - - The build target directory is "build/<platform>/release/ble". - - - Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) - - Background: - Some of the comphy's parameters value depend on the HW connection between the SoC and the PHY. Every - board type has specific HW characteristics like wire length. Due to those differences some comphy - parameters vary between board types. Therefore each board type can have its own list of values for - all relevant comphy parameters. The PHY porting layer specifies which parameters need to be suited and - the board designer should provide relevant values. - - .. seealso:: - For XFI/SFI comphy type there is procedure "rx_training" which eases process of suiting some of - the parameters. Please see :ref:`uboot_cmd` section: rx_training. - - The PHY porting layer simplifies updating static values per board type, which are now grouped in one place. - - .. note:: - The parameters for the same type of comphy may vary even for the same board type, it is because - the lanes from comphy-x to some PHY may have different HW characteristic than lanes from - comphy-y to the same (multiplexed) or other PHY. - - - Porting: - The porting layer for PHY was introduced in TF-A. There is one file - ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the defaults. Those default - parameters are used only if there is no appropriate phy-porting-layer.h file under: - ``plat/marvell/<soc family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h exists, - the phy-default-porting-layer.h is not going to be included. - - .. warning:: - Not all comphy types are already reworked to support the PHY porting layer, currently the porting - layer is supported for XFI/SFI and SATA comphy types. - - The easiest way to prepare the PHY porting layer for custom board is to copy existing example to a new - platform: - - - cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/<soc family>/<platform>/board/phy-porting-layer.h" - - adjust relevant parameters or - - if different comphy index is used for specific feature, move it to proper table entry and then adjust. - - .. note:: - The final table size with comphy parameters can be different, depending on the CP module count for - given SoC type. - - - Example: - Example porting layer for armada-8040-db is under: ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` - - .. note:: - If there is no PHY porting layer for new platform (missing phy-porting-layer.h), the default - values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is warned: - - .. warning:: - "Using default comphy parameters - it may be required to suit them for your board". diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst new file mode 100644 index 00000000..0f529c10 --- /dev/null +++ b/docs/plat/rpi4.rst @@ -0,0 +1,85 @@ +Raspberry Pi 4 +============== + +The `Raspberry Pi 4`_ is an inexpensive single-board computer that contains four +Arm Cortex-A72 cores. Also in contrast to previous Raspberry Pi versions this +model has a GICv2 interrupt controller. + +This port is a minimal port to support loading non-secure EL2 payloads such +as a 64-bit Linux kernel. Other payloads such as U-Boot or EDK-II should work +as well, but have not been tested at this point. + +**IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM, +which is available from both the Non-secure and Secure worlds. The SoC does +not seem to feature a secure memory controller of any kind, so portions of +DRAM can't be protected properly from the Non-secure world. + +Build Instructions +------------------ + +There are no real configuration options at this point, so there is only +one universal binary (bl31.bin), which can be built with: + +.. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1 + +Copy the generated build/rpi4/debug/bl31.bin to the SD card, either +renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``, +then followed by the respective file name to ``config.txt``. +You should have AArch64 code in the file loaded as the "kernel", as BL31 +will drop into AArch64/EL2 to the respective load address. +arm64 Linux kernels are known to work this way. + +Other options that should be set in ``config.txt`` to properly boot 64-bit +kernels are: + +:: + + enable_uart=1 + arm_64bit=1 + enable_gic=1 + +The BL31 code will patch the provided device tree blob in memory to advertise +PSCI support, also will add a reserved-memory node to the DT to tell the +non-secure payload to not touch the resident TF-A code. + +If you connect a serial cable between the Mini UART and your computer, and +connect to it (for example, with ``screen /dev/ttyUSB0 115200``) you should +see some text from BL31, followed by the output of the EL2 payload. +The command line provided is read from the ``cmdline.txt`` file on the SD card. + +TF-A port design +---------------- + +In contrast to the existing Raspberry Pi 3 port this one here is a BL31-only +port, also it deviates quite a lot from the RPi3 port in many other ways. +There is not so much difference between the two models, so eventually those +two could be (more) unified in the future. + +As with the previous models, the GPU and its firmware are the first entity to +run after the SoC gets its power. The on-chip Boot ROM loads the next stage +(bootcode.bin) from flash (EEPROM), which is again GPU code. +This part knows how to access the MMC controller and how to parse a FAT +filesystem, so it will load further compononents and configuration files +from the first FAT partition on the SD card. + +To accommodate this existing way of configuring and setting up the board, +we use as much of this workflow as possible. +If bootcode.bin finds a file called ``armstub8.bin`` on the SD card or it gets +pointed to such code by finding a ``armstub=`` key in ``config.txt``, it will +load this file to the beginning of DRAM (address 0) and execute it in +AArch64 EL3. +But before doing that, it will also load a "kernel" and the device tree into +memory. The load addresses have a default, but can also be changed by +setting them in ``config.txt``. If the GPU firmware finds a magic value in the +armstub image file, it will put those two load addresses in memory locations +near the beginning of memory, where TF-A code picks them up. + +To keep things simple, we will just use the kernel load address as the BL33 +entry point, also put the DTB address in the x0 register, as requested by +the arm64 Linux kernel boot protocol. This does not necessarily mean that +the EL2 payload needs to be a Linux kernel, a bootloader or any other kernel +would work as well, as long as it can cope with having the DT address in +register x0. If the payload has other means of finding the device tree, it +could ignore this address as well. diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 94a20ba0..fb49a579 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -16,7 +16,6 @@ #include "gicv3_private.h" const gicv3_driver_data_t *gicv3_driver_data; -static unsigned int gicv2_compat; /* * Spinlock to guard registers needing read-modify-write. APIs protected by this @@ -60,51 +59,61 @@ static spinlock_t gic_lock; void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) { unsigned int gic_version; + unsigned int gicv2_compat; assert(plat_driver_data != NULL); assert(plat_driver_data->gicd_base != 0U); - assert(plat_driver_data->gicr_base != 0U); assert(plat_driver_data->rdistif_num != 0U); assert(plat_driver_data->rdistif_base_addrs != NULL); assert(IS_IN_EL3()); - assert(plat_driver_data->interrupt_props_num > 0 ? - plat_driver_data->interrupt_props != NULL : 1); + assert((plat_driver_data->interrupt_props_num != 0U) ? + (plat_driver_data->interrupt_props != NULL) : 1); /* Check for system register support */ -#ifdef __aarch64__ +#ifndef __aarch64__ + assert((read_id_pfr1() & + (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); +#else assert((read_id_aa64pfr0_el1() & (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); -#else - assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); -#endif /* __aarch64__ */ +#endif /* !__aarch64__ */ /* The GIC version should be 3.0 */ gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); - gic_version >>= PIDR2_ARCH_REV_SHIFT; + gic_version >>= PIDR2_ARCH_REV_SHIFT; gic_version &= PIDR2_ARCH_REV_MASK; assert(gic_version == ARCH_REV_GICV3); /* - * Find out whether the GIC supports the GICv2 compatibility mode. The - * ARE_S bit resets to 0 if supported + * Find out whether the GIC supports the GICv2 compatibility mode. + * The ARE_S bit resets to 0 if supported */ gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); gicv2_compat >>= CTLR_ARE_S_SHIFT; - gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); - - /* - * Find the base address of each implemented Redistributor interface. - * The number of interfaces should be equal to the number of CPUs in the - * system. The memory for saving these addresses has to be allocated by - * the platform port - */ - gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, - plat_driver_data->rdistif_num, - plat_driver_data->gicr_base, - plat_driver_data->mpidr_to_core_pos); - + gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; + + if (plat_driver_data->gicr_base != 0U) { + /* + * Find the base address of each implemented Redistributor interface. + * The number of interfaces should be equal to the number of CPUs in the + * system. The memory for saving these addresses has to be allocated by + * the platform port + */ + gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, + plat_driver_data->rdistif_num, + plat_driver_data->gicr_base, + plat_driver_data->mpidr_to_core_pos); +#if !HW_ASSISTED_COHERENCY + /* + * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. + */ + flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), + plat_driver_data->rdistif_num * + sizeof(*(plat_driver_data->rdistif_base_addrs))); +#endif + } gicv3_driver_data = plat_driver_data; /* @@ -112,19 +121,19 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) * enabled. When the secondary CPU boots up, it initializes the * GICC/GICR interface with the caches disabled. Hence flush the * driver data to ensure coherency. This is not required if the - * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY - * enabled. + * platform has HW_ASSISTED_COHERENCY enabled. */ -#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) - flush_dcache_range((uintptr_t) &gicv3_driver_data, - sizeof(gicv3_driver_data)); - flush_dcache_range((uintptr_t) gicv3_driver_data, - sizeof(*gicv3_driver_data)); +#if !HW_ASSISTED_COHERENCY + flush_dcache_range((uintptr_t)&gicv3_driver_data, + sizeof(gicv3_driver_data)); + flush_dcache_range((uintptr_t)gicv3_driver_data, + sizeof(*gicv3_driver_data)); #endif - INFO("GICv3 %s legacy support detected." - " ARM GICV3 driver initialized in EL3\n", - gicv2_compat ? "with" : "without"); + INFO("GICv3 with%s legacy support detected." + " ARM GICv3 driver initialized in EL3\n", + (gicv2_compat == 0U) ? "" : "out"); + } /******************************************************************************* @@ -192,6 +201,7 @@ void gicv3_rdistif_init(unsigned int proc_num) gicv3_rdistif_on(proc_num); gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + assert(gicr_base != 0U); /* Set the default attribute of all SGIs and PPIs */ gicv3_ppi_sgi_config_defaults(gicr_base); @@ -313,6 +323,7 @@ void gicv3_cpuif_disable(unsigned int proc_num) /* Mark the connected core as asleep */ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + assert(gicr_base != 0U); gicv3_rdistif_mark_core_asleep(gicr_base); } @@ -629,7 +640,9 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) num_ints &= TYPER_IT_LINES_NO_MASK; num_ints = (num_ints + 1U) << 5; - assert(num_ints <= (MAX_SPI_ID + 1U)); + /* Filter out special INTIDs 1020-1023 */ + if (num_ints > (MAX_SPI_ID + 1U)) + num_ints = MAX_SPI_ID + 1U; /* Wait for pending write to complete */ gicd_wait_for_pending_write(gicd_base); @@ -637,31 +650,31 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) /* Save the GICD_CTLR */ dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); - /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ + /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); - /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ + /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); - /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ + /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); - /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ + /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); - /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ + /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); - /* Save GICD_ICFGR for INTIDs 32 - 1020 */ + /* Save GICD_ICFGR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); - /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ + /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); - /* Save GICD_NSACR for INTIDs 32 - 1020 */ + /* Save GICD_NSACR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); - /* Save GICD_IROUTER for INTIDs 32 - 1024 */ + /* Save GICD_IROUTER for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); /* @@ -707,24 +720,26 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) num_ints &= TYPER_IT_LINES_NO_MASK; num_ints = (num_ints + 1U) << 5; - assert(num_ints <= (MAX_SPI_ID + 1U)); + /* Filter out special INTIDs 1020-1023 */ + if (num_ints > (MAX_SPI_ID + 1U)) + num_ints = MAX_SPI_ID + 1U; - /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ + /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); - /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ + /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); - /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ + /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); - /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ + /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); - /* Restore GICD_NSACR for INTIDs 32 - 1020 */ + /* Restore GICD_NSACR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); - /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ + /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); /* @@ -732,13 +747,13 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) * configured. */ - /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ + /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); - /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ + /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); - /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ + /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); /* Restore the GICD_CTLR */ @@ -1081,3 +1096,71 @@ unsigned int gicv3_set_pmr(unsigned int mask) return old_mask; } + +/******************************************************************************* + * This function delegates the responsibility of discovering the corresponding + * Redistributor frames to each CPU itself. It is a modified version of + * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform + * unlike the previous way in which only the Primary CPU did the discovery of + * all the Redistributor frames for every CPU. It also handles the scenario in + * which the frames of various CPUs are not contiguous in physical memory. + ******************************************************************************/ +int gicv3_rdistif_probe(const uintptr_t gicr_frame) +{ + u_register_t mpidr; + unsigned int proc_num, proc_self; + uint64_t typer_val; + uintptr_t rdistif_base; + bool gicr_frame_found = false; + + assert(gicv3_driver_data->gicr_base == 0U); + + /* Ensure this function is called with Data Cache enabled */ +#ifndef __aarch64__ + assert((read_sctlr() & SCTLR_C_BIT) != 0U); +#else + assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); +#endif /* !__aarch64__ */ + + proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1()); + rdistif_base = gicr_frame; + do { + typer_val = gicr_read_typer(rdistif_base); + if (gicv3_driver_data->mpidr_to_core_pos != NULL) { + mpidr = mpidr_from_gicr_typer(typer_val); + proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); + } else { + proc_num = (unsigned int)(typer_val >> TYPER_PROC_NUM_SHIFT) & + TYPER_PROC_NUM_MASK; + } + if (proc_num == proc_self) { + /* The base address doesn't need to be initialized on + * every warm boot. + */ + if (gicv3_driver_data->rdistif_base_addrs[proc_num] != 0U) + return 0; + gicv3_driver_data->rdistif_base_addrs[proc_num] = + rdistif_base; + gicr_frame_found = true; + break; + } + rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT); + } while ((typer_val & TYPER_LAST_BIT) == 0U); + + if (!gicr_frame_found) + return -1; + + /* + * Flush the driver data to ensure coherency. This is + * not required if platform has HW_ASSISTED_COHERENCY + * enabled. + */ +#if !HW_ASSISTED_COHERENCY + /* + * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. + */ + flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), + sizeof(*(gicv3_driver_data->rdistif_base_addrs))); +#endif + return 0; /* Found matching GICR frame */ +} diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c index 4577f06a..1b804dee 100644 --- a/drivers/partition/gpt.c +++ b/drivers/partition/gpt.c @@ -52,9 +52,10 @@ int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry) if (result != 0) { return result; } - entry->start = (uint64_t)gpt_entry->first_lba * PARTITION_BLOCK_SIZE; + entry->start = (uint64_t)gpt_entry->first_lba * + PLAT_PARTITION_BLOCK_SIZE; entry->length = (uint64_t)(gpt_entry->last_lba - gpt_entry->first_lba + 1) * - PARTITION_BLOCK_SIZE; + PLAT_PARTITION_BLOCK_SIZE; return 0; } diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c index 7fdbf538..68133eaf 100644 --- a/drivers/partition/partition.c +++ b/drivers/partition/partition.c @@ -15,7 +15,7 @@ #include <drivers/partition/mbr.h> #include <plat/common/platform.h> -static uint8_t mbr_sector[PARTITION_BLOCK_SIZE]; +static uint8_t mbr_sector[PLAT_PARTITION_BLOCK_SIZE]; static partition_entry_list_t list; #if LOG_LEVEL >= LOG_LEVEL_VERBOSE @@ -57,15 +57,15 @@ static int load_mbr_header(uintptr_t image_handle, mbr_entry_t *mbr_entry) return result; } result = io_read(image_handle, (uintptr_t)&mbr_sector, - PARTITION_BLOCK_SIZE, &bytes_read); + PLAT_PARTITION_BLOCK_SIZE, &bytes_read); if (result != 0) { WARN("Failed to read data (%i)\n", result); return result; } /* Check MBR boot signature. */ - if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || - (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { + if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || + (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { return -ENOENT; } offset = (uintptr_t)&mbr_sector + MBR_PRIMARY_ENTRY_OFFSET; @@ -120,15 +120,15 @@ static int load_mbr_entry(uintptr_t image_handle, mbr_entry_t *mbr_entry, return result; } result = io_read(image_handle, (uintptr_t)&mbr_sector, - PARTITION_BLOCK_SIZE, &bytes_read); + PLAT_PARTITION_BLOCK_SIZE, &bytes_read); if (result != 0) { WARN("Failed to read data (%i)\n", result); return result; } /* Check MBR boot signature. */ - if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || - (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { + if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || + (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { return -ENOENT; } offset = (uintptr_t)&mbr_sector + diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index 8bc4adf8..91212e8a 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -12,14 +12,40 @@ interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_on = <0x84000003>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; + enable-method = "psci"; reg = <0>; }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + enable-method = "psci"; + reg = <1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + enable-method = "psci"; + reg = <2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + enable-method = "psci"; + reg = <3>; + }; }; memory@80000000 { diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 9c72d4df..c4f42d04 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -366,6 +366,7 @@ typedef struct gicv3_its_ctx { * GICv3 EL3 driver API ******************************************************************************/ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); +int gicv3_rdistif_probe(const uintptr_t gicr_frame); void gicv3_distif_init(void); void gicv3_rdistif_init(unsigned int proc_num); void gicv3_rdistif_on(unsigned int proc_num); diff --git a/include/drivers/partition/gpt.h b/include/drivers/partition/gpt.h index 3ae160fd..d923e953 100644 --- a/include/drivers/partition/gpt.h +++ b/include/drivers/partition/gpt.h @@ -10,9 +10,9 @@ #include <drivers/partition/partition.h> #define PARTITION_TYPE_GPT 0xee -#define GPT_HEADER_OFFSET PARTITION_BLOCK_SIZE +#define GPT_HEADER_OFFSET PLAT_PARTITION_BLOCK_SIZE #define GPT_ENTRY_OFFSET (GPT_HEADER_OFFSET + \ - PARTITION_BLOCK_SIZE) + PLAT_PARTITION_BLOCK_SIZE) #define GUID_LEN 16 #define GPT_SIGNATURE "EFI PART" diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index d94c7824..5f648337 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h @@ -17,7 +17,15 @@ CASSERT(PLAT_PARTITION_MAX_ENTRIES <= 128, assert_plat_partition_max_entries); -#define PARTITION_BLOCK_SIZE 512 +#if !PLAT_PARTITION_BLOCK_SIZE +# define PLAT_PARTITION_BLOCK_SIZE 512 +#endif /* PLAT_PARTITION_BLOCK_SIZE */ + +CASSERT((PLAT_PARTITION_BLOCK_SIZE == 512) || + (PLAT_PARTITION_BLOCK_SIZE == 4096), + assert_plat_partition_block_size); + +#define LEGACY_PARTITION_BLOCK_SIZE 512 #define EFI_NAMELEN 36 diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index 04e5e3d7..7f7b7e3f 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -301,6 +301,8 @@ typedef struct plat_psci_ops { const psci_power_state_t *target_state); void (*pwr_domain_suspend)(const psci_power_state_t *target_state); void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish_late)( + const psci_power_state_t *target_state); void (*pwr_domain_suspend_finish)( const psci_power_state_t *target_state); void __dead2 (*pwr_domain_pwr_down_wfi)( diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index b82ff47e..93f86162 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -27,6 +27,7 @@ static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) int css_pwr_domain_on(u_register_t mpidr); void css_pwr_domain_on_finish(const psci_power_state_t *target_state); +void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state); void css_pwr_domain_off(const psci_power_state_t *target_state); void css_pwr_domain_suspend(const psci_power_state_t *target_state); void css_pwr_domain_suspend_finish( diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 446d9da9..d65e02d5 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -69,7 +69,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) uint32_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; - unsigned long sctlr_elx, actlr_elx; + u_register_t sctlr_elx, actlr_elx; assert(ctx != NULL); @@ -142,11 +142,11 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is * set. */ - unsigned int mte = get_armv8_5_mte_support(); #if CTX_INCLUDE_MTE_REGS - assert(mte == MTE_IMPLEMENTED_ELX); + assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); scr_el3 |= SCR_ATA_BIT; #else + unsigned int mte = get_armv8_5_mte_support(); if (mte == MTE_IMPLEMENTED_EL0) { /* * Can enable MTE across both worlds as no MTE registers are diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c index aa6b324e..470b4f33 100644 --- a/lib/psci/psci_on.c +++ b/lib/psci/psci_on.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -182,6 +182,14 @@ void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info) #endif /* + * Plat. management: Perform any platform specific actions which + * can only be done with the cpu and the cluster guaranteed to + * be coherent. + */ + if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) + psci_plat_pm_ops->pwr_domain_on_finish_late(state_info); + + /* * All the platform specific actions for turning this cpu * on have completed. Perform enough arch.initialization * to run in the non-secure address space. diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c index 728bcd06..c8a6772c 100644 --- a/plat/amlogic/common/aml_scpi.c +++ b/plat/amlogic/common/aml_scpi.c @@ -25,6 +25,7 @@ #define SCPI_CMD_JTAG_SET_STATE 0xC0 #define SCPI_CMD_EFUSE_READ 0xC2 +#define SCPI_CMD_CHIP_ID 0xC6 #define SCPI_CMD_COPY_FW 0xd4 #define SCPI_CMD_SET_FW_ADDR 0xd3 @@ -142,6 +143,28 @@ void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, aml_mhu_secure_message_end(); } +uint32_t aml_scpi_get_chip_id(uint8_t *obuff, uint32_t osize) +{ + uint32_t *response; + size_t resp_size; + + if ((osize != 16) && (osize != 12)) + return 0; + + aml_mhu_secure_message_start(); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_CHIP_ID, osize)); + aml_scpi_secure_message_receive((void *)&response, &resp_size); + aml_mhu_secure_message_end(); + + if (!((resp_size == 16) && (osize == 16)) && + !((resp_size == 0) && (osize == 12))) + return 0; + + memcpy((void *)obuff, (const void *)response, osize); + + return osize; +} + static inline void aml_scpi_copy_scp_data(uint8_t *data, size_t len) { void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c index 8a9b070d..ab4c0156 100644 --- a/plat/amlogic/common/aml_sip_svc.c +++ b/plat/amlogic/common/aml_sip_svc.c @@ -9,9 +9,39 @@ #include <lib/mmio.h> #include <platform_def.h> #include <stdint.h> +#include <string.h> #include "aml_private.h" +struct aml_cpu_info { + uint32_t version; + uint8_t chip_id[16]; +}; + +static int aml_sip_get_chip_id(uint64_t version) +{ + struct aml_cpu_info *info = (void *)AML_SHARE_MEM_OUTPUT_BASE; + uint32_t size; + + if (version > 2) + return -1; + + memset(info, 0, sizeof(struct aml_cpu_info)); + + if (version == 2) { + info->version = 2; + size = 16; + } else { + info->version = 1; + size = 12; + } + + if (aml_scpi_get_chip_id(info->chip_id, size) == 0) + return -1; + + return 0; +} + /******************************************************************************* * This function is responsible for handling all SiP calls ******************************************************************************/ @@ -47,6 +77,9 @@ static uintptr_t aml_sip_handler(uint32_t smc_fid, aml_scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1); SMC_RET1(handle, 0); + case AML_SM_GET_CHIP_ID: + SMC_RET1(handle, aml_sip_get_chip_id(x1)); + default: ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); break; diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 49237456..724f382f 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -31,6 +31,7 @@ uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size); void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3); void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); +uint32_t aml_scpi_get_chip_id(uint8_t *obuff, uint32_t osize); /* Peripherals */ void aml_thermal_unknown(void); diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index 2c926240..fa5e4fa9 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -110,6 +110,7 @@ #define AML_SM_JTAG_ON U(0x82000040) #define AML_SM_JTAG_OFF U(0x82000041) +#define AML_SM_GET_CHIP_ID U(0x82000044) #define AML_JTAG_STATE_ON U(0) #define AML_JTAG_STATE_OFF U(1) diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index ea19338e..f30eb287 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -120,6 +120,7 @@ #define AML_SM_JTAG_ON U(0x82000040) #define AML_SM_JTAG_OFF U(0x82000041) +#define AML_SM_GET_CHIP_ID U(0x82000044) #define AML_JTAG_STATE_ON U(0) #define AML_JTAG_STATE_OFF U(1) diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c index 5fd443b1..98de77d1 100644 --- a/plat/arm/board/a5ds/a5ds_pm.c +++ b/plat/arm/board/a5ds/a5ds_pm.c @@ -6,6 +6,38 @@ #include <lib/psci/psci.h> #include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> +#include <drivers/arm/gicv2.h> + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int a5ds_pwr_domain_on(u_register_t mpidr) +{ + unsigned int pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)A5DS_HOLD_BASE; + + hold_base[pos] = A5DS_HOLD_STATE_GO; + dsbish(); + sev(); + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + /* TODO: This setup is needed only after a cold boot*/ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} /******************************************************************************* * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard @@ -14,11 +46,16 @@ plat_psci_ops_t a5ds_psci_pm_ops = { /* dummy struct */ .validate_ns_entrypoint = NULL, + .pwr_domain_on = a5ds_pwr_domain_on, + .pwr_domain_on_finish = a5ds_pwr_domain_on_finish }; int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { + uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE; + *mailbox = sec_entrypoint; + *psci_ops = &a5ds_psci_pm_ops; return 0; diff --git a/plat/arm/board/a5ds/aarch32/a5ds_helpers.S b/plat/arm/board/a5ds/aarch32/a5ds_helpers.S index 23a22d9c..ed7ad9c8 100644 --- a/plat/arm/board/a5ds/aarch32/a5ds_helpers.S +++ b/plat/arm/board/a5ds/aarch32/a5ds_helpers.S @@ -12,17 +12,36 @@ .globl plat_get_my_entrypoint .globl plat_is_my_cpu_primary - /* -------------------------------------------------------------------- + /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * - * For AArch32, cold-booting secondary CPUs is not yet - * implemented and they panic. - * -------------------------------------------------------------------- + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- */ func plat_secondary_cold_boot_setup -cb_panic: - wfi - b cb_panic + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl r0, r0, #A5DS_HOLD_ENTRY_SHIFT + mov_imm r2, A5DS_HOLD_BASE + /* Clear the value stored in the hold address for the specific core */ + mov_imm r3, A5DS_HOLD_STATE_WAIT + str r3, [r2, r0] + dmb ish + + /* Wait until we have a go */ +poll_mailbox: + ldr r1, [r2, r0] + cmp r1, #A5DS_HOLD_STATE_WAIT + beq 1f + mov_imm r0, A5DS_TRUSTED_MAILBOX_BASE + ldr r1, [r0] + bx r1 +1: + wfe + b poll_mailbox endfunc plat_secondary_cold_boot_setup /* --------------------------------------------------------------------- @@ -56,3 +75,52 @@ func plat_is_my_cpu_primary movne r0, #0 bx lr endfunc plat_is_my_cpu_primary + + /* --------------------------------------------------------------------- + * Loads MPIDR in r0 and calls plat_arm_calc_core_pos + * --------------------------------------------------------------------- + */ +func plat_my_core_pos + ldcopr r0, MPIDR + b plat_arm_calc_core_pos + +endfunc plat_my_core_pos + + /* --------------------------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * + * Function to calculate the core position on A5DS. + * + * (ClusterId * A5DS_MAX_CPUS_PER_CLUSTER * A5DS_MAX_PE_PER_CPU) + + * (CPUId * A5DS_MAX_PE_PER_CPU) + + * ThreadId + * + * which can be simplified as: + * + * ((ClusterId * A5DS_MAX_CPUS_PER_CLUSTER + CPUId) * A5DS_MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- + */ +func plat_arm_calc_core_pos + mov r3, r0 + + /* + * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it + * look as if in a multi-threaded implementation + */ + tst r0, #MPIDR_MT_MASK + lsleq r3, r0, #MPIDR_AFFINITY_BITS + + /* Extract individual affinity fields from MPIDR */ + ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + + /* Compute linear position */ + mov r3, #A5DS_MAX_CPUS_PER_CLUSTER + mla r1, r2, r3, r1 + mov r3, #A5DS_MAX_PE_PER_CPU + mla r0, r1, r3, r0 + + bx lr +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index db65c377..e9e4b9ae 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -97,9 +97,9 @@ /* Default number of threads per CPU on A5DS */ #define A5DS_MAX_PE_PER_CPU 1 -#define A5DS_CORE_COUNT 1 +#define A5DS_CORE_COUNT 4 -#define A5DS_PRIMARY_CPU 0x0 +#define A5DS_PRIMARY_CPU 0x0 #define FLASH1_BASE UL(0x8000000) #define FLASH1_SIZE UL(0x2800000) @@ -229,11 +229,11 @@ #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) /* Required platform porting definitions */ -#define PLATFORM_CORE_COUNT 1 -#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ +#define PLATFORM_CORE_COUNT A5DS_CORE_COUNT +#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) + 1 -#define PLAT_MAX_PWR_LVL 2 +#define PLAT_MAX_PWR_LVL 2 /* * Other platform porting definitions are provided by included headers @@ -325,6 +325,14 @@ /* Mailbox base address */ #define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE +#define A5DS_TRUSTED_MAILBOX_SIZE (8 + A5DS_HOLD_SIZE) +#define A5DS_HOLD_BASE (A5DS_TRUSTED_MAILBOX_BASE + 8) +#define A5DS_HOLD_SIZE (PLATFORM_CORE_COUNT * \ + A5DS_HOLD_ENTRY_SIZE) +#define A5DS_HOLD_ENTRY_SHIFT 3 +#define A5DS_HOLD_ENTRY_SIZE (1 << A5DS_HOLD_ENTRY_SHIFT) +#define A5DS_HOLD_STATE_WAIT 0 +#define A5DS_HOLD_STATE_GO 1 /* * GIC related constants to cater for GICv2 diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index 42dec8df..0a62543f 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -247,10 +247,19 @@ static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) { fvp_power_domain_on_finish_common(target_state); - /* Enable the gic cpu interface */ +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on and the cpu + * and its cluster are fully participating in coherent transaction on the + * interconnect. Data cache must be enabled for CPU at this point. + ******************************************************************************/ +static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state) +{ + /* Program GIC per-cpu distributor or re-distributor interface */ plat_arm_gic_pcpu_init(); - /* Program the gic per-cpu distributor or re-distributor interface */ + /* Enable GIC CPU interface */ plat_arm_gic_cpuif_enable(); } @@ -272,7 +281,7 @@ static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state fvp_power_domain_on_finish_common(target_state); - /* Enable the gic cpu interface */ + /* Enable GIC CPU interface */ plat_arm_gic_cpuif_enable(); } @@ -397,6 +406,7 @@ plat_psci_ops_t plat_arm_psci_pm_ops = { .pwr_domain_off = fvp_pwr_domain_off, .pwr_domain_suspend = fvp_pwr_domain_suspend, .pwr_domain_on_finish = fvp_pwr_domain_on_finish, + .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late, .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, .system_off = fvp_system_off, .system_reset = fvp_system_reset, diff --git a/plat/arm/board/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_trusted_boot.c index 0d160cb1..dc507643 100644 --- a/plat/arm/board/fvp/fvp_trusted_boot.c +++ b/plat/arm/board/fvp/fvp_trusted_boot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,39 +8,41 @@ #include <stdint.h> #include <string.h> +#include <lib/mmio.h> + #include <plat/common/platform.h> #include <platform_def.h> #include <tools_share/tbbr_oid.h> /* - * Store a new non-volatile counter value. On some FVP versions, the - * non-volatile counters are RO. On these versions we expect the values in the - * certificates to always match the RO values so that this function is never - * called. + * Store a new non-volatile counter value. + * + * On some FVP versions, the non-volatile counters are read-only so this + * function will always fail. * * Return: 0 = success, Otherwise = error */ int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) { const char *oid; - uint32_t *nv_ctr_addr; + uintptr_t nv_ctr_addr; assert(cookie != NULL); oid = (const char *)cookie; if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = (uint32_t *)TFW_NVCTR_BASE; + nv_ctr_addr = TFW_NVCTR_BASE; } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = (uint32_t *)NTFW_CTR_BASE; + nv_ctr_addr = NTFW_CTR_BASE; } else { return 1; } - *(unsigned int *)nv_ctr_addr = nv_ctr; - - /* Verify that the current value is the one we just wrote. */ - if (nv_ctr != (unsigned int)(*nv_ctr_addr)) - return 1; + mmio_write_32(nv_ctr_addr, nv_ctr); - return 0; + /* + * If the FVP models a locked counter then its value cannot be updated + * and the above write operation has been silently ignored. + */ + return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1; } diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 7f4957fa..fef53761 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> #include <platform_def.h> #include <common/interrupt_props.h> @@ -67,7 +68,7 @@ static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) static const gicv3_driver_data_t arm_gic_data __unused = { .gicd_base = PLAT_ARM_GICD_BASE, - .gicr_base = PLAT_ARM_GICR_BASE, + .gicr_base = 0U, .interrupt_props = arm_interrupt_props, .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, @@ -86,6 +87,11 @@ void __init plat_arm_gic_driver_init(void) #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ (defined(__aarch64__) && defined(IMAGE_BL31)) gicv3_driver_init(&arm_gic_data); + + if (gicv3_rdistif_probe(PLAT_ARM_GICR_BASE) == -1) { + ERROR("No GICR base frame found for Primary CPU\n"); + panic(); + } #endif } @@ -116,10 +122,20 @@ void plat_arm_gic_cpuif_disable(void) } /****************************************************************************** - * ARM common helper to initialize the per-cpu redistributor interface in GICv3 + * ARM common helper function to iterate over all GICR frames and discover the + * corresponding per-cpu redistributor frame as well as initialize the + * corresponding interface in GICv3. At the moment, Arm platforms do not have + * non-contiguous GICR frames. *****************************************************************************/ void plat_arm_gic_pcpu_init(void) { + int result; + + result = gicv3_rdistif_probe(PLAT_ARM_GICR_BASE); + if (result == -1) { + ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); + panic(); + } gicv3_rdistif_init(plat_my_core_pos()); } diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index f6fc6aa7..01c674f8 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,9 +76,6 @@ static void css_pwr_domain_on_finisher_common( { assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); - /* Enable the gic cpu interface */ - plat_arm_gic_cpuif_enable(); - /* * Perform the common cluster specific operations i.e enable coherency * if this cluster was off. @@ -100,10 +97,21 @@ void css_pwr_domain_on_finish(const psci_power_state_t *target_state) /* Assert that the system power domain need not be initialized */ assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); + css_pwr_domain_on_finisher_common(target_state); +} + +/******************************************************************************* + * Handler called when a power domain has just been powered on and the cpu + * and its cluster are fully participating in coherent transaction on the + * interconnect. Data cache must be enabled for CPU at this point. + ******************************************************************************/ +void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) +{ /* Program the gic per-cpu distributor or re-distributor interface */ plat_arm_gic_pcpu_init(); - css_pwr_domain_on_finisher_common(target_state); + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); } /******************************************************************************* @@ -185,6 +193,9 @@ void css_pwr_domain_suspend_finish( arm_system_pwr_domain_resume(); css_pwr_domain_on_finisher_common(target_state); + + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); } /******************************************************************************* @@ -306,6 +317,7 @@ static int css_translate_power_state_by_mpidr(u_register_t mpidr, plat_psci_ops_t plat_arm_psci_pm_ops = { .pwr_domain_on = css_pwr_domain_on, .pwr_domain_on_finish = css_pwr_domain_on_finish, + .pwr_domain_on_finish_late = css_pwr_domain_on_finish_late, .pwr_domain_off = css_pwr_domain_off, .cpu_standby = css_cpu_standby, .pwr_domain_suspend = css_pwr_domain_suspend, diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 2f96efcd..96136ec1 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -114,6 +114,11 @@ uint32_t hikey_get_spsr_for_bl33_entry(void) } #endif /* __aarch64__ */ +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + return hikey_set_fip_addr(image_id, "fastboot"); +} + int hikey_bl2_handle_post_image_load(unsigned int image_id) { int err = 0; diff --git a/plat/hisilicon/hikey/hikey_io_storage.c b/plat/hisilicon/hikey/hikey_io_storage.c index 11dd9733..fd610d8c 100644 --- a/plat/hisilicon/hikey/hikey_io_storage.c +++ b/plat/hisilicon/hikey/hikey_io_storage.c @@ -18,6 +18,7 @@ #include <drivers/io/io_memmap.h> #include <drivers/io/io_storage.h> #include <drivers/mmc.h> +#include <drivers/partition/partition.h> #include <lib/mmio.h> #include <lib/semihosting.h> #include <tools_share/firmware_image_package.h> @@ -43,9 +44,12 @@ static uintptr_t fip_dev_handle; static int check_emmc(const uintptr_t spec); static int check_fip(const uintptr_t spec); -static const io_block_spec_t emmc_fip_spec = { - .offset = HIKEY_FIP_BASE, - .length = HIKEY_FIP_MAX_SIZE, +static io_block_spec_t emmc_fip_spec; + +static const io_block_spec_t emmc_gpt_spec = { + .offset = 0, + .length = PLAT_PARTITION_BLOCK_SIZE * + (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), }; static const io_block_dev_spec_t emmc_dev_spec = { @@ -213,6 +217,11 @@ static const struct plat_io_policy policies[] = { check_fip }, #endif /* TRUSTED_BOARD_BOOT */ + [GPT_IMAGE_ID] = { + &emmc_dev_handle, + (uintptr_t)&emmc_gpt_spec, + check_emmc + }, }; static int check_emmc(const uintptr_t spec) @@ -267,6 +276,23 @@ void hikey_io_setup(void) (void)result; } +int hikey_set_fip_addr(unsigned int image_id, const char *name) +{ + const partition_entry_t *entry; + + if (emmc_fip_spec.length == 0) { + partition_init(GPT_IMAGE_ID); + entry = get_partition_entry(name); + if (entry == NULL) { + ERROR("Could NOT find the %s partition!\n", name); + return -ENOENT; + } + emmc_fip_spec.offset = entry->start; + emmc_fip_spec.length = entry->length; + } + return 0; +} + /* Return an IO device handle and specification which can be used to access * an image. Use this to enforce platform load policy */ diff --git a/plat/hisilicon/hikey/hikey_private.h b/plat/hisilicon/hikey/hikey_private.h index d82a0794..b75bc723 100644 --- a/plat/hisilicon/hikey/hikey_private.h +++ b/plat/hisilicon/hikey/hikey_private.h @@ -72,4 +72,6 @@ int hikey_write_serialno(struct random_serial_num *serialno); void init_acpu_dvfs(void); +int hikey_set_fip_addr(unsigned int image_id, const char *name); + #endif /* HIKEY_PRIVATE_H */ diff --git a/plat/hisilicon/hikey/include/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h index 4fb3e56a..590700da 100644 --- a/plat/hisilicon/hikey/include/hikey_def.h +++ b/plat/hisilicon/hikey/include/hikey_def.h @@ -84,8 +84,6 @@ #define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000 #define EMMC_BASE 0 -#define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20)) -#define HIKEY_FIP_MAX_SIZE (8 << 20) #define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0) #define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10) #define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0) diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk index 7fd897cd..fbf74329 100644 --- a/plat/hisilicon/hikey/platform.mk +++ b/plat/hisilicon/hikey/platform.mk @@ -76,6 +76,8 @@ BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_fip.c \ drivers/io/io_storage.c \ drivers/mmc/mmc.c \ + drivers/partition/gpt.c \ + drivers/partition/partition.c \ drivers/synopsys/emmc/dw_mmc.c \ lib/cpus/aarch64/cortex_a53.S \ plat/hisilicon/hikey/aarch64/hikey_helpers.S \ diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index fc9ddab0..35d76921 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -18,6 +18,7 @@ #include <drivers/delay_timer.h> #include <drivers/dw_ufs.h> #include <drivers/generic_delay_timer.h> +#include <drivers/partition/partition.h> #include <drivers/ufs.h> #include <lib/mmio.h> #ifdef SPD_opteed @@ -263,6 +264,11 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id) * This function can be used by the platforms to update/use image * information for given `image_id`. ******************************************************************************/ +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + return hikey960_set_fip_addr(image_id, "fip"); +} + int bl2_plat_handle_post_image_load(unsigned int image_id) { return hikey960_bl2_handle_post_image_load(image_id); diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h index 4ea3acd5..9651d789 100644 --- a/plat/hisilicon/hikey960/hikey960_def.h +++ b/plat/hisilicon/hikey960/hikey960_def.h @@ -44,9 +44,6 @@ #define PL011_UART_CLK_IN_HZ 19200000 #define UFS_BASE 0 -/* FIP partition */ -#define HIKEY960_FIP_BASE (UFS_BASE + 0x1400000) -#define HIKEY960_FIP_MAX_SIZE (12 << 20) #define HIKEY960_UFS_DESC_BASE 0x20000000 #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ diff --git a/plat/hisilicon/hikey960/hikey960_io_storage.c b/plat/hisilicon/hikey960/hikey960_io_storage.c index a4e83897..e1c5845f 100644 --- a/plat/hisilicon/hikey960/hikey960_io_storage.c +++ b/plat/hisilicon/hikey960/hikey960_io_storage.c @@ -18,6 +18,7 @@ #include <drivers/io/io_fip.h> #include <drivers/io/io_memmap.h> #include <drivers/io/io_storage.h> +#include <drivers/partition/partition.h> #include <lib/mmio.h> #include <lib/semihosting.h> #include <tools_share/firmware_image_package.h> @@ -36,9 +37,12 @@ static int check_fip(const uintptr_t spec); size_t ufs_read_lun3_blks(int lba, uintptr_t buf, size_t size); size_t ufs_write_lun3_blks(int lba, const uintptr_t buf, size_t size); -static const io_block_spec_t ufs_fip_spec = { - .offset = HIKEY960_FIP_BASE, - .length = HIKEY960_FIP_MAX_SIZE, +static io_block_spec_t ufs_fip_spec; + +static const io_block_spec_t ufs_gpt_spec = { + .offset = 0, + .length = PLAT_PARTITION_BLOCK_SIZE * + (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), }; static const io_block_dev_spec_t ufs_dev_spec = { @@ -199,6 +203,11 @@ static const struct plat_io_policy policies[] = { check_fip }, #endif /* TRUSTED_BOARD_BOOT */ + [GPT_IMAGE_ID] = { + &ufs_dev_handle, + (uintptr_t)&ufs_gpt_spec, + check_ufs + }, }; static int check_ufs(const uintptr_t spec) @@ -253,6 +262,23 @@ void hikey960_io_setup(void) (void)result; } +int hikey960_set_fip_addr(unsigned int image_id, const char *name) +{ + const partition_entry_t *entry; + + if (ufs_fip_spec.length == 0) { + partition_init(GPT_IMAGE_ID); + entry = get_partition_entry(name); + if (entry == NULL) { + ERROR("Could NOT find the %s partition!\n", name); + return -ENOENT; + } + ufs_fip_spec.offset = entry->start; + ufs_fip_spec.length = entry->length; + } + return 0; +} + /* Return an IO device handle and specification which can be used to access * an image. Use this to enforce platform load policy */ diff --git a/plat/hisilicon/hikey960/hikey960_private.h b/plat/hisilicon/hikey960/hikey960_private.h index 9a18dd62..54bf5013 100644 --- a/plat/hisilicon/hikey960/hikey960_private.h +++ b/plat/hisilicon/hikey960/hikey960_private.h @@ -26,6 +26,7 @@ void hikey960_init_mmu_el3(unsigned long total_base, unsigned long coh_limit); void hikey960_io_setup(void); int hikey960_read_boardid(unsigned int *id); +int hikey960_set_fip_addr(unsigned int image_id, const char *name); void hikey960_clk_init(void); void hikey960_pmu_init(void); void hikey960_regulator_enable(void); diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk index 4f2c3c69..6cb53c7b 100644 --- a/plat/hisilicon/hikey960/platform.mk +++ b/plat/hisilicon/hikey960/platform.mk @@ -22,11 +22,13 @@ COLD_BOOT_SINGLE_CPU := 1 PLAT_PL061_MAX_GPIOS := 176 PROGRAMMABLE_RESET_ADDRESS := 1 ENABLE_SVE_FOR_NS := 0 +PLAT_PARTITION_BLOCK_SIZE := 4096 # Process flags $(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID)) $(eval $(call add_define,CRASH_CONSOLE_BASE)) $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) +$(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images # in the FIP if the platform requires. @@ -75,6 +77,8 @@ BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ drivers/io/io_storage.c \ + drivers/partition/gpt.c \ + drivers/partition/partition.c \ drivers/synopsys/ufs/dw_ufs.c \ drivers/ufs/ufs.c \ lib/cpus/aarch64/cortex_a53.S \ diff --git a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c b/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c deleted file mode 100644 index 8120d996..00000000 --- a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <common/debug.h> -#include <drivers/delay_timer.h> -#include <lib/mmio.h> - -#include <mt8173_def.h> -#include <pmic_wrap_init.h> - -/* pmic wrap module wait_idle and read polling interval (in microseconds) */ -enum { - WAIT_IDLE_POLLING_DELAY_US = 1, - READ_POLLING_DELAY_US = 2 -}; - -static inline uint32_t wait_for_state_idle(uint32_t timeout_us, - void *wacs_register, - void *wacs_vldclr_register, - uint32_t *read_reg) -{ - uint32_t reg_rdata; - uint32_t retry; - - retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) / - WAIT_IDLE_POLLING_DELAY_US; - - do { - udelay(WAIT_IDLE_POLLING_DELAY_US); - reg_rdata = mmio_read_32((uintptr_t)wacs_register); - /* if last read command timeout,clear vldclr bit - read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; - write:FSM_REQ-->idle */ - switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & - RDATA_WACS_FSM_MASK)) { - case WACS_FSM_WFVLDCLR: - mmio_write_32((uintptr_t)wacs_vldclr_register, 1); - ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); - break; - case WACS_FSM_WFDLE: - ERROR("WACS_FSM = WACS_FSM_WFDLE\n"); - break; - case WACS_FSM_REQ: - ERROR("WACS_FSM = WACS_FSM_REQ\n"); - break; - case WACS_FSM_IDLE: - goto done; - default: - break; - } - - retry--; - } while (retry); - -done: - if (!retry) /* timeout */ - return E_PWR_WAIT_IDLE_TIMEOUT; - - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -static inline uint32_t wait_for_state_ready(uint32_t timeout_us, - void *wacs_register, - uint32_t *read_reg) -{ - uint32_t reg_rdata; - uint32_t retry; - - retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US; - - do { - udelay(READ_POLLING_DELAY_US); - reg_rdata = mmio_read_32((uintptr_t)wacs_register); - - if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) - == WACS_FSM_WFVLDCLR) - break; - - retry--; - } while (retry); - - if (!retry) { /* timeout */ - ERROR("timeout when waiting for idle\n"); - return E_PWR_WAIT_IDLE_TIMEOUT_READ; - } - - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -static int32_t pwrap_wacs2(uint32_t write, - uint32_t adr, - uint32_t wdata, - uint32_t *rdata, - uint32_t init_check) -{ - uint32_t reg_rdata = 0; - uint32_t wacs_write = 0; - uint32_t wacs_adr = 0; - uint32_t wacs_cmd = 0; - uint32_t return_value = 0; - - if (init_check) { - reg_rdata = mmio_read_32((uintptr_t)&mt8173_pwrap->wacs2_rdata); - /* Prevent someone to used pwrap before pwrap init */ - if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & - RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { - ERROR("initialization isn't finished\n"); - return E_PWR_NOT_INIT_DONE; - } - } - reg_rdata = 0; - /* Check IDLE in advance */ - return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE, - &mt8173_pwrap->wacs2_rdata, - &mt8173_pwrap->wacs2_vldclr, - 0); - if (return_value != 0) { - ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value); - goto FAIL; - } - wacs_write = write << 31; - wacs_adr = (adr >> 1) << 16; - wacs_cmd = wacs_write | wacs_adr | wdata; - - mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_cmd, wacs_cmd); - if (write == 0) { - if (NULL == rdata) { - ERROR("rdata is a NULL pointer\n"); - return_value = E_PWR_INVALID_ARG; - goto FAIL; - } - return_value = wait_for_state_ready(TIMEOUT_READ, - &mt8173_pwrap->wacs2_rdata, - ®_rdata); - if (return_value != 0) { - ERROR("wait_for_fsm_vldclr fail,return_value=%d\n", - return_value); - goto FAIL; - } - *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) - & RDATA_WACS_RDATA_MASK); - mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_vldclr, 1); - } -FAIL: - return return_value; -} - -/* external API for pmic_wrap user */ - -int32_t pwrap_read(uint32_t adr, uint32_t *rdata) -{ - return pwrap_wacs2(0, adr, 0, rdata, 1); -} - -int32_t pwrap_write(uint32_t adr, uint32_t wdata) -{ - return pwrap_wacs2(1, adr, wdata, 0, 1); -} diff --git a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h index 0f097713..0dffc23e 100644 --- a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h @@ -7,11 +7,13 @@ #ifndef PMIC_WRAP_INIT_H #define PMIC_WRAP_INIT_H +#include <platform_def.h> + /* external API */ int32_t pwrap_read(uint32_t adr, uint32_t *rdata); int32_t pwrap_write(uint32_t adr, uint32_t wdata); -static struct mt8173_pmic_wrap_regs *const mt8173_pwrap = +static struct mt8173_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; /* timeout setting */ diff --git a/plat/mediatek/mt8173/drivers/rtc/rtc.c b/plat/mediatek/mt8173/drivers/rtc/rtc.c index 2b9033ed..587886c6 100644 --- a/plat/mediatek/mt8173/drivers/rtc/rtc.c +++ b/plat/mediatek/mt8173/drivers/rtc/rtc.c @@ -5,66 +5,11 @@ */ #include <assert.h> - #include <common/debug.h> -#include <drivers/delay_timer.h> #include <mt8173_def.h> -#include <pmic_wrap_init.h> #include <rtc.h> -/* RTC busy status polling interval and retry count */ -enum { - RTC_WRTGR_POLLING_DELAY_MS = 10, - RTC_WRTGR_POLLING_CNT = 100 -}; - -static uint16_t RTC_Read(uint32_t addr) -{ - uint32_t rdata = 0; - - pwrap_read((uint32_t)addr, &rdata); - return (uint16_t)rdata; -} - -static void RTC_Write(uint32_t addr, uint16_t data) -{ - pwrap_write((uint32_t)addr, (uint32_t)data); -} - -static inline int32_t rtc_busy_wait(void) -{ - uint64_t retry = RTC_WRTGR_POLLING_CNT; - - do { - mdelay(RTC_WRTGR_POLLING_DELAY_MS); - if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) - return 1; - retry--; - } while (retry); - - ERROR("[RTC] rtc cbusy time out!\n"); - return 0; -} - -static int32_t Write_trigger(void) -{ - RTC_Write(RTC_WRTGR, 1); - return rtc_busy_wait(); -} - -static int32_t Writeif_unlock(void) -{ - RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); - if (!Write_trigger()) - return 0; - RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); - if (!Write_trigger()) - return 0; - - return 1; -} - void rtc_bbpu_power_down(void) { uint16_t bbpu; @@ -73,7 +18,7 @@ void rtc_bbpu_power_down(void) bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN; if (Writeif_unlock()) { RTC_Write(RTC_BBPU, bbpu); - if (!Write_trigger()) + if (!RTC_Write_Trigger()) assert(0); } else { assert(0); diff --git a/plat/mediatek/mt8173/drivers/rtc/rtc.h b/plat/mediatek/mt8173/drivers/rtc/rtc.h index 9c4ca49a..f60a4c18 100644 --- a/plat/mediatek/mt8173/drivers/rtc/rtc.h +++ b/plat/mediatek/mt8173/drivers/rtc/rtc.h @@ -49,6 +49,12 @@ enum { RTC_BBPU_KEY = 0x43 << 8 }; +/* external API */ +uint16_t RTC_Read(uint32_t addr); +void RTC_Write(uint32_t addr, uint16_t data); +int32_t rtc_busy_wait(void); +int32_t RTC_Write_Trigger(void); +int32_t Writeif_unlock(void); void rtc_bbpu_power_down(void); #endif /* RTC_H */ diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index e5eca9fc..a66c49bb 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -35,6 +35,8 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ + ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ + ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ @@ -42,7 +44,6 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/drivers/crypt/crypt.c \ ${MTK_PLAT_SOC}/drivers/mtcmos/mtcmos.c \ - ${MTK_PLAT_SOC}/drivers/pmic/pmic_wrap_init.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ ${MTK_PLAT_SOC}/drivers/spm/spm.c \ ${MTK_PLAT_SOC}/drivers/spm/spm_hotplug.c \ diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index 337470ab..ec387f4d 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -16,6 +16,7 @@ #include <mt_gic_v3.h> #include <lib/coreboot.h> #include <lib/mmio.h> +#include <mtk_mcdi.h> #include <mtk_plat_common.h> #include <mtspmc.h> #include <plat_debug.h> @@ -23,6 +24,7 @@ #include <plat_private.h> #include <platform_def.h> #include <scu.h> +#include <spm.h> #include <drivers/ti/uart/uart_16550.h> static entry_point_info_t bl32_ep_info; @@ -32,15 +34,49 @@ static void platform_setup_cpu(void) { mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); - VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config)); - VERBOSE("addr of sync_dcm_config: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config)); - - VERBOSE("mp0_spmc: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl)); - VERBOSE("mp1_spmc: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl)); + /* Mcusys dcm control */ + /* Enable pll plldiv dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, + BUS_PLLDIV_DCM); + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, + MP0_PLLDIV_DCM); + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, + MP2_PLLDIV_DCM); + /* Enable mscib dcm */ + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, + MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, + MCSIB_DCM_MASK, MCSIB_DCM); + /* Enable adb400 dcm */ + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, + CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); + /* Enable bus clock dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, + MCU_BUS_DCM); + /* Enable bus fabric dcm */ + mmio_clrsetbits_32( + (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, + MCUSYS_BUS_FABRIC_DCM_MASK, + MCUSYS_BUS_FABRIC_DCM); + /* Enable l2c sram dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, + L2C_SRAM_DCM); + /* Enable busmp0 sync dcm */ + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, + SYNC_DCM_MASK, SYNC_DCM); + /* Enable cntvalue dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, + CNTVALUEB_DCM); + /* Enable dcm cluster stall */ + mmio_clrsetbits_32( + (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, + MCUSYS_MAX_ACCESS_LATENCY_MASK, + MCUSYS_MAX_ACCESS_LATENCY); + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, + MCU0_SYNC_DCM_STALL_WR_EN); + /* Enable rgu dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, + CPUSYS_RGU_DCM_CINFIG); } /******************************************************************************* @@ -112,6 +148,8 @@ void bl31_platform_setup(void) #if SPMC_MODE == 1 spmc_init(); #endif + spm_boot_init(); + mcdi_init(); } /******************************************************************************* diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c new file mode 100644 index 00000000..29eebcb9 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <sspm_reg.h> +#include <mtk_mcdi.h> + +static inline uint32_t mcdi_mbox_read(uint32_t id) +{ + return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2)); +} + +static inline void mcdi_mbox_write(uint32_t id, uint32_t val) +{ + mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val); +} + +void sspm_set_bootaddr(uint32_t bootaddr) +{ + mcdi_mbox_write(MCDI_MBOX_BOOTADDR, bootaddr); +} + +void sspm_cluster_pwr_off_notify(uint32_t cluster) +{ + mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 1); +} + +void sspm_cluster_pwr_on_notify(uint32_t cluster) +{ + mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 0); +} + +void sspm_standbywfi_irq_enable(uint32_t cpu_idx) +{ + mmio_write_32(SSPM_CFGREG_ACAO_INT_SET, STANDBYWFI_EN(cpu_idx)); +} + +uint32_t mcdi_avail_cpu_mask_read(void) +{ + return mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK); +} + +uint32_t mcdi_avail_cpu_mask_write(uint32_t mask) +{ + mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask); + + return mask; +} + +uint32_t mcdi_avail_cpu_mask_set(uint32_t mask) +{ + uint32_t m; + + m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK); + m |= mask; + mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m); + + return m; +} + +uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask) +{ + uint32_t m; + + m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK); + m &= ~mask; + mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m); + + return m; +} + +uint32_t mcdi_cpu_cluster_pwr_stat_read(void) +{ + return mcdi_mbox_read(MCDI_MBOX_CPU_CLUSTER_PWR_STAT); +} + +#define PAUSE_BIT 1 +#define CLUSTER_OFF_OFS 20 +#define CPU_OFF_OFS 24 +#define CLUSTER_ON_OFS 4 +#define CPU_ON_OFS 8 + +static uint32_t target_mask(int cluster, int cpu_idx, bool on) +{ + uint32_t t = 0; + + if (on) { + if (cluster >= 0) + t |= BIT(cluster + CLUSTER_ON_OFS); + + if (cpu_idx >= 0) + t |= BIT(cpu_idx + CPU_ON_OFS); + } else { + if (cluster >= 0) + t |= BIT(cluster + CLUSTER_OFF_OFS); + + if (cpu_idx >= 0) + t |= BIT(cpu_idx + CPU_OFF_OFS); + } + + return t; +} + +void mcdi_pause_clr(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION); + + m &= ~tgt; + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); +} + +void mcdi_pause_set(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION); + uint32_t tgtn = target_mask(-1, cpu_idx, !on); + + /* request on and off at the same time to ensure it can be paused */ + m |= tgt | tgtn; + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + /* wait pause_ack */ + while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK)) + ; + + /* clear non-requested operation */ + m &= ~tgtn; + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); +} + +void mcdi_pause(void) +{ + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT); + + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + /* wait pause_ack */ + while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK)) + ; +} + +void mcdi_unpause(void) +{ + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT); + + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); +} + +void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + /* wait until ack */ + while (!(ack & tgt)) + ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); +} + +void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t tgt_cpu = target_mask(-1, cpu_idx, on); + uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD); + uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + if (!(cmd & tgt)) + return; + + /* wait until ack */ + while (!(ack & tgt_cpu)) + ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + cmd &= ~tgt; + mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd); +} + +void mcdi_hotplug_set(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t tgt_cpu = target_mask(-1, cpu_idx, on); + uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD); + uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + if ((cmd & tgt) == tgt) + return; + + /* wait until ack clear */ + while (ack & tgt_cpu) + ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + cmd |= tgt; + mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd); +} + +bool check_mcdi_ctl_stat(void) +{ + uint32_t clk_regs[] = {0x100010ac, 0x100010c8}; + uint32_t clk_mask[] = {0x00028000, 0x00000018}; + uint32_t tgt = target_mask(0, 0, true); + uint32_t m; + int i; + + /* check clk status */ + for (i = 0; i < ARRAY_SIZE(clk_regs); i++) { + if (mmio_read_32(clk_regs[i]) & clk_mask[i]) { + WARN("mcdi: clk check fail.\n"); + return false; + } + } + + /* check mcdi cmd handling */ + m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT); + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + i = 500; + while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK) && --i > 0) + udelay(10); + + m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT); + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + if (i == 0) { + WARN("mcdi: pause_action fail.\n"); + return false; + } + + /* check mcdi cmd handling */ + if (mcdi_mbox_read(MCDI_MBOX_HP_CMD) || + mcdi_mbox_read(MCDI_MBOX_HP_ACK)) { + WARN("mcdi: hp_cmd fail.\n"); + return false; + } + + mcdi_mbox_write(MCDI_MBOX_HP_CMD, tgt); + + i = 500; + while ((mcdi_mbox_read(MCDI_MBOX_HP_ACK) & tgt) != tgt && --i > 0) + udelay(10); + + mcdi_mbox_write(MCDI_MBOX_HP_CMD, 0); + + if (i == 0) { + WARN("mcdi: hp_ack fail.\n"); + return false; + } + + return true; +} + +void mcdi_init(void) +{ + mcdi_avail_cpu_mask_write(0x01); /* cpu0 default on */ +} diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h new file mode 100644 index 00000000..9a40df1c --- /dev/null +++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_MCDI_H__ +#define __MTK_MCDI_H__ + +#include <stdbool.h> + +void sspm_set_bootaddr(uint32_t bootaddr); +void sspm_standbywfi_irq_enable(uint32_t cpu_idx); +void sspm_cluster_pwr_off_notify(uint32_t cluster); +void sspm_cluster_pwr_on_notify(uint32_t cluster); + +uint32_t mcdi_avail_cpu_mask_read(void); +uint32_t mcdi_avail_cpu_mask_write(uint32_t mask); +uint32_t mcdi_avail_cpu_mask_set(uint32_t mask); +uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask); +uint32_t mcdi_cpu_cluster_pwr_stat_read(void); + +void mcdi_pause(void); +void mcdi_unpause(void); +void mcdi_pause_set(int cluster, int cpu_idx, bool on); +void mcdi_pause_clr(int cluster, int cpu_idx, bool on); +void mcdi_hotplug_set(int cluster, int cpu_idx, bool on); +void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on); +void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on); + +bool check_mcdi_ctl_stat(void); +void mcdi_init(void); + +#endif /* __MTK_MCDI_H__ */ diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.c b/plat/mediatek/mt8183/drivers/pmic/pmic.c index 818c1493..b0f898e2 100644 --- a/plat/mediatek/mt8183/drivers/pmic/pmic.c +++ b/plat/mediatek/mt8183/drivers/pmic/pmic.c @@ -7,6 +7,24 @@ #include <pmic_wrap_init.h> #include <pmic.h> +void bcpu_enable(uint32_t en) +{ + pwrap_write(PMIC_VPROC11_OP_EN, 0x1); + if (en) + pwrap_write(PMIC_VPROC11_CON0, 1); + else + pwrap_write(PMIC_VPROC11_CON0, 0); +} + +void bcpu_sram_enable(uint32_t en) +{ + pwrap_write(PMIC_VSRAM_PROC11_OP_EN, 0x1); + if (en) + pwrap_write(PMIC_VSRAM_PROC11_CON0, 1); + else + pwrap_write(PMIC_VSRAM_PROC11_CON0, 0); +} + void wk_pmic_enable_sdn_delay(void) { uint32_t con; diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.h b/plat/mediatek/mt8183/drivers/pmic/pmic.h index d62c6daf..f19f9f6e 100644 --- a/plat/mediatek/mt8183/drivers/pmic/pmic.h +++ b/plat/mediatek/mt8183/drivers/pmic/pmic.h @@ -10,7 +10,11 @@ enum { PMIC_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, - PMIC_PSEQ_ELR11 = 0x0a62 + PMIC_PSEQ_ELR11 = 0x0a62, + PMIC_VPROC11_CON0 = 0x1388, + PMIC_VPROC11_OP_EN = 0x1390, + PMIC_VSRAM_PROC11_CON0 = 0x1b46, + PMIC_VSRAM_PROC11_OP_EN = 0x1b4e }; enum { @@ -18,6 +22,8 @@ enum { }; /* external API */ +void bcpu_enable(uint32_t en); +void bcpu_sram_enable(uint32_t en); void wk_pmic_enable_sdn_delay(void); void pmic_power_off(void); diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c new file mode 100644 index 00000000..dcafd55f --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm.c @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <lib/bakery_lock.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <spm.h> +#include <spm_pmic_wrap.h> + +DEFINE_BAKERY_LOCK(spm_lock); + +const char *wakeup_src_str[32] = { + [0] = "R12_PCM_TIMER", + [1] = "R12_SSPM_WDT_EVENT_B", + [2] = "R12_KP_IRQ_B", + [3] = "R12_APWDT_EVENT_B", + [4] = "R12_APXGPT1_EVENT_B", + [5] = "R12_CONN2AP_SPM_WAKEUP_B", + [6] = "R12_EINT_EVENT_B", + [7] = "R12_CONN_WDT_IRQ_B", + [8] = "R12_CCIF0_EVENT_B", + [9] = "R12_LOWBATTERY_IRQ_B", + [10] = "R12_SSPM_SPM_IRQ_B", + [11] = "R12_SCP_SPM_IRQ_B", + [12] = "R12_SCP_WDT_EVENT_B", + [13] = "R12_PCM_WDT_WAKEUP_B", + [14] = "R12_USB_CDSC_B ", + [15] = "R12_USB_POWERDWN_B", + [16] = "R12_SYS_TIMER_EVENT_B", + [17] = "R12_EINT_EVENT_SECURE_B", + [18] = "R12_CCIF1_EVENT_B", + [19] = "R12_UART0_IRQ_B", + [20] = "R12_AFE_IRQ_MCU_B", + [21] = "R12_THERM_CTRL_EVENT_B", + [22] = "R12_SYS_CIRQ_IRQ_B", + [23] = "R12_MD2AP_PEER_EVENT_B", + [24] = "R12_CSYSPWREQ_B", + [25] = "R12_MD1_WDT_B ", + [26] = "R12_CLDMA_EVENT_B", + [27] = "R12_SEJ_WDT_GPT_B", + [28] = "R12_ALL_SSPM_WAKEUP_B", + [29] = "R12_CPU_IRQ_B", + [30] = "R12_CPU_WFI_AND_B" +}; + +const char *spm_get_firmware_version(void) +{ + return "DYNAMIC_SPM_FW_VERSION"; +} + +void spm_lock_init(void) +{ + bakery_lock_init(&spm_lock); +} + +void spm_lock_get(void) +{ + bakery_lock_get(&spm_lock); +} + +void spm_lock_release(void) +{ + bakery_lock_release(&spm_lock); +} + +void spm_set_bootaddr(unsigned long bootaddr) +{ + /* initialize core4~7 boot entry address */ + mmio_write_32(SW2SPM_MAILBOX_3, bootaddr); +} + +void spm_set_cpu_status(int cpu) +{ + if (cpu >= 0 && cpu < 4) { + mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204); + mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4)); + } else if (cpu >= 4 && cpu < 8) { + mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218); + mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4)); + } else { + ERROR("%s: error cpu number %d\n", __func__, cpu); + } +} + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + mmio_write_32(SPM_AP_STANDBY_CON, + ((pwrctrl->wfi_op & 0x1) << 0) | + ((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) | + ((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->mm_mask_b & 0x3) << 16) | + ((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) | + ((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) | + ((pwrctrl->md_mask_b & 0x3) << 20) | + ((pwrctrl->sspm_mask_b & 0x1) << 22) | + ((pwrctrl->scp_mask_b & 0x1) << 23) | + ((pwrctrl->srcclkeni_mask_b & 0x1) << 24) | + ((pwrctrl->md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) | + ((pwrctrl->conn_mask_b & 0x1) << 28) | + ((pwrctrl->conn_apsrc_sel & 0x1) << 29)); + + mmio_write_32(SPM_SRC_REQ, + ((pwrctrl->spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->spm_f26m_req & 0x1) << 1) | + ((pwrctrl->spm_infra_req & 0x1) << 3) | + ((pwrctrl->spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->spm_ddren_req & 0x1) << 7) | + ((pwrctrl->spm_rsv_src_req & 0x7) << 8) | + ((pwrctrl->spm_ddren_2_req & 0x1) << 11) | + ((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16)); + + mmio_write_32(SPM_SRC_MASK, + ((pwrctrl->csyspwreq_mask & 0x1) << 0) | + ((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) | + ((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) | + ((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) | + ((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) | + ((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) | + ((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) | + ((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) | + ((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) | + ((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) | + ((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) | + ((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) | + ((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) | + ((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) | + ((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) | + ((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) | + ((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) | + ((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) | + ((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->mfg_req_mask_b & 0x1) << 26) | + ((pwrctrl->vdec_req_mask_b & 0x1) << 27)); + + mmio_write_32(SPM_SRC2_MASK, + ((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) | + ((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) | + ((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) | + ((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) | + ((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) | + ((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) | + ((pwrctrl->gce_ddren_mask_b & 0x1) << 7) | + ((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1) + << 8) | + ((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1) + << 9)); + + mmio_write_32(SPM_WAKEUP_EVENT_MASK, + ((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0)); + + mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, + ((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff) + << 0)); + + mmio_write_32(SPM_SRC3_MASK, + ((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) | + ((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) | + ((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) | + ((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) | + ((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) | + ((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) | + ((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) | + ((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1) + << 8) | + ((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1) + << 9)); + + mmio_write_32(MP0_CPU0_WFI_EN, + ((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0)); + mmio_write_32(MP0_CPU1_WFI_EN, + ((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0)); + mmio_write_32(MP0_CPU2_WFI_EN, + ((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0)); + mmio_write_32(MP0_CPU3_WFI_EN, + ((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0)); + + mmio_write_32(MP1_CPU0_WFI_EN, + ((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0)); + mmio_write_32(MP1_CPU1_WFI_EN, + ((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0)); + mmio_write_32(MP1_CPU2_WFI_EN, + ((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0)); + mmio_write_32(MP1_CPU3_WFI_EN, + ((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0)); +} + +void spm_disable_pcm_timer(void) +{ + mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + uint32_t val, mask, isr; + + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + mmio_write_32(PCM_TIMER_VAL, val); + mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); + + mask = pwrctrl->wake_src; + + if (pwrctrl->csyspwreq_mask) + mask &= ~WAKE_SRC_R12_CSYSPWREQ_B; + + mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); + + isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB; + mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX); +} + +void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +{ + mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags); + mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1); +} + +void spm_set_pcm_wdt(int en) +{ + if (en) { + mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, + SPM_REGWR_CFG_KEY); + + if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) + mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); + mmio_write_32(PCM_WDT_VAL, + mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); + mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); + } else { + mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, + SPM_REGWR_CFG_KEY); + } +} + +void spm_send_cpu_wakeup_event(void) +{ + mmio_write_32(PCM_REG_DATA_INI, 0); + mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); +} + +void spm_get_wakeup_status(struct wake_status *wakesta) +{ + wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI); + wakesta->r12 = mmio_read_32(SPM_SW_RSV_0); + wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA); + wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); + wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); + wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR); + wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR); + wakesta->r13 = mmio_read_32(PCM_REG13_DATA); + wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); + wakesta->req_sta = mmio_read_32(SRC_REQ_STA); + wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG); + wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2); + wakesta->r15 = mmio_read_32(PCM_REG15_DATA); + wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG); + wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX); + wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR); + wakesta->isr = mmio_read_32(SPM_IRQ_STA); +} + +void spm_clean_after_wakeup(void) +{ + mmio_write_32(SPM_SW_RSV_0, + mmio_read_32(SPM_WAKEUP_STA) | + mmio_read_32(SPM_SW_RSV_0)); + mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); + mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0); + mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); + mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); + mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); +} + +void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario) +{ + uint32_t i; + + if (wakesta->assert_pc != 0) { + INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n", + scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON)); + goto spm_debug_flags; + } + + for (i = 0; i <= 31; i++) { + if (wakesta->r12 & (1U << i)) { + INFO("%s: wake up by %s, timer_out = %u\n", + scenario, wakeup_src_str[i], wakesta->timer_out); + break; + } + } + +spm_debug_flags: + INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", + wakesta->r15, wakesta->r13, wakesta->debug_flag, + wakesta->debug_flag1); + INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n", + wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12, + wakesta->r12_ext); + INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n", + wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg); + INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n", + wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta); + INFO("wake_misc = 0x%x\n", wakesta->wake_misc); +} + +void spm_boot_init(void) +{ + NOTICE("%s() start\n", __func__); + + spm_lock_init(); + mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); + + NOTICE("%s() end\n", __func__); +} diff --git a/plat/mediatek/mt8183/drivers/spm/spm.h b/plat/mediatek/mt8183/drivers/spm/spm.h new file mode 100644 index 00000000..b2e83dc7 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm.h @@ -0,0 +1,2552 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_H +#define SPM_H + +/************************************** + * Define and Declare + **************************************/ + +#define POWERON_CONFIG_EN (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) +#define SPM_CLK_CON (SPM_BASE + 0x00C) +#define SPM_CLK_SETTLE (SPM_BASE + 0x010) +#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) +#define PCM_CON0 (SPM_BASE + 0x018) +#define PCM_CON1 (SPM_BASE + 0x01C) +#define PCM_IM_PTR (SPM_BASE + 0x020) +#define PCM_IM_LEN (SPM_BASE + 0x024) +#define PCM_REG_DATA_INI (SPM_BASE + 0x028) +#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) +#define PCM_TIMER_VAL (SPM_BASE + 0x030) +#define PCM_WDT_VAL (SPM_BASE + 0x034) +#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) +#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) +#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) +#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) +#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) +#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) +#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) +#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) +#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) +#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) +#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) +#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) +#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) +#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) +#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) +#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) +#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) +#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) +#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) +#define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) +#define SPM_SWINT (SPM_BASE + 0x08C) +#define SPM_SWINT_SET (SPM_BASE + 0x090) +#define SPM_SWINT_CLR (SPM_BASE + 0x094) +#define SPM_SCP_MAILBOX (SPM_BASE + 0x098) +#define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) +#define SPM_TWAM_CON (SPM_BASE + 0x0A0) +#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) +#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) +#define SPM_SCP_IRQ (SPM_BASE + 0x0AC) +#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) +#define SPM_IRQ_MASK (SPM_BASE + 0x0B4) +#define SPM_SRC_REQ (SPM_BASE + 0x0B8) +#define SPM_SRC_MASK (SPM_BASE + 0x0BC) +#define SPM_SRC2_MASK (SPM_BASE + 0x0C0) +#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) +#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) +#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0CC) +#define SCP_CLK_CON (SPM_BASE + 0x0D0) +#define PCM_DEBUG_CON (SPM_BASE + 0x0D4) +#define DDR_EN_DBC_LEN (SPM_BASE + 0x0D8) +#define AHB_BUS_CON (SPM_BASE + 0x0DC) +#define SPM_SRC3_MASK (SPM_BASE + 0x0E0) +#define DDR_EN_EMI_DBC_CON (SPM_BASE + 0x0E4) +#define SSPM_CLK_CON (SPM_BASE + 0x0E8) +#define PCM_REG0_DATA (SPM_BASE + 0x100) +#define PCM_REG1_DATA (SPM_BASE + 0x104) +#define PCM_REG2_DATA (SPM_BASE + 0x108) +#define PCM_REG3_DATA (SPM_BASE + 0x10C) +#define PCM_REG4_DATA (SPM_BASE + 0x110) +#define PCM_REG5_DATA (SPM_BASE + 0x114) +#define PCM_REG6_DATA (SPM_BASE + 0x118) +#define PCM_REG7_DATA (SPM_BASE + 0x11C) +#define PCM_REG8_DATA (SPM_BASE + 0x120) +#define PCM_REG9_DATA (SPM_BASE + 0x124) +#define PCM_REG10_DATA (SPM_BASE + 0x128) +#define PCM_REG11_DATA (SPM_BASE + 0x12C) +#define PCM_REG12_DATA (SPM_BASE + 0x130) +#define PCM_REG13_DATA (SPM_BASE + 0x134) +#define PCM_REG14_DATA (SPM_BASE + 0x138) +#define PCM_REG15_DATA (SPM_BASE + 0x13C) +#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) +#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) +#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) +#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) +#define PCM_TIMER_OUT (SPM_BASE + 0x150) +#define PCM_WDT_OUT (SPM_BASE + 0x154) +#define SPM_IRQ_STA (SPM_BASE + 0x158) +#define SPM_WAKEUP_STA (SPM_BASE + 0x15C) +#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) +#define SPM_WAKEUP_MISC (SPM_BASE + 0x164) +#define BUS_PROTECT_RDY (SPM_BASE + 0x168) +#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) +#define SUBSYS_IDLE_STA (SPM_BASE + 0x170) +#define CPU_IDLE_STA (SPM_BASE + 0x174) +#define PCM_FSM_STA (SPM_BASE + 0x178) +#define SRC_REQ_STA (SPM_BASE + 0x17C) +#define PWR_STATUS (SPM_BASE + 0x180) +#define PWR_STATUS_2ND (SPM_BASE + 0x184) +#define CPU_PWR_STATUS (SPM_BASE + 0x188) +#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) +#define MISC_STA (SPM_BASE + 0x190) +#define SPM_SRC_RDY_STA (SPM_BASE + 0x194) +#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) +#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) +#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) +#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) +#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) +#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) +#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) +#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) +#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) +#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) +#define SPM_DVFS_STA (SPM_BASE + 0x1C8) +#define BUS_PROTECT3_RDY (SPM_BASE + 0x1CC) +#define SRC_DDREN_STA (SPM_BASE + 0x1E0) +#define MCU_PWR_CON (SPM_BASE + 0x200) +#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) +#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) +#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) +#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) +#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) +#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) +#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) +#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) +#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) +#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) +#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) +#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) +#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) +#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) +#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) +#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) +#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) +#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) +#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) +#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) +#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) +#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) +#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) +#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) +#define BYPASS_SPMC (SPM_BASE + 0x2B4) +#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) +#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) +#define SPMC_IN_RET (SPM_BASE + 0x2C0) +#define VDE_PWR_CON (SPM_BASE + 0x300) +#define VEN_PWR_CON (SPM_BASE + 0x304) +#define ISP_PWR_CON (SPM_BASE + 0x308) +#define DIS_PWR_CON (SPM_BASE + 0x30C) +#define MFG_CORE1_PWR_CON (SPM_BASE + 0x310) +#define AUDIO_PWR_CON (SPM_BASE + 0x314) +#define IFR_PWR_CON (SPM_BASE + 0x318) +#define DPY_PWR_CON (SPM_BASE + 0x31C) +#define MD1_PWR_CON (SPM_BASE + 0x320) +#define VPU_TOP_PWR_CON (SPM_BASE + 0x324) +#define CONN_PWR_CON (SPM_BASE + 0x32C) +#define VPU_CORE2_PWR_CON (SPM_BASE + 0x330) +#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) +#define MFG_PWR_CON (SPM_BASE + 0x338) +#define VPU_CORE0_PWR_CON (SPM_BASE + 0x33C) +#define VPU_CORE1_PWR_CON (SPM_BASE + 0x340) +#define CAM_PWR_CON (SPM_BASE + 0x344) +#define MFG_2D_PWR_CON (SPM_BASE + 0x348) +#define MFG_CORE0_PWR_CON (SPM_BASE + 0x34C) +#define SYSRAM_CON (SPM_BASE + 0x350) +#define SYSROM_CON (SPM_BASE + 0x354) +#define SSPM_SRAM_CON (SPM_BASE + 0x358) +#define SCP_SRAM_CON (SPM_BASE + 0x35C) +#define UFS_SRAM_CON (SPM_BASE + 0x36C) +#define DUMMY_SRAM_CON (SPM_BASE + 0x380) +#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x390) +#define MD_SRAM_ISO_CON (SPM_BASE + 0x394) +#define MD_EXTRA_PWR_CON (SPM_BASE + 0x398) +#define EXT_BUCK_CON (SPM_BASE + 0x3A0) +#define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x3D0) +#define SPM_DVFS_CON (SPM_BASE + 0x400) +#define SPM_MDBSI_CON (SPM_BASE + 0x404) +#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) +#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) +#define SPM_BSI_GEN (SPM_BASE + 0x410) +#define SPM_BSI_EN_SR (SPM_BASE + 0x414) +#define SPM_BSI_CLK_SR (SPM_BASE + 0x418) +#define SPM_BSI_D0_SR (SPM_BASE + 0x41C) +#define SPM_BSI_D1_SR (SPM_BASE + 0x420) +#define SPM_BSI_D2_SR (SPM_BASE + 0x424) +#define SPM_AP_SEMA (SPM_BASE + 0x428) +#define SPM_SPM_SEMA (SPM_BASE + 0x42C) +#define AP_MDSRC_REQ (SPM_BASE + 0x430) +#define SPM2MD_DVFS_CON (SPM_BASE + 0x438) +#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) +#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) +#define DPY_LP_CON (SPM_BASE + 0x444) +#define CPU_DVFS_REQ (SPM_BASE + 0x448) +#define SPM_PLL_CON (SPM_BASE + 0x44C) +#define SPM_EMI_BW_MODE (SPM_BASE + 0x450) +#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) +#define ULPOSC_CON (SPM_BASE + 0x458) +#define SPM2MM_CON (SPM_BASE + 0x45C) +#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) +#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) +#define SPM_S1_MODE_CH (SPM_BASE + 0x468) +#define EMI_SELF_REFRESH_CH_STA (SPM_BASE + 0x46C) +#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) +#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) +#define DRAMC_DMYRD_CON (SPM_BASE + 0x478) +#define SPM_DRS_CON (SPM_BASE + 0x47C) +#define SPM_SEMA_M0 (SPM_BASE + 0x480) +#define SPM_SEMA_M1 (SPM_BASE + 0x484) +#define SPM_SEMA_M2 (SPM_BASE + 0x488) +#define SPM_SEMA_M3 (SPM_BASE + 0x48C) +#define SPM_SEMA_M4 (SPM_BASE + 0x490) +#define SPM_SEMA_M5 (SPM_BASE + 0x494) +#define SPM_SEMA_M6 (SPM_BASE + 0x498) +#define SPM_SEMA_M7 (SPM_BASE + 0x49C) +#define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x4A0) +#define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x4A4) +#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) +#define SRAM_DREQ_CON (SPM_BASE + 0x4B0) +#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) +#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) +#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x4BC) +#define SPM_SSPM_IRQ (SPM_BASE + 0x4C0) +#define SPM2PMCU_INT (SPM_BASE + 0x4C4) +#define SPM2PMCU_INT_SET (SPM_BASE + 0x4C8) +#define SPM2PMCU_INT_CLR (SPM_BASE + 0x4CC) +#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x4D0) +#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x4D4) +#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x4D8) +#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x4DC) +#define PMCU2SPM_INT (SPM_BASE + 0x4E0) +#define PMCU2SPM_INT_SET (SPM_BASE + 0x4E4) +#define PMCU2SPM_INT_CLR (SPM_BASE + 0x4E8) +#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x4EC) +#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x4F0) +#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x4F4) +#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x4F8) +#define PMCU2SPM_CFG (SPM_BASE + 0x4FC) +#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) +#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) +#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) +#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) +#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) +#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) +#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) +#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) +#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) +#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) +#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) +#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) +#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) +#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) +#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) +#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) +#define MP0_L2CFLUSH (SPM_BASE + 0x554) +#define MP1_L2CFLUSH (SPM_BASE + 0x558) +#define CPU_PTPOD2_CON (SPM_BASE + 0x560) +#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) +#define ROOT_CORE_ADDR (SPM_BASE + 0x574) +#define CPU_SPARE_CON (SPM_BASE + 0x580) +#define CPU_SPARE_CON_SET (SPM_BASE + 0x584) +#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) +#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0) +#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x5D4) +#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x5D8) +#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x5DC) +#define SW2SPM_INT (SPM_BASE + 0x5E0) +#define SW2SPM_INT_SET (SPM_BASE + 0x5E4) +#define SW2SPM_INT_CLR (SPM_BASE + 0x5E8) +#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x5EC) +#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x5F0) +#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x5F4) +#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x5F8) +#define SW2SPM_CFG (SPM_BASE + 0x5FC) +#define SPM_SW_FLAG (SPM_BASE + 0x600) +#define SPM_SW_DEBUG (SPM_BASE + 0x604) +#define SPM_SW_RSV_0 (SPM_BASE + 0x608) +#define SPM_SW_RSV_1 (SPM_BASE + 0x60C) +#define SPM_SW_RSV_2 (SPM_BASE + 0x610) +#define SPM_SW_RSV_3 (SPM_BASE + 0x614) +#define SPM_SW_RSV_4 (SPM_BASE + 0x618) +#define SPM_SW_RSV_5 (SPM_BASE + 0x61C) +#define SPM_RSV_CON (SPM_BASE + 0x620) +#define SPM_RSV_STA (SPM_BASE + 0x624) +#define SPM_RSV_CON1 (SPM_BASE + 0x628) +#define SPM_RSV_STA1 (SPM_BASE + 0x62C) +#define SPM_PASR_DPD_0 (SPM_BASE + 0x630) +#define SPM_PASR_DPD_1 (SPM_BASE + 0x634) +#define SPM_PASR_DPD_2 (SPM_BASE + 0x638) +#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) +#define SPM_SPARE_CON (SPM_BASE + 0x640) +#define SPM_SPARE_CON_SET (SPM_BASE + 0x644) +#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) +#define SPM_SW_RSV_6 (SPM_BASE + 0x64C) +#define SPM_SW_RSV_7 (SPM_BASE + 0x650) +#define SPM_SW_RSV_8 (SPM_BASE + 0x654) +#define SPM_SW_RSV_9 (SPM_BASE + 0x658) +#define SPM_SW_RSV_10 (SPM_BASE + 0x65C) +#define SPM_SW_RSV_18 (SPM_BASE + 0x67C) +#define SPM_SW_RSV_19 (SPM_BASE + 0x680) +#define DVFSRC_EVENT_MASK_CON (SPM_BASE + 0x690) +#define DVFSRC_EVENT_FORCE_ON (SPM_BASE + 0x694) +#define DVFSRC_EVENT_SEL (SPM_BASE + 0x698) +#define SPM_DVFS_EVENT_STA (SPM_BASE + 0x69C) +#define SPM_DVFS_EVENT_STA1 (SPM_BASE + 0x6A0) +#define SPM_DVFS_LEVEL (SPM_BASE + 0x6A4) +#define DVFS_ABORT_STA (SPM_BASE + 0x6A8) +#define DVFS_ABORT_OTHERS_MASK (SPM_BASE + 0x6AC) +#define SPM_DFS_LEVEL (SPM_BASE + 0x6B0) +#define SPM_DVS_LEVEL (SPM_BASE + 0x6B4) +#define SPM_DVFS_MISC (SPM_BASE + 0x6B8) +#define SPARE_SRC_REQ_MASK (SPM_BASE + 0x6C0) +#define SCP_VCORE_LEVEL (SPM_BASE + 0x6C4) +#define SC_MM_CK_SEL_CON (SPM_BASE + 0x6C8) +#define SPARE_ACK_STA (SPM_BASE + 0x6F0) +#define SPARE_ACK_MASK (SPM_BASE + 0x6F4) +#define SPM_DVFS_CON1 (SPM_BASE + 0x700) +#define SPM_DVFS_CON1_STA (SPM_BASE + 0x704) +#define SPM_DVFS_CMD0 (SPM_BASE + 0x710) +#define SPM_DVFS_CMD1 (SPM_BASE + 0x714) +#define SPM_DVFS_CMD2 (SPM_BASE + 0x718) +#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) +#define SPM_DVFS_CMD4 (SPM_BASE + 0x720) +#define SPM_DVFS_CMD5 (SPM_BASE + 0x724) +#define SPM_DVFS_CMD6 (SPM_BASE + 0x728) +#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) +#define SPM_DVFS_CMD8 (SPM_BASE + 0x730) +#define SPM_DVFS_CMD9 (SPM_BASE + 0x734) +#define SPM_DVFS_CMD10 (SPM_BASE + 0x738) +#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) +#define SPM_DVFS_CMD12 (SPM_BASE + 0x740) +#define SPM_DVFS_CMD13 (SPM_BASE + 0x744) +#define SPM_DVFS_CMD14 (SPM_BASE + 0x748) +#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) +#define WDT_LATCH_SPARE0_FIX (SPM_BASE + 0x780) +#define WDT_LATCH_SPARE1_FIX (SPM_BASE + 0x784) +#define WDT_LATCH_SPARE2_FIX (SPM_BASE + 0x788) +#define WDT_LATCH_SPARE3_FIX (SPM_BASE + 0x78C) +#define SPARE_ACK_IN_FIX (SPM_BASE + 0x790) +#define DCHA_LATCH_RSV0_FIX (SPM_BASE + 0x794) +#define DCHB_LATCH_RSV0_FIX (SPM_BASE + 0x798) +#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) +#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) +#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) +#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) +#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) +#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) +#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) +#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) +#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) +#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) +#define WDT_LATCH_SPARE0 (SPM_BASE + 0x828) +#define WDT_LATCH_SPARE1 (SPM_BASE + 0x82C) +#define WDT_LATCH_SPARE2 (SPM_BASE + 0x830) +#define WDT_LATCH_SPARE3 (SPM_BASE + 0x834) +#define PCM_WDT_LATCH_10 (SPM_BASE + 0x838) +#define PCM_WDT_LATCH_11 (SPM_BASE + 0x83C) +#define DCHA_GATING_LATCH_0 (SPM_BASE + 0x840) +#define DCHA_GATING_LATCH_1 (SPM_BASE + 0x844) +#define DCHA_GATING_LATCH_2 (SPM_BASE + 0x848) +#define DCHA_GATING_LATCH_3 (SPM_BASE + 0x84C) +#define DCHA_GATING_LATCH_4 (SPM_BASE + 0x850) +#define DCHA_GATING_LATCH_5 (SPM_BASE + 0x854) +#define DCHA_GATING_LATCH_6 (SPM_BASE + 0x858) +#define DCHA_GATING_LATCH_7 (SPM_BASE + 0x85C) +#define DCHB_GATING_LATCH_0 (SPM_BASE + 0x860) +#define DCHB_GATING_LATCH_1 (SPM_BASE + 0x864) +#define DCHB_GATING_LATCH_2 (SPM_BASE + 0x868) +#define DCHB_GATING_LATCH_3 (SPM_BASE + 0x86C) +#define DCHB_GATING_LATCH_4 (SPM_BASE + 0x870) +#define DCHB_GATING_LATCH_5 (SPM_BASE + 0x874) +#define DCHB_GATING_LATCH_6 (SPM_BASE + 0x878) +#define DCHB_GATING_LATCH_7 (SPM_BASE + 0x87C) +#define DCHA_LATCH_RSV0 (SPM_BASE + 0x880) +#define DCHB_LATCH_RSV0 (SPM_BASE + 0x884) +#define PCM_WDT_LATCH_12 (SPM_BASE + 0x888) +#define PCM_WDT_LATCH_13 (SPM_BASE + 0x88C) +#define SPM_PC_TRACE_CON (SPM_BASE + 0x8C0) +#define SPM_PC_TRACE_G0 (SPM_BASE + 0x8C4) +#define SPM_PC_TRACE_G1 (SPM_BASE + 0x8C8) +#define SPM_PC_TRACE_G2 (SPM_BASE + 0x8CC) +#define SPM_PC_TRACE_G3 (SPM_BASE + 0x8D0) +#define SPM_PC_TRACE_G4 (SPM_BASE + 0x8D4) +#define SPM_PC_TRACE_G5 (SPM_BASE + 0x8D8) +#define SPM_PC_TRACE_G6 (SPM_BASE + 0x8DC) +#define SPM_PC_TRACE_G7 (SPM_BASE + 0x8E0) +#define SPM_ACK_CHK_CON (SPM_BASE + 0x900) +#define SPM_ACK_CHK_PC (SPM_BASE + 0x904) +#define SPM_ACK_CHK_SEL (SPM_BASE + 0x908) +#define SPM_ACK_CHK_TIMER (SPM_BASE + 0x90C) +#define SPM_ACK_CHK_STA (SPM_BASE + 0x910) +#define SPM_ACK_CHK_LATCH (SPM_BASE + 0x914) +#define SPM_ACK_CHK_CON2 (SPM_BASE + 0x920) +#define SPM_ACK_CHK_PC2 (SPM_BASE + 0x924) +#define SPM_ACK_CHK_SEL2 (SPM_BASE + 0x928) +#define SPM_ACK_CHK_TIMER2 (SPM_BASE + 0x92C) +#define SPM_ACK_CHK_STA2 (SPM_BASE + 0x930) +#define SPM_ACK_CHK_LATCH2 (SPM_BASE + 0x934) +#define SPM_ACK_CHK_CON3 (SPM_BASE + 0x940) +#define SPM_ACK_CHK_PC3 (SPM_BASE + 0x944) +#define SPM_ACK_CHK_SEL3 (SPM_BASE + 0x948) +#define SPM_ACK_CHK_TIMER3 (SPM_BASE + 0x94C) +#define SPM_ACK_CHK_STA3 (SPM_BASE + 0x950) +#define SPM_ACK_CHK_LATCH3 (SPM_BASE + 0x954) +#define SPM_ACK_CHK_CON4 (SPM_BASE + 0x960) +#define SPM_ACK_CHK_PC4 (SPM_BASE + 0x964) +#define SPM_ACK_CHK_SEL4 (SPM_BASE + 0x968) +#define SPM_ACK_CHK_TIMER4 (SPM_BASE + 0x96C) +#define SPM_ACK_CHK_STA4 (SPM_BASE + 0x970) +#define SPM_ACK_CHK_LATCH4 (SPM_BASE + 0x974) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ +#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ +/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ +#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ +#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ +#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ +#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ +#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ +#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ +/* SPM_CLK_SETTLE (0x10006000+0x010) */ +#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ +/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ +#define WFI_OP_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ +#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ +#define MM_MASK_B_LSB (1U << 16) /* 2b */ +#define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */ +#define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */ +#define MD_MASK_B_LSB (1U << 20) /* 2b */ +#define SSPM_MASK_B_LSB (1U << 22) /* 1b */ +#define SCP_MASK_B_LSB (1U << 23) /* 1b */ +#define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */ +#define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ +#define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ +#define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */ +#define CONN_MASK_B_LSB (1U << 28) /* 1b */ +#define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_IM_PTR (0x10006000+0x020) */ +#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ +/* PCM_IM_LEN (0x10006000+0x024) */ +#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ +/* PCM_REG_DATA_INI (0x10006000+0x028) */ +#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ +/* PCM_PWR_IO_EN (0x10006000+0x02C) */ +#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ +#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ +/* PCM_TIMER_VAL (0x10006000+0x030) */ +#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ +/* PCM_WDT_VAL (0x10006000+0x034) */ +#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ +/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ +#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ +/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ +#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ +#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ +#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ +#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ +#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ +#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ +#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ +#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ +#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ +#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ +#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ +#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ +#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ +#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ +#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ +#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ +#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ +#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ +/* SPM_SRAM_RSV_CON (0x10006000+0x088) */ +#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ +/* SPM_SWINT (0x10006000+0x08C) */ +#define SPM_SWINT_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_SET (0x10006000+0x090) */ +#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_CLR (0x10006000+0x094) */ +#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ +/* SPM_SCP_MAILBOX (0x10006000+0x098) */ +#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ +/* SCP_SPM_MAILBOX (0x10006000+0x09C) */ +#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CON (0x10006000+0x0A0) */ +#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ +#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ +#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ +#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ +#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ +#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ +#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ +#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ +#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ +#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ +#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ +/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ +#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ +#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ +/* SPM_SCP_IRQ (0x10006000+0x0AC) */ +#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ +#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ +#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ +/* SPM_SRC_REQ (0x10006000+0x0B8) */ +#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ +#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ +#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ +#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ +#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ +#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ +#define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */ +#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ +/* SPM_SRC_MASK (0x10006000+0x0BC) */ +#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ +#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ +#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ +#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ +#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ +#define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */ +#define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */ +#define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */ +#define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */ +#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */ +#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */ +#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */ +#define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ +#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */ +#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */ +#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */ +#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */ +#define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ +#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */ +#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */ +#define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ +#define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */ +#define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */ +#define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */ +/* SPM_SRC2_MASK (0x10006000+0x0C0) */ +#define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ +#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */ +#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ +/* SCP_CLK_CON (0x10006000+0x0D0) */ +#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ +#define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */ +#define SCP_SLP_REQ_LSB (1U << 2) /* 1b */ +#define SCP_SLP_ACK_LSB (1U << 3) /* 1b */ +/* PCM_DEBUG_CON (0x10006000+0x0D4) */ +#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ +/* DDR_EN_DBC_LEN (0x10006000+0x0D8) */ +#define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */ +#define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */ +/* AHB_BUS_CON (0x10006000+0x0DC) */ +#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ +#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ +/* SPM_SRC3_MASK (0x10006000+0x0E0) */ +#define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */ +#define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */ +#define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */ +#define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */ +/* SSPM_CLK_CON (0x10006000+0x0E8) */ +#define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */ +/* PCM_REG0_DATA (0x10006000+0x100) */ +#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG1_DATA (0x10006000+0x104) */ +#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG2_DATA (0x10006000+0x108) */ +#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG3_DATA (0x10006000+0x10C) */ +#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG4_DATA (0x10006000+0x110) */ +#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG5_DATA (0x10006000+0x114) */ +#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG6_DATA (0x10006000+0x118) */ +#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG7_DATA (0x10006000+0x11C) */ +#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG8_DATA (0x10006000+0x120) */ +#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG9_DATA (0x10006000+0x124) */ +#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG10_DATA (0x10006000+0x128) */ +#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG11_DATA (0x10006000+0x12C) */ +#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_DATA (0x10006000+0x130) */ +#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG13_DATA (0x10006000+0x134) */ +#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG14_DATA (0x10006000+0x138) */ +#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG15_DATA (0x10006000+0x13C) */ +#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ +#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ +#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ +#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ +#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ +/* PCM_TIMER_OUT (0x10006000+0x150) */ +#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* PCM_WDT_OUT (0x10006000+0x154) */ +#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ +/* SPM_IRQ_STA (0x10006000+0x158) */ +#define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */ +#define TWAM_IRQ_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_LSB (1U << 3) /* 1b */ +/* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */ +/* SPM_WAKEUP_STA (0x10006000+0x15C) */ +#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ +#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_MISC (0x10006000+0x164) */ +#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ +#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ +#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ +/* BUS_PROTECT_RDY (0x10006000+0x168) */ +#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ +#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ +/* SUBSYS_IDLE_STA (0x10006000+0x170) */ +#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ +/* CPU_IDLE_STA (0x10006000+0x174) */ +#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ +#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ +#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ +#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ +#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ +#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ +#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ +#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ +#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ +#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ +#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ +#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ +/* PCM_FSM_STA (0x10006000+0x178) */ +#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ +#define PC_STATE_LSB (1U << 4) /* 3b */ +#define IM_STATE_LSB (1U << 7) /* 3b */ +#define MASTER_STATE_LSB (1U << 10) /* 5b */ +#define EVENT_FSM_LSB (1U << 15) /* 3b */ +#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ +#define PCM_KICK_LSB (1U << 21) /* 1b */ +#define IM_KICK_LSB (1U << 22) /* 1b */ +#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ +#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ +/* SRC_REQ_STA (0x10006000+0x17C) */ +#define SRC_REQ_STA_LSB (1U << 0) /* 32b */ +/* PWR_STATUS (0x10006000+0x180) */ +#define PWR_STATUS_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_2ND (0x10006000+0x184) */ +#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS (0x10006000+0x188) */ +#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ +#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* MISC_STA (0x10006000+0x190) */ +#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ +/* SPM_SRC_RDY_STA (0x10006000+0x194) */ +#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ +#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ +/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ +#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ +#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ +#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ +#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ +#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ +#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ +#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ +#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ +#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ +#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_STA (0x10006000+0x1C8) */ +#define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */ +/* BUS_PROTECT3_RDY (0x10006000+0x1CC) */ +#define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */ +#define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */ +/* SRC_DDREN_STA (0x10006000+0x1E0) */ +#define SRC_DDREN_STA_LSB (1U << 0) /* 32b */ +/* MCU_PWR_CON (0x10006000+0x200) */ +#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ +#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ +#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ +#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ +#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ +#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ +#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ +#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ +#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ +#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ +#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ +#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ +#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ +#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ +#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ +#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ +#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ +#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ +#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ +#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ +#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ +#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ +#define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ +/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ +#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ +#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +/* BYPASS_SPMC (0x10006000+0x2B4) */ +#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ +/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ +#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ +#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ +/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ +#define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */ +#define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */ +#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */ +#define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */ +#define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */ +/* SPMC_IN_RET (0x10006000+0x2C0) */ +#define SPMC_STATUS_LSB (1U << 0) /* 8b */ +/* VDE_PWR_CON (0x10006000+0x300) */ +#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VEN_PWR_CON (0x10006000+0x304) */ +#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* ISP_PWR_CON (0x10006000+0x308) */ +#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DIS_PWR_CON (0x10006000+0x30C) */ +#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ +#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE1_PWR_CON (0x10006000+0x310) */ +#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* AUDIO_PWR_CON (0x10006000+0x314) */ +#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ +#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ +#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* IFR_PWR_CON (0x10006000+0x318) */ +#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DPY_PWR_CON (0x10006000+0x31C) */ +#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MD1_PWR_CON (0x10006000+0x320) */ +#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ +/* VPU_TOP_PWR_CON (0x10006000+0x324) */ +#define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CONN_PWR_CON (0x10006000+0x32C) */ +#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ +#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VPU_CORE2_PWR_CON (0x10006000+0x330) */ +#define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ +#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_PWR_CON (0x10006000+0x338) */ +#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VPU_CORE0_PWR_CON (0x10006000+0x33C) */ +#define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* VPU_CORE1_PWR_CON (0x10006000+0x340) */ +#define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CAM_PWR_CON (0x10006000+0x344) */ +#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_2D_PWR_CON (0x10006000+0x348) */ +#define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE0_PWR_CON (0x10006000+0x34C) */ +#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* SYSRAM_CON (0x10006000+0x350) */ +#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* SYSROM_CON (0x10006000+0x354) */ +#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ +/* SSPM_SRAM_CON (0x10006000+0x358) */ +#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* SCP_SRAM_CON (0x10006000+0x35C) */ +#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* UFS_SRAM_CON (0x10006000+0x36C) */ +#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ +#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ +/* DUMMY_SRAM_CON (0x10006000+0x380) */ +#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */ +#define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */ +#define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */ +/* MD_SRAM_ISO_CON (0x10006000+0x394) */ +#define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */ +/* MD_EXTRA_PWR_CON (0x10006000+0x398) */ +#define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */ +#define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */ +/* EXT_BUCK_CON (0x10006000+0x3A0) */ +#define RG_VA09_ON_LSB (1U << 0) /* 1b */ +/* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */ +#define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON (0x10006000+0x400) */ +#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ +#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ +/* SPM_MDBSI_CON (0x10006000+0x404) */ +#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ +/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ +#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ +#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BSI_GEN (0x10006000+0x410) */ +#define SPM_BSI_START_LSB (1U << 0) /* 1b */ +/* SPM_BSI_EN_SR (0x10006000+0x414) */ +#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_CLK_SR (0x10006000+0x418) */ +#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D0_SR (0x10006000+0x41C) */ +#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D1_SR (0x10006000+0x420) */ +#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D2_SR (0x10006000+0x424) */ +#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ +/* SPM_AP_SEMA (0x10006000+0x428) */ +#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ +/* SPM_SPM_SEMA (0x10006000+0x42C) */ +#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ +/* AP_MDSRC_REQ (0x10006000+0x430) */ +#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ +#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ +#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ +#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ +#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ +#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ +/* SPM2MD_DVFS_CON (0x10006000+0x438) */ +#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ +/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ +#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ +/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ +#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ +#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ +#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ +#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ +#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ +#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ +#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ +/* DPY_LP_CON (0x10006000+0x444) */ +#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ +/* CPU_DVFS_REQ (0x10006000+0x448) */ +#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ +/* SPM_PLL_CON (0x10006000+0x44C) */ +#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ +#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ +#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ +#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ +#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ +#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ +#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ +#define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */ +/* SPM_EMI_BW_MODE (0x10006000+0x450) */ +#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ +#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ +#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ +#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ +/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ +#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ +/* ULPOSC_CON (0x10006000+0x458) */ +#define ULPOSC_EN_LSB (1U << 0) /* 1b */ +#define ULPOSC_RST_LSB (1U << 1) /* 1b */ +#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ +#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ +/* SPM2MM_CON (0x10006000+0x45C) */ +#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ +#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ +#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ +#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ +#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ +#define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */ +#define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */ +#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ +#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ +#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ +/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ +#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ +#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ +#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ +#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ +#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ +#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ +#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ +#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ +#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ +#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ +#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ +/* SPM_S1_MODE_CH (0x10006000+0x468) */ +#define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */ +#define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */ +/* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */ +#define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ +#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ +#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ +#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ +#define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */ +/* DRAMC_DMYRD_CON (0x10006000+0x478) */ +#define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */ +#define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */ +/* SPM_DRS_CON (0x10006000+0x47C) */ +#define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */ +#define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */ +#define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */ +#define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */ +/* SPM_SEMA_M0 (0x10006000+0x480) */ +#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M1 (0x10006000+0x484) */ +#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M2 (0x10006000+0x488) */ +#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M3 (0x10006000+0x48C) */ +#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M4 (0x10006000+0x490) */ +#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M5 (0x10006000+0x494) */ +#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M6 (0x10006000+0x498) */ +#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M7 (0x10006000+0x49C) */ +#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ +/* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */ +#define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */ +#define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ +#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON (0x10006000+0x4B0) */ +#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ +#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ +#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ +/* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */ +#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ +/* SPM_SSPM_IRQ (0x10006000+0x4C0) */ +#define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM2PMCU_INT (0x10006000+0x4C4) */ +#define SPM2PMCU_INT_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_SET (0x10006000+0x4C8) */ +#define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */ +#define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */ +#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */ +#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */ +#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */ +#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_INT (0x10006000+0x4E0) */ +#define PMCU2SPM_INT_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_SET (0x10006000+0x4E4) */ +#define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */ +#define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */ +#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */ +#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */ +#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */ +#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_CFG (0x10006000+0x4FC) */ +#define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ +#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ +#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ +#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ +#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ +#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ +#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ +#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ +#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ +#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ +#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ +#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ +#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ +#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ +#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ +#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ +#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_L2CFLUSH (0x10006000+0x554) */ +#define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* MP1_L2CFLUSH (0x10006000+0x558) */ +#define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* CPU_PTPOD2_CON (0x10006000+0x560) */ +#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ +#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ +#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ +#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ +#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ +#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ +/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ +#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ +/* ROOT_CORE_ADDR (0x10006000+0x574) */ +#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON (0x10006000+0x580) */ +#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_SET (0x10006000+0x584) */ +#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ +#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */ +#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */ +#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */ +#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */ +#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_INT (0x10006000+0x5E0) */ +#define SW2SPM_INT_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_SET (0x10006000+0x5E4) */ +#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_CLR (0x10006000+0x5E8) */ +#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */ +#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */ +#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */ +#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */ +#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_CFG (0x10006000+0x5FC) */ +#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* SPM_SW_FLAG (0x10006000+0x600) */ +#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ +/* SPM_SW_DEBUG (0x10006000+0x604) */ +#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_0 (0x10006000+0x608) */ +#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_1 (0x10006000+0x60C) */ +#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_2 (0x10006000+0x610) */ +#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_3 (0x10006000+0x614) */ +#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_4 (0x10006000+0x618) */ +#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_5 (0x10006000+0x61C) */ +#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ +/* SPM_RSV_CON (0x10006000+0x620) */ +#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA (0x10006000+0x624) */ +#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ +/* SPM_RSV_CON1 (0x10006000+0x628) */ +#define SPM_RSV_CON1_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA1 (0x10006000+0x62C) */ +#define SPM_RSV_STA1_LSB (1U << 0) /* 16b */ +/* SPM_PASR_DPD_0 (0x10006000+0x630) */ +#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_1 (0x10006000+0x634) */ +#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_2 (0x10006000+0x638) */ +#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ +#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON (0x10006000+0x640) */ +#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_SET (0x10006000+0x644) */ +#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ +#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_6 (0x10006000+0x64C) */ +#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_7 (0x10006000+0x650) */ +#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_8 (0x10006000+0x654) */ +#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_9 (0x10006000+0x658) */ +#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_10 (0x10006000+0x65C) */ +#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_18 (0x10006000+0x67C) */ +#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_19 (0x10006000+0x680) */ +#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ +/* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */ +#define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */ +#define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_SEL (0x10006000+0x698) */ +#define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */ +/* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */ +#define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */ +#define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_LEVEL (0x10006000+0x6A4) */ +#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */ +/* DVFS_ABORT_STA (0x10006000+0x6A8) */ +#define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */ +#define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */ +/* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */ +#define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_DFS_LEVEL (0x10006000+0x6B0) */ +#define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */ +/* SPM_DVS_LEVEL (0x10006000+0x6B4) */ +#define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +#define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */ +#define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */ +/* SPM_DVFS_MISC (0x10006000+0x6B8) */ +#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ +#define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */ +#define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */ +/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ +#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ +#define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */ +#define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */ +#define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */ +#define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */ +#define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */ +#define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */ +#define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */ +#define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ +#define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ +#define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */ +/* SCP_VCORE_LEVEL (0x10006000+0x6C4) */ +#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +/* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */ +#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ +#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ +/* SPARE_ACK_STA (0x10006000+0x6F0) */ +#define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_MASK (0x10006000+0x6F4) */ +#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1 (0x10006000+0x700) */ +#define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1_STA (0x10006000+0x704) */ +#define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD0 (0x10006000+0x710) */ +#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD1 (0x10006000+0x714) */ +#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD2 (0x10006000+0x718) */ +#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD3 (0x10006000+0x71C) */ +#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD4 (0x10006000+0x720) */ +#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD5 (0x10006000+0x724) */ +#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD6 (0x10006000+0x728) */ +#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD7 (0x10006000+0x72C) */ +#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD8 (0x10006000+0x730) */ +#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD9 (0x10006000+0x734) */ +#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD10 (0x10006000+0x738) */ +#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD11 (0x10006000+0x73C) */ +#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD12 (0x10006000+0x740) */ +#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD13 (0x10006000+0x744) */ +#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD14 (0x10006000+0x748) */ +#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD15 (0x10006000+0x74C) */ +#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */ +#define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */ +#define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */ +#define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */ +#define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_IN_FIX (0x10006000+0x790) */ +#define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */ +#define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */ +#define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_0 (0x10006000+0x800) */ +#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_1 (0x10006000+0x804) */ +#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_2 (0x10006000+0x808) */ +#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ +#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_4 (0x10006000+0x810) */ +#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_5 (0x10006000+0x814) */ +#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_6 (0x10006000+0x818) */ +#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ +#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_8 (0x10006000+0x820) */ +#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_9 (0x10006000+0x824) */ +#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0 (0x10006000+0x828) */ +#define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1 (0x10006000+0x82C) */ +#define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2 (0x10006000+0x830) */ +#define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3 (0x10006000+0x834) */ +#define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_10 (0x10006000+0x838) */ +#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_11 (0x10006000+0x83C) */ +#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_0 (0x10006000+0x840) */ +#define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_1 (0x10006000+0x844) */ +#define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_2 (0x10006000+0x848) */ +#define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */ +#define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_4 (0x10006000+0x850) */ +#define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_5 (0x10006000+0x854) */ +#define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_6 (0x10006000+0x858) */ +#define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */ +#define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_0 (0x10006000+0x860) */ +#define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_1 (0x10006000+0x864) */ +#define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_2 (0x10006000+0x868) */ +#define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */ +#define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_4 (0x10006000+0x870) */ +#define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_5 (0x10006000+0x874) */ +#define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_6 (0x10006000+0x878) */ +#define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */ +#define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0 (0x10006000+0x880) */ +#define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0 (0x10006000+0x884) */ +#define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_12 (0x10006000+0x888) */ +#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_13 (0x10006000+0x88C) */ +#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ +/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ +#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ +#define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */ +/* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */ +#define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */ +#define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */ +#define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */ +#define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */ +#define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */ +#define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */ +#define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */ +#define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */ +/* SPM_ACK_CHK_CON (0x10006000+0x900) */ +#define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC (0x10006000+0x904) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL (0x10006000+0x908) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */ +#define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA (0x10006000+0x910) */ +#define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH (0x10006000+0x914) */ +#define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON2 (0x10006000+0x920) */ +#define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC2 (0x10006000+0x924) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */ +#define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA2 (0x10006000+0x930) */ +#define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */ +#define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON3 (0x10006000+0x940) */ +#define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC3 (0x10006000+0x944) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */ +#define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA3 (0x10006000+0x950) */ +#define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */ +#define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON4 (0x10006000+0x960) */ +#define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC4 (0x10006000+0x964) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */ +#define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA4 (0x10006000+0x970) */ +#define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */ +#define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */ + +/* --- SPM Flag Define --- */ +#define SPM_FLAG_DIS_CPU_PDN (1U << 0) +#define SPM_FLAG_DIS_INFRA_PDN (1U << 1) +#define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2) +#define SPM_FLAG_DIS_VCORE_DVS (1U << 3) +#define SPM_FLAG_DIS_VCORE_DFS (1U << 4) +#define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5) +#define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6) +#define SPM_FLAG_DIS_ATF_ABORT (1U << 7) +#define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8) +#define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9) +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) +#define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11) +#define SPM_FLAG_SODI_CG_MODE (1U << 12) +#define SPM_FLAG_SODI_NO_EVENT (1U << 13) +#define SPM_FLAG_ENABLE_SODI3 (1U << 14) +#define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15) +#define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16) +#define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17) +#define SPM_FLAG_DIS_VMODEM_DVS (1U << 18) +#define SPM_FLAG_SUSPEND_OPTION (1U << 19) +#define SPM_FLAG_DEEPIDLE_OPTION (1U << 20) +#define SPM_FLAG_SODI_OPTION (1U << 21) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31) + +/* --- SPM Flag1 Define --- */ +#define SPM_FLAG1_RESERVED_BIT0 (1U << 0) +#define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1) +#define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2) +#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3) +#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4) +#define SPM_FLAG1_VCORE_LP_0P7V (1U << 5) +#define SPM_FLAG1_DISABLE_MCDSR (1U << 6) +#define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7) +#define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8) +#define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9) +#define SPM_FLAG1_RESERVED_BIT10 (1U << 10) +#define SPM_FLAG1_RESERVED_BIT11 (1U << 11) +#define SPM_FLAG1_RESERVED_BIT12 (1U << 12) +#define SPM_FLAG1_RESERVED_BIT13 (1U << 13) +#define SPM_FLAG1_RESERVED_BIT14 (1U << 14) +#define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15) +#define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16) +#define SPM_FLAG1_DIS_IMP_DIS (1U << 17) +#define SPM_FLAG1_DIS_IMP_COPY (1U << 18) +#define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19) +#define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20) +#define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21) +#define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22) +#define SPM_FLAG1_DIS_MPLL_OFF (1U << 23) +#define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24) +#define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25) +#define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26) +#define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27) +#define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28) +#define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29) +#define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30) +#define SPM_FLAG1_DIS_SW_MR4 (1U << 31) + +/* --- SPM DEBUG Define --- */ +#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) +#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) +#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) +#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) +#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) +#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) +#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) +#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) +#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) +#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11) +#define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12) +#define SPM_DBG_DEBUG_IDX_DPD (1U << 13) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15) +#define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16) +#define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17) +#define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18) +#define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20) +#define SPM_DBG_RESERVED_BIT21 (1U << 21) +#define SPM_DBG_RESERVED_BIT22 (1U << 22) +#define SPM_DBG_RESERVED_BIT23 (1U << 23) +#define SPM_DBG_RESERVED_BIT24 (1U << 24) +#define SPM_DBG_RESERVED_BIT25 (1U << 25) +#define SPM_DBG_RESERVED_BIT26 (1U << 26) +#define SPM_DBG_SODI1_FLAG (1U << 27) +#define SPM_DBG_SODI3_FLAG (1U << 28) +#define SPM_DBG_VCORE_DVFS_FLAG (1U << 29) +#define SPM_DBG_DEEPIDLE_FLAG (1U << 30) +#define SPM_DBG_SUSPEND_FLAG (1U << 31) + +/* --- SPM DEBUG1 Define --- */ +#define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0) +#define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1) +#define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2) +#define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3) +#define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4) +#define SPM_DBG1_RESERVED_BIT5 (1U << 5) +#define SPM_DBG1_RESERVED_BIT6 (1U << 6) +#define SPM_DBG1_RESERVED_BIT7 (1U << 7) +#define SPM_DBG1_RESERVED_BIT8 (1U << 8) +#define SPM_DBG1_RESERVED_BIT9 (1U << 9) +#define SPM_DBG1_RESERVED_BIT10 (1U << 10) +#define SPM_DBG1_RESERVED_BIT11 (1U << 11) +#define SPM_DBG1_RESERVED_BIT12 (1U << 12) +#define SPM_DBG1_RESERVED_BIT13 (1U << 13) +#define SPM_DBG1_RESERVED_BIT14 (1U << 14) +#define SPM_DBG1_RESERVED_BIT15 (1U << 15) +#define SPM_DBG1_RESERVED_BIT16 (1U << 16) +#define SPM_DBG1_RESERVED_BIT17 (1U << 17) +#define SPM_DBG1_RESERVED_BIT18 (1U << 18) +#define SPM_DBG1_RESERVED_BIT19 (1U << 19) +#define SPM_DBG1_RESERVED_BIT20 (1U << 20) +#define SPM_DBG1_RESERVED_BIT21 (1U << 21) +#define SPM_DBG1_RESERVED_BIT22 (1U << 22) +#define SPM_DBG1_RESERVED_BIT23 (1U << 23) +#define SPM_DBG1_RESERVED_BIT24 (1U << 24) +#define SPM_DBG1_RESERVED_BIT25 (1U << 25) +#define SPM_DBG1_RESERVED_BIT26 (1U << 26) +#define SPM_DBG1_RESERVED_BIT27 (1U << 27) +#define SPM_DBG1_RESERVED_BIT28 (1U << 28) +#define SPM_DBG1_RESERVED_BIT29 (1U << 29) +#define SPM_DBG1_RESERVED_BIT30 (1U << 30) +#define SPM_DBG1_RESERVED_BIT31 (1U << 31) + +/* --- R0 Define --- */ +#define R0_SC_26M_CK_OFF (1U << 0) +#define R0_BIT1 (1U << 1) +#define R0_SC_MEM_CK_OFF (1U << 2) +#define R0_SC_AXI_CK_OFF (1U << 3) +#define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4) +#define R0_SC_MD26M_CK_OFF (1U << 5) +#define R0_SC_DPY_MODE_SW_PCM (1U << 6) +#define R0_SC_DMSUS_OFF_PCM (1U << 7) +#define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8) +#define R0_BIT9 (1U << 9) +#define R0_SC_MPLLOUT_OFF (1U << 10) +#define R0_SC_TX_TRACKING_DIS (1U << 11) +#define R0_SC_DPY_DLL_EN_PCM (1U << 12) +#define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13) +#define R0_SC_DPY_VREF_EN_PCM (1U << 14) +#define R0_SC_PHYPLL_EN_PCM (1U << 15) +#define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16) +#define R0_SC_DPY_BCLK_ENABLE (1U << 17) +#define R0_SC_MPLL_OFF (1U << 18) +#define R0_SC_SHU_RESTORE (1U << 19) +#define R0_SC_CKSQ0_OFF (1U << 20) +#define R0_SC_CKSQ1_OFF (1U << 21) +#define R0_SC_DR_SHU_EN_PCM (1U << 22) +#define R0_SC_DPHY_PRECAL_UP (1U << 23) +#define R0_SC_MPLL_S_OFF (1U << 24) +#define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25) +#define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26) +#define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27) +#define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28) +#define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29) +#define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30) +#define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31) + +/* --- R7 Define --- */ +#define R7_PWRAP_SLEEP_REQ (1U << 0) +#define R7_EMI_CLK_OFF_REQ (1U << 1) +#define R7_TOP_MAS_PAU_REQ (1U << 2) +#define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3) +#define R7_PCM_CK_SEL0 (1U << 4) +#define R7_PCM_CK_SEL1 (1U << 5) +#define R7_SPM2RC_DVS_DONE (1U << 6) +#define R7_FREQH_PAUSE_MPLL (1U << 7) +#define R7_SC_26M_CK_SEL (1U << 8) +#define R7_PCM_TIMER_SET (1U << 9) +#define R7_PCM_TIMER_CLR (1U << 10) +#define R7_SRCVOLTEN (1U << 11) +#define R7_CSYSPWRUPACK (1U << 12) +#define R7_IM_SLEEP_ENABLE (1U << 13) +#define R7_SRCCLKENO_0 (1U << 14) +#define R7_SYSRST (1U << 15) +#define R7_MD_APSRC_ACK (1U << 16) +#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) +#define R7_SC_AXI_DCM_DIS (1U << 18) +#define R7_FREQH_PAUSE_MAIN (1U << 19) +#define R7_FREQH_PAUSE_MEM (1U << 20) +#define R7_SRCCLKENO_1 (1U << 21) +#define R7_WDT_KICK_P (1U << 22) +#define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23) +#define R7_WAKEUP_EXT_W_SEL (1U << 24) +#define R7_WAKEUP_EXT_R_SEL (1U << 25) +#define R7_PMIC_IRQ_REQ_EN (1U << 26) +#define R7_FORCE_26M_WAKE (1U << 27) +#define R7_FORCE_APSRC_WAKE (1U << 28) +#define R7_FORCE_INFRA_WAKE (1U << 29) +#define R7_FORCE_VRF18_WAKE (1U << 30) +#define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31) + +/* --- R12 Define --- */ +#define R12_PCM_TIMER (1U << 0) +#define R12_SSPM_WDT_EVENT_B (1U << 1) +#define R12_KP_IRQ_B (1U << 2) +#define R12_APWDT_EVENT_B (1U << 3) +#define R12_APXGPT1_EVENT_B (1U << 4) +#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) +#define R12_EINT_EVENT_B (1U << 6) +#define R12_CONN_WDT_IRQ_B (1U << 7) +#define R12_CCIF0_EVENT_B (1U << 8) +#define R12_LOWBATTERY_IRQ_B (1U << 9) +#define R12_SSPM_SPM_IRQ_B (1U << 10) +#define R12_SCP_SPM_IRQ_B (1U << 11) +#define R12_SCP_WDT_EVENT_B (1U << 12) +#define R12_PCM_WDT_WAKEUP_B (1U << 13) +#define R12_USB_CDSC_B (1U << 14) +#define R12_USB_POWERDWN_B (1U << 15) +#define R12_SYS_TIMER_EVENT_B (1U << 16) +#define R12_EINT_EVENT_SECURE_B (1U << 17) +#define R12_CCIF1_EVENT_B (1U << 18) +#define R12_UART0_IRQ_B (1U << 19) +#define R12_AFE_IRQ_MCU_B (1U << 20) +#define R12_THERM_CTRL_EVENT_B (1U << 21) +#define R12_SYS_CIRQ_IRQ_B (1U << 22) +#define R12_MD2AP_PEER_EVENT_B (1U << 23) +#define R12_CSYSPWREQ_B (1U << 24) +#define R12_MD1_WDT_B (1U << 25) +#define R12_CLDMA_EVENT_B (1U << 26) +#define R12_SEJ_WDT_GPT_B (1U << 27) +#define R12_ALL_SSPM_WAKEUP_B (1U << 28) +#define R12_CPU_IRQ_B (1U << 29) +#define R12_CPU_WFI_AND_B (1U << 30) +#define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31) + +/* --- R12ext Define --- */ +#define R12EXT_26M_WAKE (1U << 0) +#define R12EXT_26M_SLEEP (1U << 1) +#define R12EXT_INFRA_WAKE (1U << 2) +#define R12EXT_INFRA_SLEEP (1U << 3) +#define R12EXT_APSRC_WAKE (1U << 4) +#define R12EXT_APSRC_SLEEP (1U << 5) +#define R12EXT_VRF18_WAKE (1U << 6) +#define R12EXT_VRF18_SLEEP (1U << 7) +#define R12EXT_DVFS_ALL_STATE (1U << 8) +#define R12EXT_DVFS_LEVEL_STATE0 (1U << 9) +#define R12EXT_DVFS_LEVEL_STATE1 (1U << 10) +#define R12EXT_DVFS_LEVEL_STATE2 (1U << 11) +#define R12EXT_DDREN_WAKE (1U << 12) +#define R12EXT_DDREN_SLEEP (1U << 13) +#define R12EXT_NFC_CLK_BUF_WAKE (1U << 14) +#define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15) +#define R12EXT_CONN_CLK_BUF_WAKE (1U << 16) +#define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17) +#define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18) +#define R12EXT_DVFS_LEVEL_STATE3 (1U << 19) +#define R12EXT_DVFS_LEVEL_STATE4 (1U << 20) +#define R12EXT_DVFS_LEVEL_STATE5 (1U << 21) +#define R12EXT_DVFS_LEVEL_STATE6 (1U << 22) +#define R12EXT_DVFS_LEVEL_STATE7 (1U << 23) +#define R12EXT_DVFS_LEVEL_STATE8 (1U << 24) +#define R12EXT_DVFS_LEVEL_STATE9 (1U << 25) +#define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26) +#define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27) +#define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28) +#define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29) +#define R12EXT_HYBRID_DDREN_SLEEP (1U << 30) +#define R12EXT_HYBRID_DDREN_WAKE (1U << 31) + +/* --- R13 Define --- */ +#define R13_EXT_SRCCLKENI_0 (1U << 0) +#define R13_EXT_SRCCLKENI_1 (1U << 1) +#define R13_MD1_SRCCLKENA (1U << 2) +#define R13_MD1_APSRC_REQ (1U << 3) +#define R13_CONN_DDR_EN (1U << 4) +#define R13_MD2_SRCCLKENA (1U << 5) +#define R13_SSPM_SRCCLKENA (1U << 6) +#define R13_SSPM_APSRC_REQ (1U << 7) +#define R13_MD_STATE (1U << 8) +#define R13_EMI_CLK_OFF_2_ACK (1U << 9) +#define R13_MM_STATE (1U << 10) +#define R13_SSPM_STATE (1U << 11) +#define R13_MD_DDR_EN (1U << 12) +#define R13_CONN_STATE (1U << 13) +#define R13_CONN_SRCCLKENA (1U << 14) +#define R13_CONN_APSRC_REQ (1U << 15) +#define R13_SLEEP_EVENT_STA (1U << 16) +#define R13_WAKE_EVENT_STA (1U << 17) +#define R13_EMI_IDLE (1U << 18) +#define R13_CSYSPWRUPREQ (1U << 19) +#define R13_PWRAP_SLEEP_ACK (1U << 20) +#define R13_EMI_CLK_OFF_ACK_ALL (1U << 21) +#define R13_TOP_MAS_PAU_ACK (1U << 22) +#define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23) +#define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24) +#define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25) +#define R13_INFRA_AUX_IDLE (1U << 26) +#define R13_DVFS_ALL_STATE (1U << 27) +#define R13_RC2SPM_EVENT_ABORT_OR (1U << 28) +#define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29) +#define R13_MD1_VRF18_REQ (1U << 30) +#define R13_C2K_VRF18_REQ (1U << 31) + +#define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN)) +#define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN)) +#define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN)) + +#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) +#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) +#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) + +#define EVENT_VEC(event, resume, imme, pc) \ + (((pc) << 16) | \ + (!!(imme) << 7) | \ + (!!(resume) << 6) | \ + ((event) & 0x3f)) + +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF 0x00015800 +#define PCM_FSM_STA_DEF 0x00108490 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218 +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT0 (1U << 0) +#define PCM_SW_INT1 (1U << 1) +#define PCM_SW_INT2 (1U << 2) +#define PCM_SW_INT3 (1U << 3) +#define PCM_SW_INT4 (1U << 4) +#define PCM_SW_INT5 (1U << 5) +#define PCM_SW_INT6 (1U << 6) +#define PCM_SW_INT7 (1U << 7) +#define PCM_SW_INT8 (1U << 8) +#define PCM_SW_INT9 (1U << 9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ0 (1U << 8) +#define ISRM_RET_IRQ1 (1U << 9) +#define ISRM_RET_IRQ2 (1U << 10) +#define ISRM_RET_IRQ3 (1U << 11) +#define ISRM_RET_IRQ4 (1U << 12) +#define ISRM_RET_IRQ5 (1U << 13) +#define ISRM_RET_IRQ6 (1U << 14) +#define ISRM_RET_IRQ7 (1U << 15) +#define ISRM_RET_IRQ8 (1U << 16) +#define ISRM_RET_IRQ9 (1U << 17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ + ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ + ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ + ISRM_RET_IRQ1) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRS_SW_INT0 (1U << 4) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_WAKEUP_MISC */ +#define WAKE_MISC_TWAM (1U << 18) +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +enum SPM_WAKE_SRC_LIST { + WAKE_SRC_R12_PCM_TIMER = (1U << 0), + WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1), + WAKE_SRC_R12_KP_IRQ_B = (1U << 2), + WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3), + WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4), + WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5), + WAKE_SRC_R12_EINT_EVENT_B = (1U << 6), + WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7), + WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8), + WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9), + WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10), + WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11), + WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12), + WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13), + WAKE_SRC_R12_USB_CDSC_B = (1U << 14), + WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15), + WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16), + WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17), + WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18), + WAKE_SRC_R12_UART0_IRQ_B = (1U << 19), + WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20), + WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21), + WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22), + WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23), + WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24), + WAKE_SRC_R12_MD1_WDT_B = (1U << 25), + WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26), + WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27), + WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28), + WAKE_SRC_R12_CPU_IRQ_B = (1U << 29), + WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30), +}; + +struct pcm_desc { + const char *version; + const uint32_t *base; + const uint32_t base_dma; + const uint32_t size; + const uint32_t sess; + const uint32_t replace; + const uint32_t addr_2nd; + const uint32_t reserved; + + uint32_t vec0; + uint32_t vec1; + uint32_t vec2; + uint32_t vec3; + uint32_t vec4; + uint32_t vec5; + uint32_t vec6; + uint32_t vec7; + uint32_t vec8; + uint32_t vec9; + uint32_t vec10; + uint32_t vec11; + uint32_t vec12; + uint32_t vec13; + uint32_t vec14; + uint32_t vec15; +}; + +struct pwr_ctrl { + uint32_t pcm_flags; + uint32_t pcm_flags1; + uint32_t timer_val; + uint32_t wake_src; + + /* SPM_AP_STANDBY_CON */ + uint8_t wfi_op; + uint8_t mp0_cputop_idle_mask; + uint8_t mp1_cputop_idle_mask; + uint8_t mcusys_idle_mask; + uint8_t mm_mask_b; + uint8_t md_ddr_en_0_dbc_en; + uint8_t md_ddr_en_1_dbc_en; + uint8_t md_mask_b; + uint8_t sspm_mask_b; + uint8_t scp_mask_b; + uint8_t srcclkeni_mask_b; + uint8_t md_apsrc_1_sel; + uint8_t md_apsrc_0_sel; + uint8_t conn_ddr_en_dbc_en; + uint8_t conn_mask_b; + uint8_t conn_apsrc_sel; + + /* SPM_SRC_REQ */ + uint8_t spm_apsrc_req; + uint8_t spm_f26m_req; + uint8_t spm_infra_req; + uint8_t spm_vrf18_req; + uint8_t spm_ddren_req; + uint8_t spm_rsv_src_req; + uint8_t spm_ddren_2_req; + uint8_t cpu_md_dvfs_sop_force_on; + + /* SPM_SRC_MASK */ + uint8_t csyspwreq_mask; + uint8_t ccif0_md_event_mask_b; + uint8_t ccif0_ap_event_mask_b; + uint8_t ccif1_md_event_mask_b; + uint8_t ccif1_ap_event_mask_b; + uint8_t ccif2_md_event_mask_b; + uint8_t ccif2_ap_event_mask_b; + uint8_t ccif3_md_event_mask_b; + uint8_t ccif3_ap_event_mask_b; + uint8_t md_srcclkena_0_infra_mask_b; + uint8_t md_srcclkena_1_infra_mask_b; + uint8_t conn_srcclkena_infra_mask_b; + uint8_t ufs_infra_req_mask_b; + uint8_t srcclkeni_infra_mask_b; + uint8_t md_apsrc_req_0_infra_mask_b; + uint8_t md_apsrc_req_1_infra_mask_b; + uint8_t conn_apsrcreq_infra_mask_b; + uint8_t ufs_srcclkena_mask_b; + uint8_t md_vrf18_req_0_mask_b; + uint8_t md_vrf18_req_1_mask_b; + uint8_t ufs_vrf18_req_mask_b; + uint8_t gce_vrf18_req_mask_b; + uint8_t conn_infra_req_mask_b; + uint8_t gce_apsrc_req_mask_b; + uint8_t disp0_apsrc_req_mask_b; + uint8_t disp1_apsrc_req_mask_b; + uint8_t mfg_req_mask_b; + uint8_t vdec_req_mask_b; + + /* SPM_SRC2_MASK */ + uint8_t md_ddr_en_0_mask_b; + uint8_t md_ddr_en_1_mask_b; + uint8_t conn_ddr_en_mask_b; + uint8_t ddren_sspm_apsrc_req_mask_b; + uint8_t ddren_scp_apsrc_req_mask_b; + uint8_t disp0_ddren_mask_b; + uint8_t disp1_ddren_mask_b; + uint8_t gce_ddren_mask_b; + uint8_t ddren_emi_self_refresh_ch0_mask_b; + uint8_t ddren_emi_self_refresh_ch1_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + uint32_t spm_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + uint32_t spm_wakeup_event_ext_mask; + + /* SPM_SRC3_MASK */ + uint8_t md_ddr_en_2_0_mask_b; + uint8_t md_ddr_en_2_1_mask_b; + uint8_t conn_ddr_en_2_mask_b; + uint8_t ddren2_sspm_apsrc_req_mask_b; + uint8_t ddren2_scp_apsrc_req_mask_b; + uint8_t disp0_ddren2_mask_b; + uint8_t disp1_ddren2_mask_b; + uint8_t gce_ddren2_mask_b; + uint8_t ddren2_emi_self_refresh_ch0_mask_b; + uint8_t ddren2_emi_self_refresh_ch1_mask_b; + + uint8_t mp0_cpu0_wfi_en; + uint8_t mp0_cpu1_wfi_en; + uint8_t mp0_cpu2_wfi_en; + uint8_t mp0_cpu3_wfi_en; + + uint8_t mp1_cpu0_wfi_en; + uint8_t mp1_cpu1_wfi_en; + uint8_t mp1_cpu2_wfi_en; + uint8_t mp1_cpu3_wfi_en; +}; + +struct wake_status { + uint32_t assert_pc; + uint32_t r12; + uint32_t r12_ext; + uint32_t raw_sta; + uint32_t raw_ext_sta; + uint32_t wake_misc; + uint32_t timer_out; + uint32_t r13; + uint32_t r15; + uint32_t idle_sta; + uint32_t req_sta; + uint32_t debug_flag; + uint32_t debug_flag1; + uint32_t event_reg; + uint32_t isr; + uint32_t sw_flag; + uint32_t sw_flag1; + uint32_t log_index; +}; + +typedef struct spm_data { + unsigned int cmd; + union { + struct { + unsigned int sys_timestamp_l; + unsigned int sys_timestamp_h; + unsigned int sys_src_clk_l; + unsigned int sys_src_clk_h; + unsigned int spm_opt; + } suspend; + struct { + unsigned int args1; + unsigned int args2; + unsigned int args3; + unsigned int args4; + unsigned int args5; + unsigned int args6; + unsigned int args7; + } args; + } u; +} spm_data_t; + +enum { + SPM_SUSPEND, + SPM_RESUME +}; + +extern void spm_disable_pcm_timer(void); +extern void spm_set_bootaddr(unsigned long bootaddr); +extern void spm_set_cpu_status(int cpu); +extern void spm_set_power_control(const struct pwr_ctrl *pwrctrl); +extern void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); +extern void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl); +extern void spm_send_cpu_wakeup_event(void); +extern void spm_get_wakeup_status(struct wake_status *wakesta); +extern void spm_clean_after_wakeup(void); +extern void spm_output_wake_reason(struct wake_status *wakesta, + const char *scenario); +extern void spm_set_pcm_wdt(int en); +extern void spm_lock_get(void); +extern void spm_lock_release(void); +extern void spm_boot_init(void); +extern const char *spm_get_firmware_version(void); + +#endif /* SPM_H */ diff --git a/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c new file mode 100644 index 00000000..ce852726 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> +#include <platform_def.h> +#include <spm.h> +#include <spm_pmic_wrap.h> +#include <lib/libc/string.h> + +#define SLEEP_REG_MD_SPM_DVFS_CMD20 (SLEEP_REG_MD_BASE + 0x010) +#define SLEEP_REG_MD_SPM_DVFS_CMD21 (SLEEP_REG_MD_BASE + 0x014) +#define SLEEP_REG_MD_SPM_DVFS_CMD22 (SLEEP_REG_MD_BASE + 0x018) +#define SLEEP_REG_MD_SPM_DVFS_CMD23 (SLEEP_REG_MD_BASE + 0x01C) + +/* PMIC_WRAP -> PMIC MT6358 */ +#define VCORE_BASE_UV 50000 +#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) +#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV) + +#define DEFAULT_VOLT_VSRAM (100000) +#define DEFAULT_VOLT_VCORE (100000) +#define NR_PMIC_WRAP_CMD (NR_IDX_ALL) +#define MAX_RETRY_COUNT (100) +#define SPM_DATA_SHIFT (16) + +#define BUCK_VCORE_ELR0 0x14AA +#define BUCK_VPROC12_CON0 0x1408 +#define BUCK_VPROC11_CON0 0x1388 +#define TOP_SPI_CON0 0x044C +#define LDO_VSRAM_PROC12_CON0 0x1B88 +#define LDO_VSRAM_PROC11_CON0 0x1B46 +#define BUCK_VMODEM_ELR0 0x15A6 + +struct pmic_wrap_cmd { + unsigned long cmd_addr; + unsigned long cmd_wdata; +}; + +struct pmic_wrap_setting { + enum pmic_wrap_phase_id phase; + struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD]; + struct { + struct { + unsigned long cmd_addr; + unsigned long cmd_wdata; + } _[NR_PMIC_WRAP_CMD]; + const int nr_idx; + } set[NR_PMIC_WRAP_PHASE]; +}; + +static struct pmic_wrap_setting pw = { + .phase = NR_PMIC_WRAP_PHASE, + .addr = {{0, 0} }, + .set[PMIC_WRAP_PHASE_ALLINONE] = { + ._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),}, + ._[CMD_1] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(80000),}, + ._[CMD_2] = {BUCK_VPROC12_CON0, 0x3,}, + ._[CMD_3] = {BUCK_VPROC12_CON0, 0x1,}, + ._[CMD_4] = {BUCK_VPROC11_CON0, 0x3,}, + ._[CMD_5] = {BUCK_VPROC11_CON0, 0x1,}, + ._[CMD_6] = {TOP_SPI_CON0, 0x1,}, + ._[CMD_7] = {TOP_SPI_CON0, 0x0,}, + ._[CMD_8] = {BUCK_VPROC12_CON0, 0x0,}, + ._[CMD_9] = {BUCK_VPROC12_CON0, 0x1,}, + ._[CMD_10] = {BUCK_VPROC11_CON0, 0x0,}, + ._[CMD_11] = {BUCK_VPROC11_CON0, 0x1,}, + ._[CMD_12] = {LDO_VSRAM_PROC12_CON0, 0x0,}, + ._[CMD_13] = {LDO_VSRAM_PROC12_CON0, 0x1,}, + ._[CMD_14] = {LDO_VSRAM_PROC11_CON0, 0x0,}, + ._[CMD_15] = {LDO_VSRAM_PROC11_CON0, 0x1,}, + ._[CMD_20] = {BUCK_VMODEM_ELR0, VOLT_TO_PMIC_VAL(55000),}, + ._[CMD_21] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(60000),}, + ._[CMD_22] = {LDO_VSRAM_PROC11_CON0, 0x3,}, + ._[CMD_23] = {LDO_VSRAM_PROC11_CON0, 0x1,}, + .nr_idx = NR_IDX_ALL + } +}; + +void _mt_spm_pmic_table_init(void) +{ + struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = { + {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,}, + {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,}, + {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,}, + {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,}, + {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,}, + {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,}, + {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,}, + {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,}, + {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,}, + {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,}, + {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,}, + {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,}, + {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,}, + {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,}, + {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,}, + {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,} + }; + + memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); +} + +void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) +{ + uint32_t idx, addr, data; + + if (phase >= NR_PMIC_WRAP_PHASE) + return; + + if (pw.phase == phase) + return; + + if (pw.addr[0].cmd_addr == 0) + _mt_spm_pmic_table_init(); + + pw.phase = phase; + + mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | + BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); + for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { + addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; + data = pw.set[phase]._[idx].cmd_wdata; + mmio_write_32(pw.addr[idx].cmd_addr, addr | data); + } +} + +void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, + uint32_t cmd_wdata) +{ + uint32_t addr; + + if (phase >= NR_PMIC_WRAP_PHASE) + return; + + if (idx >= pw.set[phase].nr_idx) + return; + + pw.set[phase]._[idx].cmd_wdata = cmd_wdata; + + mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | + BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); + if (pw.phase == phase) { + addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; + mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); + } +} + +uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx) +{ + if (phase >= NR_PMIC_WRAP_PHASE) + return 0; + + if (idx >= pw.set[phase].nr_idx) + return 0; + + return pw.set[phase]._[idx].cmd_wdata; +} + diff --git a/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h new file mode 100644 index 00000000..194d3471 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/**************************************************************** + * Auto generated by DE, please DO NOT modify this file directly. + *****************************************************************/ + +#ifndef SPM_PMIC_WRAP__H +#define SPM_PMIC_WRAP__H + +enum pmic_wrap_phase_id { + PMIC_WRAP_PHASE_ALLINONE, + NR_PMIC_WRAP_PHASE +}; + +/* IDX mapping */ +enum { + CMD_0, /* 0x0 *//* PMIC_WRAP_PHASE_ALLINONE */ + CMD_1, /* 0x1 */ + CMD_2, /* 0x2 */ + CMD_3, /* 0x3 */ + CMD_4, /* 0x4 */ + CMD_5, /* 0x5 */ + CMD_6, /* 0x6 */ + CMD_7, /* 0x7 */ + CMD_8, /* 0x8 */ + CMD_9, /* 0x9 */ + CMD_10, /* 0xA */ + CMD_11, /* 0xB */ + CMD_12, /* 0xC */ + CMD_13, /* 0xD */ + CMD_14, /* 0xE */ + CMD_15, /* 0xF */ + CMD_20, /* 0x14 */ + CMD_21, /* 0x15 */ + CMD_22, /* 0x16 */ + CMD_23, /* 0x17 */ + NR_IDX_ALL +}; + +/* APIs */ +void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); +void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, + uint32_t idx, uint32_t cmd_wdata); +uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx); +#endif /* SPM_PMIC_WRAP__H */ + diff --git a/plat/mediatek/mt8183/drivers/spm/spm_suspend.c b/plat/mediatek/mt8183/drivers/spm/spm_suspend.c new file mode 100644 index 00000000..b9ac19f1 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_suspend.c @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <mt_gic_v3.h> +#include <lib/mmio.h> +#include <platform_def.h> +#include <pmic.h> +#include <spm.h> +#include <uart.h> + +#define SPM_SYSCLK_SETTLE 99 + +#define WAKE_SRC_FOR_SUSPEND \ + (WAKE_SRC_R12_PCM_TIMER | \ + WAKE_SRC_R12_SSPM_WDT_EVENT_B | \ + WAKE_SRC_R12_KP_IRQ_B | \ + WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B | \ + WAKE_SRC_R12_EINT_EVENT_B | \ + WAKE_SRC_R12_CONN_WDT_IRQ_B | \ + WAKE_SRC_R12_CCIF0_EVENT_B | \ + WAKE_SRC_R12_SSPM_SPM_IRQ_B | \ + WAKE_SRC_R12_SCP_SPM_IRQ_B | \ + WAKE_SRC_R12_SCP_WDT_EVENT_B | \ + WAKE_SRC_R12_USB_CDSC_B | \ + WAKE_SRC_R12_USB_POWERDWN_B | \ + WAKE_SRC_R12_SYS_TIMER_EVENT_B | \ + WAKE_SRC_R12_EINT_EVENT_SECURE_B | \ + WAKE_SRC_R12_CCIF1_EVENT_B | \ + WAKE_SRC_R12_MD2AP_PEER_EVENT_B | \ + WAKE_SRC_R12_MD1_WDT_B | \ + WAKE_SRC_R12_CLDMA_EVENT_B | \ + WAKE_SRC_R12_SEJ_WDT_GPT_B) + +#define SLP_PCM_FLAGS \ + (SPM_FLAG_DIS_VCORE_DVS | SPM_FLAG_DIS_VCORE_DFS | \ + SPM_FLAG_DIS_ATF_ABORT | SPM_FLAG_DISABLE_MMSYS_DVFS | \ + SPM_FLAG_DIS_INFRA_PDN | SPM_FLAG_SUSPEND_OPTION) + +#define SLP_PCM_FLAGS1 \ + (SPM_FLAG1_DISABLE_MCDSR) + +static const struct pwr_ctrl suspend_ctrl = { + .wake_src = WAKE_SRC_FOR_SUSPEND, + .pcm_flags = SLP_PCM_FLAGS, + .pcm_flags1 = SLP_PCM_FLAGS1, + + /* SPM_AP_STANDBY_CON */ + .wfi_op = 0x1, + .mp0_cputop_idle_mask = 0, + .mp1_cputop_idle_mask = 0, + .mcusys_idle_mask = 0, + .mm_mask_b = 0, + .md_ddr_en_0_dbc_en = 0x1, + .md_ddr_en_1_dbc_en = 0, + .md_mask_b = 0x1, + .sspm_mask_b = 0x1, + .scp_mask_b = 0x1, + .srcclkeni_mask_b = 0x1, + .md_apsrc_1_sel = 0, + .md_apsrc_0_sel = 0, + .conn_ddr_en_dbc_en = 0x1, + .conn_mask_b = 0x1, + .conn_apsrc_sel = 0, + + /* SPM_SRC_REQ */ + .spm_apsrc_req = 0, + .spm_f26m_req = 0, + .spm_infra_req = 0, + .spm_vrf18_req = 0, + .spm_ddren_req = 0, + .spm_rsv_src_req = 0, + .spm_ddren_2_req = 0, + .cpu_md_dvfs_sop_force_on = 0, + + /* SPM_SRC_MASK */ + .csyspwreq_mask = 0x1, + .ccif0_md_event_mask_b = 0x1, + .ccif0_ap_event_mask_b = 0x1, + .ccif1_md_event_mask_b = 0x1, + .ccif1_ap_event_mask_b = 0x1, + .ccif2_md_event_mask_b = 0x1, + .ccif2_ap_event_mask_b = 0x1, + .ccif3_md_event_mask_b = 0x1, + .ccif3_ap_event_mask_b = 0x1, + .md_srcclkena_0_infra_mask_b = 0x1, + .md_srcclkena_1_infra_mask_b = 0, + .conn_srcclkena_infra_mask_b = 0, + .ufs_infra_req_mask_b = 0, + .srcclkeni_infra_mask_b = 0, + .md_apsrc_req_0_infra_mask_b = 0x1, + .md_apsrc_req_1_infra_mask_b = 0x1, + .conn_apsrcreq_infra_mask_b = 0x1, + .ufs_srcclkena_mask_b = 0, + .md_vrf18_req_0_mask_b = 0, + .md_vrf18_req_1_mask_b = 0, + .ufs_vrf18_req_mask_b = 0, + .gce_vrf18_req_mask_b = 0, + .conn_infra_req_mask_b = 0x1, + .gce_apsrc_req_mask_b = 0, + .disp0_apsrc_req_mask_b = 0, + .disp1_apsrc_req_mask_b = 0, + .mfg_req_mask_b = 0, + .vdec_req_mask_b = 0, + + /* SPM_SRC2_MASK */ + .md_ddr_en_0_mask_b = 0x1, + .md_ddr_en_1_mask_b = 0, + .conn_ddr_en_mask_b = 0x1, + .ddren_sspm_apsrc_req_mask_b = 0x1, + .ddren_scp_apsrc_req_mask_b = 0x1, + .disp0_ddren_mask_b = 0x1, + .disp1_ddren_mask_b = 0x1, + .gce_ddren_mask_b = 0x1, + .ddren_emi_self_refresh_ch0_mask_b = 0, + .ddren_emi_self_refresh_ch1_mask_b = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .spm_wakeup_event_mask = 0xF1782218, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .spm_wakeup_event_ext_mask = 0xFFFFFFFF, + + /* SPM_SRC3_MASK */ + .md_ddr_en_2_0_mask_b = 0x1, + .md_ddr_en_2_1_mask_b = 0, + .conn_ddr_en_2_mask_b = 0x1, + .ddren2_sspm_apsrc_req_mask_b = 0x1, + .ddren2_scp_apsrc_req_mask_b = 0x1, + .disp0_ddren2_mask_b = 0, + .disp1_ddren2_mask_b = 0, + .gce_ddren2_mask_b = 0, + .ddren2_emi_self_refresh_ch0_mask_b = 0, + .ddren2_emi_self_refresh_ch1_mask_b = 0, + + .mp0_cpu0_wfi_en = 0x1, + .mp0_cpu1_wfi_en = 0x1, + .mp0_cpu2_wfi_en = 0x1, + .mp0_cpu3_wfi_en = 0x1, + + .mp1_cpu0_wfi_en = 0x1, + .mp1_cpu1_wfi_en = 0x1, + .mp1_cpu2_wfi_en = 0x1, + .mp1_cpu3_wfi_en = 0x1 +}; + +static uint32_t spm_set_sysclk_settle(void) +{ + mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); + return mmio_read_32(SPM_CLK_SETTLE); +} + +void go_to_sleep_before_wfi(void) +{ + int cpu = MPIDR_AFFLVL0_VAL(read_mpidr()); + uint32_t settle; + + settle = spm_set_sysclk_settle(); + spm_set_cpu_status(cpu); + spm_set_power_control(&suspend_ctrl); + spm_set_wakeup_event(&suspend_ctrl); + spm_set_pcm_flags(&suspend_ctrl); + spm_send_cpu_wakeup_event(); + spm_set_pcm_wdt(0); + spm_disable_pcm_timer(); + + if (is_infra_pdn(suspend_ctrl.pcm_flags)) + mt_uart_save(); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_BOOT); + + INFO("cpu%d: \"%s\", wakesrc = 0x%x, pcm_con1 = 0x%x\n", + cpu, spm_get_firmware_version(), suspend_ctrl.wake_src, + mmio_read_32(PCM_CON1)); + INFO("settle = %u, sec = %u, sw_flag = 0x%x 0x%x, src_req = 0x%x\n", + settle, mmio_read_32(PCM_TIMER_VAL) / 32768, + suspend_ctrl.pcm_flags, suspend_ctrl.pcm_flags1, + mmio_read_32(SPM_SRC_REQ)); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_RUNTIME); +} + +static void go_to_sleep_after_wfi(void) +{ + struct wake_status spm_wakesta; + + if (is_infra_pdn(suspend_ctrl.pcm_flags)) + mt_uart_restore(); + + spm_set_pcm_wdt(0); + spm_get_wakeup_status(&spm_wakesta); + spm_clean_after_wakeup(); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_BOOT); + + spm_output_wake_reason(&spm_wakesta, "suspend"); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_RUNTIME); +} + +static void spm_enable_armpll_l(void) +{ + /* power on */ + mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1); + + /* clear isolation */ + mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2); + + /* enable pll */ + mmio_setbits_32(ARMPLL_L_CON0, 0x1); + + /* Add 20us delay for turning on PLL */ + udelay(20); +} + +static void spm_disable_armpll_l(void) +{ + /* disable pll */ + mmio_clrbits_32(ARMPLL_L_CON0, 0x1); + + /* isolation */ + mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2); + + /* power off */ + mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1); +} + +void spm_system_suspend(void) +{ + spm_disable_armpll_l(); + bcpu_enable(0); + bcpu_sram_enable(0); + spm_lock_get(); + go_to_sleep_before_wfi(); + spm_lock_release(); +} + +void spm_system_suspend_finish(void) +{ + spm_lock_get(); + go_to_sleep_after_wfi(); + spm_lock_release(); + spm_enable_armpll_l(); + bcpu_sram_enable(1); + bcpu_enable(1); +} diff --git a/plat/mediatek/mt8183/drivers/spm/spm_suspend.h b/plat/mediatek/mt8183/drivers/spm/spm_suspend.h new file mode 100644 index 00000000..e127c2e7 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_suspend.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SPM_SUSPEND_H__ +#define __SPM_SUSPEND_H__ + +void spm_system_suspend(void); +void spm_system_suspend_finish(void); + +#endif /* __SPM_SUSPEND_H__*/ diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h index 613d4714..2228e63f 100644 --- a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h +++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h @@ -136,8 +136,7 @@ static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { /* * MCU configuration registers */ -#define MCUCFG_MP0_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp0_axi_config) -#define MCUCFG_MP1_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp1_axi_config) + /* bit-fields of MCUCFG_MP?_AXI_CONFIG */ #define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0) #define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1) @@ -146,11 +145,6 @@ static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { #define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4) #define MCUCFG_AXI_CONFIG_AINACTS (1 << 5) -/* per_cpu registers for MCUCFG_MP?_AXI_CONFIG */ -static const struct per_cpu_reg MCUCFG_SCUCTRL[] = { - [0] = { .cluster_addr = MCUCFG_MP0_AXI_CONFIG }, - [1] = { .cluster_addr = MCUCFG_MP1_AXI_CONFIG }, -}; #define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2]) #define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3]) diff --git a/plat/mediatek/mt8183/drivers/sspm/sspm.c b/plat/mediatek/mt8183/drivers/sspm/sspm.c new file mode 100644 index 00000000..39176381 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/sspm/sspm.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <errno.h> +#include <lib/mmio.h> +#include <sspm.h> + +static void memcpy_to_sspm(uint32_t dst, uint32_t *src, uint32_t len) +{ + while (len--) { + mmio_write_32(dst, *src); + dst += sizeof(uint32_t); + src++; + } +} + +static void memcpy_from_sspm(uint32_t *dst, uint32_t src, uint32_t len) +{ + while (len--) { + *dst = mmio_read_32(src); + dst++; + src += sizeof(uint32_t); + } +} + +int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len) +{ + if (slot >= 32) { + ERROR("%s:slot = %d\n", __func__, slot); + return -EINVAL; + } + + if (data) + memcpy_from_sspm(data, + MBOX3_BASE + slot * 4, + len); + + return 0; +} + +int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len) +{ + if (slot >= 32) { + ERROR("%s:slot = %d\n", __func__, slot); + return -EINVAL; + } + + if (data) + memcpy_to_sspm(MBOX3_BASE + slot * 4, + data, + len); + + return 0; +} + +static int sspm_ipi_check_ack(uint32_t id) +{ + int ret = 0; + + if (id == IPI_ID_PLATFORM) { + if ((mmio_read_32(MBOX0_BASE + MBOX_IN_IRQ_OFS) & 0x1) == 0x1) + ret = -EINPROGRESS; + } else if (id == IPI_ID_SUSPEND) { + if ((mmio_read_32(MBOX1_BASE + MBOX_IN_IRQ_OFS) & 0x2) == 0x2) + ret = -EINPROGRESS; + } else { + ERROR("%s: id = %d\n", __func__, id); + ret = -EINVAL; + } + + return ret; +} + +int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data) +{ + int ret = 0; + + ret = sspm_ipi_check_ack(id); + if (ret) + return ret; + + if (id == IPI_ID_PLATFORM) { + memcpy_to_sspm(MBOX0_BASE + PINR_OFFSET_PLATFORM * 4, + data, + PINR_SIZE_PLATFORM); + dsb(); + mmio_write_32(MBOX0_BASE + MBOX_OUT_IRQ_OFS, 0x1); + } else if (id == IPI_ID_SUSPEND) { + memcpy_to_sspm(MBOX1_BASE + PINR_OFFSET_SUSPEND * 4, + data, + PINR_SIZE_SUSPEND); + dsb(); + mmio_write_32(MBOX1_BASE + MBOX_OUT_IRQ_OFS, + 0x2); + } + + return 0; +} + +int sspm_ipi_recv_non_blocking(uint32_t id, uint32_t *data, uint32_t len) +{ + int ret = 0; + + ret = sspm_ipi_check_ack(id); + if (ret == -EINPROGRESS) { + if (id == IPI_ID_PLATFORM) { + memcpy_from_sspm(data, + MBOX0_BASE + PINR_OFFSET_PLATFORM * 4, + len); + dsb(); + /* clear interrupt bit*/ + mmio_write_32(MBOX0_BASE + MBOX_IN_IRQ_OFS, + 0x1); + ret = 0; + } else if (id == IPI_ID_SUSPEND) { + memcpy_from_sspm(data, + MBOX1_BASE + PINR_OFFSET_SUSPEND * 4, + len); + dsb(); + /* clear interrupt bit*/ + mmio_write_32(MBOX1_BASE + MBOX_IN_IRQ_OFS, + 0x2); + ret = 0; + } + } else if (ret == 0) { + ret = -EBUSY; + } + + return ret; +} + +int sspm_alive_show(void) +{ + uint32_t ipi_data, count; + int ret = 0; + + count = 5; + ipi_data = 0xdead; + + if (sspm_ipi_send_non_blocking(IPI_ID_PLATFORM, &ipi_data) != 0) { + ERROR("sspm init send fail! ret=%d\n", ret); + return -1; + } + + while (sspm_ipi_recv_non_blocking(IPI_ID_PLATFORM, + &ipi_data, + sizeof(ipi_data)) + && count) { + mdelay(100); + count--; + } + + return (ipi_data == 1) ? 0 : -1; +} diff --git a/plat/mediatek/mt8183/drivers/sspm/sspm.h b/plat/mediatek/mt8183/drivers/sspm/sspm.h new file mode 100644 index 00000000..2c2cc10e --- /dev/null +++ b/plat/mediatek/mt8183/drivers/sspm/sspm.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __SSPM_H__ +#define __SSPM_H__ +/* These should sync with sspm.bin */ +#define IPI_ID_PLATFORM 0 +#define IPI_ID_SUSPEND 6 +#define PINR_OFFSET_PLATFORM 0 +#define PINR_SIZE_PLATFORM 3 +#define PINR_OFFSET_SUSPEND 2 +#define PINR_SIZE_SUSPEND 8 + +#define MBOX0_BASE 0x10450000 +#define MBOX1_BASE 0x10460000 +#define MBOX3_BASE 0x10480000 +#define MBOX_OUT_IRQ_OFS 0x1000 +#define MBOX_IN_IRQ_OFS 0x1004 + +#define SHAREMBOX_OFFSET_MCDI 0 +#define SHAREMBOX_SIZE_MCDI 20 +#define SHAREMBOX_OFFSET_SUSPEND 26 +#define SHAREMBOX_SIZE_SUSPEND 6 + +int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len); +int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len); +int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data); +int sspm_ipi_recv_non_blocking(uint32_t slot, uint32_t *data, uint32_t len); +int sspm_alive_show(void); +#endif /* __SSPM_H__ */ diff --git a/plat/mediatek/mt8183/drivers/uart/uart.c b/plat/mediatek/mt8183/drivers/uart/uart.c new file mode 100644 index 00000000..3c6a9803 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/uart/uart.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> +#include <uart.h> + +static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS]; + +static const unsigned int uart_base_addr[DRV_SUPPORT_UART_PORTS] = { + UART0_BASE, + UART1_BASE +}; + +void mt_uart_restore(void) +{ + int uart_idx = UART_PORT0; + struct mt_uart *uart; + unsigned long base; + + /* Must NOT print any debug log before UART restore */ + for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS; + uart_idx++) { + + uart = &uart_save_addr[uart_idx]; + base = uart->base; + + mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); + mmio_write_32(UART_EFR(base), uart->registers.efr); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + mmio_write_32(UART_FCR(base), uart->registers.fcr); + + /* baudrate */ + mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); + mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); + mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); + mmio_write_32(UART_LCR(base), + uart->registers.lcr | UART_LCR_DLAB); + mmio_write_32(UART_DLL(base), uart->registers.dll); + mmio_write_32(UART_DLH(base), uart->registers.dlh); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + mmio_write_32(UART_SAMPLE_COUNT(base), + uart->registers.sample_count); + mmio_write_32(UART_SAMPLE_POINT(base), + uart->registers.sample_point); + mmio_write_32(UART_GUARD(base), uart->registers.guard); + + /* flow control */ + mmio_write_32(UART_ESCAPE_EN(base), uart->registers.escape_en); + mmio_write_32(UART_MCR(base), uart->registers.mcr); + mmio_write_32(UART_IER(base), uart->registers.ier); + mmio_write_32(UART_SCR(base), uart->registers.scr); + } +} + +void mt_uart_save(void) +{ + int uart_idx = UART_PORT0; + struct mt_uart *uart; + unsigned long base; + + for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS; + uart_idx++) { + + uart_save_addr[uart_idx].base = uart_base_addr[uart_idx]; + base = uart_base_addr[uart_idx]; + uart = &uart_save_addr[uart_idx]; + uart->registers.lcr = mmio_read_32(UART_LCR(base)); + + mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); + uart->registers.efr = mmio_read_32(UART_EFR(base)); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + uart->registers.fcr = mmio_read_32(UART_FCR_RD(base)); + + /* baudrate */ + uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base)); + uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base)); + uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base)); + mmio_write_32(UART_LCR(base), + uart->registers.lcr | UART_LCR_DLAB); + uart->registers.dll = mmio_read_32(UART_DLL(base)); + uart->registers.dlh = mmio_read_32(UART_DLH(base)); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + uart->registers.sample_count = mmio_read_32( + UART_SAMPLE_COUNT(base)); + uart->registers.sample_point = mmio_read_32( + UART_SAMPLE_POINT(base)); + uart->registers.guard = mmio_read_32(UART_GUARD(base)); + + /* flow control */ + uart->registers.escape_en = mmio_read_32(UART_ESCAPE_EN(base)); + uart->registers.mcr = mmio_read_32(UART_MCR(base)); + uart->registers.ier = mmio_read_32(UART_IER(base)); + uart->registers.scr = mmio_read_32(UART_SCR(base)); + } +} + +void mt_console_uart_cg(int on) +{ + if (on) + mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT); + else + mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT); +} + +int mt_console_uart_cg_status(void) +{ + return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT; +} diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h new file mode 100644 index 00000000..be04c350 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/uart/uart.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include <platform_def.h> + +/* UART HW information */ +#define HW_SUPPORT_UART_PORTS 2 +#define DRV_SUPPORT_UART_PORTS 2 + +/* console UART clock cg */ +#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80) +#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84) +#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90) +#define UART0_CLOCK_GATE_BIT (1U<<22) +#define UART1_CLOCK_GATE_BIT (1U<<23) + +/* UART registers */ +#define UART_RBR(_baseaddr) (_baseaddr + 0x0) +#define UART_THR(_baseaddr) (_baseaddr + 0x0) +#define UART_IER(_baseaddr) (_baseaddr + 0x4) +#define UART_IIR(_baseaddr) (_baseaddr + 0x8) +#define UART_FCR(_baseaddr) (_baseaddr + 0x8) +#define UART_LCR(_baseaddr) (_baseaddr + 0xc) +#define UART_MCR(_baseaddr) (_baseaddr + 0x10) +#define UART_LSR(_baseaddr) (_baseaddr + 0x14) +#define UART_MSR(_baseaddr) (_baseaddr + 0x18) +#define UART_SCR(_baseaddr) (_baseaddr + 0x1c) +#define UART_DLL(_baseaddr) (_baseaddr + 0x0) +#define UART_DLH(_baseaddr) (_baseaddr + 0x4) +#define UART_EFR(_baseaddr) (_baseaddr + 0x8) +#define UART_XON1(_baseaddr) (_baseaddr + 0x10) +#define UART_XON2(_baseaddr) (_baseaddr + 0x14) +#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18) +#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c) +#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20) +#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24) +#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28) +#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c) +#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30) +#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34) +#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38) +#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c) +#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40) +#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44) +#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48) +#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c) +#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50) +#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54) +#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58) +#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C) +#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0) +#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4) +#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8) +#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC) +#define UART_LCR_DLAB 0x0080 +#define UART_LCR_MODE_B 0x00bf + +enum uart_port_ID { + UART_PORT0 = 0, + UART_PORT1 +}; + +struct mt_uart_register { + unsigned int dll; + unsigned int dlh; + unsigned int ier; + unsigned int lcr; + unsigned int mcr; + unsigned int fcr; + unsigned int lsr; + unsigned int scr; + unsigned int efr; + unsigned int highspeed; + unsigned int sample_count; + unsigned int sample_point; + unsigned int fracdiv_l; + unsigned int fracdiv_m; + unsigned int escape_en; + unsigned int guard; + unsigned int rx_sel; +}; + +struct mt_uart { + unsigned long base; + struct mt_uart_register registers; +}; + +/* external API */ +void mt_uart_save(void); +void mt_uart_restore(void); +void mt_console_uart_cg(int on); +int mt_console_uart_cg_status(void); + +#endif /* __UART_H__ */ diff --git a/plat/mediatek/mt8183/include/mcucfg.h b/plat/mediatek/mt8183/include/mcucfg.h index 83ee88fa..6b03818d 100644 --- a/plat/mediatek/mt8183/include/mcucfg.h +++ b/plat/mediatek/mt8183/include/mcucfg.h @@ -28,51 +28,141 @@ struct mt8183_mcucfg_regs { uint32_t mp0_rw_rsvd0; /* 0x6C */ uint32_t mp0_rw_rsvd1; /* 0x70 */ uint32_t mp0_ro_rsvd; /* 0x74 */ - uint32_t reserved0_0[98]; /* 0x78 */ - uint32_t mp1_ca7l_cache_config; /* 0x200 */ - uint32_t mp1_miscdbg; /* 0x204 */ - uint32_t reserved0_1[9]; /* 0x208 */ - uint32_t mp1_axi_config; /* 0x22C */ - uint32_t mp1_misc_config[10]; /* 0x230 */ - uint32_t reserved0_2[3]; /* 0x258 */ - uint32_t mp1_ca7l_misc_config; /* 0x264 */ - uint32_t reserved0_3[310]; /* 0x268 */ + uint32_t reserved0_0; /* 0x78 */ + uint32_t mp0_l2_cache_parity1_rdata; /* 0x7C */ + uint32_t mp0_l2_cache_parity2_rdata; /* 0x80 */ + uint32_t reserved0_1; /* 0x84 */ + uint32_t mp0_rgu_dcm_config; /* 0x88 */ + uint32_t mp0_ca53_specific_ctrl; /* 0x8C */ + uint32_t mp0_esr_case; /* 0x90 */ + uint32_t mp0_esr_mask; /* 0x94 */ + uint32_t mp0_esr_trig_en; /* 0x98 */ + uint32_t reserved_0_2; /* 0x9C */ + uint32_t mp0_ses_cg_en; /* 0xA0 */ + uint32_t reserved0_3[216]; /* 0xA4 */ + uint32_t mp_dbg_ctrl; /* 0x404 */ + uint32_t reserved0_4[34]; /* 0x408 */ + uint32_t mp_dfd_ctrl; /* 0x490 */ + uint32_t dfd_cnt_l; /* 0x494 */ + uint32_t dfd_cnt_h; /* 0x498 */ + uint32_t misccfg_ro_rsvd; /* 0x49C */ + uint32_t reserved0_5[24]; /* 0x4A0 */ + uint32_t mp1_rst_status; /* 0x500 */ + uint32_t mp1_dbg_ctrl; /* 0x504 */ + uint32_t mp1_dbg_flag; /* 0x508 */ + uint32_t mp1_ca7l_ir_mon; /* 0x50C */ + uint32_t reserved0_6[32]; /* 0x510 */ + uint32_t mcusys_dbg_mon_sel_a; /* 0x590 */ + uint32_t mcucys_dbg_mon; /* 0x594 */ + uint32_t misccfg_sec_voi_status0; /* 0x598 */ + uint32_t misccfg_sec_vio_status1; /* 0x59C */ + uint32_t reserved0_7[18]; /* 0x5A0 */ + uint32_t gic500_int_mask; /* 0x5E8 */ + uint32_t core_rst_en_latch; /* 0x5EC */ + uint32_t reserved0_8[3]; /* 0x5F0 */ + uint32_t dbg_core_ret; /* 0x5FC */ + uint32_t mcusys_config_a; /* 0x600 */ + uint32_t mcusys_config1_a; /* 0x604 */ + uint32_t mcusys_gic_prebase_a; /* 0x608 */ + uint32_t mcusys_pinmux; /* 0x60C */ + uint32_t sec_range0_start; /* 0x610 */ + uint32_t sec_range0_end; /* 0x614 */ + uint32_t sec_range_enable; /* 0x618 */ + uint32_t l2c_mm_base; /* 0x61C */ + uint32_t reserved0_9[8]; /* 0x620 */ + uint32_t aclken_div; /* 0x640 */ + uint32_t pclken_div; /* 0x644 */ + uint32_t l2c_sram_ctrl; /* 0x648 */ + uint32_t armpll_jit_ctrl; /* 0x64C */ + uint32_t cci_addrmap; /* 0x650 */ + uint32_t cci_config; /* 0x654 */ + uint32_t cci_periphbase; /* 0x658 */ + uint32_t cci_nevntcntovfl; /* 0x65C */ + uint32_t cci_clk_ctrl; /* 0x660 */ + uint32_t cci_acel_s1_ctrl; /* 0x664 */ + uint32_t mcusys_bus_fabric_dcm_ctrl; /* 0x668 */ + uint32_t mcu_misc_dcm_ctrl; /* 0x66C */ + uint32_t xgpt_ctl; /* 0x670 */ + uint32_t xgpt_idx; /* 0x674 */ + uint32_t reserved0_10[3]; /* 0x678 */ + uint32_t mcusys_rw_rsvd0; /* 0x684 */ + uint32_t mcusys_rw_rsvd1; /* 0x688 */ + uint32_t reserved0_11[13]; /* 0x68C */ + uint32_t gic_500_delsel_ctl; /* 0x6C0 */ + uint32_t etb_delsel_ctl; /* 0x6C4 */ + uint32_t etb_rst_ctl; /* 0x6C8 */ + uint32_t reserved0_12[29]; /* 0x6CC */ uint32_t cci_adb400_dcm_config; /* 0x740 */ uint32_t sync_dcm_config; /* 0x744 */ - uint32_t reserved0_4[16]; /* 0x748 */ - uint32_t mp0_cputop_spmc_ctl; /* 0x788 */ - uint32_t mp1_cputop_spmc_ctl; /* 0x78C */ - uint32_t mp1_cputop_spmc_sram_ctl; /* 0x790 */ - uint32_t reserved0_5[23]; /* 0x794 */ + uint32_t reserved0_13; /* 0x748 */ + uint32_t sync_dcm_cluster_config; /* 0x74C */ + uint32_t sw_udi; /* 0x750 */ + uint32_t reserved0_14; /* 0x754 */ + uint32_t gic_sync_dcm; /* 0x758 */ + uint32_t big_dbg_pwr_ctrl; /* 0x75C */ + uint32_t gic_cpu_periphbase; /* 0x760 */ + uint32_t axi_cpu_config; /* 0x764 */ + uint32_t reserved0_15[2]; /* 0x768 */ + uint32_t mcsib_sys_ctrl1; /* 0x770 */ + uint32_t mcsib_sys_ctrl2; /* 0x774 */ + uint32_t mcsib_sys_ctrl3; /* 0x778 */ + uint32_t mcsib_sys_ctrl4; /* 0x77C */ + uint32_t mcsib_dbg_ctrl1; /* 0x780 */ + uint32_t pwrmcu_apb2to1; /* 0x784 */ + uint32_t mp0_spmc; /* 0x788 */ + uint32_t reserved0_16; /* 0x78C */ + uint32_t mp0_spmc_sram_ctl; /* 0x790 */ + uint32_t reserved0_17; /* 0x794 */ + uint32_t mp0_sw_rst_wait_cycle; /* 0x798 */ + uint32_t reserved0_18; /* 0x79C */ + uint32_t mp0_pll_divider_cfg; /* 0x7A0 */ + uint32_t reserved0_19; /* 0x7A4 */ + uint32_t mp2_pll_divider_cfg; /* 0x7A8 */ + uint32_t reserved0_20[5]; /* 0x7AC */ + uint32_t bus_pll_divider_cfg; /* 0x7C0 */ + uint32_t reserved0_21[7]; /* 0x7C4 */ + uint32_t clusterid_aff1; /* 0x7E0 */ + uint32_t clusterid_aff2; /* 0x7E4 */ + uint32_t reserved0_22[2]; /* 0x7E8 */ uint32_t l2_cfg_mp0; /* 0x7F0 */ uint32_t l2_cfg_mp1; /* 0x7F4 */ - uint32_t reserved0_6[1282]; /* 0x7F8 */ + uint32_t reserved0_23[218]; /* 0x7F8 */ + uint32_t mscib_dcm_en; /* 0xB60 */ + uint32_t reserved0_24[1063]; /* 0xB64 */ uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */ uint32_t cpusys0_sparken; /* 0x1C04 */ uint32_t cpusys0_amuxsel; /* 0x1C08 */ - uint32_t reserved0_7[9]; /* 0x1C0C */ + uint32_t reserved0_25[9]; /* 0x1C0C */ uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */ uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */ uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */ uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */ - uint32_t reserved0_8[370]; /* 0x1C40 */ + uint32_t reserved0_26[8]; /* 0x1C40 */ + uint32_t mp0_sync_dcm_cgavg_ctrl; /* 0x1C60 */ + uint32_t mp0_sync_dcm_cgavg_fact; /* 0x1C64 */ + uint32_t mp0_sync_dcm_cgavg_rfact; /* 0x1C68 */ + uint32_t mp0_sync_dcm_cgavg; /* 0x1C6C */ + uint32_t mp0_l2_parity_clr; /* 0x1C70 */ + uint32_t reserved0_27[357]; /* 0x1C74 */ uint32_t mp2_cpucfg; /* 0x2208 */ uint32_t mp2_axi_config; /* 0x220C */ - uint32_t reserved0_9[36]; /* 0x2210 */ - uint32_t mp2_cputop_spm_ctl; /* 0x22A0 */ - uint32_t mp2_cputop_spm_sta; /* 0x22A4 */ - uint32_t reserved0_10[98]; /* 0x22A8 */ - uint32_t cpusys2_cpu0_spmc_ctl; /* 0x2430 */ - uint32_t cpusys2_cpu0_spmc_sta; /* 0x2434 */ - uint32_t cpusys2_cpu1_spmc_ctl; /* 0x2438 */ - uint32_t cpusys2_cpu1_spmc_sta; /* 0x243C */ - uint32_t reserved0_11[176]; /* 0x2440 */ + uint32_t reserved0_28[25]; /* 0x2210 */ + uint32_t mp2_sync_dcm; /* 0x2274 */ + uint32_t reserved0_29[10]; /* 0x2278 */ + uint32_t ptp3_cputop_spmc0; /* 0x22A0 */ + uint32_t ptp3_cputop_spmc1; /* 0x22A4 */ + uint32_t reserved0_30[98]; /* 0x22A8 */ + uint32_t ptp3_cpu0_spmc0; /* 0x2430 */ + uint32_t ptp3_cpu0_spmc1; /* 0x2434 */ + uint32_t ptp3_cpu1_spmc0; /* 0x2438 */ + uint32_t ptp3_cpu1_spmc1; /* 0x243C */ + uint32_t ptp3_cpu2_spmc0; /* 0x2440 */ + uint32_t ptp3_cpu2_spmc1; /* 0x2444 */ + uint32_t ptp3_cpu3_spmc0; /* 0x2448 */ + uint32_t ptp3_cpu3_spmc1; /* 0x244C */ + uint32_t ptp3_cpux_spmc; /* 0x2450 */ + uint32_t reserved0_31[171]; /* 0x2454 */ uint32_t spark2ld0; /* 0x2700 */ - uint32_t reserved0_12[1355]; /* 0x2704 */ - uint32_t cpusys1_cpu0_spmc_ctl; /* 0x3C30 */ - uint32_t cpusys1_cpu1_spmc_ctl; /* 0x3C34 */ - uint32_t cpusys1_cpu2_spmc_ctl; /* 0x3C38 */ - uint32_t cpusys1_cpu3_spmc_ctl; /* 0x3C3C */ }; static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE; @@ -244,4 +334,235 @@ enum { MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT }; +/* bus pll divider dcm related */ +enum { + BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT = 11, + BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + + BUS_PLLDIV_DCM = (1 << BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT) | + (1 << BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT) +}; + +/* mp0 pll divider dcm related */ +enum { + MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11, + MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31, + MP0_PLLDIV_DCM = (1 << MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT) | + (1 << MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT) | + (1u << MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT) +}; + +/* mp2 pll divider dcm related */ +enum { + MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11, + MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31, + MP2_PLLDIV_DCM = (1 << MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT) | + (1 << MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT) | + (1u << MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT) +}; + +/* mcsib dcm related */ +enum { + MCSIB_CACTIVE_SEL_SHIFT = 0, + MCSIB_DCM_EN_SHIFT = 16, + + MCSIB_CACTIVE_SEL_MASK = 0xffff << MCSIB_CACTIVE_SEL_SHIFT, + MCSIB_CACTIVE_SEL = 0xffff << MCSIB_CACTIVE_SEL_SHIFT, + + MCSIB_DCM_MASK = 0xffffu << MCSIB_DCM_EN_SHIFT, + MCSIB_DCM = 0xffffu << MCSIB_DCM_EN_SHIFT, +}; + +/* cci adb400 dcm related */ +enum { + CCI_M0_ADB400_DCM_EN_SHIFT = 0, + CCI_M1_ADB400_DCM_EN_SHIFT = 1, + CCI_M2_ADB400_DCM_EN_SHIFT = 2, + CCI_S2_ADB400_DCM_EN_SHIFT = 3, + CCI_S3_ADB400_DCM_EN_SHIFT = 4, + CCI_S4_ADB400_DCM_EN_SHIFT = 5, + CCI_S5_ADB400_DCM_EN_SHIFT = 6, + ACP_S3_ADB400_DCM_EN_SHIFT = 11, + + CCI_ADB400_DCM_MASK = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M1_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M2_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S2_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S5_ADB400_DCM_EN_SHIFT) | + (1 << ACP_S3_ADB400_DCM_EN_SHIFT), + CCI_ADB400_DCM = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M1_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M2_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S2_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S5_ADB400_DCM_EN_SHIFT) | + (1 << ACP_S3_ADB400_DCM_EN_SHIFT) +}; + +/* sync dcm related */ +enum { + CCI_SYNC_DCM_DIV_EN_SHIFT = 0, + CCI_SYNC_DCM_UPDATE_TOG_SHIFT = 1, + CCI_SYNC_DCM_DIV_SEL_SHIFT = 2, + MP0_SYNC_DCM_DIV_EN_SHIFT = 10, + MP0_SYNC_DCM_UPDATE_TOG_SHIFT = 11, + MP0_SYNC_DCM_DIV_SEL_SHIFT = 12, + + SYNC_DCM_MASK = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) | + (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0x7f << CCI_SYNC_DCM_DIV_SEL_SHIFT) | + (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) | + (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0x7f << MP0_SYNC_DCM_DIV_SEL_SHIFT), + SYNC_DCM = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) | + (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0 << CCI_SYNC_DCM_DIV_SEL_SHIFT) | + (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) | + (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0 << MP0_SYNC_DCM_DIV_SEL_SHIFT) +}; + +/* mcu bus dcm related */ +enum { + MCU_BUS_DCM_EN_SHIFT = 8, + MCU_BUS_DCM = 1 << MCU_BUS_DCM_EN_SHIFT +}; + +/* mcusys bus fabric dcm related */ +enum { + ACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 0, + EMI2_ADB400_S_DCM_CTRL_SHIFT = 1, + ACLK_GPU_DYNAMIC_CG_EN_SHIFT = 2, + ACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 3, + MP0_ADB400_S_DCM_CTRL_SHIFT = 4, + MP0_ADB400_M_DCM_CTRL_SHIFT = 5, + MP1_ADB400_S_DCM_CTRL_SHIFT = 6, + MP1_ADB400_M_DCM_CTRL_SHIFT = 7, + EMICLK_EMI_DYNAMIC_CG_EN_SHIFT = 8, + INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 9, + EMICLK_GPU_DYNAMIC_CG_EN_SHIFT = 10, + INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 11, + EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT = 12, + EMI1_ADB400_S_DCM_CTRL_SHIFT = 16, + MP2_ADB400_M_DCM_CTRL_SHIFT = 17, + MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT = 18, + MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT = 19, + MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT = 20, + L2_SHARE_ADB400_DCM_CTRL_SHIFT = 21, + MP1_AGGRESS_DCM_CTRL_SHIFT = 22, + MP0_AGGRESS_DCM_CTRL_SHIFT = 23, + MP0_ADB400_ACP_S_DCM_CTRL_SHIFT = 24, + MP0_ADB400_ACP_M_DCM_CTRL_SHIFT = 25, + MP1_ADB400_ACP_S_DCM_CTRL_SHIFT = 26, + MP1_ADB400_ACP_M_DCM_CTRL_SHIFT = 27, + MP3_ADB400_M_DCM_CTRL_SHIFT = 28, + MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT = 29, + + MCUSYS_BUS_FABRIC_DCM_MASK = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) | + (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << MP0_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) | + (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP2_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) | + (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT), + + MCUSYS_BUS_FABRIC_DCM = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) | + (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (0 << MP0_ADB400_S_DCM_CTRL_SHIFT) | + (0 << MP0_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) | + (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) | + (0 << MP2_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) | + (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT) +}; + +/* l2c_sram dcm related */ +enum { + L2C_SRAM_DCM_EN_SHIFT = 0, + L2C_SRAM_DCM = 1 << L2C_SRAM_DCM_EN_SHIFT +}; + +/* mcu misc dcm related */ +enum { + MP0_CNTVALUEB_DCM_EN_SHIFT = 0, + MP_CNTVALUEB_DCM_EN = 8, + + CNTVALUEB_DCM = (1 << MP0_CNTVALUEB_DCM_EN_SHIFT) | + (1 << MP_CNTVALUEB_DCM_EN) +}; + +/* sync dcm cluster config related */ +enum { + MP0_SYNC_DCM_STALL_WR_EN_SHIFT = 7, + MCUSYS_MAX_ACCESS_LATENCY_SHIFT = 24, + + MCU0_SYNC_DCM_STALL_WR_EN = 1 << MP0_SYNC_DCM_STALL_WR_EN_SHIFT, + + MCUSYS_MAX_ACCESS_LATENCY_MASK = 0xf << MCUSYS_MAX_ACCESS_LATENCY_SHIFT, + MCUSYS_MAX_ACCESS_LATENCY = 0x5 << MCUSYS_MAX_ACCESS_LATENCY_SHIFT +}; + +/* cpusys rgu dcm related */ +enum { + CPUSYS_RGU_DCM_CONFIG_SHIFT = 0, + + CPUSYS_RGU_DCM_CINFIG = 1 << CPUSYS_RGU_DCM_CONFIG_SHIFT +}; + +/* mp2 sync dcm related */ +enum { + MP2_DCM_EN_SHIFT = 0, + + MP2_DCM_EN = 1 << MP2_DCM_EN_SHIFT +}; #endif /* MT8183_MCUCFG_H */ diff --git a/plat/mediatek/mt8183/include/plat_debug.h b/plat/mediatek/mt8183/include/plat_debug.h index e51a6ea8..c9d73cc8 100644 --- a/plat/mediatek/mt8183/include/plat_debug.h +++ b/plat/mediatek/mt8183/include/plat_debug.h @@ -24,8 +24,6 @@ #define BIT_CA15M_L2PARITY_EN (1 << 1) #define BIT_CA15M_LASTPC_DIS (1 << 8) -#define MP1_CPUTOP_PWR_CON 0x10006218 - #define MCU_ALL_PWR_ON_CTRL 0x0c530b58 #define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133 #define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134 diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index f802ac2f..766e7665 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -41,6 +41,7 @@ #define APMIXEDSYS (IO_PHYS + 0xC000) #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) +#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) #define MAINPLL_CON0 (APMIXEDSYS + 0x220) #define CCIPLL_CON0 (APMIXEDSYS + 0x290) @@ -74,6 +75,7 @@ #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604) #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0) #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4) +#define EMI_WFIFO (MCUCFG_BASE + 0x0b5c) /******************************************************************************* * GIC related constants @@ -87,6 +89,7 @@ * UART related constants ******************************************************************************/ #define UART0_BASE (IO_PHYS + 0x01002000) +#define UART1_BASE (IO_PHYS + 0x01003000) #define UART_BAUDRATE 115200 #define UART_CLOCK 26000000 diff --git a/plat/mediatek/mt8183/include/spm.h b/plat/mediatek/mt8183/include/spm.h deleted file mode 100644 index 208d760d..00000000 --- a/plat/mediatek/mt8183/include/spm.h +++ /dev/null @@ -1,1715 +0,0 @@ -/* - * Copyright (c) 2019, MediaTek Inc. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_H -#define SPM_H - -#define POWERON_CONFIG_EN (SPM_BASE + 0x000) -#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) -#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) -#define SPM_CLK_CON (SPM_BASE + 0x00C) -#define SPM_CLK_SETTLE (SPM_BASE + 0x010) -#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) -#define PCM_CON0 (SPM_BASE + 0x018) -#define PCM_CON1 (SPM_BASE + 0x01C) -#define PCM_IM_PTR (SPM_BASE + 0x020) -#define PCM_IM_LEN (SPM_BASE + 0x024) -#define PCM_REG_DATA_INI (SPM_BASE + 0x028) -#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) -#define PCM_TIMER_VAL (SPM_BASE + 0x030) -#define PCM_WDT_VAL (SPM_BASE + 0x034) -#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) -#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) -#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) -#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) -#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) -#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) -#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) -#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) -#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) -#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) -#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) -#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) -#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) -#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) -#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) -#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) -#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) -#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) -#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) -#define SPM_SWINT (SPM_BASE + 0x08C) -#define SPM_SWINT_SET (SPM_BASE + 0x090) -#define SPM_SWINT_CLR (SPM_BASE + 0x094) -#define SPM_SCP_MAILBOX (SPM_BASE + 0x098) -#define SPM_SCP_IRQ (SPM_BASE + 0x09C) -#define SPM_TWAM_CON (SPM_BASE + 0x0A0) -#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) -#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) -#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) -#define SPM_IRQ_MASK (SPM_BASE + 0x0B4) -#define SPM_SRC_REQ (SPM_BASE + 0x0B8) -#define SPM_SRC_MASK (SPM_BASE + 0x0BC) -#define SPM_SRC2_MASK (SPM_BASE + 0x0C0) -#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) -#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) -#define SCP_CLK_CON (SPM_BASE + 0x0D0) -#define PCM_DEBUG_CON (SPM_BASE + 0x0D4) -#define PCM_REG0_DATA (SPM_BASE + 0x100) -#define PCM_REG1_DATA (SPM_BASE + 0x104) -#define PCM_REG2_DATA (SPM_BASE + 0x108) -#define PCM_REG3_DATA (SPM_BASE + 0x10C) -#define PCM_REG4_DATA (SPM_BASE + 0x110) -#define PCM_REG5_DATA (SPM_BASE + 0x114) -#define PCM_REG6_DATA (SPM_BASE + 0x118) -#define PCM_REG7_DATA (SPM_BASE + 0x11C) -#define PCM_REG8_DATA (SPM_BASE + 0x120) -#define PCM_REG9_DATA (SPM_BASE + 0x124) -#define PCM_REG10_DATA (SPM_BASE + 0x128) -#define PCM_REG11_DATA (SPM_BASE + 0x12C) -#define PCM_REG12_DATA (SPM_BASE + 0x130) -#define PCM_REG13_DATA (SPM_BASE + 0x134) -#define PCM_REG14_DATA (SPM_BASE + 0x138) -#define PCM_REG15_DATA (SPM_BASE + 0x13C) -#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) -#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) -#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) -#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) -#define PCM_TIMER_OUT (SPM_BASE + 0x150) -#define PCM_WDT_OUT (SPM_BASE + 0x154) -#define SPM_IRQ_STA (SPM_BASE + 0x158) -#define SPM_WAKEUP_STA (SPM_BASE + 0x15C) -#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) -#define SPM_WAKEUP_MISC (SPM_BASE + 0x164) -#define BUS_PROTECT_RDY (SPM_BASE + 0x168) -#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) -#define SUBSYS_IDLE_STA (SPM_BASE + 0x170) -#define CPU_IDLE_STA (SPM_BASE + 0x174) -#define PCM_FSM_STA (SPM_BASE + 0x178) -#define PWR_STATUS (SPM_BASE + 0x180) -#define PWR_STATUS_2ND (SPM_BASE + 0x184) -#define CPU_PWR_STATUS (SPM_BASE + 0x188) -#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) -#define PCM_WDT_LATCH_0 (SPM_BASE + 0x190) -#define PCM_WDT_LATCH_1 (SPM_BASE + 0x194) -#define PCM_WDT_LATCH_2 (SPM_BASE + 0x198) -#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) -#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) -#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) -#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) -#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) -#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) -#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) -#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) -#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) -#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) -#define PCM_WDT_LATCH_3 (SPM_BASE + 0x1C4) -#define SPM_SRC_RDY_STA (SPM_BASE + 0x1D0) -#define MISC_STA (SPM_BASE + 0x1D4) -#define MCU_PWR_CON (SPM_BASE + 0x200) -#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) -#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) -#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) -#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) -#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) -#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) -#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) -#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) -#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) -#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) -#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) -#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) -#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) -#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) -#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) -#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) -#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) -#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) -#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) -#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) -#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) -#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) -#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) -#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) -#define BYPASS_SPMC (SPM_BASE + 0x2B4) -#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) -#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) -#define SPMC_IN_RET (SPM_BASE + 0x2C0) -#define VDE_PWR_CON (SPM_BASE + 0x300) -#define VEN_PWR_CON (SPM_BASE + 0x304) -#define ISP_PWR_CON (SPM_BASE + 0x308) -#define DIS_PWR_CON (SPM_BASE + 0x30C) -#define MJC_PWR_CON (SPM_BASE + 0x310) -#define AUDIO_PWR_CON (SPM_BASE + 0x314) -#define IFR_PWR_CON (SPM_BASE + 0x318) -#define DPY_PWR_CON (SPM_BASE + 0x31C) -#define MD1_PWR_CON (SPM_BASE + 0x320) -#define MD2_PWR_CON (SPM_BASE + 0x324) -#define C2K_PWR_CON (SPM_BASE + 0x328) -#define CONN_PWR_CON (SPM_BASE + 0x32C) -#define VCOREPDN_PWR_CON (SPM_BASE + 0x330) -#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) -#define MFG_PWR_CON (SPM_BASE + 0x338) -#define MFG_CORE0_PWR_CON (SPM_BASE + 0x33C) -#define MFG_CORE1_PWR_CON (SPM_BASE + 0x340) -#define CAM_PWR_CON (SPM_BASE + 0x344) -#define SYSRAM_CON (SPM_BASE + 0x350) -#define SYSROM_CON (SPM_BASE + 0x354) -#define SCP_SRAM_CON (SPM_BASE + 0x358) -#define GCPU_SRAM_CON (SPM_BASE + 0x35C) -#define MDSYS_INTF_INFRA_PWR_CON (SPM_BASE + 0x360) -#define MDSYS_INTF_MD1_PWR_CON (SPM_BASE + 0x364) -#define MDSYS_INTF_C2K_PWR_CON (SPM_BASE + 0x368) -#define BSI_TOP_SRAM_CON (SPM_BASE + 0x370) -#define DVFSP_SRAM_CON (SPM_BASE + 0x374) -#define MD_EXT_BUCK_ISO (SPM_BASE + 0x390) -#define DUMMY2_PWR_CON (SPM_BASE + 0x3B0) -#define MD1_OUTPUT_PISO_S_EN_IZ (SPM_BASE + 0x3B4) -#define SPM_DVFS_CON (SPM_BASE + 0x400) -#define SPM_MDBSI_CON (SPM_BASE + 0x404) -#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) -#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) -#define SPM_BSI_GEN (SPM_BASE + 0x410) -#define SPM_BSI_EN_SR (SPM_BASE + 0x414) -#define SPM_BSI_CLK_SR (SPM_BASE + 0x418) -#define SPM_BSI_D0_SR (SPM_BASE + 0x41C) -#define SPM_BSI_D1_SR (SPM_BASE + 0x420) -#define SPM_BSI_D2_SR (SPM_BASE + 0x424) -#define SPM_AP_SEMA (SPM_BASE + 0x428) -#define SPM_SPM_SEMA (SPM_BASE + 0x42C) -#define AP2MD_CROSS_TRIGGER (SPM_BASE + 0x430) -#define AP_MDSRC_REQ (SPM_BASE + 0x434) -#define SPM2MD_DVFS_CON (SPM_BASE + 0x438) -#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) -#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) -#define DPY_LP_CON (SPM_BASE + 0x444) -#define CPU_DVFS_REQ (SPM_BASE + 0x448) -#define SPM_PLL_CON (SPM_BASE + 0x44C) -#define SPM_EMI_BW_MODE (SPM_BASE + 0x450) -#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) -#define ULPOSC_CON (SPM_BASE + 0x458) -#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) -#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) -#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) -#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) -#define SPM_SEMA_M0 (SPM_BASE + 0x480) -#define SPM_SEMA_M1 (SPM_BASE + 0x484) -#define SPM_SEMA_M2 (SPM_BASE + 0x488) -#define SPM_SEMA_M3 (SPM_BASE + 0x48C) -#define SPM_SEMA_M4 (SPM_BASE + 0x490) -#define SPM_SEMA_M5 (SPM_BASE + 0x494) -#define SPM_SEMA_M6 (SPM_BASE + 0x498) -#define SPM_SEMA_M7 (SPM_BASE + 0x49C) -#define SPM_SEMA_M8 (SPM_BASE + 0x4A0) -#define SPM_SEMA_M9 (SPM_BASE + 0x4A4) -#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) -#define SRAM_DREQ_CON (SPM_BASE + 0x4B0) -#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) -#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) -#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) -#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) -#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) -#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) -#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) -#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) -#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) -#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) -#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) -#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) -#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) -#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) -#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) -#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) -#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) -#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) -#define CPU_PTPOD2_CON (SPM_BASE + 0x560) -#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) -#define ROOT_CORE_ADDR (SPM_BASE + 0x574) -#define CPU_SPARE_CON (SPM_BASE + 0x580) -#define CPU_SPARE_CON_SET (SPM_BASE + 0x584) -#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) -#define SPM_SW_FLAG (SPM_BASE + 0x600) -#define SPM_SW_DEBUG (SPM_BASE + 0x604) -#define SPM_SW_RSV_0 (SPM_BASE + 0x608) -#define SPM_SW_RSV_1 (SPM_BASE + 0x60C) -#define SPM_SW_RSV_2 (SPM_BASE + 0x610) -#define SPM_SW_RSV_3 (SPM_BASE + 0x614) -#define SPM_SW_RSV_4 (SPM_BASE + 0x618) -#define SPM_SW_RSV_5 (SPM_BASE + 0x61C) -#define SPM_RSV_CON (SPM_BASE + 0x620) -#define SPM_RSV_STA (SPM_BASE + 0x624) -#define SPM_PASR_DPD_0 (SPM_BASE + 0x630) -#define SPM_PASR_DPD_1 (SPM_BASE + 0x634) -#define SPM_PASR_DPD_2 (SPM_BASE + 0x638) -#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) -#define SPM_SPARE_CON (SPM_BASE + 0x640) -#define SPM_SPARE_CON_SET (SPM_BASE + 0x644) -#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) -#define SPM_SW_RSV_6 (SPM_BASE + 0x64C) -#define SPM_SW_RSV_7 (SPM_BASE + 0x650) -#define SPM_SW_RSV_8 (SPM_BASE + 0x654) -#define SPM_SW_RSV_9 (SPM_BASE + 0x658) -#define SPM_SW_RSV_10 (SPM_BASE + 0x65C) -#define SPM_SW_RSV_11 (SPM_BASE + 0x660) -#define SPM_SW_RSV_12 (SPM_BASE + 0x664) -#define SPM_SW_RSV_13 (SPM_BASE + 0x668) -#define SPM_SW_RSV_14 (SPM_BASE + 0x66C) -#define SPM_SW_RSV_15 (SPM_BASE + 0x670) -#define SPM_SW_RSV_16 (SPM_BASE + 0x674) -#define SPM_SW_RSV_17 (SPM_BASE + 0x678) -#define SPM_SW_RSV_18 (SPM_BASE + 0x67C) -#define SPM_SW_RSV_19 (SPM_BASE + 0x680) -#define SW_CRTL_EVENT (SPM_BASE + 0x690) - - -#define MP1_CPU3_PWR_STA_MASK (1U << 19) -#define MP1_CPU2_PWR_STA_MASK (1U << 18) -#define MP1_CPU1_PWR_STA_MASK (1U << 17) -#define MP1_CPU0_PWR_STA_MASK (1U << 16) -#define MP1_CPUTOP_PWR_STA_MASK (1U << 15) -#define MCU_PWR_STA_MASK (1U << 14) -#define MP0_CPU3_PWR_STA_MASK (1U << 12) -#define MP0_CPU2_PWR_STA_MASK (1U << 11) -#define MP0_CPU1_PWR_STA_MASK (1U << 10) -#define MP0_CPU0_PWR_STA_MASK (1U << 9) -#define MP0_CPUTOP_PWR_STA_MASK (1U << 8) - - -#define MP1_CPU3_STANDBYWFI (1U << 17) -#define MP1_CPU2_STANDBYWFI (1U << 16) -#define MP1_CPU1_STANDBYWFI (1U << 15) -#define MP1_CPU0_STANDBYWFI (1U << 14) -#define MP0_CPU3_STANDBYWFI (1U << 13) -#define MP0_CPU2_STANDBYWFI (1U << 12) -#define MP0_CPU1_STANDBYWFI (1U << 11) -#define MP0_CPU0_STANDBYWFI (1U << 10) - -#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) -#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) -#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) - -/* POWERON_CONFIG_EN (0x10006000+0x000) */ -#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ -#define PROJECT_CODE_LSB (1U << 16) /* 16b */ - -/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ -#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ - -/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ -#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ - -/* SPM_CLK_CON (0x10006000+0x00C) */ -#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ -#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ -#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ -#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ -#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ -#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ -#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ -#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ -#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ -#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ -#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ -#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ -#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ -#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ - -/* SPM_CLK_SETTLE (0x10006000+0x010) */ -#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ - -/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ -#define WFI_OP_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ -#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ -#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ -#define MM_MASK_B_LSB (1U << 16) /* 2b */ -#define MD_DDR_EN_DBC_EN_LSB (1U << 18) /* 1b */ -#define MD_MASK_B_LSB (1U << 19) /* 2b */ -#define SCP_MASK_B_LSB (1U << 21) /* 1b */ -#define LTE_MASK_B_LSB (1U << 22) /* 1b */ -#define SRCCLKENI_MASK_B_LSB (1U << 23) /* 1b */ -#define MD_APSRC_1_SEL_LSB (1U << 24) /* 1b */ -#define MD_APSRC_0_SEL_LSB (1U << 25) /* 1b */ -#define CONN_MASK_B_LSB (1U << 26) /* 1b */ -#define CONN_APSRC_SEL_LSB (1U << 27) /* 1b */ - -/* PCM_CON0 (0x10006000+0x018) */ -#define PCM_KICK_L_LSB (1U << 0) /* 1b */ -#define IM_KICK_L_LSB (1U << 1) /* 1b */ -#define PCM_CK_EN_LSB (1U << 2) /* 1b */ -#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ -#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ -#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ -#define PROJECT_CODE_LSB (1U << 16) /* 16b */ - -/* PCM_CON1 (0x10006000+0x01C) */ -#define IM_SLAVE_LSB (1U << 0) /* 1b */ -#define IM_SLEEP_LSB (1U << 1) /* 1b */ -#define MIF_APBEN_LSB (1U << 3) /* 1b */ -#define IM_PDN_LSB (1U << 4) /* 1b */ -#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ -#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ -#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ -#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ -#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ -#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ -#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ -#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ -#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ -#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ -#define PROJECT_CODE_LSB (1U << 16) /* 16b */ - -/* PCM_IM_PTR (0x10006000+0x020) */ -#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ - -/* PCM_IM_LEN (0x10006000+0x024) */ -#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ - -/* PCM_REG_DATA_INI (0x10006000+0x028) */ -#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ - -/* PCM_PWR_IO_EN (0x10006000+0x02C) */ -#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ -#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ - -/* PCM_TIMER_VAL (0x10006000+0x030) */ -#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_VAL (0x10006000+0x034) */ -#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ - -/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ -#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ -#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ -#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ - -/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ -#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ - -/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ -#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ -#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ -#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ -#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ -#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ -#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ -#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ -#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ -#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ -#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ -#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ -#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ -#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ -#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ -#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ -#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ -#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ - -/* SPM_SWINT (0x10006000+0x08C) */ -#define SPM_SWINT_LSB (1U << 0) /* 10b */ - -/* SPM_SWINT_SET (0x10006000+0x090) */ -#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ - -/* SPM_SWINT_CLR (0x10006000+0x094) */ -#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ - -/* SPM_SCP_MAILBOX (0x10006000+0x098) */ -#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ - -/* SPM_SCP_IRQ (0x10006000+0x09C) */ -#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ -#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ - -/* SPM_TWAM_CON (0x10006000+0x0A0) */ -#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ -#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ -#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ -#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ -#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ -#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ -#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ -#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ -#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ -#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ -#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ - -/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ -#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ -#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ - -/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ -#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ - -/* SPM_IRQ_MASK (0x10006000+0x0B4) */ -#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ -#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ -#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ - -/* SPM_SRC_REQ (0x10006000+0x0B8) */ -#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ -#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ -#define SPM_LTE_REQ_LSB (1U << 2) /* 1b */ -#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ -#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ -#define SPM_DVFS_REQ_LSB (1U << 5) /* 1b */ -#define SPM_DVFS_FORCE_DOWN_LSB (1U << 6) /* 1b */ -#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ -#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ -#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ - -/* SPM_SRC_MASK (0x10006000+0x0BC) */ -#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ -#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ -#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ -#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ -#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ -#define CCIFMD_MD1_EVENT_MASK_B_LSB (1U << 5) /* 1b */ -#define CCIFMD_MD2_EVENT_MASK_B_LSB (1U << 6) /* 1b */ -#define DSI0_VSYNC_MASK_B_LSB (1U << 7) /* 1b */ -#define DSI1_VSYNC_MASK_B_LSB (1U << 8) /* 1b */ -#define DPI_VSYNC_MASK_B_LSB (1U << 9) /* 1b */ -#define ISP0_VSYNC_MASK_B_LSB (1U << 10) /* 1b */ -#define ISP1_VSYNC_MASK_B_LSB (1U << 11) /* 1b */ -#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 12) /* 1b */ -#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 13) /* 1b */ -#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 14) /* 1b */ -#define MD32_SRCCLKENA_INFRA_MASK_B_LSB (1U << 15) /* 1b */ -#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 16) /* 1b */ -#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 17) /* 1b */ -#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 18) /* 1b */ -#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 19) /* 1b */ -#define MD32_APSRCREQ_INFRA_MASK_B_LSB (1U << 20) /* 1b */ -#define MD_DDR_EN_0_MASK_B_LSB (1U << 21) /* 1b */ -#define MD_DDR_EN_1_MASK_B_LSB (1U << 22) /* 1b */ -#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 23) /* 1b */ -#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 24) /* 1b */ -#define MD1_DVFS_REQ_MASK_LSB (1U << 25) /* 2b */ -#define CPU_DVFS_REQ_MASK_LSB (1U << 27) /* 1b */ -#define EMI_BW_DVFS_REQ_MASK_LSB (1U << 28) /* 1b */ -#define MD_SRCCLKENA_0_DVFS_REQ_MASK_B_LSB (1U << 29) /* 1b */ -#define MD_SRCCLKENA_1_DVFS_REQ_MASK_B_LSB (1U << 30) /* 1b */ -#define CONN_SRCCLKENA_DVFS_REQ_MASK_B_LSB (1U << 31) /* 1b */ - -/* SPM_SRC2_MASK (0x10006000+0x0C0) */ -#define DVFS_HALT_MASK_B_LSB (1U << 0) /* 5b */ -#define VDEC_REQ_MASK_B_LSB (1U << 6) /* 1b */ -#define GCE_REQ_MASK_B_LSB (1U << 7) /* 1b */ -#define CPU_MD_DVFS_REQ_MERGE_MASK_B_LSB (1U << 8) /* 1b */ -#define MD_DDR_EN_DVFS_HALT_MASK_B_LSB (1U << 9) /* 2b */ -#define DSI0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 11) /* 1b */ -#define DSI1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 12) /* 1b */ -#define DPI_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 13) /* 1b */ -#define ISP0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 14) /* 1b */ -#define ISP1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 15) /* 1b */ -#define CONN_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ -#define DISP_REQ_MASK_B_LSB (1U << 17) /* 1b */ -#define DISP1_REQ_MASK_B_LSB (1U << 18) /* 1b */ -#define MFG_REQ_MASK_B_LSB (1U << 19) /* 1b */ -#define C2K_PS_RCCIF_WAKE_MASK_B_LSB (1U << 20) /* 1b */ -#define C2K_L1_RCCIF_WAKE_MASK_B_LSB (1U << 21) /* 1b */ -#define PS_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 22) /* 1b */ -#define L1_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 23) /* 1b */ -#define SDIO_ON_DVFS_REQ_MASK_B_LSB (1U << 24) /* 1b */ -#define EMI_BOOST_DVFS_REQ_MASK_B_LSB (1U << 25) /* 1b */ -#define CPU_MD_EMI_DVFS_REQ_PROT_DIS_LSB (1U << 26) /* 1b */ -#define DRAMC_SPCMD_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */ - -/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ -#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ - -/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ -#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ - -/* SCP_CLK_CON (0x10006000+0x0D0) */ -#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ - -/* PCM_DEBUG_CON (0x10006000+0x0D4) */ -#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ - -/* PCM_REG0_DATA (0x10006000+0x100) */ -#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG1_DATA (0x10006000+0x104) */ -#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG2_DATA (0x10006000+0x108) */ -#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG3_DATA (0x10006000+0x10C) */ -#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG4_DATA (0x10006000+0x110) */ -#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG5_DATA (0x10006000+0x114) */ -#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG6_DATA (0x10006000+0x118) */ -#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG7_DATA (0x10006000+0x11C) */ -#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG8_DATA (0x10006000+0x120) */ -#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG9_DATA (0x10006000+0x124) */ -#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG10_DATA (0x10006000+0x128) */ -#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG11_DATA (0x10006000+0x12C) */ -#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_DATA (0x10006000+0x130) */ -#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG13_DATA (0x10006000+0x134) */ -#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG14_DATA (0x10006000+0x138) */ -#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG15_DATA (0x10006000+0x13C) */ -#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ -#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ -#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ -#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ - -/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ -#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ - -/* PCM_TIMER_OUT (0x10006000+0x150) */ -#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_OUT (0x10006000+0x154) */ -#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ - -/* SPM_IRQ_STA (0x10006000+0x158) */ -#define TWAM_IRQ_LSB (1U << 2) /* 1b */ -#define PCM_IRQ_LSB (1U << 3) /* 1b */ -#define SPM_IRQ_SWINT_LSB (1U << 4) /* 10b */ - -/* SPM_WAKEUP_STA (0x10006000+0x15C) */ -#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ - -/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ -#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ - -/* SPM_WAKEUP_MISC (0x10006000+0x164) */ -#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ -#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ -#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ - -/* BUS_PROTECT_RDY (0x10006000+0x168) */ -#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ - -/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ -#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ - -/* SUBSYS_IDLE_STA (0x10006000+0x170) */ -#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ - -/* CPU_IDLE_STA (0x10006000+0x174) */ -#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ -#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ -#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ -#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ -#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ -#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ -#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ -#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ -#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ -#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ -#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ -#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ -#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ -#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ -#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ -#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ -#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ -#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ -#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ - -/* PCM_FSM_STA (0x10006000+0x178) */ -#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ -#define PC_STATE_LSB (1U << 4) /* 3b */ -#define IM_STATE_LSB (1U << 7) /* 3b */ -#define MASTER_STATE_LSB (1U << 10) /* 5b */ -#define EVENT_FSM_LSB (1U << 15) /* 3b */ -#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ -#define PCM_KICK_LSB (1U << 21) /* 1b */ -#define IM_KICK_LSB (1U << 22) /* 1b */ -#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ -#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ - -/* PWR_STATUS (0x10006000+0x180) */ -#define PWR_STATUS_LSB (1U << 0) /* 32b */ - -/* PWR_STATUS_2ND (0x10006000+0x184) */ -#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ - -/* CPU_PWR_STATUS (0x10006000+0x188) */ -#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ - -/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ -#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_0 (0x10006000+0x190) */ -#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_1 (0x10006000+0x194) */ -#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_2 (0x10006000+0x198) */ -#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ - -/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ -#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ -#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ -#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ -#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ -#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ -#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ -#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ -#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ -#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ -#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_3 (0x10006000+0x1C4) */ -#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ - -/* SPM_SRC_RDY_STA (0x10006000+0x1D0) */ -#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ -#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ - -/* MISC_STA (0x10006000+0x1D4) */ -#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ - -/* MCU_PWR_CON (0x10006000+0x200) */ -#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ -#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ -#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ -#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ -#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ -#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ -#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ -#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ -#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ -#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ -#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ -#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ -#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ -#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ -#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ -#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ -#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ -#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ -#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ -#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ -#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ -#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ -#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ -#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ -#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ -#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ -#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ - -/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ -#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ -#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* BYPASS_SPMC (0x10006000+0x2B4) */ -#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ - -/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ -#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ -#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ - -/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ -#define MUXSEL_SC_CCIPLL_LSB (1U << 0) /* 1b */ -#define MUXSEL_SC_ARMPLL1_LSB (1U << 1) /* 1b */ -#define MUXSEL_SC_ARMPLL2_LSB (1U << 2) /* 1b */ -#define REG_SC_ARM_CLK_OFF_LSB (1U << 8) /* 4b */ -#define REG_SC_ARMPLL_OFF_LSB (1U << 12) /* 4b */ -#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 16) /* 4b */ -#define REG_SC_FHC_PAUSE_LSB (1U << 20) /* 4b */ -#define REG_SC_ARMPLL_S_OFF_LSB (1U << 24) /* 4b */ - -/* SPMC_IN_RET (0x10006000+0x2C0) */ -#define SPMC_STATUS_LSB (1U << 0) /* 8b */ - -/* VDE_PWR_CON (0x10006000+0x300) */ -#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ -#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ -#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* VEN_PWR_CON (0x10006000+0x304) */ -#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ -#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ -#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* ISP_PWR_CON (0x10006000+0x308) */ -#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ -#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ -#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* DIS_PWR_CON (0x10006000+0x30C) */ -#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ -#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MJC_PWR_CON (0x10006000+0x310) */ -#define MJC_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MJC_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MJC_PWR_ON_LSB (1U << 2) /* 1b */ -#define MJC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MJC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MJC_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define MJC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* AUDIO_PWR_CON (0x10006000+0x314) */ -#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ -#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ -#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* IFR_PWR_CON (0x10006000+0x318) */ -#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ -#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ -#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* DPY_PWR_CON (0x10006000+0x31C) */ -#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ -#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MD1_PWR_CON (0x10006000+0x320) */ -#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ - -/* MD2_PWR_CON (0x10006000+0x324) */ -#define MD2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MD2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MD2_PWR_ON_LSB (1U << 2) /* 1b */ -#define MD2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MD2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MD2_SRAM_PDN_LSB (1U << 8) /* 1b */ - -/* C2K_PWR_CON (0x10006000+0x328) */ -#define C2K_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define C2K_PWR_ISO_LSB (1U << 1) /* 1b */ -#define C2K_PWR_ON_LSB (1U << 2) /* 1b */ -#define C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* CONN_PWR_CON (0x10006000+0x32C) */ -#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ -#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ -#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ - -/* VCOREPDN_PWR_CON (0x10006000+0x330) */ -#define VCOREPDN_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define VCOREPDN_PWR_ISO_LSB (1U << 1) /* 1b */ -#define VCOREPDN_PWR_ON_LSB (1U << 2) /* 1b */ -#define VCOREPDN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define VCOREPDN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ -#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MFG_PWR_CON (0x10006000+0x338) */ -#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_SRAM_PDN_LSB (1U << 8) /* 6b */ -#define MFG_SRAM_PDN_ACK_LSB (1U << 16) /* 6b */ - -/* MFG_CORE0_PWR_CON (0x10006000+0x33C) */ -#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_CORE0_SRAM_PDN_LSB (1U << 5) /* 1b */ -#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */ - -/* MFG_CORE1_PWR_CON (0x10006000+0x340) */ -#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_CORE1_SRAM_PDN_LSB (1U << 5) /* 1b */ -#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */ - -/* CAM_PWR_CON (0x10006000+0x344) */ -#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ -#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ -#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* SYSRAM_CON (0x10006000+0x350) */ -#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 0) /* 8b */ -#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 8) /* 8b */ -#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 16) /* 8b */ -#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 24) /* 8b */ - -/* SYSROM_CON (0x10006000+0x354) */ -#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ - -/* SCP_SRAM_CON (0x10006000+0x358) */ -#define SCP_SRAM_PDN_LSB (1U << 0) /* 1b */ -#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ -#define SCP_SRAM_ISOINT_B_LSB (1U << 8) /* 1b */ - -/* GCPU_SRAM_CON (0x10006000+0x35C) */ -#define GCPU_SRAM_PDN_LSB (1U << 0) /* 4b */ -#define GCPU_SRAM_CKISO_LSB (1U << 4) /* 4b */ -#define GCPU_SRAM_SLEEP_B_LSB (1U << 8) /* 4b */ -#define GCPU_SRAM_ISOINT_B_LSB (1U << 12) /* 4b */ - -/* MDSYS_INTF_INFRA_PWR_CON (0x10006000+0x360) */ -#define MDSYS_INTF_INFRA_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_ON_LSB (1U << 2) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* MDSYS_INTF_MD1_PWR_CON (0x10006000+0x364) */ -#define MDSYS_INTF_MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MDSYS_INTF_MD1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MDSYS_INTF_MD1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MDSYS_INTF_MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MDSYS_INTF_MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* MDSYS_INTF_C2K_PWR_CON (0x10006000+0x368) */ -#define MDSYS_INTF_C2K_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MDSYS_INTF_C2K_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MDSYS_INTF_C2K_PWR_ON_LSB (1U << 2) /* 1b */ -#define MDSYS_INTF_C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MDSYS_INTF_C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* BSI_TOP_SRAM_CON (0x10006000+0x370) */ -#define BSI_TOP_SRAM_PDN_LSB (1U << 0) /* 7b */ -#define BSI_TOP_SRAM_DSLP_LSB (1U << 7) /* 7b */ -#define BSI_TOP_SRAM_SLEEP_B_LSB (1U << 14) /* 7b */ -#define BSI_TOP_SRAM_ISOINT_B_LSB (1U << 21) /* 7b */ -#define BSI_TOP_SRAM_ISO_EN_LSB (1U << 28) /* 2b */ - -/* DVFSP_SRAM_CON (0x10006000+0x374) */ -#define DVFSP_SRAM_PDN_LSB (1U << 0) /* 2b */ -#define DVFSP_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ -#define DVFSP_SRAM_ISOINT_B_LSB (1U << 8) /* 2b */ - -/* MD_EXT_BUCK_ISO (0x10006000+0x390) */ -#define MD_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ - -/* DUMMY2_PWR_CON (0x10006000+0x3B0) */ -#define DUMMY2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DUMMY2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DUMMY2_PWR_ON_LSB (1U << 2) /* 1b */ -#define DUMMY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DUMMY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define DUMMY2_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define DUMMY2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MD1_OUTPUT_PISO_S_EN_IZ (0x10006000+0x3B4) */ -#define MD1_OUTPUT_PISO_S_EN_IZ_LSB (1U << 0) /* 1b */ - -/* SPM_DVFS_CON (0x10006000+0x400) */ -#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ -#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ - -/* SPM_MDBSI_CON (0x10006000+0x404) */ -#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ - -/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ -#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ - -/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ -#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_GEN (0x10006000+0x410) */ -#define SPM_BSI_START_LSB (1U << 0) /* 1b */ - -/* SPM_BSI_EN_SR (0x10006000+0x414) */ -#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_CLK_SR (0x10006000+0x418) */ -#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_D0_SR (0x10006000+0x41C) */ -#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_D1_SR (0x10006000+0x420) */ -#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_D2_SR (0x10006000+0x424) */ -#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ - -/* SPM_AP_SEMA (0x10006000+0x428) */ -#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ - -/* SPM_SPM_SEMA (0x10006000+0x42C) */ -#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ - -/* AP2MD_CROSS_TRIGGER (0x10006000+0x430) */ -#define AP2MD_CROSS_TRIGGER_REQ_LSB (1U << 0) /* 1b */ -#define AP2MD_CROSS_TRIGGER_ACK_LSB (1U << 1) /* 1b */ - -/* AP_MDSRC_REQ (0x10006000+0x434) */ -#define AP_MD1SRC_REQ_LSB (1U << 0) /* 1b */ -#define AP_MD2SRC_REQ_LSB (1U << 1) /* 1b */ -#define AP_MD1SRC_ACK_LSB (1U << 4) /* 1b */ -#define AP_MD2SRC_ACK_LSB (1U << 5) /* 1b */ - -/* SPM2MD_DVFS_CON (0x10006000+0x438) */ -#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 16b */ - -/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ -#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 16b */ - -/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ -#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ -#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ -#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ -#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ -#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ -#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ -#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ - -/* DPY_LP_CON (0x10006000+0x444) */ -#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ - -/* CPU_DVFS_REQ (0x10006000+0x448) */ -#define CPU_DVFS_REQ_LSB (1U << 0) /* 16b */ -#define DVFS_HALT_LSB (1U << 16) /* 1b */ -#define MD_DVFS_ERROR_STATUS_LSB (1U << 17) /* 1b */ - -/* SPM_PLL_CON (0x10006000+0x44C) */ -#define SC_MPLLOUT_OFF_LSB (1U << 0) /* 1b */ -#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ -#define SC_MPLL_OFF_LSB (1U << 4) /* 1b */ -#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ -#define SC_MPLL_S_OFF_LSB (1U << 8) /* 1b */ -#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ -#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ -#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ - -/* SPM_EMI_BW_MODE (0x10006000+0x450) */ -#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ -#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ - -/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ -#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ - -/* ULPOSC_CON (0x10006000+0x458) */ -#define ULPOSC_EN_LSB (1U << 0) /* 1b */ -#define ULPOSC_RST_LSB (1U << 1) /* 1b */ -#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ - -/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ -#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ -#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ -#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ -#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ -#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ -#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ -#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ -#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ -#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ -#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ -#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ -#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ -#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ -#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ -#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ -#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ - -/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ -#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ -#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ -#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ -#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ -#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ -#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ -#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ -#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ -#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ -#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ -#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ -#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ -#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ -#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ -#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ - -/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ -#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ -#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ -#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ -#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ -#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ -#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ -#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ - -/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ -#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ -#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ -#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ -#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ -#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ -#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ -#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ -#define SPM2MM_ULTRAREQ_LSB (1U << 8) /* 1b */ -#define SPM2MD_ULTRAREQ_LSB (1U << 9) /* 1b */ -#define SPM2MM_ULTRAACK_D2T_LSB (1U << 30) /* 1b */ -#define SPM2MD_ULTRAACK_D2T_LSB (1U << 31) /* 1b */ - -/* SPM_SEMA_M0 (0x10006000+0x480) */ -#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M1 (0x10006000+0x484) */ -#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M2 (0x10006000+0x488) */ -#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M3 (0x10006000+0x48C) */ -#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M4 (0x10006000+0x490) */ -#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M5 (0x10006000+0x494) */ -#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M6 (0x10006000+0x498) */ -#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M7 (0x10006000+0x49C) */ -#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M8 (0x10006000+0x4A0) */ -#define SPM_SEMA_M8_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M9 (0x10006000+0x4A4) */ -#define SPM_SEMA_M9_LSB (1U << 0) /* 8b */ - -/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ -#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ - -/* SRAM_DREQ_CON (0x10006000+0x4B0) */ -#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ - -/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ -#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ - -/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ -#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ - -/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ -#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ -#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ -#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ -#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ -#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ -#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ -#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ -#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ -#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ -#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ -#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ -#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ -#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ -#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ -#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ -#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ - -/* CPU_PTPOD2_CON (0x10006000+0x560) */ -#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ -#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ -#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ -#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ -#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ -#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ - -/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ -#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ - -/* ROOT_CORE_ADDR (0x10006000+0x574) */ -#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ - -/* CPU_SPARE_CON (0x10006000+0x580) */ -#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ - -/* CPU_SPARE_CON_SET (0x10006000+0x584) */ -#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ - -/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ -#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ - -/* SPM_SW_FLAG (0x10006000+0x600) */ -#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ - -/* SPM_SW_DEBUG (0x10006000+0x604) */ -#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_0 (0x10006000+0x608) */ -#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_1 (0x10006000+0x60C) */ -#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_2 (0x10006000+0x610) */ -#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_3 (0x10006000+0x614) */ -#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_4 (0x10006000+0x618) */ -#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_5 (0x10006000+0x61C) */ -#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ - -/* SPM_RSV_CON (0x10006000+0x620) */ -#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ - -/* SPM_RSV_STA (0x10006000+0x624) */ -#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ - -/* SPM_PASR_DPD_0 (0x10006000+0x630) */ -#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ - -/* SPM_PASR_DPD_1 (0x10006000+0x634) */ -#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ - -/* SPM_PASR_DPD_2 (0x10006000+0x638) */ -#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ - -/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ -#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ - -/* SPM_SPARE_CON (0x10006000+0x640) */ -#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ - -/* SPM_SPARE_CON_SET (0x10006000+0x644) */ -#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ - -/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ -#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_6 (0x10006000+0x64C) */ -#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_7 (0x10006000+0x650) */ -#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_8 (0x10006000+0x654) */ -#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_9 (0x10006000+0x658) */ -#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_10 (0x10006000+0x65C) */ -#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_11 (0x10006000+0x660) */ -#define SPM_SW_RSV_11_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_12 (0x10006000+0x664) */ -#define SPM_SW_RSV_12_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_13 (0x10006000+0x668) */ -#define SPM_SW_RSV_13_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_14 (0x10006000+0x66C) */ -#define SPM_SW_RSV_14_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_15 (0x10006000+0x670) */ -#define SPM_SW_RSV_15_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_16 (0x10006000+0x674) */ -#define SPM_SW_RSV_16_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_17 (0x10006000+0x678) */ -#define SPM_SW_RSV_17_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_18 (0x10006000+0x67C) */ -#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_19 (0x10006000+0x680) */ -#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ - -/* SW_CRTL_EVENT (0x10006000+0x690) */ -#define SW_CRTL_EVENT_ON_LSB (1U << 0) /* 1b */ - -#define SPM_PROJECT_CODE 0xb16 - -#define SPM_REGWR_EN (1U << 0) -#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) - -#define SPM_CPU_PDN_DIS (1U << 0) -#define SPM_INFRA_PDN_DIS (1U << 1) -#define SPM_DDRPHY_PDN_DIS (1U << 2) -#define SPM_DUALVCORE_PDN_DIS (1U << 3) -#define SPM_PASR_DIS (1U << 4) -#define SPM_DPD_DIS (1U << 5) -#define SPM_SODI_DIS (1U << 6) -#define SPM_MEMPLL_RESET (1U << 7) -#define SPM_MAINPLL_PDN_DIS (1U << 8) -#define SPM_CPU_DVS_DIS (1U << 9) -#define SPM_CPU_DORMANT (1U << 10) -#define SPM_EXT_VSEL_GPIO103 (1U << 11) -#define SPM_DDR_HIGH_SPEED (1U << 12) -#define SPM_OPT (1U << 13) - -#define POWER_ON_VAL1_DEF 0x15820 -#define PCM_FSM_STA_DEF 0x48490 -#define PCM_END_FSM_STA_DEF 0x08490 -#define PCM_END_FSM_STA_MASK 0x3fff0 -#define PCM_HANDSHAKE_SEND1 0xbeefbeef - -#define PCM_WDT_TIMEOUT (30 * 32768) -#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) - -#define CON0_PCM_KICK (1U << 0) -#define CON0_IM_KICK (1U << 1) -#define CON0_IM_SLEEP_DVS (1U << 3) -#define CON0_PCM_SW_RESET (1U << 15) -#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) - -#define CON1_IM_SLAVE (1U << 0) -#define CON1_MIF_APBEN (1U << 3) -#define CON1_PCM_TIMER_EN (1U << 5) -#define CON1_IM_NONRP_EN (1U << 6) -#define CON1_PCM_WDT_EN (1U << 8) -#define CON1_PCM_WDT_WAKE_MODE (1U << 9) -#define CON1_SPM_SRAM_SLP_B (1U << 10) -#define CON1_SPM_SRAM_ISO_B (1U << 11) -#define CON1_EVENT_LOCK_EN (1U << 12) -#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) - -#define PCM_PWRIO_EN_R0 (1U << 0) -#define PCM_PWRIO_EN_R7 (1U << 7) -#define PCM_RF_SYNC_R0 (1U << 16) -#define PCM_RF_SYNC_R2 (1U << 18) -#define PCM_RF_SYNC_R6 (1U << 22) -#define PCM_RF_SYNC_R7 (1U << 23) - -#define CC_SYSCLK0_EN_0 (1U << 0) -#define CC_SYSCLK0_EN_1 (1U << 1) -#define CC_SYSCLK1_EN_0 (1U << 2) -#define CC_SYSCLK1_EN_1 (1U << 3) -#define CC_SYSSETTLE_SEL (1U << 4) -#define CC_LOCK_INFRA_DCM (1U << 5) -#define CC_SRCLKENA_MASK_0 (1U << 6) -#define CC_CXO32K_RM_EN_MD1 (1U << 9) -#define CC_CXO32K_RM_EN_MD2 (1U << 10) -#define CC_CLKSQ1_SEL (1U << 12) -#define CC_DISABLE_DORM_PWR (1U << 14) -#define CC_MD32_DCM_EN (1U << 18) - -#define WFI_OP_AND 1 -#define WFI_OP_OR 0 - -#define WAKE_MISC_PCM_TIMER (1U << 19) -#define WAKE_MISC_CPU_WAKE (1U << 20) - -/* define WAKE_SRC_XXX */ -#define WAKE_SRC_SPM_MERGE (1 << 0) -#define WAKE_SRC_KP (1 << 2) -#define WAKE_SRC_WDT (1 << 3) -#define WAKE_SRC_GPT (1 << 4) -#define WAKE_SRC_EINT (1 << 6) -#define WAKE_SRC_LOW_BAT (1 << 9) -#define WAKE_SRC_MD32 (1 << 10) -#define WAKE_SRC_USB_CD (1 << 14) -#define WAKE_SRC_USB_PDN (1 << 15) -#define WAKE_SRC_AFE (1 << 20) -#define WAKE_SRC_THERM (1 << 21) -#define WAKE_SRC_SYSPWREQ (1 << 24) -#define WAKE_SRC_SEJ (1 << 27) -#define WAKE_SRC_ALL_MD32 (1 << 28) -#define WAKE_SRC_CPU_IRQ (1 << 29) - -#define spm_read(addr) mmio_read_32(addr) -#define spm_write(addr, val) mmio_write_32(addr, val) - -#endif /* SPM_H */ diff --git a/plat/mediatek/mt8183/include/sspm_reg.h b/plat/mediatek/mt8183/include/sspm_reg.h new file mode 100644 index 00000000..3f1ac869 --- /dev/null +++ b/plat/mediatek/mt8183/include/sspm_reg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SSPM_REG_H__ +#define __SSPM_REG_H__ + +#include "platform_def.h" + +#define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100) +#define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8) +#define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC) +#define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204) + +#define STANDBYWFI_EN(n) (1 << (n + 8)) +#define GIC_IRQOUT_EN(n) (1 << (n + 0)) + +#define NF_MCDI_MBOX 19 +#define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF 0 +#define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF 1 +#define MCDI_MBOX_BUCK_POWER_OFF_MASK 2 +#define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE 3 +#define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE 4 +#define MCDI_MBOX_BOOTADDR 5 +#define MCDI_MBOX_PAUSE_ACTION 6 +#define MCDI_MBOX_AVAIL_CPU_MASK 7 +#define MCDI_MBOX_CPU_CLUSTER_PWR_STAT 8 +#define MCDI_MBOX_ACTION_STAT 9 +#define MCDI_MBOX_CLUSTER_0_CNT 10 +#define MCDI_MBOX_CLUSTER_1_CNT 11 +#define MCDI_MBOX_CPU_ISOLATION_MASK 12 +#define MCDI_MBOX_PAUSE_ACK 13 +#define MCDI_MBOX_PENDING_ON_EVENT 14 +#define MCDI_MBOX_PROF_CMD 15 +#define MCDI_MBOX_DRCC_CALI_DONE 16 +#define MCDI_MBOX_HP_CMD 17 +#define MCDI_MBOX_HP_ACK 18 + +#endif /* __SSPM_REG_H__ */ diff --git a/plat/mediatek/mt8183/plat_debug.c b/plat/mediatek/mt8183/plat_debug.c index 51816dba..2f0b67dc 100644 --- a/plat/mediatek/mt8183/plat_debug.c +++ b/plat/mediatek/mt8183/plat_debug.c @@ -9,6 +9,7 @@ #include <lib/mmio.h> #include <plat_debug.h> #include <platform_def.h> +#include <spm.h> void circular_buffer_setup(void) { diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index 83c8d4cd..555b3895 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -16,6 +16,7 @@ #include <platform_def.h> #include <scu.h> #include <mt_gic_v3.h> +#include <mtk_mcdi.h> #include <mtk_plat_common.h> #include <mtgpio.h> #include <mtspmc.h> @@ -25,9 +26,103 @@ #include <plat_private.h> #include <power_tracer.h> #include <pmic.h> +#include <spm.h> +#include <spm_suspend.h> +#include <sspm.h> #include <rtc.h> -#define MTK_LOCAL_STATE_OFF 2 +/* Local power state for power domains in Run state. */ +#define MTK_LOCAL_STATE_RUN 0 +/* Local power state for retention. */ +#define MTK_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. */ +#define MTK_LOCAL_STATE_OFF 2 + +#if PSCI_EXTENDED_STATE_ID +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define MTK_LOCAL_PSTATE_WIDTH 4 +#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1) + +/* Macros to construct the composite power state */ + +/* Make composite power state parameter till power level 0 */ + +#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) + +#else /* !PSCI_EXTENDED_STATE_ID */ + +#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#endif /* PSCI_EXTENDED_STATE_ID */ + +/* Make composite power state parameter till power level 1 */ +#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \ + mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* Make composite power state parameter till power level 2 */ +#define mtk_make_pwrstate_lvl2( \ + lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \ + mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) + +#define MTK_PWR_LVL0 0 +#define MTK_PWR_LVL1 1 +#define MTK_PWR_LVL2 2 + +/* Macros to read the MTK power domain state */ +#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] +#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] +#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ? \ + (state)->pwr_domain_state[MTK_PWR_LVL2] : 0) + +#if PSCI_EXTENDED_STATE_ID +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int mtk_pm_idle_states[] = { + /* State-id - 0x001 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN, + MTK_LOCAL_STATE_RET, MTK_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x002 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x022 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_OFF, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL1, PSTATE_TYPE_POWERDOWN), +#if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1 + /* State-id - 0x222 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_OFF, MTK_LOCAL_STATE_OFF, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL2, PSTATE_TYPE_POWERDOWN), +#endif + 0, +}; +#endif + +#define CPU_IDX(cluster, cpu) ((cluster << 2) + cpu) +#define ON true +#define OFF false + +/* Pause MCDI when CPU hotplug */ +static bool HP_SSPM_PAUSE; +/* CPU Hotplug by SSPM */ +static bool HP_SSPM_CTRL = true; +/* Turn off cluster when CPU hotplug off */ +static bool HP_CLUSTER_OFF = true; +/* Turn off cluster when CPU MCDI off */ +static bool MCDI_C2 = true; +/* Enable MCDI */ +static bool MCDI_SSPM = true; static uintptr_t secure_entrypoint; @@ -38,30 +133,171 @@ static void mp1_L2_desel_config(void) dsb(); } +static bool clst_single_pwr(int cluster, int cpu) +{ + uint32_t cpu_mask[2] = {0x00001e00, 0x000f0000}; + uint32_t cpu_pwr_bit[] = {9, 10, 11, 12, 16, 17, 18, 19}; + int my_idx = (cluster << 2) + cpu; + uint32_t pwr_stat = mmio_read_32(0x10006180); + + return !(pwr_stat & (cpu_mask[cluster] & ~BIT(cpu_pwr_bit[my_idx]))); +} + +static bool clst_single_on(int cluster, int cpu) +{ + uint32_t cpu_mask[2] = {0x0f, 0xf0}; + int my_idx = (cluster << 2) + cpu; + uint32_t on_stat = mcdi_avail_cpu_mask_read(); + + return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx))); +} + +static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster) +{ + if (cluster > 0) + mt_gic_sync_dcm_enable(); + + /* Disable coherency */ + plat_mtk_cci_disable(); + disable_scu(mpidr); +} + +static void plat_cluster_pwron_common(uint64_t mpidr, int cluster) +{ + if (cluster > 0) { + l2c_parity_check_setup(); + circular_buffer_setup(); + mp1_L2_desel_config(); + mt_gic_sync_dcm_disable(); + } + + /* Enable coherency */ + enable_scu(mpidr); + plat_mtk_cci_enable(); + /* Enable big core dcm */ + plat_dcm_restore_cluster_on(mpidr); + /* Enable rgu dcm */ + plat_dcm_rgu_enable(); +} + +static void plat_cpu_standby(plat_local_state_t cpu_state) +{ + unsigned int scr; + + scr = read_scr_el3(); + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); + + isb(); + dsb(); + wfi(); + + write_scr_el3(scr); +} + +static void mcdi_ctrl_before_hotplug_on(int cluster, int cpu) +{ + if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM) { + mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), OFF); + mcdi_pause_set(cluster, CPU_IDX(cluster, cpu), ON); + } +} + +static void mcdi_ctrl_before_hotplug_off(int cluster, int cpu, bool cluster_off) +{ + if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM) + mcdi_pause_set(cluster_off ? cluster : -1, + CPU_IDX(cluster, cpu), OFF); +} + +static void mcdi_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off) +{ + if (MCDI_SSPM) { + sspm_set_bootaddr(secure_entrypoint); + + sspm_standbywfi_irq_enable(CPU_IDX(cluster, cpu)); + + if (cluster_off) + sspm_cluster_pwr_off_notify(cluster); + else + sspm_cluster_pwr_on_notify(cluster); + } +} + +static void mcdi_ctrl_suspend(void) +{ + if (MCDI_SSPM) + mcdi_pause(); +} + +static void mcdi_ctrl_resume(void) +{ + if (MCDI_SSPM) + mcdi_unpause(); +} + +static void hotplug_ctrl_cluster_on(int cluster, int cpu) +{ + if (HP_SSPM_CTRL && MCDI_SSPM) { + mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), OFF); + mcdi_hotplug_set(cluster, -1, ON); + mcdi_hotplug_wait_ack(cluster, -1, ON); + } else { + /* power on cluster */ + if (!spm_get_cluster_powerstate(cluster)) + spm_poweron_cluster(cluster); + } +} + +static void hotplug_ctrl_cpu_on(int cluster, int cpu) +{ + if (HP_SSPM_CTRL && MCDI_SSPM) + mcdi_hotplug_set(cluster, CPU_IDX(cluster, cpu), ON); + else + spm_poweron_cpu(cluster, cpu); +} + +static void hotplug_ctrl_cpu_on_finish(int cluster, int cpu) +{ + spm_disable_cpu_auto_off(cluster, cpu); + + if (HP_SSPM_CTRL && MCDI_SSPM) + mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), ON); + else if (HP_SSPM_PAUSE && MCDI_SSPM) + mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), ON); + + mcdi_avail_cpu_mask_set(BIT(CPU_IDX(cluster, cpu))); +} + +static void hotplug_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off) +{ + mcdi_avail_cpu_mask_clr(BIT(CPU_IDX(cluster, cpu))); + + if (HP_SSPM_CTRL && MCDI_SSPM) { + mcdi_hotplug_set(cluster_off ? cluster : -1, + CPU_IDX(cluster, cpu), OFF); + } else { + spm_enable_cpu_auto_off(cluster, cpu); + + if (cluster_off) + spm_enable_cluster_auto_off(cluster); + + spm_set_cpu_power_off(cluster, cpu); + } +} + static int plat_mtk_power_domain_on(unsigned long mpidr) { int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); - INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n", - __func__, __LINE__, mpidr, cluster, cpu); - - /* power on cluster */ - if (!spm_get_cluster_powerstate(cluster)) { - spm_poweron_cluster(cluster); - if (cluster == 1) { - l2c_parity_check_setup(); - circular_buffer_setup(); - mp1_L2_desel_config(); - mt_gic_sync_dcm_disable(); - } - } + mcdi_ctrl_before_hotplug_on(cluster, cpu); + hotplug_ctrl_cluster_on(cluster, cpu); /* init cpu reset arch as AARCH64 */ mcucfg_init_archstate(cluster, cpu, 1); mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); - spm_poweron_cpu(cluster, cpu); + hotplug_ctrl_cpu_on(cluster, cpu); return PSCI_E_SUCCESS; } @@ -71,53 +307,189 @@ static void plat_mtk_power_domain_off(const psci_power_state_t *state) uint64_t mpidr = read_mpidr(); int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); + bool cluster_off = (HP_CLUSTER_OFF && afflvl1 && + clst_single_on(cluster, cpu)); - INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu); - - /* Prevent interrupts from spuriously waking up this cpu */ mt_gic_cpuif_disable(); - spm_enable_cpu_auto_off(cluster, cpu); + if (cluster_off) + plat_cluster_pwrdwn_common(mpidr, cluster); - if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { - if (cluster == 1) - mt_gic_sync_dcm_enable(); + mcdi_ctrl_before_hotplug_off(cluster, cpu, cluster_off); + hotplug_ctrl_cluster_cpu_off(cluster, cpu, cluster_off); +} - plat_mtk_cci_disable(); - spm_enable_cluster_auto_off(cluster); - } +static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cpu = MPIDR_AFFLVL0_VAL(mpidr); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); + + if (afflvl1) + plat_cluster_pwron_common(mpidr, cluster); - spm_set_cpu_power_off(cluster, cpu); + mt_gic_pcpu_init(); + mt_gic_cpuif_enable(); + + hotplug_ctrl_cpu_on_finish(cluster, cpu); } -static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) +static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) { uint64_t mpidr = read_mpidr(); int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); + bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); + bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu); + + /* init cpu reset arch as AARCH64 */ + mcucfg_init_archstate(cluster, cpu, 1); + mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + + mt_gic_cpuif_disable(); + mt_gic_irq_save(); + plat_dcm_mcsi_a_backup(); + + if (cluster_off || afflvl2) + plat_cluster_pwrdwn_common(mpidr, cluster); + + if (afflvl2) { + spm_data_t spm_d = { .cmd = SPM_SUSPEND }; + uint32_t *d = (uint32_t *)&spm_d; + uint32_t l = sizeof(spm_d) / sizeof(uint32_t); - INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu); + mcdi_ctrl_suspend(); - assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); + spm_set_bootaddr(secure_entrypoint); - if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { - enable_scu(mpidr); + if (MCDI_SSPM) + sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d); - /* Enable coherency if this cluster was off */ - plat_mtk_cci_enable(); - /* Enable big core dcm if this cluster was on */ - plat_dcm_restore_cluster_on(mpidr); - /* Enable rgu dcm if this cluster was off */ - plat_dcm_rgu_enable(); + spm_system_suspend(); + + if (MCDI_SSPM) + while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l)) + ; + } else { + mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off); } +} - spm_disable_cpu_auto_off(cluster, cpu); +static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); - /* Enable the gic cpu interface */ - mt_gic_pcpu_init(); - mt_gic_cpuif_enable(); + if (afflvl2) { + spm_data_t spm_d = { .cmd = SPM_RESUME }; + uint32_t *d = (uint32_t *)&spm_d; + uint32_t l = sizeof(spm_d) / sizeof(uint32_t); + + mt_gic_init(); + mt_gic_irq_restore(); + mmio_write_32(EMI_WFIFO, 0xf); + + if (MCDI_SSPM) + sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d); + + spm_system_suspend_finish(); + + if (MCDI_SSPM) + while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l)) + ; + + mcdi_ctrl_resume(); + } + + plat_cluster_pwron_common(mpidr, cluster); + + plat_dcm_mcsi_a_restore(); +} + +#if PSCI_EXTENDED_STATE_ID + +static int plat_mtk_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + if (!MCDI_SSPM) + return PSCI_E_INVALID_PARAMS; + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!mtk_pm_idle_states[i]; i++) { + if (power_state == mtk_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!mtk_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + MTK_LOCAL_PSTATE_MASK; + state_id >>= MTK_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +#else /* if !PSCI_EXTENDED_STATE_ID */ + +static int plat_mtk_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pstate = psci_get_pstate_type(power_state); + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int i; + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on power level 0 + * Ignore any other power level. + */ + if (pwr_lvl != 0) + return PSCI_E_INVALID_PARAMS; + + req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET; + } else if (!MCDI_SSPM) { + return PSCI_E_INVALID_PARAMS; + } else { + for (i = 0; i <= pwr_lvl; i++) + req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; + } + + return PSCI_E_SUCCESS; } +#endif /* PSCI_EXTENDED_STATE_ID */ + /******************************************************************************* * MTK handlers to shutdown/reboot the system ******************************************************************************/ @@ -147,21 +519,29 @@ static void __dead2 plat_mtk_system_reset(void) panic(); } +static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + assert(PLAT_MAX_PWR_LVL >= 2); + + for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; +} + /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned * on. The level and mpidr determine the affinity instance. ******************************************************************************/ static const plat_psci_ops_t plat_plat_pm_ops = { - .cpu_standby = NULL, + .cpu_standby = plat_cpu_standby, .pwr_domain_on = plat_mtk_power_domain_on, .pwr_domain_on_finish = plat_mtk_power_domain_on_finish, .pwr_domain_off = plat_mtk_power_domain_off, - .pwr_domain_suspend = NULL, - .pwr_domain_suspend_finish = NULL, + .pwr_domain_suspend = plat_mtk_power_domain_suspend, + .pwr_domain_suspend_finish = plat_mtk_power_domain_suspend_finish, .system_off = plat_mtk_system_off, .system_reset = plat_mtk_system_reset, - .validate_power_state = NULL, - .get_sys_suspend_power_state = NULL, + .validate_power_state = plat_mtk_validate_power_state, + .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state, }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, @@ -169,5 +549,11 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, { *psci_ops = &plat_plat_pm_ops; secure_entrypoint = sec_entrypoint; + + if (!check_mcdi_ctl_stat()) { + HP_SSPM_CTRL = false; + MCDI_SSPM = false; + } + return 0; } diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 09fd1331..efa7e9e2 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -9,10 +9,14 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ + -I${MTK_PLAT_SOC}/drivers/spm/ \ + -I${MTK_PLAT_SOC}/drivers/sspm/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ + -I${MTK_PLAT_SOC}/drivers/uart/ \ -I${MTK_PLAT_SOC}/include/ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ @@ -45,15 +49,21 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mtk_mcdi.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ + ${MTK_PLAT_SOC}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_mt_gic.c \ ${MTK_PLAT_SOC}/plat_dcm.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/plat_debug.c \ - ${MTK_PLAT_SOC}/scu.c + ${MTK_PLAT_SOC}/scu.c \ + ${MTK_PLAT_SOC}/drivers/sspm/sspm.c # Enable workarounds for selected Cortex-A53 erratas. ERRATA_A53_826319 := 0 diff --git a/plat/qemu/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S index aebcfa78..aebcfa78 100644 --- a/plat/qemu/aarch32/plat_helpers.S +++ b/plat/qemu/common/aarch32/plat_helpers.S diff --git a/plat/qemu/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S index 13a5ee46..13a5ee46 100644 --- a/plat/qemu/aarch64/plat_helpers.S +++ b/plat/qemu/common/aarch64/plat_helpers.S diff --git a/plat/qemu/include/plat_macros.S b/plat/qemu/common/include/plat_macros.S index b6cdb071..b6cdb071 100644 --- a/plat/qemu/include/plat_macros.S +++ b/plat/qemu/common/include/plat_macros.S diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/common/qemu_bl1_setup.c index 67f33273..67f33273 100644 --- a/plat/qemu/qemu_bl1_setup.c +++ b/plat/qemu/common/qemu_bl1_setup.c diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/common/qemu_bl2_mem_params_desc.c index a01f2dc9..f8b9066d 100644 --- a/plat/qemu/qemu_bl2_mem_params_desc.c +++ b/plat/qemu/common/qemu_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,8 +139,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), .image_info.image_base = NS_IMAGE_OFFSET, - .image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE - - NS_IMAGE_OFFSET, + .image_info.image_max_size = NS_IMAGE_MAX_SIZE, # endif /* !PRELOADED_BL33_BASE */ .next_handoff_image_id = INVALID_IMAGE_ID, diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c index 166d2454..166d2454 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/common/qemu_bl2_setup.c diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c index 4d36b039..4d36b039 100644 --- a/plat/qemu/qemu_bl31_setup.c +++ b/plat/qemu/common/qemu_bl31_setup.c diff --git a/plat/qemu/qemu_common.c b/plat/qemu/common/qemu_common.c index 56bf9532..56bf9532 100644 --- a/plat/qemu/qemu_common.c +++ b/plat/qemu/common/qemu_common.c diff --git a/plat/qemu/qemu_console.c b/plat/qemu/common/qemu_console.c index fec18289..fec18289 100644 --- a/plat/qemu/qemu_console.c +++ b/plat/qemu/common/qemu_console.c diff --git a/plat/qemu/qemu_gicv2.c b/plat/qemu/common/qemu_gicv2.c index fb566227..fb566227 100644 --- a/plat/qemu/qemu_gicv2.c +++ b/plat/qemu/common/qemu_gicv2.c diff --git a/plat/qemu/qemu_gicv3.c b/plat/qemu/common/qemu_gicv3.c index 28572c5e..28572c5e 100644 --- a/plat/qemu/qemu_gicv3.c +++ b/plat/qemu/common/qemu_gicv3.c diff --git a/plat/qemu/qemu_image_load.c b/plat/qemu/common/qemu_image_load.c index 9970d1de..9970d1de 100644 --- a/plat/qemu/qemu_image_load.c +++ b/plat/qemu/common/qemu_image_load.c diff --git a/plat/qemu/qemu_io_storage.c b/plat/qemu/common/qemu_io_storage.c index 0e81cd19..0e81cd19 100644 --- a/plat/qemu/qemu_io_storage.c +++ b/plat/qemu/common/qemu_io_storage.c diff --git a/plat/qemu/qemu_pm.c b/plat/qemu/common/qemu_pm.c index a199688d..a199688d 100644 --- a/plat/qemu/qemu_pm.c +++ b/plat/qemu/common/qemu_pm.c diff --git a/plat/qemu/qemu_private.h b/plat/qemu/common/qemu_private.h index 71ea4de1..71ea4de1 100644 --- a/plat/qemu/qemu_private.h +++ b/plat/qemu/common/qemu_private.h diff --git a/plat/qemu/qemu_rotpk.S b/plat/qemu/common/qemu_rotpk.S index 5d1b83f4..5d1b83f4 100644 --- a/plat/qemu/qemu_rotpk.S +++ b/plat/qemu/common/qemu_rotpk.S diff --git a/plat/qemu/qemu_stack_protector.c b/plat/qemu/common/qemu_stack_protector.c index c226158a..c226158a 100644 --- a/plat/qemu/qemu_stack_protector.c +++ b/plat/qemu/common/qemu_stack_protector.c diff --git a/plat/qemu/qemu_trusted_boot.c b/plat/qemu/common/qemu_trusted_boot.c index 1ef7e431..1ef7e431 100644 --- a/plat/qemu/qemu_trusted_boot.c +++ b/plat/qemu/common/qemu_trusted_boot.c diff --git a/plat/qemu/sp_min/sp_min-qemu.mk b/plat/qemu/common/sp_min/sp_min-qemu.mk index e93a0c23..e93a0c23 100644 --- a/plat/qemu/sp_min/sp_min-qemu.mk +++ b/plat/qemu/common/sp_min/sp_min-qemu.mk diff --git a/plat/qemu/sp_min/sp_min_setup.c b/plat/qemu/common/sp_min/sp_min_setup.c index 7ec657b7..7ec657b7 100644 --- a/plat/qemu/sp_min/sp_min_setup.c +++ b/plat/qemu/common/sp_min/sp_min_setup.c diff --git a/plat/qemu/topology.c b/plat/qemu/common/topology.c index 6352706e..6352706e 100644 --- a/plat/qemu/topology.c +++ b/plat/qemu/common/topology.c diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index d7f77cc7..a9057371 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -165,7 +165,8 @@ # error "Unsupported BL32_RAM_LOCATION_ID value" #endif -#define NS_IMAGE_OFFSET 0x60000000 +#define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) +#define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/qemu/platform.mk b/plat/qemu/qemu/platform.mk index bc4a21bc..5fda2cd4 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/qemu/platform.mk @@ -32,16 +32,20 @@ ifeq ($(NEED_BL32),yes) $(eval $(call add_define,QEMU_LOAD_BL32)) endif -PLAT_PATH := plat/qemu/ -PLAT_INCLUDES := -Iplat/qemu/include +PLAT_QEMU_PATH := plat/qemu/qemu +PLAT_QEMU_COMMON_PATH := plat/qemu/common +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -I${PLAT_QEMU_COMMON_PATH}/include \ + -I${PLAT_QEMU_PATH}/include \ + -Iinclude/common/tbbr ifeq (${ARM_ARCH_MAJOR},8) PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} endif -PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ - plat/qemu/qemu_console.c \ - drivers/arm/pl011/${ARCH}/pl011_console.S \ +PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} @@ -59,13 +63,13 @@ ifneq (${TRUSTED_BOARD_BOOT},0) BL1_SOURCES += ${AUTH_SOURCES} \ bl1/tbbr/tbbr_img_desc.c \ plat/common/tbbr/plat_tbbr.c \ - plat/qemu/qemu_trusted_boot.c \ - $(PLAT_PATH)/qemu_rotpk.S + ${PLAT_QEMU_COMMON_PATH}/qemu_trusted_boot.c \ + $(PLAT_QEMU_COMMON_PATH)/qemu_rotpk.S BL2_SOURCES += ${AUTH_SOURCES} \ plat/common/tbbr/plat_tbbr.c \ - plat/qemu/qemu_trusted_boot.c \ - $(PLAT_PATH)/qemu_rotpk.S + ${PLAT_QEMU_COMMON_PATH}/qemu_trusted_boot.c \ + $(PLAT_QEMU_COMMON_PATH)/qemu_rotpk.S ROT_KEY = $(BUILD_PLAT)/rot_key.pem ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin @@ -93,9 +97,9 @@ BL1_SOURCES += drivers/io/io_semihosting.c \ drivers/io/io_memmap.c \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ - plat/qemu/qemu_io_storage.c \ - plat/qemu/${ARCH}/plat_helpers.S \ - plat/qemu/qemu_bl1_setup.c + ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ + ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c ifeq (${ARM_ARCH_MAJOR},8) BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \ @@ -110,13 +114,13 @@ BL2_SOURCES += drivers/io/io_semihosting.c \ drivers/io/io_fip.c \ drivers/io/io_memmap.c \ lib/semihosting/semihosting.c \ - lib/semihosting/${ARCH}/semihosting_call.S\ - plat/qemu/qemu_io_storage.c \ - plat/qemu/${ARCH}/plat_helpers.S \ - plat/qemu/qemu_bl2_setup.c \ - common/fdt_fixup.c \ - plat/qemu/qemu_bl2_mem_params_desc.c \ - plat/qemu/qemu_image_load.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ + ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \ + common/fdt_fixup.c \ common/desc_image_load.c ifeq ($(add-lib-optee),yes) @@ -127,13 +131,13 @@ QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/common/gic_common.c \ plat/common/plat_gicv2.c \ - plat/qemu/qemu_gicv2.c + ${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ drivers/arm/gic/v3/gicv3_main.c \ drivers/arm/gic/common/gic_common.c \ plat/common/plat_gicv3.c \ - plat/qemu/qemu_gicv3.c + ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV2) QEMU_GIC_SOURCES := ${QEMU_GICV2_SOURCES} @@ -148,10 +152,10 @@ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/plat_psci_common.c \ - plat/qemu/qemu_pm.c \ - plat/qemu/topology.c \ - plat/qemu/aarch64/plat_helpers.S \ - plat/qemu/qemu_bl31_setup.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \ + ${PLAT_QEMU_COMMON_PATH}/topology.c \ + ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \ ${QEMU_GIC_SOURCES} endif @@ -167,7 +171,7 @@ endif SEPARATE_CODE_AND_RODATA := 1 ENABLE_STACK_PROTECTOR := 0 ifneq ($(ENABLE_STACK_PROTECTOR), 0) - PLAT_BL_COMMON_SOURCES += plat/qemu/qemu_stack_protector.c + PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c endif BL32_RAM_LOCATION := tdram diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h index c101cdc8..9dccab82 100644 --- a/plat/rockchip/px30/include/platform_def.h +++ b/plat/rockchip/px30/include/platform_def.h @@ -69,7 +69,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 512KB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x80000) @@ -79,7 +79,7 @@ /* * Put BL3-1 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* diff --git a/plat/rockchip/rk3288/include/shared/bl32_param.h b/plat/rockchip/rk3288/include/shared/bl32_param.h index 743dad41..ffdb2f38 100644 --- a/plat/rockchip/rk3288/include/shared/bl32_param.h +++ b/plat/rockchip/rk3288/include/shared/bl32_param.h @@ -10,9 +10,9 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 2MB */ +/* TF text, ro, rw, Size: 1MB */ #define TZRAM_BASE (0x0) -#define TZRAM_SIZE (0x200000) +#define TZRAM_SIZE (0x100000) /******************************************************************************* * BL32 specific defines. @@ -20,7 +20,7 @@ /* * Put BL32 at the top of the Trusted RAM */ -#define BL32_BASE (TZRAM_BASE + 0x100000) +#define BL32_BASE (TZRAM_BASE + 0x40000) #define BL32_LIMIT (TZRAM_BASE + TZRAM_SIZE) #endif /* BL32_PARAM_H */ diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index 3104d9fc..baac12d3 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -66,7 +66,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 512KB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x80000) @@ -76,7 +76,7 @@ /* * Put BL3-1 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 7b3cc6eb..9334a83a 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -67,7 +67,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 512KB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x80000) @@ -77,7 +77,7 @@ /* * Put BL3-1 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* diff --git a/plat/rockchip/rk3399/include/shared/bl31_param.h b/plat/rockchip/rk3399/include/shared/bl31_param.h index e7f2226c..6e7e8ba0 100644 --- a/plat/rockchip/rk3399/include/shared/bl31_param.h +++ b/plat/rockchip/rk3399/include/shared/bl31_param.h @@ -20,7 +20,7 @@ /* * Put BL31 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) #endif /* BL31_PARAM_H */ diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h index 68634389..de835716 100644 --- a/plat/rpi/common/include/rpi_shared.h +++ b/plat/rpi/common/include/rpi_shared.h @@ -14,7 +14,7 @@ ******************************************************************************/ /* Utility functions */ -void rpi3_console_init(void); +void rpi3_console_init(unsigned int base_clk_rate); void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, uintptr_t rodata_limit diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c index ab63d98f..ff336942 100644 --- a/plat/rpi/common/rpi3_common.c +++ b/plat/rpi/common/rpi3_common.c @@ -104,14 +104,14 @@ static const mmap_region_t plat_rpi3_mmap[] = { ******************************************************************************/ static console_16550_t rpi3_console; -void rpi3_console_init(void) +void rpi3_console_init(unsigned int base_clk_rate) { int console_scope = CONSOLE_FLAG_BOOT; #if RPI3_RUNTIME_UART != -1 console_scope |= CONSOLE_FLAG_RUNTIME; #endif int rc = console_16550_register(PLAT_RPI3_UART_BASE, - PLAT_RPI3_UART_CLK_IN_HZ, + base_clk_rate, PLAT_RPI3_UART_BAUDRATE, &rpi3_console); if (rc == 0) { @@ -176,18 +176,6 @@ void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, } /******************************************************************************* - * Return entrypoint of BL33. - ******************************************************************************/ -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_RPI3_NS_IMAGE_OFFSET; -#endif -} - -/******************************************************************************* * Gets SPSR for BL32 entry ******************************************************************************/ uint32_t rpi3_get_spsr_for_bl32_entry(void) diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c index 3ac30e0f..dcce76e4 100644 --- a/plat/rpi/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi/rpi3/rpi3_bl1_setup.c @@ -35,7 +35,7 @@ void bl1_early_platform_setup(void) 0x80000000); /* Initialize the console to provide early debug support */ - rpi3_console_init(); + rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c index 991c0fcb..44827c63 100644 --- a/plat/rpi/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi/rpi3/rpi3_bl2_setup.c @@ -62,7 +62,7 @@ void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, meminfo_t *mem_layout = (meminfo_t *) arg1; /* Initialize the console to provide early debug support */ - rpi3_console_init(); + rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ); /* Enable arch timer */ generic_delay_timer_init(); diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c index a9efc52b..24a56139 100644 --- a/plat/rpi/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi/rpi3/rpi3_bl31_setup.c @@ -48,6 +48,18 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) } /******************************************************************************* + * Return entrypoint of BL33. + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_RPI3_NS_IMAGE_OFFSET; +#endif +} + +/******************************************************************************* * Perform any BL31 early platform setup. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before * they are lost (potentially). This needs to be done before the MMU is @@ -60,7 +72,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { /* Initialize the console to provide early debug support */ - rpi3_console_init(); + rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ); /* * In debug builds, a special value is passed in 'arg1' to verify diff --git a/plat/rpi/rpi4/aarch64/armstub8_header.S b/plat/rpi/rpi4/aarch64/armstub8_header.S new file mode 100644 index 00000000..246358d0 --- /dev/null +++ b/plat/rpi/rpi4/aarch64/armstub8_header.S @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * armstub8.bin header to let the GPU firmware recognise this code. + * It will then write the load address of the kernel image and the DT + * after the header magic in RAM, so we can read those addresses at runtime. + */ + +.text + b armstub8_end + +.global stub_magic +.global dtb_ptr32 +.global kernel_entry32 + +.org 0xf0 +armstub8: +stub_magic: + .word 0x5afe570b +stub_version: + .word 0 +dtb_ptr32: + .word 0x0 +kernel_entry32: + .word 0x0 + +/* + * Technically an offset of 0x100 would suffice, but the follow-up code + * (bl31_entrypoint.S at BL31_BASE) needs to be page aligned, so pad here + * till the end of the first 4K page. + */ +.org 0x1000 +armstub8_end: diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S new file mode 100644 index 00000000..46073b79 --- /dev/null +++ b/plat/rpi/rpi4/aarch64/plat_helpers.S @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <platform_def.h> +#include <cortex_a72.h> + +#include "../include/rpi_hw.h" + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_rpi3_calc_core_pos + .globl plat_secondary_cold_boot_setup + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * + * This function uses the plat_rpi3_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_rpi3_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); + * + * CorePos = (ClusterId * 4) + CoreId + * ----------------------------------------------------- + */ +func plat_rpi3_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_rpi3_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #RPI4_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl x0, x0, #3 + mov_imm x2, PLAT_RPI3_TM_HOLD_BASE + add x0, x0, x2 + + /* + * This code runs way before requesting the warmboot of this core, + * so it is possible to clear the mailbox before getting a request + * to boot. + */ + mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT + str x1,[x0] + + /* Wait until we have a go */ +poll_mailbox: + wfe + ldr x1, [x0] + cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO + bne poll_mailbox + + /* Jump to the provided entrypoint */ + mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT + ldr x1, [x0] + br x1 +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * uintptr_t plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and a warm + * boot. + * + * This functions returns: + * - 0 for a cold boot. + * - Any other value for a warm boot. + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO: support warm boot */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + + /* --------------------------------------------- + * void platform_mem_init (void); + * + * No need to carry out any memory initialization. + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x3 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_RPI3_UART_BASE + mov_imm x1, PLAT_RPI4_VPU_CLK_RATE + mov_imm x2, PLAT_RPI3_UART_BAUDRATE + b console_16550_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_RPI3_UART_BASE + b console_16550_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_RPI3_UART_BASE + b console_16550_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + /* ------------------------------------------------ + * Set L2 read/write cache latency: + * - L2 Data RAM latency: 3 cycles (0b010) + * - L2 Data RAM setup: 1 cycle (bit 5) + * ------------------------------------------------ + */ + mrs x0, CORTEX_A72_L2CTLR_EL1 + mov x1, #0x22 + orr x0, x0, x1 + msr CORTEX_A72_L2CTLR_EL1, x0 + isb + + ret +endfunc plat_reset_handler diff --git a/plat/rpi/rpi4/include/plat.ld.S b/plat/rpi/rpi4/include/plat.ld.S new file mode 100644 index 00000000..9262fad8 --- /dev/null +++ b/plat/rpi/rpi4/include/plat.ld.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Stub linker script to provide the armstub8.bin header before the actual + * code. If the GPU firmware finds a magic value at offset 240 in + * armstub8.bin, it will put the DTB and kernel load address in subsequent + * words. We can then read those values to find the proper NS entry point + * and find our DTB more flexibly. + */ + +MEMORY { + PRERAM (rwx): ORIGIN = 0, LENGTH = 4096 +} + +SECTIONS +{ + .armstub8 . : { + *armstub8_header.o(.text*) + KEEP(*(.armstub8)) + } >PRERAM +} diff --git a/plat/rpi/rpi4/include/plat_macros.S b/plat/rpi/rpi4/include/plat_macros.S new file mode 100644 index 00000000..6007d031 --- /dev/null +++ b/plat/rpi/rpi4/include/plat_macros.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h new file mode 100644 index 00000000..a9ecdba2 --- /dev/null +++ b/plat/rpi/rpi4/include/platform_def.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +#include "rpi_hw.h" + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) + +#define PLATFORM_STACK_SIZE ULL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define RPI4_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* + * I/O registers. + */ +#define DEVICE0_BASE RPI_IO_BASE +#define DEVICE0_SIZE RPI_IO_SIZE + +/* + * Mailbox to control the secondary cores. All secondary cores are held in a + * wait loop in cold boot. To release them perform the following steps (plus + * any additional barriers that may be needed): + * + * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; + * *entrypoint = ADDRESS_TO_JUMP_TO; + * + * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; + * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; + * + * sev(); + */ +/* The secure entry point to be used on warm reset by all CPUs. */ +#define PLAT_RPI3_TM_ENTRYPOINT 0x100 +#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) + +/* Hold entries for each CPU. */ +#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ + PLAT_RPI3_TM_ENTRYPOINT_SIZE) +#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) +#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ + PLATFORM_CORE_COUNT) + +#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ + PLAT_RPI3_TM_HOLD_SIZE) + +#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) +#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) + +/* + * BL31 specific defines. + * + * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL31 debug size plus a little space for growth. + */ +#define PLAT_MAX_BL31_SIZE ULL(0x80000) + +#define BL31_BASE ULL(0x1000) +#define BL31_LIMIT ULL(0x80000) +#define BL31_PROGBITS_LIMIT ULL(0x80000) + +#define SEC_SRAM_ID 0 +#define SEC_DRAM_ID 1 + +/* + * Other memory-related defines. + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 8 +#define MAX_XLAT_TABLES 4 + +#define MAX_IO_DEVICES U(3) +#define MAX_IO_HANDLES U(4) + +#define MAX_IO_BLOCK_DEVICES U(1) + +/* + * Serial-related constants. + */ +#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE +#define PLAT_RPI3_UART_BAUDRATE ULL(115200) + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS ULL(54000000) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h new file mode 100644 index 00000000..ed367ee2 --- /dev/null +++ b/plat/rpi/rpi4/include/rpi_hw.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI_HW_H +#define RPI_HW_H + +#include <lib/utils_def.h> + +/* + * Peripherals + */ + +#define RPI_IO_BASE ULL(0xFE000000) +#define RPI_IO_SIZE ULL(0x02000000) + +/* + * ARM <-> VideoCore mailboxes + */ +#define RPI3_MBOX_OFFSET ULL(0x0000B880) +#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ + +/* + * Power management, reset controller, watchdog. + */ +#define RPI3_IO_PM_OFFSET ULL(0x00100000) +#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) +/* Registers on top of RPI3_PM_BASE. */ +#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) +#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) +#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) +/* Watchdog constants */ +#define RPI3_PM_PASSWORD U(0x5A000000) +#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) +#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) +/* + * The RSTS register is used by the VideoCore firmware when booting the + * Raspberry Pi to know which partition to boot from. The partition value is + * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware + * to indicate halt. + */ +#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) + +/* + * Clock controller + */ +#define RPI4_IO_CLOCK_OFFSET ULL(0x00101000) +#define RPI4_CLOCK_BASE (RPI_IO_BASE + RPI4_IO_CLOCK_OFFSET) +#define RPI4_VPU_CLOCK_DIVIDER ULL(0x0000000c) + +/* + * Hardware random number generator. + */ +#define RPI3_IO_RNG_OFFSET ULL(0x00104000) +#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) +#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) +#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) +#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) +/* Enable/disable RNG */ +#define RPI3_RNG_CTRL_ENABLE U(0x1) +#define RPI3_RNG_CTRL_DISABLE U(0x0) +/* Number of currently available words */ +#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) +#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) +/* Value to mask interrupts caused by the RNG */ +#define RPI3_RNG_INT_MASK_DISABLE U(0x1) + +/* + * Serial port (called 'Mini UART' in the Broadcom documentation). + */ +#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) +#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define PLAT_RPI4_VPU_CLK_RATE ULL(1000000000) + +/* + * GPIO controller + */ +#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) +#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) + +/* + * SDHost controller + */ +#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) +#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) + +/* + * GIC interrupt controller + */ +#define RPI_HAVE_GIC +#define RPI4_GIC_GICD_BASE ULL(0xff841000) +#define RPI4_GIC_GICC_BASE ULL(0xff842000) + +#define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000) +#define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008) + +#endif /* RPI_HW_H */ diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk new file mode 100644 index 00000000..2038021a --- /dev/null +++ b/plat/rpi/rpi4/platform.mk @@ -0,0 +1,103 @@ +# +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/libfdt/libfdt.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -Iplat/rpi/common/include \ + -Iplat/rpi/rpi4/include + +PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ + plat/rpi/common/rpi3_common.c \ + ${XLAT_TABLES_LIB_SRCS} + +BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ + plat/rpi/rpi4/aarch64/plat_helpers.S \ + plat/rpi/rpi4/aarch64/armstub8_header.S \ + drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + plat/common/plat_gicv2.c \ + plat/rpi/rpi4/rpi4_bl31_setup.c \ + plat/rpi/common/rpi3_pm.c \ + plat/common/plat_psci_common.c \ + plat/rpi/common/rpi3_topology.c \ + common/fdt_fixup.c \ + ${LIBFDT_SRCS} + +# For now we only support BL31, using the kernel loaded by the GPU firmware. +RESET_TO_BL31 := 1 + +# All CPUs enter armstub8.bin. +COLD_BOOT_SINGLE_CPU := 0 + +# Tune compiler for Cortex-A72 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a72 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a72 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a72 +endif + +# Add support for platform supplied linker script for BL31 build +$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) + +# Enable all errata workarounds for Cortex-A72 +ERRATA_A72_859971 := 1 + +WORKAROUND_CVE_2017_5715 := 1 + +# Add new default target when compiling this platform +all: bl31 + +# Build config flags +# ------------------ + +# Disable stack protector by default +ENABLE_STACK_PROTECTOR := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Platform build flags +# -------------------- + +# There is not much else than a Linux kernel to load at the moment. +RPI3_DIRECT_LINUX_BOOT := 1 + +# BL33 images are in AArch64 by default +RPI3_BL33_IN_AARCH32 := 0 + +# UART to use at runtime. -1 means the runtime UART is disabled. +# Any other value means the default UART will be used. +RPI3_RUNTIME_UART := 0 + +# Use normal memory mapping for ROM, FIP, SRAM and DRAM +RPI3_USE_UEFI_MAP := 0 + +# Process platform flags +# ---------------------- + +$(eval $(call add_define,RPI3_BL33_IN_AARCH32)) +$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) +ifdef RPI3_PRELOADED_DTB_BASE +$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) +endif +$(eval $(call add_define,RPI3_RUNTIME_UART)) +$(eval $(call add_define,RPI3_USE_UEFI_MAP)) + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on rpi4) +endif + +ifneq ($(ENABLE_STACK_PROTECTOR), 0) +PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ + plat/rpi/common/rpi3_stack_protector.c +endif diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c new file mode 100644 index 00000000..53ab0c2e --- /dev/null +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <libfdt.h> + +#include <platform_def.h> +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <common/fdt_fixup.h> +#include <libfdt.h> + +#include <drivers/arm/gicv2.h> + +#include <rpi_shared.h> + +/* + * Fields at the beginning of armstub8.bin. + * While building the BL31 image, we put the stub magic into the binary. + * The GPU firmware detects this at boot time, clears that field as a + * confirmation and puts the kernel and DT address in the following words. + */ +extern uint32_t stub_magic; +extern uint32_t dtb_ptr32; +extern uint32_t kernel_entry32; + +static const gicv2_driver_data_t rpi4_gic_data = { + .gicd_base = RPI4_GIC_GICD_BASE, + .gicc_base = RPI4_GIC_GICC_BASE, +}; + +/* + * To be filled by the code below. At the moment BL32 is not supported. + * In the future these might be passed down from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type) != 0); + + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc) { + return next_image_info; + } else { + return NULL; + } +} + +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + /* Cleared by the GPU if kernel address is valid. */ + if (stub_magic == 0) + return kernel_entry32; + + WARN("Stub magic failure, using default kernel address 0x80000\n"); + return 0x80000; +#endif +} + +static uintptr_t rpi4_get_dtb_address(void) +{ +#ifdef RPI3_PRELOADED_DTB_BASE + return RPI3_PRELOADED_DTB_BASE; +#else + /* Cleared by the GPU if DTB address is valid. */ + if (stub_magic == 0) + return dtb_ptr32; + + WARN("Stub magic failure, DTB address unknown\n"); + return 0; +#endif +} + +static void ldelay(register_t delay) +{ + __asm__ volatile ( + "1:\tcbz %0, 2f\n\t" + "sub %0, %0, #1\n\t" + "b 1b\n" + "2:" + : "=&r" (delay) : "0" (delay) + ); +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) + +{ + uint32_t div_reg; + + /* + * LOCAL_CONTROL: + * Bit 9 clear: Increment by 1 (vs. 2). + * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB). + */ + mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0); + + /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */ + mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000); + + /* Early GPU firmware revisions need a little break here. */ + ldelay(100000); + + /* + * Initialize the console to provide early debug support. + * Different GPU firmware revisions set up the VPU divider differently, + * so read the actual divider register to learn the UART base clock + * rate. The divider is encoded as a 12.12 fixed point number, but we + * just care about the integer part of it. + */ + div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER); + div_reg = (div_reg >> 12) & 0xfff; + if (div_reg == 0) + div_reg = 1; + rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg); + + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#if RPI3_DIRECT_LINUX_BOOT +# if RPI3_BL33_IN_AARCH32 + /* + * According to the file ``Documentation/arm/Booting`` of the Linux + * kernel tree, Linux expects: + * r0 = 0 + * r1 = machine type number, optional in DT-only platforms (~0 if so) + * r2 = Physical address of the device tree blob + */ + VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n"); + bl33_image_ep_info.args.arg0 = 0U; + bl33_image_ep_info.args.arg1 = ~0U; + bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address(); +# else + /* + * According to the file ``Documentation/arm64/booting.txt`` of the + * Linux kernel tree, Linux expects the physical address of the device + * tree blob (DTB) in x0, while x1-x3 are reserved for future use and + * must be 0. + */ + VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n"); + bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address(); + bl33_image_ep_info.args.arg1 = 0ULL; + bl33_image_ep_info.args.arg2 = 0ULL; + bl33_image_ep_info.args.arg3 = 0ULL; +# endif /* RPI3_BL33_IN_AARCH32 */ +#endif /* RPI3_DIRECT_LINUX_BOOT */ +} + +void bl31_plat_arch_setup(void) +{ + /* + * Is the dtb_ptr32 pointer valid? If yes, map the DTB region. + * We map the 2MB region the DTB start address lives in, plus + * the next 2MB, to have enough room for expansion. + */ + if (stub_magic == 0) { + unsigned long long dtb_region = dtb_ptr32; + + dtb_region &= ~0x1fffff; /* Align to 2 MB. */ + mmap_add_region(dtb_region, dtb_region, 4U << 20, + MT_MEMORY | MT_RW | MT_NS); + } + /* + * Add the first page of memory, which holds the stub magic, + * the kernel and the DT address. + * This also holds the secondary CPU's entrypoints and mailboxes. + */ + mmap_add_region(0, 0, 4096, MT_NON_CACHEABLE | MT_RW | MT_SECURE); + + rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, + BL_CODE_BASE, BL_CODE_END, + BL_RO_DATA_BASE, BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END +#endif + ); + + enable_mmu_el3(0); +} + +static uint32_t dtb_size(const void *dtb) +{ + const uint32_t *dtb_header = dtb; + + return fdt32_to_cpu(dtb_header[1]); +} + +static void rpi4_prepare_dtb(void) +{ + void *dtb = (void *)rpi4_get_dtb_address(); + uint32_t gic_int_prop[3]; + int ret, offs; + + /* Return if no device tree is detected */ + if (fdt_check_header(dtb) != 0) + return; + + ret = fdt_open_into(dtb, dtb, 0x100000); + if (ret < 0) { + ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); + return; + } + + if (dt_add_psci_node(dtb)) { + ERROR("Failed to add PSCI Device Tree node\n"); + return; + } + + if (dt_add_psci_cpu_enable_methods(dtb)) { + ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); + return; + } + + /* Reserve memory used by Trusted Firmware. */ + if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000)) + WARN("Failed to add reserved memory nodes to DT.\n"); + + offs = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-400"); + gic_int_prop[0] = cpu_to_fdt32(1); // PPI + gic_int_prop[1] = cpu_to_fdt32(9); // PPI #9 + gic_int_prop[2] = cpu_to_fdt32(0x0f04); // all cores, level high + fdt_setprop(dtb, offs, "interrupts", gic_int_prop, 12); + + offs = fdt_path_offset(dtb, "/chosen"); + fdt_setprop_string(dtb, offs, "stdout-path", "serial0"); + + ret = fdt_pack(dtb); + if (ret < 0) + ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); + + clean_dcache_range((uintptr_t)dtb, dtb_size(dtb)); + INFO("Changed device tree to advertise PSCI.\n"); +} + +void bl31_platform_setup(void) +{ + rpi4_prepare_dtb(); + + /* Configure the interrupt controller */ + gicv2_driver_init(&rpi4_gic_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} |