diff options
| -rw-r--r-- | plat/imx/common/imx_sip_svc.c | 3 | ||||
| -rw-r--r-- | plat/imx/common/include/imx_sip_svc.h | 11 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mq/imx8mq_misc.c | 41 |
3 files changed, 55 insertions, 0 deletions
diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c index ea76640a..b0285143 100644 --- a/plat/imx/common/imx_sip_svc.c +++ b/plat/imx/common/imx_sip_svc.c @@ -41,6 +41,9 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid, case IMX_SIP_HAB: SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4)); break; + case IMX_SIP_NOC: + SMC_RET1(handle, imx_noc_handler(smc_fid, x1, x2, x3)); + break; #endif #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) case IMX_SIP_DDR_DVFS: diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h index 6b1371f3..9b5619b1 100644 --- a/plat/imx/common/include/imx_sip_svc.h +++ b/plat/imx/common/include/imx_sip_svc.h @@ -41,6 +41,15 @@ #define IMX_SIP_HAB_FAILSAFE 0x05 #define IMX_SIP_HAB_CHECK_TARGET 0x06 +#define IMX_SIP_NOC 0xc2000008 +#define IMX_SIP_NOC_LCDIF 0x0 +#define IMX_SIP_NOC_PRIORITY 0x1 +#define NOC_GPU_PRIORITY 0x10 +#define NOC_DCSS_PRIORITY 0x11 +#define NOC_VPU_PRIORITY 0x12 +#define NOC_CPU_PRIORITY 0x13 +#define NOC_MIX_PRIORITY 0x14 + #define IMX_SIP_WAKEUP_SRC 0xC2000009 #define IMX_SIP_WAKEUP_SRC_SCU 0x1 #define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 @@ -63,6 +72,8 @@ int dram_dvfs_handler(uint32_t smc_fid, void *handle, int imx_hab_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3, u_register_t x4); +int imx_noc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3); #endif #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) int dram_dvfs_handler(uint32_t smc_fid, void *handle, diff --git a/plat/imx/imx8m/imx8mq/imx8mq_misc.c b/plat/imx/imx8m/imx8mq/imx8mq_misc.c index 17213660..9ee3b2ad 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_misc.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_misc.c @@ -31,3 +31,44 @@ int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, return 0; } + +int imx_noc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, + u_register_t x3) +{ + if (IMX_SIP_NOC_LCDIF == x1) { + /* config NOC for VPU */ + mmio_write_32(IMX_NOC_BASE + 0x108, 0x34); + mmio_write_32(IMX_NOC_BASE + 0x10c, 0x1); + mmio_write_32(IMX_NOC_BASE + 0x110, 0x500); + mmio_write_32(IMX_NOC_BASE + 0x114, 0x30); + /* config NOC for CPU */ + mmio_write_32(IMX_NOC_BASE + 0x188, 0x34); + mmio_write_32(IMX_NOC_BASE + 0x18c, 0x1); + mmio_write_32(IMX_NOC_BASE + 0x190, 0x500); + mmio_write_32(IMX_NOC_BASE + 0x194, 0x30); + } else if (IMX_SIP_NOC_PRIORITY == x1) { + switch(x2) { + case NOC_GPU_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x008, x3); + break; + case NOC_DCSS_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x088, x3); + break; + case NOC_VPU_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x108, x3); + break; + case NOC_CPU_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x188, x3); + break; + case NOC_MIX_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x288, x3); + break; + default: + return SMC_UNK; + }; + } else { + return SMC_UNK; + } + + return 0; +} |