diff options
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_bl31_setup.c | 8 | ||||
| -rw-r--r-- | plat/imx/imx8qm/include/sec_rsrc.h | 8 | ||||
| -rw-r--r-- | plat/imx/imx8qx/imx8qx_bl31_setup.c | 7 | ||||
| -rw-r--r-- | plat/imx/imx8qx/include/sec_rsrc.h | 8 |
4 files changed, 29 insertions, 2 deletions
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index c9cdf406..dd1f107f 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -426,6 +426,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, /* turn on MU1 for non-secure OS/Hypervisor */ sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); + /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */ sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); @@ -437,6 +438,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, */ mx8_partition_resources(); +#ifdef SPD_trusty + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2_OUT, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON); +#endif + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); #ifdef SPD_trusty diff --git a/plat/imx/imx8qm/include/sec_rsrc.h b/plat/imx/imx8qm/include/sec_rsrc.h index 260c2c72..f2d71560 100644 --- a/plat/imx/imx8qm/include/sec_rsrc.h +++ b/plat/imx/imx8qm/include/sec_rsrc.h @@ -19,7 +19,13 @@ sc_rsrc_t secure_rsrcs[] = { SC_R_CCI, SC_R_SYSTEM, SC_R_IRQSTR_SCU2, - SC_R_GPT_0 + SC_R_GPT_0, +#ifdef SPD_trusty + SC_R_CAAM_JR2, + SC_R_CAAM_JR2_OUT, + SC_R_CAAM_JR3, + SC_R_CAAM_JR3_OUT +#endif }; /* resources that have register access for non-secure domain */ diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c index 0b10191c..e15b9b38 100644 --- a/plat/imx/imx8qx/imx8qx_bl31_setup.c +++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c @@ -414,6 +414,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, */ imx8_partition_resources(); +#ifdef SPD_trusty + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2_OUT, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON); +#endif + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); #ifdef SPD_trusty diff --git a/plat/imx/imx8qx/include/sec_rsrc.h b/plat/imx/imx8qx/include/sec_rsrc.h index b7fe0e81..8a9a817f 100644 --- a/plat/imx/imx8qx/include/sec_rsrc.h +++ b/plat/imx/imx8qx/include/sec_rsrc.h @@ -15,7 +15,13 @@ sc_rsrc_t secure_rsrcs[] = { SC_R_GIC, SC_R_SYSTEM, SC_R_IRQSTR_SCU2, - SC_R_GPT_0 + SC_R_GPT_0, +#ifdef SPD_trusty + SC_R_CAAM_JR2, + SC_R_CAAM_JR2_OUT, + SC_R_CAAM_JR3, + SC_R_CAAM_JR3_OUT +#endif }; /* resources that have register access for non-secure domain */ |