diff options
| -rw-r--r-- | .gitignore | 2 | ||||
| -rw-r--r-- | docs/maintainers.rst | 8 | ||||
| -rw-r--r-- | drivers/amlogic/console/aarch64/meson_console.S (renamed from drivers/meson/console/aarch64/meson_console.S) | 4 | ||||
| -rw-r--r-- | drivers/amlogic/crypto/sha_dma.c (renamed from drivers/meson/gxl/crypto/sha_dma.c) | 4 | ||||
| -rw-r--r-- | include/drivers/amlogic/crypto/sha_dma.h (renamed from include/drivers/meson/gxl/crypto/sha_dma.h) | 0 | ||||
| -rw-r--r-- | include/drivers/amlogic/meson_console.h (renamed from include/drivers/meson/meson_console.h) | 0 | ||||
| -rw-r--r-- | plat/amlogic/common/aarch64/aml_helpers.S (renamed from plat/meson/gxbb/aarch64/gxbb_helpers.S) | 24 | ||||
| -rw-r--r-- | plat/amlogic/common/aml_efuse.c | 25 | ||||
| -rw-r--r-- | plat/amlogic/common/aml_mhu.c | 52 | ||||
| -rw-r--r-- | plat/amlogic/common/aml_scpi.c | 211 | ||||
| -rw-r--r-- | plat/amlogic/common/aml_sip_svc.c (renamed from plat/meson/gxl/gxl_sip_svc.c) | 38 | ||||
| -rw-r--r-- | plat/amlogic/common/aml_thermal.c (renamed from plat/meson/gxbb/gxbb_thermal.c) | 12 | ||||
| -rw-r--r-- | plat/amlogic/common/aml_topology.c (renamed from plat/meson/gxl/gxl_topology.c) | 6 | ||||
| -rw-r--r-- | plat/amlogic/common/include/aml_private.h | 40 | ||||
| -rw-r--r-- | plat/amlogic/common/include/plat_macros.S (renamed from plat/meson/gxl/include/plat_macros.S) | 6 | ||||
| -rw-r--r-- | plat/amlogic/gxbb/gxbb_bl31_setup.c (renamed from plat/meson/gxbb/gxbb_bl31_setup.c) | 22 | ||||
| -rw-r--r-- | plat/amlogic/gxbb/gxbb_common.c (renamed from plat/meson/gxl/gxl_common.c) | 56 | ||||
| -rw-r--r-- | plat/amlogic/gxbb/gxbb_def.h | 118 | ||||
| -rw-r--r-- | plat/amlogic/gxbb/gxbb_pm.c (renamed from plat/meson/gxbb/gxbb_pm.c) | 50 | ||||
| -rw-r--r-- | plat/amlogic/gxbb/include/platform_def.h (renamed from plat/meson/gxbb/include/platform_def.h) | 6 | ||||
| -rw-r--r-- | plat/amlogic/gxbb/platform.mk | 74 | ||||
| -rw-r--r-- | plat/amlogic/gxl/gxl_bl31_setup.c (renamed from plat/meson/gxl/gxl_bl31_setup.c) | 40 | ||||
| -rw-r--r-- | plat/amlogic/gxl/gxl_common.c (renamed from plat/meson/gxbb/gxbb_common.c) | 72 | ||||
| -rw-r--r-- | plat/amlogic/gxl/gxl_def.h | 128 | ||||
| -rw-r--r-- | plat/amlogic/gxl/gxl_pm.c (renamed from plat/meson/gxl/gxl_pm.c) | 102 | ||||
| -rw-r--r-- | plat/amlogic/gxl/include/platform_def.h (renamed from plat/meson/gxl/include/platform_def.h) | 7 | ||||
| -rw-r--r-- | plat/amlogic/gxl/platform.mk | 90 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_def.h | 118 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_efuse.c | 25 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_mhu.c | 53 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_private.h | 38 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_scpi.c | 139 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_sip_svc.c | 68 | ||||
| -rw-r--r-- | plat/meson/gxbb/gxbb_topology.c | 55 | ||||
| -rw-r--r-- | plat/meson/gxbb/include/plat_macros.S | 71 | ||||
| -rw-r--r-- | plat/meson/gxbb/platform.mk | 69 | ||||
| -rw-r--r-- | plat/meson/gxl/aarch64/gxl_helpers.S | 97 | ||||
| -rw-r--r-- | plat/meson/gxl/gxl_def.h | 128 | ||||
| -rw-r--r-- | plat/meson/gxl/gxl_efuse.c | 25 | ||||
| -rw-r--r-- | plat/meson/gxl/gxl_mhu.c | 52 | ||||
| -rw-r--r-- | plat/meson/gxl/gxl_private.h | 40 | ||||
| -rw-r--r-- | plat/meson/gxl/gxl_scpi.c | 211 | ||||
| -rw-r--r-- | plat/meson/gxl/gxl_thermal.c | 27 | ||||
| -rw-r--r-- | plat/meson/gxl/platform.mk | 87 | ||||
| -rw-r--r-- | tools/amlogic/Makefile (renamed from tools/meson/Makefile) | 0 | ||||
| -rw-r--r-- | tools/amlogic/doimage.c (renamed from tools/meson/doimage.c) | 0 |
46 files changed, 963 insertions, 1537 deletions
@@ -22,7 +22,7 @@ tools/cert_create/src/**/*.o tools/cert_create/cert_create tools/cert_create/cert_create.exe tools/marvell/doimage/doimage -tools/meson/doimage +tools/amlogic/doimage tools/stm32image/*.o tools/stm32image/stm32image tools/stm32image/stm32image.exe diff --git a/docs/maintainers.rst b/docs/maintainers.rst index cbfc652f..7731c72e 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -37,16 +37,16 @@ Amlogic Meson S905 (GXBB) platform port :M: Andre Przywara <andre.przywara@arm.com> :G: `Andre-ARM`_ :F: docs/plat/meson-gxbb.rst -:F: drivers/meson/ -:F: plat/meson/gxbb/ +:F: drivers/amlogic/ +:F: plat/amlogic/gxbb/ Amlogic Meson S905x (GXL) platform port --------------------------------------- :M: Remi Pommarel <repk@triplefau.lt> :G: `remi-triplefault`_ :F: docs/plat/meson-gxl.rst -:F: drivers/meson/gxl -:F: plat/meson/gxl/ +:F: drivers/amlogic/gxl +:F: plat/amlogic/gxl/ Armv7-A architecture port ------------------------- diff --git a/drivers/meson/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S index 22d07733..e645cbab 100644 --- a/drivers/meson/console/aarch64/meson_console.S +++ b/drivers/amlogic/console/aarch64/meson_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include <asm_macros.S> #include <assert_macros.S> #include <console_macros.S> -#include <drivers/meson/meson_console.h> +#include <drivers/amlogic/meson_console.h> .globl console_meson_register .globl console_meson_init diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c index a969dea7..d48ded98 100644 --- a/drivers/meson/gxl/crypto/sha_dma.c +++ b/drivers/amlogic/crypto/sha_dma.c @@ -4,10 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <assert.h> #include <arch_helpers.h> -#include <lib/mmio.h> +#include <assert.h> #include <crypto/sha_dma.h> +#include <lib/mmio.h> #define AML_SHA_DMA_BASE 0xc883e000 diff --git a/include/drivers/meson/gxl/crypto/sha_dma.h b/include/drivers/amlogic/crypto/sha_dma.h index 52129a61..52129a61 100644 --- a/include/drivers/meson/gxl/crypto/sha_dma.h +++ b/include/drivers/amlogic/crypto/sha_dma.h diff --git a/include/drivers/meson/meson_console.h b/include/drivers/amlogic/meson_console.h index 70e3b0bd..70e3b0bd 100644 --- a/include/drivers/meson/meson_console.h +++ b/include/drivers/amlogic/meson_console.h diff --git a/plat/meson/gxbb/aarch64/gxbb_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S index 760d6c46..39bff083 100644 --- a/plat/meson/gxbb/aarch64/gxbb_helpers.S +++ b/plat/amlogic/common/aarch64/aml_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ .globl plat_is_my_cpu_primary .globl plat_my_core_pos .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos + .globl plat_calc_core_pos /* ----------------------------------------------------- * unsigned int plat_my_core_pos(void); @@ -24,17 +24,17 @@ */ func plat_my_core_pos mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos + b plat_calc_core_pos endfunc plat_my_core_pos /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); + * unsigned int plat_calc_core_pos(u_register_t mpidr); * ----------------------------------------------------- */ -func plat_gxbb_calc_core_pos +func plat_calc_core_pos and x0, x0, #MPIDR_CPU_MASK ret -endfunc plat_gxbb_calc_core_pos +endfunc plat_calc_core_pos /* ----------------------------------------------------- * unsigned int plat_is_my_cpu_primary(void); @@ -43,7 +43,7 @@ endfunc plat_gxbb_calc_core_pos func plat_is_my_cpu_primary mrs x0, mpidr_el1 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU + cmp x0, #AML_PRIMARY_CPU cset w0, eq ret endfunc plat_is_my_cpu_primary @@ -61,9 +61,9 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE + mov_imm x0, AML_UART0_AO_BASE + mov_imm x1, AML_UART0_AO_CLK_IN_HZ + mov_imm x2, AML_UART_BAUDRATE b console_meson_init endfunc plat_crash_console_init @@ -73,7 +73,7 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE + mov_imm x1, AML_UART0_AO_BASE b console_meson_core_putc endfunc plat_crash_console_putc @@ -84,7 +84,7 @@ endfunc plat_crash_console_putc * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE + mov_imm x0, AML_UART0_AO_BASE b console_meson_core_flush endfunc plat_crash_console_flush diff --git a/plat/amlogic/common/aml_efuse.c b/plat/amlogic/common/aml_efuse.c new file mode 100644 index 00000000..00884ebd --- /dev/null +++ b/plat/amlogic/common/aml_efuse.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include "aml_private.h" + +#define EFUSE_BASE 0x140 +#define EFUSE_SIZE 0xC0 + +uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size) +{ + if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) + return 0; + + return aml_scpi_efuse_read(dst, offset + EFUSE_BASE, size); +} + +uint64_t aml_efuse_user_max(void) +{ + return EFUSE_SIZE; +} diff --git a/plat/amlogic/common/aml_mhu.c b/plat/amlogic/common/aml_mhu.c new file mode 100644 index 00000000..001686af --- /dev/null +++ b/plat/amlogic/common/aml_mhu.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/bakery_lock.h> +#include <lib/mmio.h> +#include <platform_def.h> + +static DEFINE_BAKERY_LOCK(mhu_lock); + +void aml_mhu_secure_message_start(void) +{ + bakery_lock_get(&mhu_lock); + + while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0) + ; +} + +void aml_mhu_secure_message_send(uint32_t msg) +{ + mmio_write_32(AML_HIU_MAILBOX_SET_3, msg); + + while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0) + ; +} + +uint32_t aml_mhu_secure_message_wait(void) +{ + uint32_t val; + + do { + val = mmio_read_32(AML_HIU_MAILBOX_STAT_0); + } while (val == 0); + + return val; +} + +void aml_mhu_secure_message_end(void) +{ + mmio_write_32(AML_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); + + bakery_lock_release(&mhu_lock); +} + +void aml_mhu_secure_init(void) +{ + bakery_lock_init(&mhu_lock); + + mmio_write_32(AML_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); +} diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c new file mode 100644 index 00000000..728bcd06 --- /dev/null +++ b/plat/amlogic/common/aml_scpi.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <crypto/sha_dma.h> +#include <lib/mmio.h> +#include <plat/common/platform.h> +#include <platform_def.h> +#include <string.h> + +#include "aml_private.h" + +#define SIZE_SHIFT 20 +#define SIZE_MASK 0x1FF +#define SIZE_FWBLK 0x200UL + +/* + * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. + */ +#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 +#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 + +#define SCPI_CMD_JTAG_SET_STATE 0xC0 +#define SCPI_CMD_EFUSE_READ 0xC2 + +#define SCPI_CMD_COPY_FW 0xd4 +#define SCPI_CMD_SET_FW_ADDR 0xd3 +#define SCPI_CMD_FW_SIZE 0xd2 + +static inline uint32_t aml_scpi_cmd(uint32_t command, uint32_t size) +{ + return command | (size << SIZE_SHIFT); +} + +static void aml_scpi_secure_message_send(uint32_t command, uint32_t size) +{ + aml_mhu_secure_message_send(aml_scpi_cmd(command, size)); +} + +static uint32_t aml_scpi_secure_message_receive(void **message_out, size_t *size_out) +{ + uint32_t response = aml_mhu_secure_message_wait(); + + size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; + + response &= ~(SIZE_MASK << SIZE_SHIFT); + + if (size_out != NULL) + *size_out = size; + + if (message_out != NULL) + *message_out = (void *)AML_MHU_SECURE_SCP_TO_AP_PAYLOAD; + + return response; +} + +void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state) +{ + uint32_t state = (mpidr & 0x0F) | /* CPU ID */ + ((mpidr & 0xF00) >> 4) | /* Cluster ID */ + (cpu_state << 8) | + (cluster_state << 12) | + (css_state << 16); + + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + aml_mhu_secure_message_wait(); + aml_mhu_secure_message_end(); +} + +uint32_t aml_scpi_sys_power_state(uint64_t system_state) +{ + uint32_t *response; + size_t size; + + aml_mhu_secure_message_start(); + mmio_write_8(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + aml_scpi_secure_message_receive((void *)&response, &size); + aml_mhu_secure_message_end(); + + return *response; +} + +void aml_scpi_jtag_set_state(uint32_t state, uint8_t select) +{ + assert(state <= AML_JTAG_STATE_OFF); + + if (select > AML_JTAG_A53_EE) { + WARN("BL31: Invalid JTAG select (0x%x).\n", select); + return; + } + + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, + (state << 8) | (uint32_t)select); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + aml_mhu_secure_message_wait(); + aml_mhu_secure_message_end(); +} + +uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size) +{ + uint32_t *response; + size_t resp_size; + + if (size > 0x1FC) + return 0; + + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + aml_scpi_secure_message_receive((void *)&response, &resp_size); + aml_mhu_secure_message_end(); + + /* + * response[0] is the size of the response message. + * response[1 ... N] are the contents. + */ + if (*response != 0) + memcpy(dst, response + 1, *response); + + return *response; +} + +void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); + aml_mhu_secure_message_send(aml_scpi_cmd(0xC3, 16)); + aml_mhu_secure_message_wait(); + aml_mhu_secure_message_end(); +} + +static inline void aml_scpi_copy_scp_data(uint8_t *data, size_t len) +{ + void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; + size_t sz; + + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + aml_mhu_secure_message_wait(); + + for (sz = 0; sz < len; sz += SIZE_FWBLK) { + memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); + aml_mhu_secure_message_send(SCPI_CMD_COPY_FW); + } +} + +static inline void aml_scpi_set_scp_addr(uint64_t addr, size_t len) +{ + volatile uint64_t *dst = (uint64_t *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + /* + * It is ok as AML_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as + * non cachable + */ + *dst = addr; + aml_scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); + aml_mhu_secure_message_wait(); + + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + aml_mhu_secure_message_wait(); +} + +static inline void aml_scpi_send_fw_hash(uint8_t hash[], size_t len) +{ + void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + memcpy(dst, hash, len); + aml_mhu_secure_message_send(0xd0); + aml_mhu_secure_message_send(0xd1); + aml_mhu_secure_message_send(0xd5); + aml_mhu_secure_message_end(); +} + +/** + * Upload a FW to SCP. + * + * @param addr: firmware data address + * @param size: size of firmware + * @param send: If set, actually copy the firmware in SCP memory otherwise only + * send the firmware address. + */ +void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) +{ + struct asd_ctx ctx; + + asd_sha_init(&ctx, ASM_SHA256); + asd_sha_update(&ctx, (void *)addr, size); + asd_sha_finalize(&ctx); + + aml_mhu_secure_message_start(); + if (send == 0) + aml_scpi_set_scp_addr(addr, size); + else + aml_scpi_copy_scp_data((void *)addr, size); + + aml_scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); +} diff --git a/plat/meson/gxl/gxl_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c index 74fbc80e..8a9b070d 100644 --- a/plat/meson/gxl/gxl_sip_svc.c +++ b/plat/amlogic/common/aml_sip_svc.c @@ -1,21 +1,21 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <common/debug.h> +#include <common/runtime_svc.h> #include <lib/mmio.h> #include <platform_def.h> -#include <common/runtime_svc.h> #include <stdint.h> -#include "gxl_private.h" +#include "aml_private.h" /******************************************************************************* * This function is responsible for handling all SiP calls ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, +static uintptr_t aml_sip_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3, u_register_t x4, void *cookie, void *handle, @@ -23,28 +23,28 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid, { switch (smc_fid) { - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); + case AML_SM_GET_SHARE_MEM_INPUT_BASE: + SMC_RET1(handle, AML_SHARE_MEM_INPUT_BASE); - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); + case AML_SM_GET_SHARE_MEM_OUTPUT_BASE: + SMC_RET1(handle, AML_SHARE_MEM_OUTPUT_BASE); - case GXBB_SM_EFUSE_READ: + case AML_SM_EFUSE_READ: { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); + void *dst = (void *)AML_SHARE_MEM_OUTPUT_BASE; + uint64_t ret = aml_efuse_read(dst, (uint32_t)x1, x2); SMC_RET1(handle, ret); } - case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); + case AML_SM_EFUSE_USER_MAX: + SMC_RET1(handle, aml_efuse_user_max()); - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); + case AML_SM_JTAG_ON: + aml_scpi_jtag_set_state(AML_JTAG_STATE_ON, x1); SMC_RET1(handle, 0); - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); + case AML_SM_JTAG_OFF: + aml_scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1); SMC_RET1(handle, 0); default: @@ -56,11 +56,11 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid, } DECLARE_RT_SVC( - gxbb_sip_handler, + aml_sip_handler, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_FAST, NULL, - gxbb_sip_handler + aml_sip_handler ); diff --git a/plat/meson/gxbb/gxbb_thermal.c b/plat/amlogic/common/aml_thermal.c index b6048eee..53ed1032 100644 --- a/plat/meson/gxbb/gxbb_thermal.c +++ b/plat/amlogic/common/aml_thermal.c @@ -1,27 +1,27 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <stdint.h> -#include "gxbb_private.h" +#include "aml_private.h" static int32_t modules_initialized = -1; /******************************************************************************* * Unknown commands related to something thermal-related ******************************************************************************/ -void gxbb_thermal_unknown(void) +void aml_thermal_unknown(void) { uint16_t ret; if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); + aml_scpi_efuse_read(&ret, 0, 2); modules_initialized = ret; } - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ + aml_scpi_unknown_thermal(10, 2, /* thermal */ + 13, 1); /* thermalver */ } diff --git a/plat/meson/gxl/gxl_topology.c b/plat/amlogic/common/aml_topology.c index cca3ead5..0a04c110 100644 --- a/plat/meson/gxl/gxl_topology.c +++ b/plat/amlogic/common/aml_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #include <platform_def.h> #include <stdint.h> -#include "gxl_private.h" +#include "aml_private.h" /* The power domain tree descriptor */ static unsigned char power_domain_tree_desc[] = { @@ -49,5 +49,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr) if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) return -1; - return plat_gxbb_calc_core_pos(mpidr); + return plat_calc_core_pos(mpidr); } diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h new file mode 100644 index 00000000..49237456 --- /dev/null +++ b/plat/amlogic/common/include/aml_private.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AML_PRIVATE_H +#define AML_PRIVATE_H + +#include <stddef.h> +#include <stdint.h> + +/* Utility functions */ +unsigned int plat_calc_core_pos(u_register_t mpidr); +void aml_console_init(void); +void aml_setup_page_tables(void); + +/* MHU functions */ +void aml_mhu_secure_message_start(void); +void aml_mhu_secure_message_send(uint32_t msg); +uint32_t aml_mhu_secure_message_wait(void); +void aml_mhu_secure_message_end(void); +void aml_mhu_secure_init(void); + +/* SCPI functions */ +void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t aml_scpi_sys_power_state(uint64_t system_state); +void aml_scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); +void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); + +/* Peripherals */ +void aml_thermal_unknown(void); +uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t aml_efuse_user_max(void); + +#endif /* AML_PRIVATE_H */ diff --git a/plat/meson/gxl/include/plat_macros.S b/plat/amlogic/common/include/plat_macros.S index c721c21b..d620fcfb 100644 --- a/plat/meson/gxl/include/plat_macros.S +++ b/plat/amlogic/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,7 +33,7 @@ spacer: /* GICC registers */ - mov_imm x17, GXBB_GICC_BASE + mov_imm x17, AML_GICC_BASE adr x6, gicc_regs ldr w8, [x17, #GICC_HPPIR] @@ -43,7 +43,7 @@ spacer: /* GICD registers */ - mov_imm x16, GXBB_GICD_BASE + mov_imm x16, AML_GICD_BASE add x7, x16, #GICD_ISPENDR adr x4, gicd_pend_reg diff --git a/plat/meson/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index b867a584..cc7a1c49 100644 --- a/plat/meson/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -1,20 +1,18 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> - -#include <platform_def.h> - #include <common/bl_common.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv2.h> #include <lib/xlat_tables/xlat_mmu_helpers.h> #include <plat/common/platform.h> +#include <platform_def.h> -#include "gxbb_private.h" +#include "aml_private.h" /* * Placeholder variables for copying the arguments that have been passed to @@ -67,13 +65,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, struct gxbb_bl31_param *from_bl2; /* Initialize the console to provide early debug support */ - gxbb_console_init(); + aml_console_init(); /* * In debug builds, we pass a special value in 'arg1' to verify platform * parameters from BL2 to BL31. In release builds it's not used. */ - assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL); + assert(arg1 == AML_BL31_PLAT_PARAM_VAL); /* Check that params passed from BL2 are not NULL. */ from_bl2 = (struct gxbb_bl31_param *) arg0; @@ -97,7 +95,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - gxbb_setup_page_tables(); + aml_setup_page_tables(); enable_mmu_el3(0); } @@ -127,20 +125,20 @@ static const interrupt_prop_t gxbb_interrupt_props[] = { }; static const gicv2_driver_data_t gxbb_gic_data = { - .gicd_base = GXBB_GICD_BASE, - .gicc_base = GXBB_GICC_BASE, + .gicd_base = AML_GICD_BASE, + .gicc_base = AML_GICC_BASE, .interrupt_props = gxbb_interrupt_props, .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), }; void bl31_platform_setup(void) { - mhu_secure_init(); + aml_mhu_secure_init(); gicv2_driver_init(&gxbb_gic_data); gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); - gxbb_thermal_unknown(); + aml_thermal_unknown(); } diff --git a/plat/meson/gxl/gxl_common.c b/plat/amlogic/gxbb/gxbb_common.c index e3bd6048..e98748e7 100644 --- a/plat/meson/gxl/gxl_common.c +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -1,49 +1,49 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> +#include <bl31/interrupt_mgmt.h> #include <common/bl_common.h> #include <common/debug.h> #include <common/ep_info.h> -#include <bl31/interrupt_mgmt.h> -#include <meson_console.h> +#include <drivers/amlogic/meson_console.h> #include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> #include <platform_def.h> #include <stdint.h> -#include <lib/xlat_tables/xlat_tables_v2.h> /******************************************************************************* * Platform memory map regions ******************************************************************************/ -#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ - GXBB_NSDRAM0_SIZE, \ +#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ + AML_NSDRAM0_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ - GXBB_NSDRAM1_SIZE, \ +#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \ + AML_NSDRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ - GXBB_SEC_DEVICE0_SIZE, \ +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ + AML_SEC_DEVICE0_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ - GXBB_SEC_DEVICE1_SIZE, \ +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ + AML_SEC_DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ - GXBB_TZRAM_SIZE, \ +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ - GXBB_SEC_DEVICE2_SIZE, \ +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ + AML_SEC_DEVICE2_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ - GXBB_SEC_DEVICE3_SIZE, \ +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \ + AML_SEC_DEVICE3_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) static const mmap_region_t gxbb_mmap[] = { @@ -79,7 +79,7 @@ static const mmap_region_t gxbb_mmap[] = { /******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ -void gxbb_setup_page_tables(void) +void aml_setup_page_tables(void) { #if IMAGE_BL31 const mmap_region_t gxbb_bl_mmap[] = { @@ -105,11 +105,11 @@ void gxbb_setup_page_tables(void) ******************************************************************************/ static console_meson_t gxbb_console; -void gxbb_console_init(void) +void aml_console_init(void) { - int rc = console_meson_register(GXBB_UART0_AO_BASE, - GXBB_UART0_AO_CLK_IN_HZ, - GXBB_UART_BAUDRATE, + int rc = console_meson_register(AML_UART0_AO_BASE, + AML_UART0_AO_CLK_IN_HZ, + AML_UART_BAUDRATE, &gxbb_console); if (rc == 0) { /* @@ -131,13 +131,13 @@ unsigned int plat_get_syscnt_freq2(void) { uint32_t val; - val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val = mmio_read_32(AML_SYS_CPU_CFG7); val &= 0xFDFFFFFF; - mmio_write_32(GXBB_SYS_CPU_CFG7, val); + mmio_write_32(AML_SYS_CPU_CFG7, val); - val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val = mmio_read_32(AML_AO_TIMESTAMP_CNTL); val &= 0xFFFFFE00; - mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + mmio_write_32(AML_AO_TIMESTAMP_CNTL, val); - return GXBB_OSC24M_CLK_IN_HZ; + return AML_OSC24M_CLK_IN_HZ; } diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h new file mode 100644 index 00000000..2f6d1d2a --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_DEF_H +#define GXBB_DEF_H + +#include <lib/utils_def.h> + +/******************************************************************************* + * System oscillator + ******************************************************************************/ +#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ + +/******************************************************************************* + * Memory regions + ******************************************************************************/ +#define AML_NSDRAM0_BASE UL(0x01000000) +#define AML_NSDRAM0_SIZE UL(0x0F000000) + +#define AML_NSDRAM1_BASE UL(0x10000000) +#define AML_NSDRAM1_SIZE UL(0x00100000) + +#define BL31_BASE UL(0x10100000) +#define BL31_SIZE UL(0x000C0000) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* Shared memory used for SMC services */ +#define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000) +#define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) + +#define AML_SEC_DEVICE0_BASE UL(0xC0000000) +#define AML_SEC_DEVICE0_SIZE UL(0x09000000) + +#define AML_SEC_DEVICE1_BASE UL(0xD0040000) +#define AML_SEC_DEVICE1_SIZE UL(0x00008000) + +#define AML_TZRAM_BASE UL(0xD9000000) +#define AML_TZRAM_SIZE UL(0x00014000) +/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ + +/* Mailboxes */ +#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) + +#define AML_TZROM_BASE UL(0xD9040000) +#define AML_TZROM_SIZE UL(0x00010000) + +#define AML_SEC_DEVICE2_BASE UL(0xDA000000) +#define AML_SEC_DEVICE2_SIZE UL(0x00200000) + +#define AML_SEC_DEVICE3_BASE UL(0xDA800000) +#define AML_SEC_DEVICE3_SIZE UL(0x00200000) + +/******************************************************************************* + * GIC-400 and interrupt handling related constants + ******************************************************************************/ +#define AML_GICD_BASE UL(0xC4301000) +#define AML_GICC_BASE UL(0xC4302000) + +#define IRQ_SEC_PHY_TIMER 29 + +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 + +/******************************************************************************* + * UART definitions + ******************************************************************************/ +#define AML_UART0_AO_BASE UL(0xC81004C0) +#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ +#define AML_UART_BAUDRATE U(115200) + +/******************************************************************************* + * Memory-mapped I/O Registers + ******************************************************************************/ +#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4) + +#define AML_SYS_CPU_CFG7 UL(0xC8834664) + +#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) + +#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) + +/******************************************************************************* + * System Monitor Call IDs and arguments + ******************************************************************************/ +#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) + +#define AML_SM_EFUSE_READ U(0x82000030) +#define AML_SM_EFUSE_USER_MAX U(0x82000033) + +#define AML_SM_JTAG_ON U(0x82000040) +#define AML_SM_JTAG_OFF U(0x82000041) + +#define AML_JTAG_STATE_ON U(0) +#define AML_JTAG_STATE_OFF U(1) + +#define AML_JTAG_M3_AO U(0) +#define AML_JTAG_M3_EE U(1) +#define AML_JTAG_A53_AO U(2) +#define AML_JTAG_A53_EE U(3) + +#endif /* GXBB_DEF_H */ diff --git a/plat/meson/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c index 59b9436f..48bff7ba 100644 --- a/plat/meson/gxbb/gxbb_pm.c +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -1,23 +1,21 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <assert.h> -#include <errno.h> - -#include <platform_def.h> - #include <arch_helpers.h> +#include <assert.h> #include <common/debug.h> #include <drivers/arm/gicv2.h> #include <drivers/console.h> +#include <errno.h> #include <lib/mmio.h> #include <lib/psci/psci.h> #include <plat/common/platform.h> +#include <platform_def.h> -#include "gxbb_private.h" +#include "aml_private.h" #define SCPI_POWER_ON 0 #define SCPI_POWER_RETENTION 1 @@ -31,8 +29,8 @@ static volatile uint32_t gxbb_cpu0_go; static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + unsigned int core = plat_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); @@ -42,7 +40,7 @@ static void __dead2 gxbb_system_reset(void) { INFO("BL31: PSCI_SYSTEM_RESET\n"); - uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3); NOTICE("BL31: Reboot reason: 0x%x\n", status); @@ -50,9 +48,9 @@ static void __dead2 gxbb_system_reset(void) console_flush(); - mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + mmio_write_32(AML_AO_RTI_STATUS_REG3, status); - int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); @@ -69,7 +67,7 @@ static void __dead2 gxbb_system_off(void) { INFO("BL31: PSCI_SYSTEM_OFF\n"); - unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + unsigned int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); @@ -86,10 +84,10 @@ static void __dead2 gxbb_system_off(void) static int32_t gxbb_pwr_domain_on(u_register_t mpidr) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); gxbb_cpu0_go = 1; @@ -103,8 +101,8 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) } gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); - scpi_set_css_power_state(mpidr, - SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); dmbsy(); sev(); @@ -113,12 +111,12 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { gxbb_cpu0_go = 0; flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); dsb(); @@ -132,8 +130,8 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); + unsigned int core = plat_calc_core_pos(mpidr); + uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4); mmio_write_32(addr, 0xFFFFFFFF); flush_dcache_range(addr, sizeof(uint32_t)); @@ -141,20 +139,20 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) gicv2_cpuif_disable(); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) + if (core == AML_PRIMARY_CPU) return; - scpi_set_css_power_state(mpidr, - SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); } static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: CPU0 entering wait loop...\n"); while (gxbb_cpu0_go == 0) diff --git a/plat/meson/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h index da4aedde..a5cbe78e 100644 --- a/plat/meson/gxbb/include/platform_def.h +++ b/plat/amlogic/gxbb/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ #define PLATFORM_LINKER_ARCH aarch64 /* Special value used to verify platform parameters from BL2 to BL31 */ -#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) +#define AML_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) #define PLATFORM_STACK_SIZE UL(0x1000) @@ -25,7 +25,7 @@ #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT -#define GXBB_PRIMARY_CPU U(0) +#define AML_PRIMARY_CPU U(0) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk new file mode 100644 index 00000000..59c4f3d6 --- /dev/null +++ b/plat/amlogic/gxbb/platform.mk @@ -0,0 +1,74 @@ +# +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/xlat_tables_v2/xlat_tables.mk + +AML_PLAT := plat/amlogic +AML_PLAT_SOC := ${AML_PLAT}/${PLAT} +AML_PLAT_COMMON := ${AML_PLAT}/common + +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -I${AML_PLAT_SOC}/include \ + -I${AML_PLAT_COMMON}/include + +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + drivers/amlogic/console/aarch64/meson_console.S \ + ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ + ${AML_PLAT_SOC}/gxbb_pm.c \ + ${AML_PLAT_SOC}/gxbb_common.c \ + ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ + ${AML_PLAT_COMMON}/aml_efuse.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ + ${XLAT_TABLES_LIB_SRCS} \ + ${GIC_SOURCES} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_826319 := 1 +ERRATA_A53_835769 := 1 +ERRATA_A53_836870 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Verify build config +# ------------------- + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: ${PLAT} needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on ${PLAT}) +endif diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index b1da7942..f581dd13 100644 --- a/plat/meson/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -6,14 +6,14 @@ #include <assert.h> #include <common/bl_common.h> -#include <drivers/arm/gicv2.h> #include <common/interrupt_props.h> -#include <plat/common/platform.h> -#include <platform_def.h> +#include <drivers/arm/gicv2.h> #include <lib/mmio.h> #include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <plat/common/platform.h> +#include <platform_def.h> -#include "gxl_private.h" +#include "aml_private.h" /* * Placeholder variables for copying the arguments that have been passed to @@ -69,7 +69,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, struct gxl_bl31_param *from_bl2; /* Initialize the console to provide early debug support */ - gxbb_console_init(); + aml_console_init(); /* Check that params passed from BL2 are not NULL. */ from_bl2 = (struct gxl_bl31_param *) arg0; @@ -96,22 +96,22 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - gxbb_setup_page_tables(); + aml_setup_page_tables(); enable_mmu_el3(0); } static inline bool gxl_scp_ready(void) { - return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT)); + return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT)); } static inline void gxl_scp_boot(void) { - scpi_upload_scp_fw(bl30_image_info.image_base, - bl30_image_info.image_size, 0); - scpi_upload_scp_fw(bl301_image_info.image_base, - bl301_image_info.image_size, 1); + aml_scpi_upload_scp_fw(bl30_image_info.image_base, + bl30_image_info.image_size, 0); + aml_scpi_upload_scp_fw(bl301_image_info.image_base, + bl301_image_info.image_size, 1); while (!gxl_scp_ready()) ; } @@ -119,7 +119,7 @@ static inline void gxl_scp_boot(void) /******************************************************************************* * GICv2 driver setup information ******************************************************************************/ -static const interrupt_prop_t gxbb_interrupt_props[] = { +static const interrupt_prop_t gxl_interrupt_props[] = { INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, @@ -140,23 +140,23 @@ static const interrupt_prop_t gxbb_interrupt_props[] = { GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), }; -static const gicv2_driver_data_t gxbb_gic_data = { - .gicd_base = GXBB_GICD_BASE, - .gicc_base = GXBB_GICC_BASE, - .interrupt_props = gxbb_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), +static const gicv2_driver_data_t gxl_gic_data = { + .gicd_base = AML_GICD_BASE, + .gicc_base = AML_GICC_BASE, + .interrupt_props = gxl_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props), }; void bl31_platform_setup(void) { - mhu_secure_init(); + aml_mhu_secure_init(); - gicv2_driver_init(&gxbb_gic_data); + gicv2_driver_init(&gxl_gic_data); gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); gxl_scp_boot(); - gxbb_thermal_unknown(); + aml_thermal_unknown(); } diff --git a/plat/meson/gxbb/gxbb_common.c b/plat/amlogic/gxl/gxl_common.c index 0ca15e86..46868853 100644 --- a/plat/meson/gxbb/gxbb_common.c +++ b/plat/amlogic/gxl/gxl_common.c @@ -1,54 +1,52 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> -#include <stdint.h> - -#include <platform_def.h> - #include <bl31/interrupt_mgmt.h> #include <common/bl_common.h> #include <common/debug.h> #include <common/ep_info.h> -#include <drivers/meson/meson_console.h> #include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables_v2.h> +#include <meson_console.h> +#include <platform_def.h> +#include <stdint.h> /******************************************************************************* * Platform memory map regions ******************************************************************************/ -#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ - GXBB_NSDRAM0_SIZE, \ +#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ + AML_NSDRAM0_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ - GXBB_NSDRAM1_SIZE, \ +#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \ + AML_NSDRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ - GXBB_SEC_DEVICE0_SIZE, \ +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ + AML_SEC_DEVICE0_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ - GXBB_SEC_DEVICE1_SIZE, \ +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ + AML_SEC_DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ - GXBB_TZRAM_SIZE, \ +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ - GXBB_SEC_DEVICE2_SIZE, \ +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ + AML_SEC_DEVICE2_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ - GXBB_SEC_DEVICE3_SIZE, \ +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \ + AML_SEC_DEVICE3_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -static const mmap_region_t gxbb_mmap[] = { +static const mmap_region_t gxl_mmap[] = { MAP_NSDRAM0, MAP_NSDRAM1, MAP_SEC_DEVICE0, @@ -81,10 +79,10 @@ static const mmap_region_t gxbb_mmap[] = { /******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ -void gxbb_setup_page_tables(void) +void aml_setup_page_tables(void) { #if IMAGE_BL31 - const mmap_region_t gxbb_bl_mmap[] = { + const mmap_region_t gxl_bl_mmap[] = { MAP_BL31, MAP_BL_CODE, MAP_BL_RO_DATA, @@ -95,9 +93,9 @@ void gxbb_setup_page_tables(void) }; #endif - mmap_add(gxbb_bl_mmap); + mmap_add(gxl_bl_mmap); - mmap_add(gxbb_mmap); + mmap_add(gxl_mmap); init_xlat_tables(); } @@ -105,14 +103,14 @@ void gxbb_setup_page_tables(void) /******************************************************************************* * Function that sets up the console ******************************************************************************/ -static console_meson_t gxbb_console; +static console_meson_t gxl_console; -void gxbb_console_init(void) +void aml_console_init(void) { - int rc = console_meson_register(GXBB_UART0_AO_BASE, - GXBB_UART0_AO_CLK_IN_HZ, - GXBB_UART_BAUDRATE, - &gxbb_console); + int rc = console_meson_register(AML_UART0_AO_BASE, + AML_UART0_AO_CLK_IN_HZ, + AML_UART_BAUDRATE, + &gxl_console); if (rc == 0) { /* * The crash console doesn't use the multi console API, it uses @@ -122,7 +120,7 @@ void gxbb_console_init(void) panic(); } - console_set_scope(&gxbb_console.console, + console_set_scope(&gxl_console.console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); } @@ -133,13 +131,13 @@ unsigned int plat_get_syscnt_freq2(void) { uint32_t val; - val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val = mmio_read_32(AML_SYS_CPU_CFG7); val &= 0xFDFFFFFF; - mmio_write_32(GXBB_SYS_CPU_CFG7, val); + mmio_write_32(AML_SYS_CPU_CFG7, val); - val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val = mmio_read_32(AML_AO_TIMESTAMP_CNTL); val &= 0xFFFFFE00; - mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + mmio_write_32(AML_AO_TIMESTAMP_CNTL, val); - return GXBB_OSC24M_CLK_IN_HZ; + return AML_OSC24M_CLK_IN_HZ; } diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h new file mode 100644 index 00000000..6f49ed2b --- /dev/null +++ b/plat/amlogic/gxl/gxl_def.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXL_DEF_H +#define GXL_DEF_H + +#include <lib/utils_def.h> + +/******************************************************************************* + * System oscillator + ******************************************************************************/ +#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ + +/******************************************************************************* + * Memory regions + ******************************************************************************/ +#define AML_NSDRAM0_BASE UL(0x01000000) +#define AML_NSDRAM0_SIZE UL(0x0F000000) + +#define AML_NSDRAM1_BASE UL(0x10000000) +#define AML_NSDRAM1_SIZE UL(0x00100000) + +#define BL31_BASE UL(0x05100000) +#define BL31_SIZE UL(0x000C0000) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* Shared memory used for SMC services */ +#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000) +#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) + +#define AML_SEC_DEVICE0_BASE UL(0xC0000000) +#define AML_SEC_DEVICE0_SIZE UL(0x09000000) + +#define AML_SEC_DEVICE1_BASE UL(0xD0040000) +#define AML_SEC_DEVICE1_SIZE UL(0x00008000) + +#define AML_TZRAM_BASE UL(0xD9000000) +#define AML_TZRAM_SIZE UL(0x00014000) +/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ + +/* Mailboxes */ +#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) + +// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) +// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * +// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + +#define AML_TZROM_BASE UL(0xD9040000) +#define AML_TZROM_SIZE UL(0x00010000) + +#define AML_SEC_DEVICE2_BASE UL(0xDA000000) +#define AML_SEC_DEVICE2_SIZE UL(0x00200000) + +#define AML_SEC_DEVICE3_BASE UL(0xDA800000) +#define AML_SEC_DEVICE3_SIZE UL(0x00200000) + +/******************************************************************************* + * GIC-400 and interrupt handling related constants + ******************************************************************************/ +#define AML_GICD_BASE UL(0xC4301000) +#define AML_GICC_BASE UL(0xC4302000) + +#define IRQ_SEC_PHY_TIMER 29 + +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 + +/******************************************************************************* + * UART definitions + ******************************************************************************/ +#define AML_UART0_AO_BASE UL(0xC81004C0) +#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ +#define AML_UART_BAUDRATE U(115200) + +/******************************************************************************* + * Memory-mapped I/O Registers + ******************************************************************************/ +#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4) + +#define AML_SYS_CPU_CFG7 UL(0xC8834664) + +#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) +#define AML_AO_RTI_SCP_STAT UL(0xDA10023C) +#define AML_AO_RTI_SCP_READY_OFF U(0x14) +#define AML_A0_RTI_SCP_READY_MASK U(3) +#define AML_AO_RTI_SCP_IS_READY(v) \ + ((((v) >> AML_AO_RTI_SCP_READY_OFF) & \ + AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK) + +#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) + +/******************************************************************************* + * System Monitor Call IDs and arguments + ******************************************************************************/ +#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) + +#define AML_SM_EFUSE_READ U(0x82000030) +#define AML_SM_EFUSE_USER_MAX U(0x82000033) + +#define AML_SM_JTAG_ON U(0x82000040) +#define AML_SM_JTAG_OFF U(0x82000041) + +#define AML_JTAG_STATE_ON U(0) +#define AML_JTAG_STATE_OFF U(1) + +#define AML_JTAG_M3_AO U(0) +#define AML_JTAG_M3_EE U(1) +#define AML_JTAG_A53_AO U(2) +#define AML_JTAG_A53_EE U(3) + +#endif /* GXL_DEF_H */ diff --git a/plat/meson/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c index 4a5d26e9..433140b7 100644 --- a/plat/meson/gxl/gxl_pm.c +++ b/plat/amlogic/gxl/gxl_pm.c @@ -6,16 +6,16 @@ #include <arch_helpers.h> #include <assert.h> -#include <drivers/console.h> #include <common/debug.h> -#include <errno.h> #include <drivers/arm/gicv2.h> +#include <drivers/console.h> +#include <errno.h> #include <lib/mmio.h> +#include <lib/psci/psci.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <lib/psci/psci.h> -#include "gxl_private.h" +#include "aml_private.h" #define SCPI_POWER_ON 0 #define SCPI_POWER_RETENTION 1 @@ -24,31 +24,31 @@ #define SCPI_SYSTEM_SHUTDOWN 0 #define SCPI_SYSTEM_REBOOT 1 -static uintptr_t gxbb_sec_entrypoint; -static volatile uint32_t gxbb_cpu0_go; +static uintptr_t gxl_sec_entrypoint; +static volatile uint32_t gxl_cpu0_go; static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + unsigned int core = plat_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); } static void gxl_pm_reset(u_register_t mpidr) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8; + unsigned int core = plat_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; mmio_write_32(cpu_mailbox_addr, 0); } -static void __dead2 gxbb_system_reset(void) +static void __dead2 gxl_system_reset(void) { INFO("BL31: PSCI_SYSTEM_RESET\n"); u_register_t mpidr = read_mpidr_el1(); - uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3); int ret; NOTICE("BL31: Reboot reason: 0x%x\n", status); @@ -57,9 +57,9 @@ static void __dead2 gxbb_system_reset(void) console_flush(); - mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + mmio_write_32(AML_AO_RTI_STATUS_REG3, status); - ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); @@ -74,14 +74,14 @@ static void __dead2 gxbb_system_reset(void) panic(); } -static void __dead2 gxbb_system_off(void) +static void __dead2 gxl_system_off(void) { INFO("BL31: PSCI_SYSTEM_OFF\n"); u_register_t mpidr = read_mpidr_el1(); int ret; - ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); @@ -97,17 +97,17 @@ static void __dead2 gxbb_system_off(void) panic(); } -static int32_t gxbb_pwr_domain_on(u_register_t mpidr) +static int32_t gxl_pwr_domain_on(u_register_t mpidr) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); - gxbb_cpu0_go = 1; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, - sizeof(gxbb_cpu0_go)); + gxl_cpu0_go = 1; + flush_dcache_range((uintptr_t)&gxl_cpu0_go, + sizeof(gxl_cpu0_go)); dsb(); isb(); @@ -116,26 +116,26 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } - gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint); - scpi_set_css_power_state(mpidr, - SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + gxl_pm_set_reset_addr(mpidr, gxl_sec_entrypoint); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); dmbsy(); sev(); return PSCI_E_SUCCESS; } -static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) +static void gxl_pwr_domain_on_finish(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); - if (core == GXBB_PRIMARY_CPU) { - gxbb_cpu0_go = 0; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, - sizeof(gxbb_cpu0_go)); + if (core == AML_PRIMARY_CPU) { + gxl_cpu0_go = 0; + flush_dcache_range((uintptr_t)&gxl_cpu0_go, + sizeof(gxl_cpu0_go)); dsb(); isb(); } @@ -144,32 +144,32 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) gicv2_cpuif_enable(); } -static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) +static void gxl_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); gicv2_cpuif_disable(); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) + if (core == AML_PRIMARY_CPU) return; - scpi_set_css_power_state(mpidr, - SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); } -static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t +static void __dead2 gxl_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: CPU0 entering wait loop...\n"); - while (gxbb_cpu0_go == 0) + while (gxl_cpu0_go == 0) wfe(); VERBOSE("BL31: CPU0 resumed.\n"); @@ -181,7 +181,7 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t * In order to avoid an assert, mmu has to be disabled. */ disable_mmu_el3(); - ((void(*)(void))gxbb_sec_entrypoint)(); + ((void(*)(void))gxl_sec_entrypoint)(); } dsbsy(); @@ -195,20 +195,20 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t /******************************************************************************* * Platform handlers and setup function. ******************************************************************************/ -static const plat_psci_ops_t gxbb_ops = { - .pwr_domain_on = gxbb_pwr_domain_on, - .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, - .pwr_domain_off = gxbb_pwr_domain_off, - .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, - .system_off = gxbb_system_off, - .system_reset = gxbb_system_reset, +static const plat_psci_ops_t gxl_ops = { + .pwr_domain_on = gxl_pwr_domain_on, + .pwr_domain_on_finish = gxl_pwr_domain_on_finish, + .pwr_domain_off = gxl_pwr_domain_off, + .pwr_domain_pwr_down_wfi = gxl_pwr_domain_pwr_down_wfi, + .system_off = gxl_system_off, + .system_reset = gxl_system_reset, }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { - gxbb_sec_entrypoint = sec_entrypoint; - *psci_ops = &gxbb_ops; - gxbb_cpu0_go = 0; + gxl_sec_entrypoint = sec_entrypoint; + *psci_ops = &gxl_ops; + gxl_cpu0_go = 0; return 0; } diff --git a/plat/meson/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h index b32ec56d..ec64d685 100644 --- a/plat/meson/gxl/include/platform_def.h +++ b/plat/amlogic/gxl/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,9 +15,6 @@ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 -/* Special value used to verify platform parameters from BL2 to BL31 */ -#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) - #define PLATFORM_STACK_SIZE UL(0x1000) #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) @@ -25,7 +22,7 @@ #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT -#define GXBB_PRIMARY_CPU U(0) +#define AML_PRIMARY_CPU U(0) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk new file mode 100644 index 00000000..80c991ce --- /dev/null +++ b/plat/amlogic/gxl/platform.mk @@ -0,0 +1,90 @@ +# +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/xlat_tables_v2/xlat_tables.mk + +AML_PLAT := plat/amlogic +AML_PLAT_SOC := ${AML_PLAT}/${PLAT} +AML_PLAT_COMMON := ${AML_PLAT}/common + +DOIMAGEPATH ?= tools/amlogic +DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage + +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -I${AML_PLAT_SOC}/include \ + -I${AML_PLAT_COMMON}/include + +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + drivers/amlogic/console/aarch64/meson_console.S \ + ${AML_PLAT_SOC}/gxl_bl31_setup.c \ + ${AML_PLAT_SOC}/gxl_pm.c \ + ${AML_PLAT_SOC}/gxl_common.c \ + ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ + ${AML_PLAT_COMMON}/aml_efuse.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ + drivers/amlogic/crypto/sha_dma.c \ + ${XLAT_TABLES_LIB_SRCS} \ + ${GIC_SOURCES} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_855873 := 1 +ERRATA_A53_819472 := 1 +ERRATA_A53_824069 := 1 +ERRATA_A53_827319 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Verify build config +# ------------------- + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: ${PLAT} needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on ${PLAT}) +endif + +all: ${BUILD_PLAT}/bl31.img +distclean realclean clean: cleanimage + +cleanimage: + ${Q}${MAKE} -C ${DOIMAGEPATH} clean + +${DOIMAGETOOL}: + ${Q}${MAKE} -C ${DOIMAGEPATH} + +${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} + ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img + diff --git a/plat/meson/gxbb/gxbb_def.h b/plat/meson/gxbb/gxbb_def.h deleted file mode 100644 index 3e27097c..00000000 --- a/plat/meson/gxbb/gxbb_def.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_DEF_H -#define GXBB_DEF_H - -#include <lib/utils_def.h> - -/******************************************************************************* - * System oscillator - ******************************************************************************/ -#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ - -/******************************************************************************* - * Memory regions - ******************************************************************************/ -#define GXBB_NSDRAM0_BASE UL(0x01000000) -#define GXBB_NSDRAM0_SIZE UL(0x0F000000) - -#define GXBB_NSDRAM1_BASE UL(0x10000000) -#define GXBB_NSDRAM1_SIZE UL(0x00100000) - -#define BL31_BASE UL(0x10100000) -#define BL31_SIZE UL(0x000C0000) -#define BL31_LIMIT (BL31_BASE + BL31_SIZE) - -/* Shared memory used for SMC services */ -#define GXBB_SHARE_MEM_INPUT_BASE UL(0x100FE000) -#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) - -#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) -#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) - -#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) -#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) - -#define GXBB_TZRAM_BASE UL(0xD9000000) -#define GXBB_TZRAM_SIZE UL(0x00014000) -/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ - -/* Mailboxes */ -#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) -#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) -#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) - -#define GXBB_TZROM_BASE UL(0xD9040000) -#define GXBB_TZROM_SIZE UL(0x00010000) - -#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) -#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) - -#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) -#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) - -/******************************************************************************* - * GIC-400 and interrupt handling related constants - ******************************************************************************/ -#define GXBB_GICD_BASE UL(0xC4301000) -#define GXBB_GICC_BASE UL(0xC4302000) - -#define IRQ_SEC_PHY_TIMER 29 - -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 - -/******************************************************************************* - * UART definitions - ******************************************************************************/ -#define GXBB_UART0_AO_BASE UL(0xC81004C0) -#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ -#define GXBB_UART_BAUDRATE U(115200) - -/******************************************************************************* - * Memory-mapped I/O Registers - ******************************************************************************/ -#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) - -#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) - -#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) - -#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) -#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) -#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) -#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) -#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) - -/******************************************************************************* - * System Monitor Call IDs and arguments - ******************************************************************************/ -#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) -#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) - -#define GXBB_SM_EFUSE_READ U(0x82000030) -#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) - -#define GXBB_SM_JTAG_ON U(0x82000040) -#define GXBB_SM_JTAG_OFF U(0x82000041) - -#define GXBB_JTAG_STATE_ON U(0) -#define GXBB_JTAG_STATE_OFF U(1) - -#define GXBB_JTAG_M3_AO U(0) -#define GXBB_JTAG_M3_EE U(1) -#define GXBB_JTAG_A53_AO U(2) -#define GXBB_JTAG_A53_EE U(3) - -#endif /* GXBB_DEF_H */ diff --git a/plat/meson/gxbb/gxbb_efuse.c b/plat/meson/gxbb/gxbb_efuse.c deleted file mode 100644 index edea5426..00000000 --- a/plat/meson/gxbb/gxbb_efuse.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include "gxbb_private.h" - -#define EFUSE_BASE 0x140 -#define EFUSE_SIZE 0xC0 - -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) -{ - if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) - return 0; - - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); -} - -uint64_t gxbb_efuse_user_max(void) -{ - return EFUSE_SIZE; -} diff --git a/plat/meson/gxbb/gxbb_mhu.c b/plat/meson/gxbb/gxbb_mhu.c deleted file mode 100644 index 903ef411..00000000 --- a/plat/meson/gxbb/gxbb_mhu.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <platform_def.h> - -#include <lib/bakery_lock.h> -#include <lib/mmio.h> - -static DEFINE_BAKERY_LOCK(mhu_lock); - -void mhu_secure_message_start(void) -{ - bakery_lock_get(&mhu_lock); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -void mhu_secure_message_send(uint32_t msg) -{ - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - uint32_t val; - - do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); - } while (val == 0); - - return val; -} - -void mhu_secure_message_end(void) -{ - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); - - bakery_lock_release(&mhu_lock); -} - -void mhu_secure_init(void) -{ - bakery_lock_init(&mhu_lock); - - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); -} diff --git a/plat/meson/gxbb/gxbb_private.h b/plat/meson/gxbb/gxbb_private.h deleted file mode 100644 index 910a42c1..00000000 --- a/plat/meson/gxbb/gxbb_private.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H - -#include <stdint.h> - -/* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); - -/* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); - -/* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); - -/* Peripherals */ -void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); - -#endif /* GXBB_PRIVATE_H */ diff --git a/plat/meson/gxbb/gxbb_scpi.c b/plat/meson/gxbb/gxbb_scpi.c deleted file mode 100644 index 83eeda29..00000000 --- a/plat/meson/gxbb/gxbb_scpi.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <string.h> - -#include <platform_def.h> - -#include <lib/mmio.h> -#include <plat/common/platform.h> - -#include "gxbb_private.h" - -#define SIZE_SHIFT 20 -#define SIZE_MASK 0x1FF - -/* - * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. - */ -#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 -#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 - -#define SCPI_CMD_JTAG_SET_STATE 0xC0 -#define SCPI_CMD_EFUSE_READ 0xC2 - -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) -{ - return command | (size << SIZE_SHIFT); -} - -void scpi_secure_message_send(uint32_t command, uint32_t size) -{ - mhu_secure_message_send(scpi_cmd(command, size)); -} - -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - response &= ~(SIZE_MASK << SIZE_SHIFT); - - if (size_out != NULL) - *size_out = size; - - if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state) -{ - uint32_t state = (mpidr & 0x0F) | /* CPU ID */ - ((mpidr & 0xF00) >> 4) | /* Cluster ID */ - (cpu_state << 8) | - (cluster_state << 12) | - (css_state << 16); - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_sys_power_state(uint64_t system_state) -{ - uint32_t *response; - size_t size; - - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); - - return *response; -} - -void scpi_jtag_set_state(uint32_t state, uint8_t select) -{ - assert(state <= GXBB_JTAG_STATE_OFF); - - if (select > GXBB_JTAG_A53_EE) { - WARN("BL31: Invalid JTAG select (0x%x).\n", select); - return; - } - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, - (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) -{ - uint32_t *response; - size_t resp_size; - - if (size > 0x1FC) - return 0; - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); - - /* - * response[0] is the size of the response message. - * response[1 ... N] are the contents. - */ - if (*response != 0) - memcpy(dst, response + 1, *response); - - return *response; -} - -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) -{ - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} diff --git a/plat/meson/gxbb/gxbb_sip_svc.c b/plat/meson/gxbb/gxbb_sip_svc.c deleted file mode 100644 index 63c7dba1..00000000 --- a/plat/meson/gxbb/gxbb_sip_svc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include <platform_def.h> - -#include <common/debug.h> -#include <common/runtime_svc.h> -#include <lib/mmio.h> - -#include "gxbb_private.h" - -/******************************************************************************* - * This function is responsible for handling all SiP calls - ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, - u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, - void *cookie, void *handle, - u_register_t flags) -{ - switch (smc_fid) { - - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); - - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); - - case GXBB_SM_EFUSE_READ: - { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); - - SMC_RET1(handle, ret); - } - case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); - - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); - SMC_RET1(handle, 0); - - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); - SMC_RET1(handle, 0); - - default: - ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); - break; - } - - SMC_RET1(handle, SMC_UNK); -} - -DECLARE_RT_SVC( - gxbb_sip_handler, - - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - gxbb_sip_handler -); diff --git a/plat/meson/gxbb/gxbb_topology.c b/plat/meson/gxbb/gxbb_topology.c deleted file mode 100644 index eec2d34d..00000000 --- a/plat/meson/gxbb/gxbb_topology.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include <platform_def.h> - -#include <arch.h> - -#include "gxbb_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return plat_gxbb_calc_core_pos(mpidr); -} diff --git a/plat/meson/gxbb/include/plat_macros.S b/plat/meson/gxbb/include/plat_macros.S deleted file mode 100644 index c721c21b..00000000 --- a/plat/meson/gxbb/include/plat_macros.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include <drivers/arm/gicv2.h> -#include <platform_def.h> - -.section .rodata.gic_reg_name, "aS" - -gicc_regs: - .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" -gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" -newline: - .asciz "\n" -spacer: - .asciz ":\t\t0x" - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant GIC and CCI registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - - /* GICC registers */ - - mov_imm x17, GXBB_GICC_BASE - - adr x6, gicc_regs - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] - bl str_in_crash_buf_print - - /* GICD registers */ - - mov_imm x16, GXBB_GICD_BASE - - add x7, x16, #GICD_ISPENDR - adr x4, gicd_pend_reg - bl asm_print_str - -gicd_ispendr_loop: - sub x4, x7, x16 - cmp x4, #0x280 - b.eq exit_print_gic_regs - bl asm_print_hex - - adr x4, spacer - bl asm_print_str - - ldr x4, [x7], #8 - bl asm_print_hex - - adr x4, newline - bl asm_print_str - b gicd_ispendr_loop -exit_print_gic_regs: - - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/meson/gxbb/platform.mk b/plat/meson/gxbb/platform.mk deleted file mode 100644 index 9e65040b..00000000 --- a/plat/meson/gxbb/platform.mk +++ /dev/null @@ -1,69 +0,0 @@ -# -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include lib/xlat_tables_v2/xlat_tables.mk - -PLAT_INCLUDES := -Iplat/meson/gxbb/include - -GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c - -PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \ - plat/meson/gxbb/gxbb_common.c \ - plat/meson/gxbb/gxbb_topology.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/meson/gxbb/aarch64/gxbb_helpers.S \ - plat/meson/gxbb/gxbb_bl31_setup.c \ - plat/meson/gxbb/gxbb_efuse.c \ - plat/meson/gxbb/gxbb_mhu.c \ - plat/meson/gxbb/gxbb_pm.c \ - plat/meson/gxbb/gxbb_scpi.c \ - plat/meson/gxbb/gxbb_sip_svc.c \ - plat/meson/gxbb/gxbb_thermal.c \ - ${GXBB_GIC_SOURCES} - -# Tune compiler for Cortex-A53 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else - TF_CFLAGS_aarch64 += -mtune=cortex-a53 -endif - -# Build config flags -# ------------------ - -# Enable all errata workarounds for Cortex-A53 -ERRATA_A53_826319 := 1 -ERRATA_A53_835769 := 1 -ERRATA_A53_836870 := 1 -ERRATA_A53_843419 := 1 -ERRATA_A53_855873 := 1 - -WORKAROUND_CVE_2017_5715 := 0 - -# Have different sections for code and rodata -SEPARATE_CODE_AND_RODATA := 1 - -# Use Coherent memory -USE_COHERENT_MEM := 1 - -# Verify build config -# ------------------- - -ifneq (${RESET_TO_BL31}, 0) - $(error Error: gxbb needs RESET_TO_BL31=0) -endif - -ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on gxbb) -endif diff --git a/plat/meson/gxl/aarch64/gxl_helpers.S b/plat/meson/gxl/aarch64/gxl_helpers.S deleted file mode 100644 index 760d6c46..00000000 --- a/plat/meson/gxl/aarch64/gxl_helpers.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> -#include <assert_macros.S> -#include <platform_def.h> - - .globl plat_crash_console_flush - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl platform_mem_init - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_my_core_pos(void); - * ----------------------------------------------------- - */ -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos -endfunc plat_my_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); - * ----------------------------------------------------- - */ -func plat_gxbb_calc_core_pos - and x0, x0, #MPIDR_CPU_MASK - ret -endfunc plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary(void); - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* --------------------------------------------- - * void platform_mem_init(void); - * --------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE - b console_meson_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE - b console_meson_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE - b console_meson_core_flush -endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - ret -endfunc plat_reset_handler diff --git a/plat/meson/gxl/gxl_def.h b/plat/meson/gxl/gxl_def.h deleted file mode 100644 index 089fa8db..00000000 --- a/plat/meson/gxl/gxl_def.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_DEF_H -#define GXBB_DEF_H - -#include <lib/utils_def.h> - -/******************************************************************************* - * System oscillator - ******************************************************************************/ -#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ - -/******************************************************************************* - * Memory regions - ******************************************************************************/ -#define GXBB_NSDRAM0_BASE UL(0x01000000) -#define GXBB_NSDRAM0_SIZE UL(0x0F000000) - -#define GXBB_NSDRAM1_BASE UL(0x10000000) -#define GXBB_NSDRAM1_SIZE UL(0x00100000) - -#define BL31_BASE UL(0x05100000) -#define BL31_SIZE UL(0x000C0000) -#define BL31_LIMIT (BL31_BASE + BL31_SIZE) - -/* Shared memory used for SMC services */ -#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000) -#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) - -#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) -#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) - -#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) -#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) - -#define GXBB_TZRAM_BASE UL(0xD9000000) -#define GXBB_TZRAM_SIZE UL(0x00014000) -/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ - -/* Mailboxes */ -#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) -#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) -#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) - -// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) -// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * -// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * - -#define GXBB_TZROM_BASE UL(0xD9040000) -#define GXBB_TZROM_SIZE UL(0x00010000) - -#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) -#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) - -#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) -#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) - -/******************************************************************************* - * GIC-400 and interrupt handling related constants - ******************************************************************************/ -#define GXBB_GICD_BASE UL(0xC4301000) -#define GXBB_GICC_BASE UL(0xC4302000) - -#define IRQ_SEC_PHY_TIMER 29 - -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 - -/******************************************************************************* - * UART definitions - ******************************************************************************/ -#define GXBB_UART0_AO_BASE UL(0xC81004C0) -#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ -#define GXBB_UART_BAUDRATE U(115200) - -/******************************************************************************* - * Memory-mapped I/O Registers - ******************************************************************************/ -#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) - -#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) - -#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) -#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C) -#define GXBB_AO_RTI_SCP_READY_OFF U(0x14) -#define GXBB_A0_RTI_SCP_READY_MASK U(3) -#define GXBB_AO_RTI_SCP_IS_READY(v) \ - ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \ - GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK) - -#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) -#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) -#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) -#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) -#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) - -/******************************************************************************* - * System Monitor Call IDs and arguments - ******************************************************************************/ -#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) -#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) - -#define GXBB_SM_EFUSE_READ U(0x82000030) -#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) - -#define GXBB_SM_JTAG_ON U(0x82000040) -#define GXBB_SM_JTAG_OFF U(0x82000041) - -#define GXBB_JTAG_STATE_ON U(0) -#define GXBB_JTAG_STATE_OFF U(1) - -#define GXBB_JTAG_M3_AO U(0) -#define GXBB_JTAG_M3_EE U(1) -#define GXBB_JTAG_A53_AO U(2) -#define GXBB_JTAG_A53_EE U(3) - -#endif /* GXBB_DEF_H */ diff --git a/plat/meson/gxl/gxl_efuse.c b/plat/meson/gxl/gxl_efuse.c deleted file mode 100644 index b17d1b8e..00000000 --- a/plat/meson/gxl/gxl_efuse.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include "gxl_private.h" - -#define EFUSE_BASE 0x140 -#define EFUSE_SIZE 0xC0 - -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) -{ - if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) - return 0; - - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); -} - -uint64_t gxbb_efuse_user_max(void) -{ - return EFUSE_SIZE; -} diff --git a/plat/meson/gxl/gxl_mhu.c b/plat/meson/gxl/gxl_mhu.c deleted file mode 100644 index 4c1d5b60..00000000 --- a/plat/meson/gxl/gxl_mhu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <lib/bakery_lock.h> -#include <lib/mmio.h> -#include <platform_def.h> - -static DEFINE_BAKERY_LOCK(mhu_lock); - -void mhu_secure_message_start(void) -{ - bakery_lock_get(&mhu_lock); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -void mhu_secure_message_send(uint32_t msg) -{ - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - uint32_t val; - - do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); - } while (val == 0); - - return val; -} - -void mhu_secure_message_end(void) -{ - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); - - bakery_lock_release(&mhu_lock); -} - -void mhu_secure_init(void) -{ - bakery_lock_init(&mhu_lock); - - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); -} diff --git a/plat/meson/gxl/gxl_private.h b/plat/meson/gxl/gxl_private.h deleted file mode 100644 index 913cbf65..00000000 --- a/plat/meson/gxl/gxl_private.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H - -#include <stdint.h> -#include <stddef.h> - -/* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); - -/* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); - -/* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); - -/* Peripherals */ -void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); - -#endif /* GXBB_PRIVATE_H */ diff --git a/plat/meson/gxl/gxl_scpi.c b/plat/meson/gxl/gxl_scpi.c deleted file mode 100644 index 13d65243..00000000 --- a/plat/meson/gxl/gxl_scpi.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <lib/mmio.h> -#include <plat/common/platform.h> -#include <platform_def.h> -#include <string.h> -#include <crypto/sha_dma.h> - -#include "gxl_private.h" - -#define SIZE_SHIFT 20 -#define SIZE_MASK 0x1FF -#define SIZE_FWBLK 0x200UL - -/* - * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. - */ -#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 -#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 - -#define SCPI_CMD_JTAG_SET_STATE 0xC0 -#define SCPI_CMD_EFUSE_READ 0xC2 - -#define SCPI_CMD_COPY_FW 0xd4 -#define SCPI_CMD_SET_FW_ADDR 0xd3 -#define SCPI_CMD_FW_SIZE 0xd2 - -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) -{ - return command | (size << SIZE_SHIFT); -} - -static void scpi_secure_message_send(uint32_t command, uint32_t size) -{ - mhu_secure_message_send(scpi_cmd(command, size)); -} - -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - response &= ~(SIZE_MASK << SIZE_SHIFT); - - if (size_out != NULL) - *size_out = size; - - if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state) -{ - uint32_t state = (mpidr & 0x0F) | /* CPU ID */ - ((mpidr & 0xF00) >> 4) | /* Cluster ID */ - (cpu_state << 8) | - (cluster_state << 12) | - (css_state << 16); - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_sys_power_state(uint64_t system_state) -{ - uint32_t *response; - size_t size; - - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); - - return *response; -} - -void scpi_jtag_set_state(uint32_t state, uint8_t select) -{ - assert(state <= GXBB_JTAG_STATE_OFF); - - if (select > GXBB_JTAG_A53_EE) { - WARN("BL31: Invalid JTAG select (0x%x).\n", select); - return; - } - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, - (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) -{ - uint32_t *response; - size_t resp_size; - - if (size > 0x1FC) - return 0; - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); - - /* - * response[0] is the size of the response message. - * response[1 ... N] are the contents. - */ - if (*response != 0) - memcpy(dst, response + 1, *response); - - return *response; -} - -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) -{ - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -static inline void scpi_copy_scp_data(uint8_t *data, size_t len) -{ - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - size_t sz; - - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); - - for (sz = 0; sz < len; sz += SIZE_FWBLK) { - memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); - mhu_secure_message_send(SCPI_CMD_COPY_FW); - } -} - -static inline void scpi_set_scp_addr(uint64_t addr, size_t len) -{ - volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - - /* - * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as - * non cachable - */ - *dst = addr; - scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); - mhu_secure_message_wait(); - - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); -} - -static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) -{ - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - - memcpy(dst, hash, len); - mhu_secure_message_send(0xd0); - mhu_secure_message_send(0xd1); - mhu_secure_message_send(0xd5); - mhu_secure_message_end(); -} - -/** - * Upload a FW to SCP. - * - * @param addr: firmware data address - * @param size: size of firmware - * @param send: If set, actually copy the firmware in SCP memory otherwise only - * send the firmware address. - */ -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) -{ - struct asd_ctx ctx; - - asd_sha_init(&ctx, ASM_SHA256); - asd_sha_update(&ctx, (void *)addr, size); - asd_sha_finalize(&ctx); - - mhu_secure_message_start(); - if (send == 0) - scpi_set_scp_addr(addr, size); - else - scpi_copy_scp_data((void *)addr, size); - - scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); -} diff --git a/plat/meson/gxl/gxl_thermal.c b/plat/meson/gxl/gxl_thermal.c deleted file mode 100644 index 3af1c6dc..00000000 --- a/plat/meson/gxl/gxl_thermal.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include "gxl_private.h" - -static int32_t modules_initialized = -1; - -/******************************************************************************* - * Unknown commands related to something thermal-related - ******************************************************************************/ -void gxbb_thermal_unknown(void) -{ - uint16_t ret; - - if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); - modules_initialized = ret; - } - - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ -} diff --git a/plat/meson/gxl/platform.mk b/plat/meson/gxl/platform.mk deleted file mode 100644 index a788e963..00000000 --- a/plat/meson/gxl/platform.mk +++ /dev/null @@ -1,87 +0,0 @@ -# -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include lib/xlat_tables_v2/xlat_tables.mk - -DOIMAGEPATH ?= tools/meson -DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage - -PLAT_INCLUDES := -Iinclude/drivers/meson/ \ - -Iinclude/drivers/meson/gxl \ - -Iplat/meson/gxl/include - -GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c - -PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \ - plat/meson/gxl/gxl_common.c \ - plat/meson/gxl/gxl_topology.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/meson/gxl/aarch64/gxl_helpers.S \ - plat/meson/gxl/gxl_bl31_setup.c \ - plat/meson/gxl/gxl_efuse.c \ - plat/meson/gxl/gxl_mhu.c \ - plat/meson/gxl/gxl_pm.c \ - plat/meson/gxl/gxl_scpi.c \ - plat/meson/gxl/gxl_sip_svc.c \ - plat/meson/gxl/gxl_thermal.c \ - drivers/meson/gxl/crypto/sha_dma.c \ - ${GXBB_GIC_SOURCES} - -# Tune compiler for Cortex-A53 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else - TF_CFLAGS_aarch64 += -mtune=cortex-a53 -endif - -# Build config flags -# ------------------ - -# Enable all errata workarounds for Cortex-A53 -ERRATA_A53_855873 := 1 -ERRATA_A53_819472 := 1 -ERRATA_A53_824069 := 1 -ERRATA_A53_827319 := 1 - -WORKAROUND_CVE_2017_5715 := 0 - -# Have different sections for code and rodata -SEPARATE_CODE_AND_RODATA := 1 - -# Use Coherent memory -USE_COHERENT_MEM := 1 - -# Verify build config -# ------------------- - -ifneq (${RESET_TO_BL31}, 0) - $(error Error: gxl needs RESET_TO_BL31=0) -endif - -ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on gxl) -endif - -all: ${BUILD_PLAT}/bl31.img -distclean realclean clean: cleanimage - -cleanimage: - ${Q}${MAKE} -C ${DOIMAGEPATH} clean - -${DOIMAGETOOL}: - ${Q}${MAKE} -C ${DOIMAGEPATH} - -${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} - ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img - diff --git a/tools/meson/Makefile b/tools/amlogic/Makefile index 1a1d1f81..1a1d1f81 100644 --- a/tools/meson/Makefile +++ b/tools/amlogic/Makefile diff --git a/tools/meson/doimage.c b/tools/amlogic/doimage.c index b304038d..b304038d 100644 --- a/tools/meson/doimage.c +++ b/tools/amlogic/doimage.c |