diff options
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 11 | ||||
| -rw-r--r-- | bl32/sp_min/aarch32/entrypoint.S | 11 | ||||
| -rw-r--r-- | docs/porting-guide.rst | 19 | ||||
| -rw-r--r-- | docs/user-guide.rst | 4 | ||||
| -rw-r--r-- | lib/xlat_tables/xlat_tables_private.h | 4 | ||||
| -rw-r--r-- | plat/common/aarch64/plat_common.c | 12 | ||||
| -rw-r--r-- | plat/common/aarch64/platform_helpers.S | 22 |
7 files changed, 57 insertions, 26 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 0d1077cb..58e8afbd 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -170,15 +170,12 @@ func bl31_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ - mov x0, #DISABLE_DCACHE - bl bl31_plat_enable_mmu - #if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_C_BIT - msr sctlr_el3, x0 - isb + mov x0, xzr +#else + mov x0, #DISABLE_DCACHE #endif + bl bl31_plat_enable_mmu bl psci_warmboot_entrypoint diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 87ef3f36..d6853cc4 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -298,20 +298,17 @@ func sp_min_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ +#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY + mov r0, #0 +#else mov r0, #DISABLE_DCACHE +#endif bl bl32_plat_enable_mmu #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r0 #endif -#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - ldcopr r0, SCTLR - orr r0, r0, #SCTLR_C_BIT - stcopr r0, SCTLR - isb -#endif - bl sp_min_warm_boot bl smc_get_next_ctx /* r0 points to `smc_ctx_t` */ diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index a737cf4e..5462cc1e 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -1997,6 +1997,25 @@ state. This function must return a pointer to the ``entry_point_info`` structure (that was copied during ``bl31_early_platform_setup()``) if the image exists. It should return NULL otherwise. +Function : bl31_plat_enable_mmu [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uint32_t + Return : void + +This function enables the MMU. The boot code calls this function with MMU and +caches disabled. This function should program necessary registers to enable +translation, and upon return, the MMU on the calling PE must be enabled. + +The function must honor flags passed in the first argument. These flags are +defined by the translation library, and can be found in the file +``include/lib/xlat_tables/xlat_mmu_helpers.h``. + +On DynamIQ systems, this function must not use stack while enabling MMU, which +is how the function in xlat table library version 2 is implementated. + Function : plat\_get\_syscnt\_freq2() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/user-guide.rst b/docs/user-guide.rst index a40615db..68a74edd 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -454,6 +454,10 @@ Common build options management operations. This option defaults to 0 and if it is enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of + translation library (xlat tables v2) must be used; version 1 of translation + library is not supported. + - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h index 50d6bd59..810c48e1 100644 --- a/lib/xlat_tables/xlat_tables_private.h +++ b/lib/xlat_tables/xlat_tables_private.h @@ -11,6 +11,10 @@ #include <platform_def.h> #include <xlat_tables_arch.h> +#if HW_ASSISTED_COHERENCY +#error xlat tables v2 must be used with HW_ASSISTED_COHERENCY +#endif + /* * If the platform hasn't defined a physical and a virtual address space size * default to ADDR_SPACE_SIZE. diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index 409ae55a..5f2972cc 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -18,8 +18,6 @@ * provide typical implementations that may be re-used by multiple * platforms but may also be overridden by a platform if required. */ -#pragma weak bl31_plat_enable_mmu -#pragma weak bl32_plat_enable_mmu #pragma weak bl31_plat_runtime_setup #if !ERROR_DEPRECATED #pragma weak plat_get_syscnt_freq2 @@ -33,16 +31,6 @@ #pragma weak plat_ea_handler -void bl31_plat_enable_mmu(uint32_t flags) -{ - enable_mmu_el3(flags); -} - -void bl32_plat_enable_mmu(uint32_t flags) -{ - enable_mmu_el1(flags); -} - void bl31_plat_runtime_setup(void) { #if MULTI_CONSOLE_API diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 033a12f8..a413f5fd 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -17,6 +17,8 @@ .weak plat_disable_acp .weak bl1_plat_prepare_exit .weak plat_panic_handler + .weak bl31_plat_enable_mmu + .weak bl32_plat_enable_mmu #if !ENABLE_PLAT_COMPAT .globl platform_get_core_pos @@ -164,3 +166,23 @@ func plat_panic_handler wfi b plat_panic_handler endfunc plat_panic_handler + + /* ----------------------------------------------------- + * void bl31_plat_enable_mmu(uint32_t flags); + * + * Enable MMU in BL31. + * ----------------------------------------------------- + */ +func bl31_plat_enable_mmu + b enable_mmu_direct_el3 +endfunc bl31_plat_enable_mmu + + /* ----------------------------------------------------- + * void bl32_plat_enable_mmu(uint32_t flags); + * + * Enable MMU in BL32. + * ----------------------------------------------------- + */ +func bl32_plat_enable_mmu + b enable_mmu_direct_el1 +endfunc bl32_plat_enable_mmu |