diff options
| -rw-r--r-- | include/arch/aarch64/arch.h | 8 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 6 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 13 |
3 files changed, 27 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 913b62c5..e4147d7e 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -219,6 +219,13 @@ #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ +#define ID_AA64PFR1_EL1_MTE_SHIFT U(8) +#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) + +#define MTE_UNIMPLEMENTED ULL(0) +#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ +#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ + /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) #define ID_PFR1_VIRTEXT_MASK U(0xf) @@ -278,6 +285,7 @@ /* SCR definitions */ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) +#define SCR_ATA_BIT (U(1) << 26) #define SCR_FIEN_BIT (U(1) << 21) #define SCR_API_BIT (U(1) << 17) #define SCR_APK_BIT (U(1) << 16) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 1129b8e4..2f29f487 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -54,4 +54,10 @@ static inline bool is_armv8_5_bti_present(void) ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED; } +static inline unsigned int get_armv8_5_mte_support(void) +{ + return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & + ID_AA64PFR1_EL1_MTE_MASK); +} + #endif /* ARCH_FEATURES_H */ diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 89d7ed68..05ba5ed6 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -12,6 +12,7 @@ #include <arch.h> #include <arch_helpers.h> +#include <arch_features.h> #include <bl31/interrupt_mgmt.h> #include <common/bl_common.h> #include <context.h> @@ -136,6 +137,18 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) scr_el3 |= SCR_API_BIT | SCR_APK_BIT; #endif /* !CTX_INCLUDE_PAUTH_REGS */ + unsigned int mte = get_armv8_5_mte_support(); + + /* + * Enable MTE support unilaterally for normal world if the CPU supports + * it. + */ + if (mte != MTE_UNIMPLEMENTED) { + if (security_state == NON_SECURE) { + scr_el3 |= SCR_ATA_BIT; + } + } + #ifdef IMAGE_BL31 /* * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as |