diff options
| -rw-r--r-- | docs/plat/ti-k3.rst | 55 | ||||
| -rw-r--r-- | maintainers.rst | 11 | ||||
| -rw-r--r-- | plat/ti/k3/common/k3_bl31_setup.c | 65 | ||||
| -rw-r--r-- | plat/ti/k3/common/plat_common.mk | 37 | ||||
| -rw-r--r-- | plat/ti/k3/include/plat_macros.S | 21 | ||||
| -rw-r--r-- | plat/ti/k3/include/platform_def.h | 58 | ||||
| -rw-r--r-- | plat/ti/k3/platform.mk | 12 | ||||
| -rw-r--r-- | readme.rst | 1 |
8 files changed, 260 insertions, 0 deletions
diff --git a/docs/plat/ti-k3.rst b/docs/plat/ti-k3.rst new file mode 100644 index 00000000..6515c644 --- /dev/null +++ b/docs/plat/ti-k3.rst @@ -0,0 +1,55 @@ +Trusted Firmware-A for Texas Instruments K3 SoCs +================================================ + +Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Texas Instruments K3 SoCs. + +Boot Flow +--------- + +R5(U-Boot) --> TF-A BL31 --> BL32(OP-TEE) --> TF-A BL31 --> BL33(U-Boot) --> Linux + \ + Optional direct to Linux boot + \ + --> BL33(Linux) + +Texas Instruments K3 SoCs contain an R5 processor used as the boot master, it +loads the needed images for A53 startup, because of this we do not need BL1 or +BL2 TF-A stages. + +Build Instructions +------------------ + +https://github.com/ARM-software/arm-trusted-firmware.git + +TF-A: + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all + +OP-TEE: + +.. code:: shell + + make ARCH=arm CROSS_COMPILE64=aarch64-linux-gnu- PLATFORM=k3 CFG_ARM64_core=y all + +R5 U-Boot: + +.. code:: shell + + make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig + make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- SYSFW=<path to SYSFW> + +A53 U-Boot: + +.. code:: shell + + make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig + make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path> TEE=<path> + +Deploy Images +------------- + +.. code:: shell + + cp tiboot3.bin tispl.bin u-boot.img /sdcard/boot/ diff --git a/maintainers.rst b/maintainers.rst index 81c30c07..96ff0e06 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -132,6 +132,16 @@ Files: - plat/rockchip/\* +Texas Instruments platform sub-maintainer +----------------------------------------- + +Andrew F. Davis (afd@ti.com, `glneo`_) + +Files: + +- docs/plat/ti-k3.rst +- plat/ti/\* + UniPhier platform sub-maintainer -------------------------------- @@ -167,6 +177,7 @@ Etienne Carriere (etienne.carriere@linaro.org, `etienne-lms`_) .. _masahir0y: https://github.com/masahir0y .. _mtk09422: https://github.com/mtk09422 .. _TonyXie06: https://github.com/TonyXie06 +.. _glneo: https://github.com/glneo .. _sivadur: https://github.com/sivadur .. _rockchip-linux: https://github.com/rockchip-linux .. _etienne-lms: https://github.com/etienne-lms diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c new file mode 100644 index 00000000..c9133c19 --- /dev/null +++ b/plat/ti/k3/common/k3_bl31_setup.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <debug.h> +#include <platform_def.h> +#include <string.h> + +/******************************************************************************* + * Perform any BL3-1 early platform setup, such as console init and deciding on + * memory layout. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + /* There are no parameters from BL2 if BL31 is a reset vector */ + assert(from_bl2 == NULL); + assert(plat_params_from_bl2 == NULL); +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + bl31_early_platform_setup((void *)arg0, (void *)arg1); +} + +void bl31_plat_arch_setup(void) +{ + /* TODO: Initialize the MMU tables */ +} + +void bl31_platform_setup(void) +{ + /* TODO: Initialize the GIC CPU and distributor interfaces */ +} + +void platform_mem_init(void) +{ + /* Do nothing for now... */ +} + +/* + * Empty function to prevent the console from being uninitialized after BL33 is + * started and allow us to see messages from BL31. + */ +void bl31_plat_runtime_setup(void) +{ +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image + * for the security state specified. BL3-3 corresponds to the non-secure + * image type while BL3-2 corresponds to the secure image type. A NULL + * pointer is returned if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + return NULL; +} diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk new file mode 100644 index 00000000..8ba2e84f --- /dev/null +++ b/plat/ti/k3/common/plat_common.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# We don't use BL1 or BL2, so BL31 is the first image to execute +RESET_TO_BL31 := 1 +# Only one core starts up at first +COLD_BOOT_SINGLE_CPU := 1 +# We can choose where a core starts executing +PROGRAMMABLE_RESET_ADDRESS:= 1 + +# System coherency is managed in hardware +HW_ASSISTED_COHERENCY := 1 +USE_COHERENT_MEM := 0 + +ERROR_DEPRECATED := 1 +ENABLE_PLAT_COMPAT := 0 + +# A53 erratum for SoC. (enable them all) +ERRATA_A53_826319 := 1 +ERRATA_A53_835769 := 1 +ERRATA_A53_836870 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 + +PLAT_INCLUDES += \ + -I${PLAT_PATH}/include \ + -Iinclude/plat/arm/common/ \ + -Iinclude/plat/arm/common/aarch64/ \ + +PLAT_BL_COMMON_SOURCES += \ + lib/cpus/aarch64/cortex_a53.S \ + +BL31_SOURCES += \ + ${PLAT_PATH}/common/k3_bl31_setup.c \ diff --git a/plat/ti/k3/include/plat_macros.S b/plat/ti/k3/include/plat_macros.S new file mode 100644 index 00000000..96d1cd20 --- /dev/null +++ b/plat/ti/k3/include/plat_macros.S @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* STUB */ + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h new file mode 100644 index 00000000..eaeef5a2 --- /dev/null +++ b/plat/ti/k3/include/platform_def.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include <arch.h> +#include <board_def.h> +#include <common_def.h> + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stack */ +#if IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#else +#define PLATFORM_STACK_SIZE 0x1000 +#endif + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 + +/******************************************************************************* + * Memory layout constants + ******************************************************************************/ + +/* + * ARM-TF lives in SRAM, partition it here + */ + +#define SHARED_RAM_BASE BL31_LIMIT +#define SHARED_RAM_SIZE 0x00001000 + +/* + * BL3-1 specific defines. + * + * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. + */ +#define BL31_BASE SEC_SRAM_BASE +#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL31_LIMIT + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk new file mode 100644 index 00000000..613942c9 --- /dev/null +++ b/plat/ti/k3/platform.mk @@ -0,0 +1,12 @@ +# +# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +PLAT_PATH := plat/ti/k3 + +include ${PLAT_PATH}/common/plat_common.mk + +# modify BUILD_PLAT to point to board specific build directory +BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE} @@ -183,6 +183,7 @@ This release also contains the following platform support: - Raspberry Pi 3 board - RockChip RK3328, RK3368 and RK3399 SoCs - Socionext UniPhier SoC family +- Texas Instruments K3 SoCs - Xilinx Zynq UltraScale + MPSoC Still to come |