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-rw-r--r--plat/freescale/imx8mq/gpc.c2
-rw-r--r--plat/freescale/imx8mq/imx8m_bl31_setup.c4
2 files changed, 6 insertions, 0 deletions
diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c
index 66323487..26755c0a 100644
--- a/plat/freescale/imx8mq/gpc.c
+++ b/plat/freescale/imx8mq/gpc.c
@@ -443,6 +443,8 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on)
uint32_t val;
uintptr_t reg;
+ return;
+
/*
* PCIE1 and PCIE2 share the same reset signal, if we power down
* PCIE2, PCIE1 will be hold in reset too.
diff --git a/plat/freescale/imx8mq/imx8m_bl31_setup.c b/plat/freescale/imx8mq/imx8m_bl31_setup.c
index 132deb37..21b7fdf9 100644
--- a/plat/freescale/imx8mq/imx8m_bl31_setup.c
+++ b/plat/freescale/imx8mq/imx8m_bl31_setup.c
@@ -177,6 +177,10 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
mmio_write_32(0x32df004c, 0x0);
mmio_write_32(0x32df0050, 0x0);
+ mmio_write_32(0x303a00ec, 0x0000ffff);
+ /* Power up VPU, DISP, GPU etc */
+ mmio_write_32(0x303a00f8, 0x3fef);
+
#if DEBUG_CONSOLE
console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE);