diff options
25 files changed, 132 insertions, 37 deletions
@@ -151,6 +151,7 @@ TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ -ffreestanding -fno-builtin -Wall -std=gnu99 \ -Os -ffunction-sections -fdata-sections +LDFLAGS += $(LDFLAGS_$(ARCH)) LDFLAGS += --fatal-warnings -O1 LDFLAGS += --gc-sections diff --git a/bl1/aarch32/bl1_arch_setup.c b/bl1/aarch32/bl1_arch_setup.c index 23a65648..ce04aaab 100644 --- a/bl1/aarch32/bl1_arch_setup.c +++ b/bl1/aarch32/bl1_arch_setup.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include "../bl1_private.h" /******************************************************************************* * TODO: Function that does the first bit of architectural setup. diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c index cbf5cb69..6623dfc4 100644 --- a/bl1/aarch32/bl1_context_mgmt.c +++ b/bl1/aarch32/bl1_context_mgmt.c @@ -11,6 +11,7 @@ #include <debug.h> #include <platform.h> #include <smcc_helpers.h> +#include "../bl1_private.h" /* * Following arrays will be used for context management. @@ -26,13 +27,13 @@ static void *bl1_next_cpu_context_ptr; static void *bl1_next_smc_context_ptr; /* Following functions are used for SMC context handling */ -void *smc_get_ctx(int security_state) +void *smc_get_ctx(unsigned int security_state) { assert(sec_state_is_valid(security_state)); return &bl1_smc_context[security_state]; } -void smc_set_next_ctx(int security_state) +void smc_set_next_ctx(unsigned int security_state) { assert(sec_state_is_valid(security_state)); bl1_next_smc_context_ptr = &bl1_smc_context[security_state]; diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index a7a45225..624bd80f 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -6,6 +6,7 @@ #include <arch.h> #include <arch_helpers.h> +#include "../bl1_private.h" /******************************************************************************* * Function that does the first bit of architectural setup that affects diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c index 2c7fe070..b9304dcf 100644 --- a/bl1/aarch64/bl1_context_mgmt.c +++ b/bl1/aarch64/bl1_context_mgmt.c @@ -10,6 +10,7 @@ #include <context_mgmt.h> #include <debug.h> #include <platform.h> +#include "../bl1_private.h" /* * Following array will be used for context management. diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 85eee1ad..8dfc55f6 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -52,8 +52,6 @@ static unsigned int sec_exec_image_id = INVALID_IMAGE_ID; /* Authentication status of each image. */ extern unsigned int auth_img_flags[]; -void cm_set_next_context(void *cpu_context); - /******************************************************************************* * Top level handler for servicing FWU SMCs. ******************************************************************************/ diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c index d27c0233..1c83cbe1 100644 --- a/bl32/sp_min/sp_min_main.c +++ b/bl32/sp_min/sp_min_main.c @@ -34,13 +34,13 @@ static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; /****************************************************************************** * Define the smcc helper library API's *****************************************************************************/ -void *smc_get_ctx(int security_state) +void *smc_get_ctx(unsigned int security_state) { assert(security_state == NON_SECURE); return &sp_min_smc_context[plat_my_core_pos()]; } -void smc_set_next_ctx(int security_state) +void smc_set_next_ctx(unsigned int security_state) { assert(security_state == NON_SECURE); /* SP_MIN stores only non secure smc context. Nothing to do here */ diff --git a/docs/change-log.md b/docs/change-log.md index 74edf988..4eb1254b 100644 --- a/docs/change-log.md +++ b/docs/change-log.md @@ -1090,7 +1090,7 @@ _Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ [OP-TEE Dispatcher]: optee-dispatcher.md [Power Domain Topology Design]: psci-pd-tree.md -[TF Image Terminology]: https://github.com/ARM-software/arm-trusted-firmware/wiki/Trusted-Firmware-Image-Terminology +[TF Image Terminology]: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology [Authentication Framework]: auth-framework.md [Firmware Update]: firmware-update.md [TF Reset Design]: reset-design.md diff --git a/docs/firmware-update.md b/docs/firmware-update.md index e3eec26f..b04586e3 100644 --- a/docs/firmware-update.md +++ b/docs/firmware-update.md @@ -384,5 +384,5 @@ _Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved._ [Porting Guide]: ./porting-guide.md [Auth Framework]: ./auth-framework.md [Trusted Board Boot]: ./trusted-board-boot.md -[TF Image Terminology]: https://github.com/ARM-software/arm-trusted-firmware/wiki/Trusted-Firmware-Image-Terminology +[TF Image Terminology]: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology [UUID]: https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace" diff --git a/drivers/delay_timer/delay_timer.c b/drivers/delay_timer/delay_timer.c index 403c60fd..43f5af7b 100644 --- a/drivers/delay_timer/delay_timer.c +++ b/drivers/delay_timer/delay_timer.c @@ -19,10 +19,10 @@ static const timer_ops_t *ops; ***********************************************************/ void udelay(uint32_t usec) { - assert(ops != 0 && + assert(ops != NULL && (ops->clk_mult != 0) && (ops->clk_div != 0) && - (ops->get_timer_value != 0)); + (ops->get_timer_value != NULL)); uint32_t start, delta, total_delta; @@ -57,10 +57,10 @@ void mdelay(uint32_t msec) ***********************************************************/ void timer_init(const timer_ops_t *ops_ptr) { - assert(ops_ptr != 0 && + assert(ops_ptr != NULL && (ops_ptr->clk_mult != 0) && (ops_ptr->clk_div != 0) && - (ops_ptr->get_timer_value != 0)); + (ops_ptr->get_timer_value != NULL)); ops = ops_ptr; } diff --git a/drivers/delay_timer/generic_delay_timer.c b/drivers/delay_timer/generic_delay_timer.c index 6a9d3147..8a36c8ab 100644 --- a/drivers/delay_timer/generic_delay_timer.c +++ b/drivers/delay_timer/generic_delay_timer.c @@ -9,6 +9,7 @@ #include <bl_common.h> #include <debug.h> #include <delay_timer.h> +#include <generic_delay_timer.h> #include <platform.h> /* Ticks elapsed in one second by a signal of 1 MHz */ diff --git a/drivers/io/io_dummy.c b/drivers/io/io_dummy.c index a06aeb9c..d4020e3a 100644 --- a/drivers/io/io_dummy.c +++ b/drivers/io/io_dummy.c @@ -7,6 +7,7 @@ #include <assert.h> #include <debug.h> #include <io_driver.h> +#include <io_dummy.h> #include <io_storage.h> #include <string.h> @@ -18,7 +19,7 @@ struct file_state { static struct file_state current_file = {0}; /* Identify the device type as dummy */ -io_type_t device_type_dummy(void) +static io_type_t device_type_dummy(void) { return IO_TYPE_DUMMY; } diff --git a/drivers/io/io_storage.c b/drivers/io/io_storage.c index fe654236..0918de0a 100644 --- a/drivers/io/io_storage.c +++ b/drivers/io/io_storage.c @@ -94,7 +94,7 @@ static void set_handle(uintptr_t *handle, io_entity_t *entity) static int find_first_entity(const io_entity_t *entity, unsigned int *index_out) { int result = -ENOENT; - for (int index = 0; index < MAX_IO_HANDLES; ++index) { + for (unsigned int index = 0; index < MAX_IO_HANDLES; ++index) { if (entity_map[index] == entity) { result = 0; *index_out = index; diff --git a/include/lib/aarch32/smcc_helpers.h b/include/lib/aarch32/smcc_helpers.h index 5fb5a964..1bc84381 100644 --- a/include/lib/aarch32/smcc_helpers.h +++ b/include/lib/aarch32/smcc_helpers.h @@ -144,10 +144,10 @@ CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); */ /* Get the pointer to `smc_ctx_t` corresponding to the security state. */ -void *smc_get_ctx(int security_state); +void *smc_get_ctx(unsigned int security_state); /* Set the next `smc_ctx_t` corresponding to the security state. */ -void smc_set_next_ctx(int security_state); +void smc_set_next_ctx(unsigned int security_state); /* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */ void *smc_get_next_ctx(void); diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 94798691..eb7a9534 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -86,6 +86,7 @@ static inline void cm_set_next_context(void *context) #else void *cm_get_next_context(void); +void cm_set_next_context(void *context); #endif /* AARCH32 */ #endif /* __CM_H__ */ diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index d369c6db..7a17f8f1 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -138,6 +138,26 @@ func check_errata_855873 b cpu_rev_var_hs endfunc check_errata_855873 +/* + * Errata workaround for Cortex A53 Errata #835769. + * This applies to revisions <= r0p4 of Cortex A53. + * This workaround is statically enabled at build time. + */ +func check_errata_835769 + mov x1, #0x04 + b cpu_rev_var_ls +endfunc check_errata_835769 + +/* + * Errata workaround for Cortex A53 Errata #843419. + * This applies to revisions <= r0p4 of Cortex A53. + * This workaround is statically enabled at build time. + */ +func check_errata_843419 + mov x1, #0x04 + b cpu_rev_var_ls +endfunc check_errata_843419 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A53. * Shall clobber: x0-x19 @@ -251,7 +271,9 @@ func cortex_a53_errata_report * checking functions of each errata. */ report_errata ERRATA_A53_826319, cortex_a53, 826319 + report_errata ERRATA_A53_835769, cortex_a53, 835769 report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint + report_errata ERRATA_A53_843419, cortex_a53, 843419 report_errata ERRATA_A53_855873, cortex_a53, 855873 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 9f1dea49..218a5482 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -37,11 +37,22 @@ $(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) # only to revision <= r0p2 of the Cortex A53 cpu. ERRATA_A53_826319 ?=0 +# Flag to apply erratum 835769 workaround at compile and link time. This +# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this +# workaround can lead the linker to create "*.stub" sections. +ERRATA_A53_835769 ?=0 + # Flag to apply erratum 836870 workaround during reset. This erratum applies # only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this # erratum workaround is enabled by default in hardware. ERRATA_A53_836870 ?=0 +# Flag to apply erratum 843419 workaround at link time. +# This erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this +# workaround could lead the linker to emit "*.stub" sections which are 4kB +# aligned. +ERRATA_A53_843419 ?=0 + # Flag to apply errata 855873 during reset. This errata applies to all # revisions of the Cortex A53 CPU, but this firmware workaround only works # for revisions r0p3 and higher. Earlier revisions are taken care @@ -84,10 +95,18 @@ ERRATA_A57_833471 ?=0 $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) +# Process ERRATA_A53_835769 flag +$(eval $(call assert_boolean,ERRATA_A53_835769)) +$(eval $(call add_define,ERRATA_A53_835769)) + # Process ERRATA_A53_836870 flag $(eval $(call assert_boolean,ERRATA_A53_836870)) $(eval $(call add_define,ERRATA_A53_836870)) +# Process ERRATA_A53_843419 flag +$(eval $(call assert_boolean,ERRATA_A53_843419)) +$(eval $(call add_define,ERRATA_A53_843419)) + # Process ERRATA_A53_855873 flag $(eval $(call assert_boolean,ERRATA_A53_855873)) $(eval $(call add_define,ERRATA_A53_855873)) @@ -123,3 +142,13 @@ $(eval $(call add_define,ERRATA_A57_829520)) # Process ERRATA_A57_833471 flag $(eval $(call assert_boolean,ERRATA_A57_833471)) $(eval $(call add_define,ERRATA_A57_833471)) + +# Errata build flags +ifneq (${ERRATA_A53_843419},0) +LDFLAGS_aarch64 += --fix-cortex-a53-843419 +endif + +ifneq (${ERRATA_A53_835769},0) +TF_CFLAGS_aarch64 += -mfix-cortex-a53-835769 +LDFLAGS_aarch64 += --fix-cortex-a53-835769 +endif diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index 1e1fc786..8d9f704a 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c @@ -72,7 +72,7 @@ void errata_print_msg(unsigned int status, const char *cpu, const char *id) const char *msg __unused; - assert(status >= 0 && status < ARRAY_SIZE(errata_status_str)); + assert(status < ARRAY_SIZE(errata_status_str)); assert(cpu); assert(id); diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c index f5237919..4a55248d 100644 --- a/lib/psci/psci_system_off.c +++ b/lib/psci/psci_system_off.c @@ -12,7 +12,7 @@ #include <platform.h> #include "psci_private.h" -void psci_system_off(void) +void __dead2 psci_system_off(void) { psci_print_power_domain_map(); @@ -31,7 +31,7 @@ void psci_system_off(void) /* This function does not return. We should never get here */ } -void psci_system_reset(void) +void __dead2 psci_system_reset(void) { psci_print_power_domain_map(); diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c index 17e7e6e0..c6fa10ee 100644 --- a/lib/xlat_tables/xlat_tables_common.c +++ b/lib/xlat_tables/xlat_tables_common.c @@ -23,9 +23,9 @@ #define LVL2_SPACER " " #define LVL3_SPACER " " #define get_level_spacer(level) \ - (((level) == 0) ? LVL0_SPACER : \ - (((level) == 1) ? LVL1_SPACER : \ - (((level) == 2) ? LVL2_SPACER : LVL3_SPACER))) + (((level) == U(0)) ? LVL0_SPACER : \ + (((level) == U(1)) ? LVL1_SPACER : \ + (((level) == U(2)) ? LVL2_SPACER : LVL3_SPACER))) #define debug_print(...) tf_printf(__VA_ARGS__) #else #define debug_print(...) ((void)0) @@ -36,7 +36,7 @@ static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] __aligned(XLAT_TABLE_SIZE) __section("xlat_table"); -static unsigned next_xlat; +static unsigned int next_xlat; static unsigned long long xlat_max_pa; static uintptr_t xlat_max_va; @@ -178,7 +178,7 @@ void mmap_add(const mmap_region_t *mm) } static uint64_t mmap_desc(mmap_attr_t attr, unsigned long long addr_pa, - int level) + unsigned int level) { uint64_t desc; int mem_type; @@ -309,7 +309,7 @@ static int mmap_region_attr(mmap_region_t *mm, uintptr_t base_va, static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, uintptr_t base_va, uint64_t *table, - int level) + unsigned int level) { assert(level >= XLAT_TABLE_LEVEL_MIN && level <= XLAT_TABLE_LEVEL_MAX); @@ -378,7 +378,7 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, } void init_xlation_table(uintptr_t base_va, uint64_t *table, - int level, uintptr_t *max_va, + unsigned int level, uintptr_t *max_va, unsigned long long *max_pa) { execute_never_mask = xlat_arch_get_xn_desc(xlat_arch_current_el()); diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h index 92078525..b5c3ac84 100644 --- a/lib/xlat_tables/xlat_tables_private.h +++ b/lib/xlat_tables/xlat_tables_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -77,7 +77,7 @@ int xlat_arch_current_el(void); uint64_t xlat_arch_get_xn_desc(int el); void init_xlation_table(uintptr_t base_va, uint64_t *table, - int level, uintptr_t *max_va, + unsigned int level, uintptr_t *max_va, unsigned long long *max_pa); #endif /* __XLAT_TABLES_PRIVATE_H__ */ diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S index 8d00a1a7..5e7f08e7 100644 --- a/plat/arm/board/juno/aarch64/juno_helpers.S +++ b/plat/arm/board/juno/aarch64/juno_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -266,6 +266,16 @@ endfunc plat_get_my_entrypoint * to AArch32 mode is then requested by writing into RMR_EL3. */ func juno_reset_to_aarch32_state + /* + * Invalidate all caches before the warm reset to AArch32 state. + * This is required on the Juno AArch32 boot flow because the L2 + * unified cache may contain code and data from when the processor + * was still executing in AArch64 state. This code only runs on + * the primary core, all other cores are powered down. + */ + mov x0, #DCISW + bl dcsw_op_all + emit_movw w0, BL32_BASE emit_movt w1, BL32_BASE /* opcode "bx r0" to branch using r0 in AArch32 mode */ diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c index 8f18531a..abceb0f5 100644 --- a/plat/arm/board/juno/juno_bl2_setup.c +++ b/plat/arm/board/juno/juno_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,4 +29,28 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) return err; } + +/* + * We need to override some of the platform functions when booting SP_MIN + * on Juno AArch32. + */ + +static unsigned int scp_boot_config; + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); + + /* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */ + VERBOSE("BL2: Saving SCP Boot config = 0x%x\n", scp_boot_config); + scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + + mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config); + VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config); +} #endif /* JUNO_AARCH32_EL3_RUNTIME */ diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 04cd6b33..b972d26a 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -56,6 +56,8 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ endif # Enable workarounds for selected Cortex-A53 and A57 errata. +ERRATA_A53_835769 := 1 +ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 ERRATA_A57_806969 := 0 ERRATA_A57_813419 := 1 diff --git a/plat/compat/plat_topology_compat.c b/plat/compat/plat_topology_compat.c index d22feee8..48d565c3 100644 --- a/plat/compat/plat_topology_compat.c +++ b/plat/compat/plat_topology_compat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -88,8 +88,8 @@ void sort_mpidr_by_cpu_idx(unsigned int aff_count, unsigned long mpidr_list[]) ******************************************************************************/ static unsigned int init_pwr_domain_tree_desc(unsigned long mpidr, unsigned int affmap_idx, - int cur_afflvl, - int tgt_afflvl) + unsigned int cur_afflvl, + unsigned int tgt_afflvl) { unsigned int ctr, aff_count; @@ -137,18 +137,20 @@ static unsigned int init_pwr_domain_tree_desc(unsigned long mpidr, ******************************************************************************/ const unsigned char *plat_get_power_domain_tree_desc(void) { - int afflvl, affmap_idx; + int afflvl; + unsigned int affmap_idx; /* * We assume that the platform allocates affinity instance ids from * 0 onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0 */ affmap_idx = 0; - for (afflvl = PLATFORM_MAX_AFFLVL; afflvl >= MPIDR_AFFLVL0; afflvl--) { + for (afflvl = (int) PLATFORM_MAX_AFFLVL; + afflvl >= (int) MPIDR_AFFLVL0; afflvl--) { affmap_idx = init_pwr_domain_tree_desc(FIRST_MPIDR, affmap_idx, PLATFORM_MAX_AFFLVL, - afflvl); + (unsigned int) afflvl); } assert(affmap_idx == (PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1)); |