diff options
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 3 | ||||
| -rw-r--r-- | plat/arm/board/common/board_common.mk | 6 | ||||
| -rw-r--r-- | plat/arm/board/fvp/aarch32/fvp_helpers.S | 115 | ||||
| -rw-r--r-- | plat/arm/board/fvp/fvp_common.c | 3 | ||||
| -rw-r--r-- | plat/arm/board/fvp/platform.mk | 10 | ||||
| -rw-r--r-- | plat/arm/common/aarch32/arm_helpers.S | 59 | ||||
| -rw-r--r-- | plat/arm/common/arm_common.c | 23 | ||||
| -rw-r--r-- | plat/arm/common/arm_common.mk | 53 | ||||
| -rw-r--r-- | plat/arm/common/arm_gicv3.c | 2 | ||||
| -rw-r--r-- | plat/common/aarch32/plat_common.c | 44 | ||||
| -rw-r--r-- | plat/common/aarch32/platform_helpers.S | 78 | ||||
| -rw-r--r-- | plat/common/aarch32/platform_mp_stack.S | 71 | ||||
| -rw-r--r-- | plat/common/plat_gicv3.c | 7 | ||||
| -rw-r--r-- | plat/compat/plat_compat.mk | 3 |
14 files changed, 449 insertions, 28 deletions
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 0b3e66b1..4a4dfd40 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -321,9 +321,12 @@ # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" #endif +/* BL32 is mandatory in AArch32 */ +#ifndef AARCH32 #ifdef SPD_none #undef BL32_BASE #endif /* SPD_none */ +#endif /******************************************************************************* * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index 3d5a985b..49136e68 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -31,8 +31,10 @@ PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ \ -Iinclude/plat/arm/board/common/drivers -PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/aarch64/pl011_console.S \ - plat/arm/board/common/aarch64/board_arm_helpers.S +PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S +ifeq (${ARCH}, aarch64) +PLAT_BL_COMMON_SOURCES += plat/arm/board/common/aarch64/board_arm_helpers.S +endif BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c diff --git a/plat/arm/board/fvp/aarch32/fvp_helpers.S b/plat/arm/board/fvp/aarch32/fvp_helpers.S new file mode 100644 index 00000000..373036c9 --- /dev/null +++ b/plat/arm/board/fvp/aarch32/fvp_helpers.S @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> +#include "../drivers/pwrc/fvp_pwrc.h" +#include "../fvp_def.h" + + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On FVP, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, read the mailbox and return the address it contains. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* --------------------------------------------------------------------- + * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC + * WakeRequest signal" then it is a warm boot. + * --------------------------------------------------------------------- + */ + ldcopr r2, MPIDR + ldr r1, =PWRC_BASE + str r2, [r1, #PSYSR_OFF] + ldr r2, [r1, #PSYSR_OFF] + ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH + cmp r2, #WKUP_PPONR + beq warm_reset + cmp r2, #WKUP_GICREQ + beq warm_reset + + /* Cold reset */ + mov r0, #0 + bx lr + +warm_reset: + /* --------------------------------------------------------------------- + * A mailbox is maintained in the trusted SRAM. It is flushed out of the + * caches after every update using normal memory so it is safe to read + * it here with SO attributes. + * --------------------------------------------------------------------- + */ + ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE + ldr r0, [r0] + cmp r0, #0 + beq _panic + bx lr + + /* --------------------------------------------------------------------- + * The power controller indicates this is a warm reset but the mailbox + * is empty. This should never happen! + * --------------------------------------------------------------------- + */ +_panic: + b _panic +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + ldcopr r0, MPIDR + ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + and r0, r1 + cmp r0, #FVP_PRIMARY_CPU + moveq r0, #1 + movne r0, #0 + bx lr +endfunc plat_is_my_cpu_primary diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 002cff67..fbbe34e6 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -121,6 +121,9 @@ const mmap_region_t plat_arm_mmap[] = { #endif #if IMAGE_BL32 const mmap_region_t plat_arm_mmap[] = { +#ifdef AARCH32 + ARM_MAP_SHARED_RAM, +#endif V2M_MAP_IOFPGA, MAP_DEVICE0, MAP_DEVICE1, diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 1ea98222..2865569a 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -69,6 +69,9 @@ FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ plat/common/plat_gicv2.c \ plat/arm/common/arm_gicv2.c else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY) + ifeq (${ARCH}, aarch32) + $(error "GICV3 Legacy driver not supported for AArch32 build") + endif FVP_GIC_SOURCES := drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ @@ -98,12 +101,15 @@ PLAT_INCLUDES := -Iplat/arm/board/fvp/include PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c -FVP_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a35.S \ +FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S + +ifeq (${ARCH}, aarch64) +FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a73.S +endif BL1_SOURCES += drivers/io/io_semihosting.c \ lib/semihosting/semihosting.c \ diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S new file mode 100644 index 00000000..08399137 --- /dev/null +++ b/plat/arm/common/aarch32/arm_helpers.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include <asm_macros.S> +#include <platform_def.h> + + .weak plat_arm_calc_core_pos + .weak plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_arm_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + ldcopr r0, MPIDR + b plat_arm_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) + * Helper function to calculate the core position. + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func plat_arm_calc_core_pos + and r1, r0, #MPIDR_CPU_MASK + and r0, r0, #MPIDR_CLUSTER_MASK + add r0, r1, r0, LSR #6 + bx lr +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 93355fe4..c53723d5 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -134,6 +134,7 @@ uint32_t arm_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ +#ifndef AARCH32 uint32_t arm_get_spsr_for_bl33_entry(void) { unsigned long el_status; @@ -154,6 +155,28 @@ uint32_t arm_get_spsr_for_bl33_entry(void) spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); return spsr; } +#else +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +uint32_t arm_get_spsr_for_bl33_entry(void) +{ + unsigned int hyp_status, mode, spsr; + + hyp_status = GET_VIRT_EXT(read_id_pfr1()); + + mode = (hyp_status) ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#endif /* AARCH32 */ /******************************************************************************* * Configures access to the system counter timer module. diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 03b9fe47..0b961ea7 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -28,23 +28,30 @@ # POSSIBILITY OF SUCH DAMAGE. # -# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted -# DRAM (if available) or the TZC secured area of DRAM. -# Trusted SRAM is the default. - -ARM_TSP_RAM_LOCATION := tsram -ifeq (${ARM_TSP_RAM_LOCATION}, tsram) - ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID -else ifeq (${ARM_TSP_RAM_LOCATION}, tdram) - ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID -else ifeq (${ARM_TSP_RAM_LOCATION}, dram) - ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID -else - $(error "Unsupported ARM_TSP_RAM_LOCATION value") -endif +ifeq (${ARCH}, aarch64) + # On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted + # DRAM (if available) or the TZC secured area of DRAM. + # Trusted SRAM is the default. + + ARM_TSP_RAM_LOCATION := tsram + ifeq (${ARM_TSP_RAM_LOCATION}, tsram) + ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID + else ifeq (${ARM_TSP_RAM_LOCATION}, tdram) + ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID + else ifeq (${ARM_TSP_RAM_LOCATION}, dram) + ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID + else + $(error "Unsupported ARM_TSP_RAM_LOCATION value") + endif -# Process flags -$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID)) + # Process flags + $(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID)) + + # Process ARM_BL31_IN_DRAM flag + ARM_BL31_IN_DRAM := 0 + $(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) + $(eval $(call add_define,ARM_BL31_IN_DRAM)) +endif # For the original power-state parameter format, the State-ID can be encoded # according to the recommended encoding or zero. This flag determines which @@ -83,7 +90,7 @@ $(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) $(eval $(call add_define,ARM_BL31_IN_DRAM)) # Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms -ENABLE_PSCI_STAT = 1 +ENABLE_PSCI_STAT := 1 # On ARM platforms, separate the code and read-only data sections to allow # mapping the former as executable and the latter as execute-never. @@ -91,15 +98,17 @@ SEPARATE_CODE_AND_RODATA := 1 PLAT_INCLUDES += -Iinclude/common/tbbr \ - -Iinclude/plat/arm/common \ - -Iinclude/plat/arm/common/aarch64 + -Iinclude/plat/arm/common +ifeq (${ARCH}, aarch64) +PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64 +endif PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \ - lib/xlat_tables/aarch64/xlat_tables.c \ - plat/arm/common/aarch64/arm_helpers.S \ + lib/xlat_tables/${ARCH}/xlat_tables.c \ + plat/arm/common/${ARCH}/arm_helpers.S \ plat/arm/common/arm_common.c \ - plat/common/aarch64/plat_common.c + plat/common/${ARCH}/plat_common.c BL1_SOURCES += drivers/arm/sp805/sp805.c \ drivers/io/io_fip.c \ diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index a20fd56f..ac309f2b 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -77,7 +77,7 @@ void plat_arm_gic_driver_init(void) * can use GIC system registers to manage interrupts and does * not need GIC interface base addresses to be configured. */ -#if IMAGE_BL31 +#if (AARCH32 && IMAGE_BL32) || (IMAGE_BL31 && !AARCH32) gicv3_driver_init(&arm_gic_data); #endif } diff --git a/plat/common/aarch32/plat_common.c b/plat/common/aarch32/plat_common.c new file mode 100644 index 00000000..a5b9535c --- /dev/null +++ b/plat/common/aarch32/plat_common.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <platform.h> +#include <xlat_tables.h> + +/* + * The following platform setup functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak bl32_plat_enable_mmu + +void bl32_plat_enable_mmu(uint32_t flags) +{ + enable_mmu_secure(flags); +} diff --git a/plat/common/aarch32/platform_helpers.S b/plat/common/aarch32/platform_helpers.S new file mode 100644 index 00000000..481dd68d --- /dev/null +++ b/plat/common/aarch32/platform_helpers.S @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <asm_macros.S> + + .weak plat_my_core_pos + .weak plat_reset_handler + .weak platform_mem_init + .weak plat_panic_handler + + /* ----------------------------------------------------- + * int plat_my_core_pos(void); + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func plat_my_core_pos + ldcopr r0, MPIDR + and r1, r0, #MPIDR_CPU_MASK + and r0, r0, #MPIDR_CLUSTER_MASK + add r0, r1, r0, LSR #6 + bx lr +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_reset_handler + bx lr +endfunc plat_reset_handler + + /* --------------------------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * --------------------------------------------------------------------- + */ +func platform_mem_init + bx lr +endfunc platform_mem_init + + /* ----------------------------------------------------- + * void plat_panic_handler(void) __dead2; + * Endless loop by default. + * ----------------------------------------------------- + */ +func plat_panic_handler + b plat_panic_handler +endfunc plat_panic_handler diff --git a/plat/common/aarch32/platform_mp_stack.S b/plat/common/aarch32/platform_mp_stack.S new file mode 100644 index 00000000..a0154369 --- /dev/null +++ b/plat/common/aarch32/platform_mp_stack.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + + .globl plat_get_my_stack + .globl plat_set_my_stack + + /* ----------------------------------------------------- + * uintptr_t plat_get_my_stack (u_register_t mpidr) + * + * For a given CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + mov r3, lr + get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + bx r3 +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For the current CPU, this function sets the stack + * pointer to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + mov r3, lr + get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + mov sp, r0 + bx r3 +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * Per-cpu stacks in normal memory. Each cpu gets a + * stack of PLATFORM_STACK_SIZE bytes. + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index 249caf8e..c961d629 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -186,6 +186,11 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, #pragma weak plat_ic_acknowledge_interrupt #pragma weak plat_ic_end_of_interrupt +/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ +#ifdef AARCH32 +#define IS_IN_EL1() IS_IN_SECURE() +#endif + /* * This function returns the highest priority pending interrupt at * the Interrupt controller diff --git a/plat/compat/plat_compat.mk b/plat/compat/plat_compat.mk index d9d50f6e..a1cdd809 100644 --- a/plat/compat/plat_compat.mk +++ b/plat/compat/plat_compat.mk @@ -33,6 +33,9 @@ ifeq (${PSCI_EXTENDED_STATE_ID}, 1) PSCI_EXTENDED_STATE_ID is not set") endif +ifneq (${ARCH}, aarch64) + $(error "PSCI Compatibility mode is only supported for AArch64 platforms") +endif PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S |