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| author | Imre Kis <imre.kis@arm.com> | 2019-07-18 14:30:03 +0200 |
|---|---|---|
| committer | Imre Kis <imre.kis@arm.com> | 2019-10-02 18:12:28 +0200 |
| commit | 6ad216dca5e388f9aa1518a20a81c836c7eb2d21 (patch) | |
| tree | bbd31955d0b50cb0d473a9d4f80a2de078f45d04 /include | |
| parent | 5f38b5362cff958225c6ad9b3d45a56b3d613fbf (diff) | |
Introducing support for Cortex-A65
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47
Signed-off-by: Imre Kis <imre.kis@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a65.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h new file mode 100644 index 00000000..0df34c9c --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65_H +#define CORTEX_A65_H + +#include <lib/utils_def.h> + +#define CORTEX_A65_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65_H */ |