From 6ad216dca5e388f9aa1518a20a81c836c7eb2d21 Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Thu, 18 Jul 2019 14:30:03 +0200 Subject: Introducing support for Cortex-A65 Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis --- include/lib/cpus/aarch64/cortex_a65.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 include/lib/cpus/aarch64/cortex_a65.h (limited to 'include') diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h new file mode 100644 index 00000000..0df34c9c --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65_H +#define CORTEX_A65_H + +#include + +#define CORTEX_A65_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65_H */ -- cgit v1.2.3