Add support for BL3-1 as a reset vector

This change adds optional reset vector support to BL3-1
which means BL3-1 entry point can detect cold/warm boot,
initialise primary cpu, set up cci and mail box.

When using BL3-1 as a reset vector it is assumed that
the BL3-1 platform code can determine the location of
the BL3-2 images, or load them as there are no parameters
that can be passed to BL3-1 at reset.

It also fixes the incorrect initialisation of mailbox
registers on the FVP platform

This feature can be enabled by building the code with
make variable RESET_TO_BL31 set as 1

Fixes ARM-software/TF-issues#133
Fixes ARM-software/TF-issues#20

Change-Id: I4e23939b1c518614b899f549f1e8d412538ee570

1 files changed, 40 insertions, 34 deletions

diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index 7259601d..cbbaeadd 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -59,6 +59,15 @@ func bl1_entrypoint
 	 */
 	bl	cpu_reset_handler
 
+	/* -------------------------------
+	 * Enable the instruction cache.
+	 * -------------------------------
+	 */
+	mrs	x0, sctlr_el3
+	orr	x0, x0, #SCTLR_I_BIT
+	msr	sctlr_el3, x0
+	isb
+
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
 	 * ---------------------------------------------
@@ -90,16 +99,6 @@ func bl1_entrypoint
 	msr	cptr_el3, x0
 
 	/* ---------------------------------------------
-	 * Enable the instruction cache.
-	 * ---------------------------------------------
-	 */
-	mrs	x0, sctlr_el3
-	orr	x0, x0, #SCTLR_I_BIT
-	msr	sctlr_el3, x0
-	isb
-
-_wait_for_entrypoint:
-	/* ---------------------------------------------
 	 * Find the type of reset and jump to handler
 	 * if present. If the handler is null then it is
 	 * a cold boot. The primary cpu will set up the
@@ -107,22 +106,10 @@ _wait_for_entrypoint:
 	 * their turn to be woken up
 	 * ---------------------------------------------
 	 */
-	mrs	x0, mpidr_el1
-	bl	platform_get_entrypoint
-	cbnz	x0, _do_warm_boot
-	mrs	x0, mpidr_el1
-	bl	platform_is_primary_cpu
-	cbnz	x0, _do_cold_boot
+	wait_for_entrypoint
 
-	/* ---------------------------------------------
-	 * Perform any platform specific secondary cpu
-	 * actions
-	 * ---------------------------------------------
-	 */
-	bl	plat_secondary_cold_boot_setup
-	b	_wait_for_entrypoint
+	bl	platform_mem_init
 
-_do_cold_boot:
 	/* ---------------------------------------------
 	 * Init C runtime environment.
 	 *   - Zero-initialise the NOBITS sections.
@@ -148,19 +135,38 @@ _do_cold_boot:
 	bl	memcpy16
 
 	/* ---------------------------------------------
-	 * Initialize platform and jump to our c-entry
-	 * point for this type of reset
+	 * Give ourselves a small coherent stack to
+	 * ease the pain of initializing the MMU and
+	 * CCI in assembler
+	 * ---------------------------------------------
+	 */
+	mrs	x0, mpidr_el1
+	bl	platform_set_coherent_stack
+
+	/* ---------------------------------------------
+	 * Architectural init. can be generic e.g.
+	 * enabling stack alignment and platform spec-
+	 * ific e.g. MMU & page table setup as per the
+	 * platform memory map. Perform the latter here
+	 * and the former in bl1_main.
 	 * ---------------------------------------------
 	 */
-	adr	x0, bl1_main
-	bl	platform_cold_boot_init
-	b	_panic
+	bl	bl1_early_platform_setup
+	bl	bl1_plat_arch_setup
 
-_do_warm_boot:
 	/* ---------------------------------------------
-	 * Jump to BL31 for all warm boot init.
+	 * Give ourselves a stack allocated in Normal
+	 * -IS-WBWA memory
 	 * ---------------------------------------------
 	 */
-	blr	x0
-_panic:
-	b	_panic
+	mrs	x0, mpidr_el1
+	bl	platform_set_stack
+
+	/* --------------------------------------------------
+	 * Initialize platform and jump to our c-entry point
+	 * for this type of reset. Panic if it returns
+	 * --------------------------------------------------
+	 */
+	bl	bl1_main
+panic:
+	b	panic