diff options
| author | Vikram Kanigiri <vikram.kanigiri@arm.com> | 2014-04-15 18:08:08 +0100 |
|---|---|---|
| committer | Vikram Kanigiri <vikram.kanigiri@arm.com> | 2014-05-22 16:14:19 +0100 |
| commit | 4112bfa0c223eda73af1cfe57ca7dc926f767dd8 (patch) | |
| tree | 652b5cb01c095a39c771209caac10b6332a62929 /bl1/aarch64 | |
| parent | 29fb905d5f36a415a170a4bffeadf13b5f084345 (diff) | |
Populate BL31 input parameters as per new spec
This patch is based on spec published at
https://github.com/ARM-software/tf-issues/issues/133
It rearranges the bl31_args struct into
bl31_params and bl31_plat_params which provide the
information needed for Trusted firmware and platform
specific data via x0 and x1
On the FVP platform BL3-1 params and BL3-1 plat params
and its constituents are stored at the start of TZDRAM.
The information about memory availability and size for
BL3-1, BL3-2 and BL3-3 is moved into platform specific data.
Change-Id: I8b32057a3d0dd3968ea26c2541a0714177820da9
Diffstat (limited to 'bl1/aarch64')
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 3613b9f4..8ab9df86 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -117,7 +117,7 @@ SynchronousExceptionA64: * BL1 to pass EL3 control to BL31 is expected * here. * It expects X0 with RUN_IMAGE SMC function id - * X1 with address of a el_change_info_t structure + * X1 with address of a entry_point_info_t structure * describing the BL3-1 entrypoint * ------------------------------------------------ */ @@ -136,7 +136,7 @@ SynchronousExceptionA64: mov x0, x20 bl display_boot_progress - ldp x0, x1, [x20, #EL_CHANGE_INFO_PC_OFFSET] + ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] msr elr_el3, x0 msr spsr_el3, x1 ubfx x0, x1, #MODE_EL_SHIFT, #2 @@ -146,10 +146,10 @@ SynchronousExceptionA64: bl disable_mmu_icache_el3 tlbi alle3 - ldp x6, x7, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x30)] - ldp x4, x5, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x20)] - ldp x2, x3, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x10)] - ldp x0, x1, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x0)] + ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] + ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] + ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] + ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] eret panic: mov x0, #SYNC_EXCEPTION_AARCH64 |