diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-02-27 14:43:14 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-13 10:45:49 +0800 |
| commit | e6c4bf28eb7caa7a24bf630e68572d9c30453778 (patch) | |
| tree | 9b75dcf069f71c5cc02027aa5ff6bdec3c430a3b | |
| parent | ebcf5d9ade406573f42192c624f344ee8bae369c (diff) | |
imx: set CPU boot entry for partition reboot
With SPL running on OCRAM, when linux suspend, OCRAM
will lose power and if partition reboot is started from
SPL, system will hang as the OCRAM data lost, so for
partition reboot, the CPU boot entry can be set to
be from ATF BL31 entry directly, SCFW exposes such API
for this scenario.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_psci.c | 10 | ||||
| -rw-r--r-- | plat/imx/imx8qx/imx8qx_psci.c | 6 |
2 files changed, 16 insertions, 0 deletions
diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c index 65cad5b0..7911bc9e 100644 --- a/plat/imx/imx8qm/imx8qm_psci.c +++ b/plat/imx/imx8qm/imx8qm_psci.c @@ -303,6 +303,9 @@ static const plat_psci_ops_t imx_plat_psci_ops = { int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + imx_mailbox_init(sec_entrypoint); *psci_ops = &imx_plat_psci_ops; @@ -324,5 +327,12 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + /* + * set partition reboot address for primary CPU, boot device is NOT owned + * by ATF, so pass 0 here + */ + sc_pm_set_boot_parm(ipc_handle, cluster_id == 0 ? SC_R_A53_0 : SC_R_A72_0, + BL31_BASE, SC_R_MU_0A, 0); + return 0; } diff --git a/plat/imx/imx8qx/imx8qx_psci.c b/plat/imx/imx8qx/imx8qx_psci.c index 24a46f7a..2d8ca5c3 100644 --- a/plat/imx/imx8qx/imx8qx_psci.c +++ b/plat/imx/imx8qx/imx8qx_psci.c @@ -244,5 +244,11 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + /* + * set partition reboot address for primary CPU, boot device is NOT owned + * by ATF, so pass 0 here + */ + sc_pm_set_boot_parm(ipc_handle, SC_R_A35_0, BL31_BASE, SC_R_MU_0A, 0); + return 0; } |