diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2019-12-09 13:27:39 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-01-03 13:11:52 +0800 |
| commit | cbab087cbffa801869ec9c448a1b0cd0bef47091 (patch) | |
| tree | 434206167b15ef3d7adb9362460a288246f0634e | |
| parent | 5c94297e76b11e034fa3d2148f1709fd3452d4c9 (diff) | |
plat: imx8m: Add the anamix pll override setting
Add PLL power down override & bypass support when
system enter DSM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/gpc_common.c | 39 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8m_psci_common.c | 2 | ||||
| -rw-r--r-- | plat/imx/imx8m/include/gpc.h | 1 |
3 files changed, 42 insertions, 0 deletions
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 8aae1a62..81755a70 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -233,3 +233,42 @@ void imx_clear_rbc_count(void) mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | (0x3f << SLPCR_RBC_COUNT_SHIFT)); } + +#define MAX_PLL_NUM 10 +struct pll_override { + uint32_t reg; + uint32_t override_mask; +}; + +struct pll_override pll[MAX_PLL_NUM] = { + {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), }, + {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), }, + {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), }, + {.reg = 0x94, .override_mask = 0x5555500, }, + {.reg = 0x104, .override_mask = 0x5555500, }, + {.reg = 0x114, .override_mask = 0x500, }, +}; + +#define PLL_BYPASS BIT(4) +void imx_anamix_override(bool enter) +{ + int i; + + /* + * bypass all the plls & enable the override bit before + * entering DSM mode. + */ + for (i = 0; i < MAX_PLL_NUM; i++) { + if (enter) { + mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); + mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); + } else { + mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); + mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); + } + } +} diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c index f074db3a..68ac23d5 100644 --- a/plat/imx/imx8m/imx8m_psci_common.c +++ b/plat/imx/imx8m/imx8m_psci_common.c @@ -122,6 +122,7 @@ void imx_domain_suspend(const psci_power_state_t *target_state) if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { imx_set_sys_lpm(core_id, true); dram_enter_retention(); + imx_anamix_override(true); } } @@ -131,6 +132,7 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state) unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { + imx_anamix_override(false); dram_exit_retention(); imx_set_sys_lpm(core_id, false); } diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h index 139132c4..f27ab6a3 100644 --- a/plat/imx/imx8m/include/gpc.h +++ b/plat/imx/imx8m/include/gpc.h @@ -103,5 +103,6 @@ void imx_set_sys_wakeup(unsigned int last_core, bool pdn); void imx_set_sys_lpm(unsigned last_core, bool retention); void imx_set_rbc_count(void); void imx_clear_rbc_count(void); +void imx_anamix_override(bool enter); #endif /*IMX8M_GPC_H */ |