plat: imx8m: Add the src handler for m4/m7 core boot support

Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>

10 files changed, 110 insertions, 1 deletions

diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c
index 6a595571..ea76640a 100644
--- a/plat/imx/common/imx_sip_svc.c
+++ b/plat/imx/common/imx_sip_svc.c
@@ -33,6 +33,9 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
 	case IMX_SIP_GPC:
 		SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
 		break;
+	case IMX_SIP_SRC:
+		SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3));
+		break;
 	case IMX_SIP_DDR_DVFS:
 		return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
 	case IMX_SIP_HAB:
@@ -45,6 +48,9 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
 	case IMX_SIP_GPC:
 		SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
 		break;
+	case IMX_SIP_SRC:
+		SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3));
+		break;
 	case IMX_SIP_HAB:
 		SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4));
 		break;
diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h
index 0deb6ae8..6b1371f3 100644
--- a/plat/imx/common/include/imx_sip_svc.h
+++ b/plat/imx/common/include/imx_sip_svc.h
@@ -26,6 +26,10 @@
 #define IMX_SIP_BUILDINFO			0xC2000003
 #define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
+#define IMX_SIP_SRC			0xc2000005
+#define IMX_SIP_SRC_M4_START		0x00
+#define IMX_SIP_SRC_M4_STARTED		0x01
+
 #define IMX_SIP_GET_SOC_INFO		0xC2000006
 
 #define IMX_SIP_HAB            0xc2000007
@@ -52,6 +56,8 @@ int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
 			 u_register_t x2, u_register_t x3);
 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
 		    u_register_t x2, u_register_t x3);
+int imx_src_handler(uint32_t smc_fid, u_register_t x1,
+		    u_register_t x2, u_register_t x3);
 int dram_dvfs_handler(uint32_t smc_fid, void *handle,
 	u_register_t x1, u_register_t x2, u_register_t x3);
 
@@ -64,7 +70,8 @@ int dram_dvfs_handler(uint32_t smc_fid, void *handle,
 
 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
 		    u_register_t x2, u_register_t x3);
-
+int imx_src_handler(uint32_t smc_fid, u_register_t x1,
+		    u_register_t x2, u_register_t x3);
 int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
 	u_register_t x2, u_register_t x3, u_register_t x4);
 #endif
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c
index adb43608..091cf451 100644
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -15,6 +15,7 @@
 
 #include <gpc.h>
 #include <imx8m_psci.h>
+#include <imx_sip_svc.h>
 #include <plat_imx8.h>
 
 #define FSL_SIP_CONFIG_GPC_PM_DOMAIN		0x03
@@ -305,3 +306,25 @@ int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_regist
 
 	return 0;
 }
+
+#pragma weak imx_src_handler
+/* imx8mq/imx8mm need to verrride below function */
+int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	uint32_t val;
+
+	switch(x1) {
+	case IMX_SIP_SRC_M4_START:
+		mmio_clrbits_32(IMX_IOMUX_GPR_BASE + 0x58, 0x1);
+		break;
+	case IMX_SIP_SRC_M4_STARTED:
+		val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x58);
+		return !(val & 0x1);
+	default:
+		return SMC_UNK;
+
+	};
+
+	return 0;
+}
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c
index 3051ce3a..a1bbe35b 100644
--- a/plat/imx/imx8m/imx8mm/gpc.c
+++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -394,3 +394,26 @@ void imx_gpc_init(void)
 	mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
 	mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
 }
+
+int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	uint32_t val;
+
+	switch(x1) {
+	case IMX_SIP_SRC_M4_START:
+		val = mmio_read_32(IMX_SRC_BASE + SRC_M4RCR);
+		val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK;
+		val |= SRC_SCR_M4_ENABLE_MASK;
+		mmio_write_32(IMX_SRC_BASE + SRC_M4RCR, val);
+		break;
+	case IMX_SIP_SRC_M4_STARTED:
+		val = mmio_read_32(IMX_SRC_BASE + SRC_M4RCR);
+		return !(val & SRC_SCR_M4C_NON_SCLR_RST_MASK);
+	default:
+		return SMC_UNK;
+
+	};
+
+	return 0;
+}
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index dbe579a7..5eedaa02 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -111,10 +111,14 @@
 
 #define SRC_A53RCR0			U(0x4)
 #define SRC_A53RCR1			U(0x8)
+#define SRC_M4RCR			U(0xc)
 #define SRC_OTG1PHY_SCR			U(0x20)
 #define SRC_OTG2PHY_SCR			U(0x24)
 #define SRC_GPR1_OFFSET			U(0x74)
 
+#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK  	BIT(0)
+
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
 #define SNVS_LPCR_DP_EN			BIT(5)
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index 8e7a8d6b..7078767d 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -203,6 +203,10 @@ void bl31_platform_setup(void)
 	plat_gic_init();
 
 	imx_gpc_init();
+
+	/* Enable and reset M7 */
+	mmio_setbits_32(IMX_SRC_BASE + 0xc,  SRC_SCR_M4_ENABLE_MASK);
+	mmio_clrbits_32(IMX_SRC_BASE + 0xc, SRC_SCR_M4C_NON_SCLR_RST_MASK);
 }
 
 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index f059c10b..e90fc8dd 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -107,9 +107,13 @@
 
 #define SRC_A53RCR0			U(0x4)
 #define SRC_A53RCR1			U(0x8)
+#define SRC_M4RCR			U(0xc)
 #define SRC_OTG1PHY_SCR			U(0x20)
 #define SRC_GPR1_OFFSET			U(0x74)
 
+#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK  	BIT(0)
+
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
 #define SNVS_LPCR_DP_EN			BIT(5)
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_misc.c b/plat/imx/imx8m/imx8mq/imx8mq_misc.c
new file mode 100644
index 00000000..17213660
--- /dev/null
+++ b/plat/imx/imx8m/imx8mq/imx8mq_misc.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/runtime_svc.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <imx_sip_svc.h>
+
+int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	uint32_t val;
+
+	switch(x1) {
+	case IMX_SIP_SRC_M4_START:
+		val = mmio_read_32(IMX_SRC_BASE + SRC_M4RCR);
+		val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK;
+		val |= SRC_SCR_M4_ENABLE_MASK;
+		mmio_write_32(IMX_SRC_BASE + SRC_M4RCR, val);
+		break;
+	case IMX_SIP_SRC_M4_STARTED:
+		val = mmio_read_32(IMX_SRC_BASE + SRC_M4RCR);
+		return !(val & SRC_SCR_M4C_NON_SCLR_RST_MASK);
+	default:
+		return SMC_UNK;
+
+	};
+
+	return 0;
+}
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 9241067f..dba6efc7 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -108,10 +108,14 @@
 
 #define SRC_A53RCR0			U(0x4)
 #define SRC_A53RCR1			U(0x8)
+#define SRC_M4RCR			U(0xc)
 #define SRC_OTG1PHY_SCR			U(0x20)
 #define SRC_OTG2PHY_SCR			U(0x24)
 #define SRC_GPR1_OFFSET			U(0x74)
 
+#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK  	BIT(0)
+
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
 #define SNVS_LPCR_DP_EN			BIT(5)
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 4efba258..8a8bf087 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -26,6 +26,7 @@ IMX_GIC_SOURCES		:=	drivers/arm/gic/v3/gicv3_helpers.c	\
 BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S			\
 				plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c	\
 				plat/imx/imx8m/imx8mq/imx8mq_psci.c		\
+				plat/imx/imx8m/imx8mq/imx8mq_misc.c		\
 				plat/imx/imx8m/gpc_common.c			\
 				plat/imx/imx8m/hab.c				\
 				plat/imx/imx8m/imx_aipstz.c			\