diff options
| author | Nitin Garg <nitin.garg@nxp.com> | 2019-07-17 09:29:32 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-13 10:45:49 +0800 |
| commit | 48dfc8d9495ec1c58524ec71c9af876dd582c8e9 (patch) | |
| tree | 41fdcf6bfe8576838f6da9c85c71b84bae091254 | |
| parent | 823f912b333a4cc114286b65ca821e7f9b1dcbf7 (diff) | |
Fix A72 L2 DATA latency settings.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/imx/common/imx8_helpers.S | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/plat/imx/common/imx8_helpers.S b/plat/imx/common/imx8_helpers.S index f9d5ad49..8ded1f22 100644 --- a/plat/imx/common/imx8_helpers.S +++ b/plat/imx/common/imx8_helpers.S @@ -7,6 +7,7 @@ #include <asm_macros.S> #include <platform_def.h> #include <cortex_a35.h> +#include <cortex_a72.h> .globl plat_is_my_cpu_primary .globl plat_my_core_pos @@ -86,6 +87,34 @@ func plat_calc_core_pos ret endfunc plat_calc_core_pos + /* ---------------------------------------------- + * function to handle platform specific reset. + * ---------------------------------------------- + */ +func plat_reset_handler + /* enable EL2 cpuectlr RW access */ + mov x0, #0x73 + msr actlr_el3, x0 + msr actlr_el2, x0 + isb + /* -------------------------------------------------------------------- + * Nothing to do on Cortex-A53. + * -------------------------------------------------------------------- + */ + jump_if_cpu_midr CORTEX_A72_MIDR, A72 + ret + +A72: + /* -------------------------------------------------------------------- + * Cortex-A72 specific settings + * -------------------------------------------------------------------- + */ + mov x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) + msr CORTEX_A72_L2CTLR_EL1, x0 + isb + ret +endfunc plat_reset_handler + /* --------------------------------------------- * function to get the entrypoint. * --------------------------------------------- |