diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-11-22 14:38:54 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-13 10:45:49 +0800 |
| commit | 14a33a44fa242cb6565737bb9c43303c0a3ea13d (patch) | |
| tree | fb9bc438b9033a8b89dde7e7a93764e6396debcb | |
| parent | 418dd9bcdeb429223bbc4a6f0d5d11e646c08198 (diff) | |
plat: imx: Enable L2 ECC & parity for A72 cluster
As per design team's suggestion, L2 cache's ECC & parity
should be enabled for A72 cluster.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 1 | ||||
| -rw-r--r-- | plat/imx/common/imx8_helpers.S | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 4a444c67..4e886fee 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -52,6 +52,7 @@ #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A72_L2CTLR_ECC_PARITY_ENABLE_SHIFT 21 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) diff --git a/plat/imx/common/imx8_helpers.S b/plat/imx/common/imx8_helpers.S index 8ded1f22..0d78c6be 100644 --- a/plat/imx/common/imx8_helpers.S +++ b/plat/imx/common/imx8_helpers.S @@ -110,6 +110,7 @@ A72: * -------------------------------------------------------------------- */ mov x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) + orr x0, x0, #(1 << CORTEX_A72_L2CTLR_ECC_PARITY_ENABLE_SHIFT) msr CORTEX_A72_L2CTLR_EL1, x0 isb ret |