Add i.MX8 SoCs support

This patch adds i.MX8 SoCs ATFW support, including below
basic features:

* LPUART
* SCFW RPC
* SMP boot up

Each SoC will have its own platform definition and driver
to support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>

23 files changed, 4488 insertions, 0 deletions

diff --git a/plat/freescale/common/imx8_helpers.S b/plat/freescale/common/imx8_helpers.S
new file mode 100644
index 00000000..6f677ca9
--- /dev/null
+++ b/plat/freescale/common/imx8_helpers.S
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl	plat_is_my_cpu_primary
+	.globl	plat_my_core_pos
+	.globl	plat_calc_core_pos
+	.globl	plat_reset_handler
+	.globl	plat_get_my_entrypoint
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	platform_mem_init
+	.globl  imx_mailbox_init
+
+	/* ----------------------------------------------
+	 * The mailbox_base is used to distinguish warm/cold
+	 * reset. The mailbox_base is in the data section, not
+	 * in .bss, this allows function to start using this
+	 * variable before the runtime memory is initialized.
+	 * ----------------------------------------------
+	 */
+.section .data.mailbox_base ; .align 3
+	mailbox_base: .quad 0x0
+
+	/* ----------------------------------------------
+	 * unsigned int plat_is_my_cpu_primary(void);
+	 * This function checks if this is the primary CPU
+	 * ----------------------------------------------
+	 */
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, #PLAT_PRIMARY_CPU
+	cset	x0, eq
+	ret
+endfunc plat_is_my_cpu_primary
+
+	/* ----------------------------------------------
+	 * unsigned int plat_my_core_pos(void)
+	 * This Function uses the plat_calc_core_pos()
+	 * to get the index of the calling CPU.
+	 * ----------------------------------------------
+	 */
+func plat_my_core_pos
+	mrs	x0, mpidr_el1
+	and	x1, x0, #MPIDR_CPU_MASK
+	and 	x0, x0, #MPIDR_CLUSTER_MASK
+	add	x0, x1, x0, LSR #6
+	ret
+endfunc plat_my_core_pos
+
+	/*
+	 * unsigned int plat_calc_core_pos(uint64_t mpidr)
+	 * helper function to calculate the core position.
+	 * With this function.
+	 */
+func plat_calc_core_pos
+	and	x1, x0, #MPIDR_CPU_MASK
+	and 	x0, x0, #MPIDR_CLUSTER_MASK
+	add	x0, x1, x0, LSR #6
+	ret
+endfunc plat_calc_core_pos
+
+
+	/* ----------------------------------------------
+	 * function to handle platform specific reset.
+	 * ----------------------------------------------
+	 */
+func plat_reset_handler
+	/* enable EL2 cpuectlr RW access */
+	mov	x0, #0x73
+	msr	actlr_el3, x0
+	msr	actlr_el2, x0
+	isb
+	ret
+endfunc plat_reset_handler
+
+	/* ---------------------------------------------
+	 * function to get the entrypoint.
+	 * ---------------------------------------------
+	 */
+func plat_get_my_entrypoint
+	adrp	x1, mailbox_base
+	ldr	x0, [x1, :lo12:mailbox_base]
+	ret
+endfunc	plat_get_my_entrypoint
+
+func plat_secondary_cold_boot_setup
+	b	.
+endfunc plat_secondary_cold_boot_setup
+
+func plat_crash_console_init
+	/* TODO */
+	ret
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+	/* TODO */
+	ret
+endfunc plat_crash_console_putc
+
+func platform_mem_init
+	ret
+endfunc platform_mem_init
+
+/* Init the mailbox base address */
+func imx_mailbox_init
+	adrp	x1, mailbox_base
+	str	x0, [x1, :lo12:mailbox_base]
+	ret
+endfunc imx_mailbox_init
diff --git a/plat/freescale/common/imx8_topology.c b/plat/freescale/common/imx8_topology.c
new file mode 100644
index 00000000..ce45d12a
--- /dev/null
+++ b/plat/freescale/common/imx8_topology.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <platform.h>
+
+extern const unsigned char imx_power_domain_tree_desc[];
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return imx_power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int cluster_id, cpu_id;
+
+	mpidr &= MPIDR_AFFINITY_MASK;
+
+	if(mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
+		return -1;
+
+	cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
+	cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
+
+	if (cluster_id > PLATFORM_CLUSTER_COUNT ||
+		cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER)
+		return -1;
+
+	return (cpu_id + (cluster_id * 4));
+}
diff --git a/plat/freescale/common/include/lpuart.h b/plat/freescale/common/include/lpuart.h
new file mode 100644
index 00000000..2c5914a1
--- /dev/null
+++ b/plat/freescale/common/include/lpuart.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IMX_LPUART_H__
+#define __IMX_LPUART_H__
+
+#define VERID	0x0
+#define PARAM	0x4
+#define GLOBAL	0x8
+#define PINCFG	0xC
+#define BAUD	0x10
+#define STAT	0x14
+#define CTRL	0x18
+#define DATA	0x1C
+#define MATCH	0x20
+#define MODIR	0x24
+#define FIFO	0x28
+#define WATER	0x2C
+
+#define CTRL_TE		(1 << 19)
+#define CTRL_RE		(1 << 18)
+
+#define FIFO_TXFE	0x80
+#define FIFO_RXFE	0x40
+
+#define WATER_TXWATER_OFF	1
+#define WATER_RXWATER_OFF	16
+
+#define LPUART_CTRL_PT_MASK	0x1
+#define LPUART_CTRL_PE_MASK	0x2
+#define LPUART_CTRL_M_MASK	0x10
+
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+
+#endif  /* __IMX_LPUART_H__*/
diff --git a/plat/freescale/common/include/plat_imx8.h b/plat/freescale/common/include/plat_imx8.h
new file mode 100644
index 00000000..4e21b846
--- /dev/null
+++ b/plat/freescale/common/include/plat_imx8.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLAT_IMX8_H__
+#define __PLAT_IMX8_H__
+
+unsigned int plat_calc_core_pos(uint64_t mpidr);
+void imx_mailbox_init(uintptr_t base_addr);
+void plat_gic_driver_init(void);
+void plat_gic_init(void);
+void plat_gic_cpuif_enable(void);
+void plat_gic_cpuif_disable(void);
+void plat_gic_pcpu_init(void);
+
+#endif /*__PLAT_IMX8_H__ */
diff --git a/plat/freescale/common/include/plat_macros.S b/plat/freescale/common/include/plat_macros.S
new file mode 100755
index 00000000..366601cb
--- /dev/null
+++ b/plat/freescale/common/include/plat_macros.S
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * the below macro print out relevant GIC
+ * registers whenever an unhandled exception is
+ * taken in BL3-1
+ */
+.macro plat_print_gic_regs
+	/* TODO */
+.endm
+
+/*
+ * the below macro print out relevant interconnect
+ * registers whenever an unhandled exception is
+ * taken in BL3-1
+ */
+.macro plat_print_interconnect_regs
+	/* TODO */
+.endm
diff --git a/plat/freescale/common/include/sci/ipc.h b/plat/freescale/common/include/sci/ipc.h
new file mode 100755
index 00000000..d9ad74b2
--- /dev/null
+++ b/plat/freescale/common/include/sci/ipc.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file for the IPC implementation.
+ */
+
+#ifndef _SC_IPC_H
+#define _SC_IPC_H
+
+/* Includes */
+
+#include <sci/types.h>
+
+/* Defines */
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function opens an IPC channel.
+ *
+ * @param[out]    ipc         return pointer for ipc handle
+ * @param[in]     id          id of channel to open
+ *
+ * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC
+ *         otherwise).
+ *
+ * The \a id parameter is implementation specific. Could be an MU
+ * address, pointer to a driver path, channel index, etc.
+ */
+sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id);
+
+/*!
+ * This function closes an IPC channel.
+ *
+ * @param[in]     ipc         id of channel to close
+ */
+void sc_ipc_close(sc_ipc_t ipc);
+
+/*!
+ * This function reads a message from an IPC channel.
+ *
+ * @param[in]     ipc         id of channel read from
+ * @param[out]    data        pointer to message buffer to read
+ *
+ * This function will block if no message is available to be read.
+ */
+void sc_ipc_read(sc_ipc_t ipc, void *data);
+
+/*!
+ * This function writes a message to an IPC channel.
+ *
+ * @param[in]     ipc         id of channel to write to
+ * @param[in]     data        pointer to message buffer to write
+ *
+ * This function will block if the outgoing buffer is full.
+ */
+void sc_ipc_write(sc_ipc_t ipc, void *data);
+
+#endif /* _SC_IPC_H */
+
diff --git a/plat/freescale/common/include/sci/rpc.h b/plat/freescale/common/include/sci/rpc.h
new file mode 100755
index 00000000..2e6ed6a9
--- /dev/null
+++ b/plat/freescale/common/include/sci/rpc.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file for the RPC implementation.
+ */
+
+#ifndef _SC_RPC_H
+#define _SC_RPC_H
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/ipc.h>
+
+/* Defines */
+
+#define SC_RPC_VERSION          1
+
+#define SC_RPC_MAX_MSG          8
+
+#define RPC_VER(MSG)            ((MSG)->version)
+#define RPC_SIZE(MSG)           ((MSG)->size)
+#define RPC_SVC(MSG)            ((MSG)->svc)
+#define RPC_FUNC(MSG)           ((MSG)->func)
+#define RPC_R8(MSG)             ((MSG)->func)
+#define RPC_D32(MSG, IDX)       ((MSG)->DATA.d32[IDX / 4])
+#define RPC_F32(MSG, IDX)       ((MSG)->DATA.f32[IDX / 4])
+#define RPC_D16(MSG, IDX)       ((MSG)->DATA.d16[IDX / 2])
+#define RPC_D8(MSG, IDX)        ((MSG)->DATA.d8[IDX])
+
+/* Types */
+
+typedef enum sc_rpc_svc_e
+{
+    SC_RPC_SVC_UNKNOWN          = 0,
+    SC_RPC_SVC_RETURN           = 1,
+    SC_RPC_SVC_PM               = 2,
+    SC_RPC_SVC_RM               = 3,
+    SC_RPC_SVC_OTP              = 4,
+    SC_RPC_SVC_TIMER            = 5,
+    SC_RPC_SVC_PAD              = 6,
+    SC_RPC_SVC_MISC             = 7,
+    SC_RPC_SVC_IRQ              = 8,
+    SC_RPC_SVC_ABORT            = 9
+} sc_rpc_svc_t;
+
+typedef struct sc_rpc_msg_s
+{
+    uint8_t version;
+    uint8_t size;
+    uint8_t svc;
+    uint8_t func;
+    union
+    {
+        uint32_t d32[(SC_RPC_MAX_MSG - 1)];
+        uint16_t d16[(SC_RPC_MAX_MSG - 1) * 2];
+        uint8_t d8[(SC_RPC_MAX_MSG - 1) * 4];
+    } DATA;
+} sc_rpc_msg_t;
+
+typedef enum sc_rpc_async_state_e
+{
+    SC_RPC_ASYNC_STATE_RD_START     = 0,
+    SC_RPC_ASYNC_STATE_RD_ACTIVE    = 1,
+    SC_RPC_ASYNC_STATE_RD_DONE      = 2,
+    SC_RPC_ASYNC_STATE_WR_START     = 3,
+    SC_RPC_ASYNC_STATE_WR_ACTIVE    = 4,
+    SC_RPC_ASYNC_STATE_WR_DONE      = 5,
+} sc_rpc_async_state_t;
+
+typedef struct sc_rpc_async_msg_s
+{
+    sc_rpc_async_state_t state;
+    uint8_t wordIdx;
+    sc_rpc_msg_t msg;
+    uint32_t timeStamp;
+} sc_rpc_async_msg_t;
+
+/* Functions */
+
+/*!
+ * This is an internal function to send an RPC message over an IPC
+ * channel. It is called by client-side SCFW API function shims.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in,out] msg         handle to a message
+ * @param[in]     no_resp     response flag
+ *
+ * If \a no_resp is false then this function waits for a response
+ * and returns the result in \a msg.
+ */
+void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
+
+/*!
+ * This is an internal function to dispath an RPC call that has
+ * arrived via IPC over an MU. It is called by server-side SCFW.
+ *
+ * @param[in]     mu          MU message arrived on
+ * @param[in,out] msg         handle to a message
+ *
+ * The function result is returned in \a msg.
+ */
+void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates an RPC message and forwards on to the
+ * normal RPC API.  It is used only by hypervisors.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in,out] msg         handle to a message
+ *
+ * This function decodes a message, calls macros to translate the
+ * resources, pins, addresses, partitions, memory regions, etc. and
+ * then forwards on to the hypervisors SCFW API.Return results are
+ * translated back abd placed back into the message to be returned
+ * to the original API.
+ */
+void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* _SC_RPC_H */
+
diff --git a/plat/freescale/common/include/sci/scfw.h b/plat/freescale/common/include/sci/scfw.h
new file mode 100755
index 00000000..30756059
--- /dev/null
+++ b/plat/freescale/common/include/sci/scfw.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SC_SCFW_H
+#define _SC_SCFW_H
+
+/* Includes */
+
+#include <types.h>
+
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*!
+ * This type is used to declare a handle for an IPC communication
+ * channel. Its meaning is specific to the IPC implementation.
+ */
+typedef uint64_t sc_ipc_t;
+
+/*!
+ * This type is used to declare an ID for an IPC communication
+ * channel. For the reference IPC implementation, this ID 
+ * selects the base address of the MU used for IPC.
+ */
+typedef uint64_t sc_ipc_id_t;
+
+
+#endif /* _SC_SCFW_H */
+
diff --git a/plat/freescale/common/include/sci/sci.h b/plat/freescale/common/include/sci/sci.h
new file mode 100644
index 00000000..29f05697
--- /dev/null
+++ b/plat/freescale/common/include/sci/sci.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SC_SCI_H
+#define _SC_SCI_H
+
+/* Defines */
+
+/* Includes */
+
+#include <types.h>
+#include <sci/ipc.h>
+//#include <sci/svc/irq/api.h>
+//#include <sci/svc/misc/api.h>
+//#include <sci/svc/otp/api.h>
+#include <sci/svc/pad/api.h>
+#include <sci/svc/pm/api.h>
+//#include <sci/svc/rm/api.h>
+//#include <sci/svc/timer/api.h>
+//#include <asm/arch/pins.h>
+
+#ifdef PLAT_IMX8QM
+#define MU_BASE_ADDR(id)	((0x5D1B0000UL + (id*0x10000)))
+#endif
+#ifdef PLAT_IMX8QXP
+#define MU_BASE_ADDR(id)	((0x5D1B0000UL + (id*0x10000)))
+#endif
+#define SC_IPC_AP_CH0       	(MU_BASE_ADDR(0))
+#define SC_IPC_AP_CH1       	(MU_BASE_ADDR(1))
+#define SC_IPC_AP_CH2       	(MU_BASE_ADDR(2))
+#define SC_IPC_AP_CH3       	(MU_BASE_ADDR(3))
+#define SC_IPC_AP_CH4       	(MU_BASE_ADDR(4))
+
+#define SC_IPC_CH		SC_IPC_AP_CH0
+
+/* Types */
+
+/* Functions */
+
+#endif /* _SC_SCI_H */
+
+/**@}*/
+
diff --git a/plat/freescale/common/include/sci/svc/pad/api.h b/plat/freescale/common/include/sci/svc/pad/api.h
new file mode 100755
index 00000000..d84f3fd8
--- /dev/null
+++ b/plat/freescale/common/include/sci/svc/pad/api.h
@@ -0,0 +1,503 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Pad Control (PAD) function.
+ *
+ * @addtogroup PAD_SVC (SVC) Pad Service
+ *
+ * Module for the Pad Control (PAD) service.
+ *
+ * @{
+ */
+
+#ifndef _SC_PAD_API_H
+#define _SC_PAD_API_H
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/svc/rm/api.h>
+
+/* Defines */
+
+/* Types */
+
+/*!
+ * This type is used to declare a pad config. It determines how the
+ * output data is driven, pull-up is controlled, and input signal is
+ * connected. Normal and OD are typical and only connect the input
+ * when the output is not driven.  The IN options are less common and
+ * force an input connection even when driving the output.
+ */
+typedef enum sc_pad_config_e
+{
+    SC_PAD_CONFIG_NORMAL    = 0,    //!< Normal
+    SC_PAD_CONFIG_OD        = 1,    //!< Open Drain
+    SC_PAD_CONFIG_OD_IN     = 2,    //!< Open Drain and input
+    SC_PAD_CONFIG_OUT_IN    = 3     //!< Output and input
+} sc_pad_config_t;
+
+/*!
+ * This type is used to declare a pad low-power isolation config.
+ * ISO_LATE is the most common setting. ISO_EARLY is only used when
+ * an output pin is directly determined by another input pin. The
+ * other two are only used when SW wants to directly contol isolation.
+ */
+typedef enum sc_pad_iso_e
+{
+    SC_PAD_ISO_OFF          = 0,    //!< ISO latch is transparent
+    SC_PAD_ISO_EARLY        = 1,    //!< Follow EARLY_ISO
+    SC_PAD_ISO_LATE         = 2,    //!< Follow LATE_ISO
+    SC_PAD_ISO_ON           = 3     //!< ISO latched data is held
+} sc_pad_iso_t;
+
+/*!
+ * This type is used to declare a drive strength. Note it is specific
+ * to 28LPP.
+ */
+typedef enum sc_pad_28lpp_dse_e
+{
+    SC_PAD_28LPP_DSE_x1     = 0,    //!< Drive strength x1
+    SC_PAD_28LPP_DSE_x4     = 1,    //!< Drive strength x4
+    SC_PAD_28LPP_DSE_x2     = 2,    //!< Drive strength x2
+    SC_PAD_28LPP_DSE_x6     = 3     //!< Drive strength x6
+} sc_pad_28lpp_dse_t;
+
+/*!
+ * This type is used to declare a drive strength. Note it is specific
+ * to 28FDSOI. Also note that valid values depend on the pad type.
+ */
+typedef enum sc_pad_28fdsio_dse_e
+{
+    SC_PAD_28FDSOI_DSE_18V_1MA   = 0,    //!< Drive strength of 1mA for 1.8v
+    SC_PAD_28FDSOI_DSE_33V_2MA   = 0,    //!< Drive strength of 2mA for 3.3v
+    SC_PAD_28FDSOI_DSE_DV_HIGH   = 0,    //!< Drive strength of 12mA for dual volt
+    SC_PAD_28FDSOI_DSE_18V_2MA   = 1,    //!< Drive strength of 2mA for 1.8v
+    SC_PAD_28FDSOI_DSE_33V_4MA   = 1,    //!< Drive strength of 4mA for 3.3v
+    SC_PAD_28FDSOI_DSE_DV_LOW    = 1,    //!< Drive strength of 12mA for dual volt
+    SC_PAD_28FDSOI_DSE_18V_4MA   = 2,    //!< Drive strength of 4mA for 1.8v
+    SC_PAD_28FDSOI_DSE_33V_8MA   = 2,    //!< Drive strength of 8mA for 3.3v
+    SC_PAD_28FDSOI_DSE_18V_6MA   = 3,    //!< Drive strength of 6mA for 1.8v
+    SC_PAD_28FDSOI_DSE_33V_12MA  = 3,    //!< Drive strength of 12mA for 3.3v
+    SC_PAD_28FDSOI_DSE_18V_8MA   = 4,    //!< Drive strength of 8mA for 1.8v
+    SC_PAD_28FDSOI_DSE_18V_10MA  = 5,    //!< Drive strength of 10mA for 1.8v
+    SC_PAD_28FDSOI_DSE_18V_12MA  = 6,    //!< Drive strength of 12mA for 1.8v
+    SC_PAD_28FDSOI_DSE_33V_HS    = 7     //!< High-speed drive strength for 1.8v
+} sc_pad_28fdsoi_dse_t;
+
+/*!
+ * This type is used to declare a pull select. Note it is specific
+ * to 28LPP.
+ */
+typedef enum sc_pad_28lpp_ps_e
+{
+    SC_PAD_28LPP_PS_PD      = 0,    //!< Pull down
+    SC_PAD_28LPP_PS_PU_5K   = 1,    //!< 5K pull up
+    SC_PAD_28LPP_PS_PU_47K  = 2,    //!< 47K pull up
+    SC_PAD_28LPP_PS_PU_100K = 3     //!< 100K pull up
+} sc_pad_28lpp_ps_t;
+
+/*!
+ * This type is used to declare a pull select. Note it is specific
+ * to 28FDSOI.
+ */
+typedef enum sc_pad_28fdsoi_ps_e
+{
+    SC_PAD_28FDSOI_PS_KEEPER = 0,    //!< Bus-keeper (only valid for 1.8v)
+    SC_PAD_28FDSOI_PS_PU     = 1,    //!< Pull-up
+    SC_PAD_28FDSOI_PS_PD     = 2,    //!< Pull-down
+    SC_PAD_28FDSOI_PS_NONE   = 3     //!< No pull (disabled)
+} sc_pad_28fdsoi_ps_t;
+
+/*!
+ * This type is used to declare a wakeup mode of a pin.
+ */
+typedef enum sc_pad_wakeup_e
+{
+    SC_PAD_WAKEUP_OFF       = 0,    //!< Off
+    SC_PAD_WAKEUP_CLEAR     = 1,    //!< Clears pending flag
+    SC_PAD_WAKEUP_LOW_LVL   = 4,    //!< Low level
+    SC_PAD_WAKEUP_FALL_EDGE = 5,    //!< Falling edge
+    SC_PAD_WAKEUP_RISE_EDGE = 6,    //!< Rising edge
+    SC_PAD_WAKEUP_HIGH_LVL  = 7     //!< High-level
+} sc_pad_wakeup_t;
+
+/* Functions */
+
+/*!
+ * This function configures the mux settings for a pin. This includes
+ * the signal mux, pad config, and low-power isolation mode.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     mux         mux setting
+ * @param[in]     config      pad config
+ * @param[in]     iso         low-power isolation mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
+
+/*!
+ * This function configures the general purpose pad control. This
+ * is technology dependent and includes things like drive strength,
+ * slew rate, pull up/down, etc. Refer to the SoC Reference Manual
+ * for bit field details.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     ctrl        control value to set
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl);
+
+/*!
+ * This function configures the pad control specific to 28LPP.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     dse         drive strength
+ * @param[in]     sre         slew rate
+ * @param[in]     hys         hysteresis
+ * @param[in]     pe          pull enable
+ * @param[in]     ps          pull select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28lpp_dse_t dse, bool sre, bool hys, bool pe,
+    sc_pad_28lpp_ps_t ps);
+
+/*!
+ * This function configures the wakeup mode of the pin.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     wakeup      wakeup to set
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_wakeup_t wakeup);
+
+/*!
+ * This function configures a pad.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     mux         mux setting
+ * @param[in]     config      pad config
+ * @param[in]     iso         low-power isolation mode
+ * @param[in]     ctrl        control value
+ * @param[in]     wakeup      wakeup to set
+ *
+ * @see sc_pad_set_mux().
+ * @see sc_pad_set_gp().
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t mux,
+    sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+    sc_pad_wakeup_t wakeup);
+
+/*!
+ * This function gets the mux settings for a pin. This includes
+ * the signal mux, pad config, and low-power isolation mode.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    mux         pointer to return mux setting
+ * @param[out]    config      pointer to return pad config
+ * @param[out]    iso         pointer to return low-power isolation mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso);
+
+/*!
+ * This function gets the general purpose pad control. This
+ * is technology dependent and includes things like drive strength,
+ * slew rate, pull up/down, etc. Refer to the SoC Reference Manual
+ * for bit field details.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    ctrl        pointer to return control value
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl);
+
+/*!
+ * This function gets the pad control specific to 28LPP.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    dse         pointer to return drive strength
+ * @param[out]    sre         pointer to return slew rate
+ * @param[out]    hys         pointer to return hysteresis
+ * @param[out]    pe          pointer to return pull enable
+ * @param[out]    ps          pointer to return pull select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys, bool *pe,
+    sc_pad_28lpp_ps_t *ps);
+
+/*!
+ * This function gets the wakeup mode of a pin.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    wakeup      pointer to return wakeup
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_wakeup_t *wakeup);
+
+/*!
+ * This function gets a pad's config.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    mux         pointer to return mux setting
+ * @param[out]    config      pointer to return pad config
+ * @param[out]    iso         pointer to return low-power isolation mode
+ * @param[out]    ctrl        pointer to return control value
+ * @param[out]    wakeup      pointer to return wakeup to set
+ *
+ * @see sc_pad_set_mux().
+ * @see sc_pad_set_gp().
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+    sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+    sc_pad_wakeup_t *wakeup);
+
+/*!
+ * This function configures the pad control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     dse         drive strength
+ * @param[in]     ps          pull select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps);
+
+/*!
+ * This function gets the pad control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    dse         pointer to return drive strength
+ * @param[out]    ps          pointer to return pull select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps);
+
+/*!
+ * This function configures the compensation control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     compen      compensation/freeze mode
+ * @param[in]     fastfrz     fast freeze
+ * @param[in]     rasrcp      compensation code for PMOS
+ * @param[in]     rasrcn      compensation code for NMOS
+ * @param[in]     nasrc_sel   NASRC read select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+    bool nasrc_sel);
+
+/*!
+ * This function gets the compensation control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[in]     compen      pointer to return compensation/freeze mode
+ * @param[in]     fastfrz     pointer to return fast freeze
+ * @param[in]     rasrcp      pointer to return compensation code for PMOS
+ * @param[in]     rasrcn      pointer to return compensation code for NMOS
+ * @param[in]     nasrc_sel   pointer to return NASRC read select
+ * @param[in]     compok      pointer to return compensation status
+ * @param[in]     nasrc       pointer to return NASRCP/NASRCN
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+    bool *nasrc_sel, bool *compok, uint8_t *nasrc);
+
+/*!
+ * This function configures the settings for a pin. This setting is SoC
+ * specific.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to configure
+ * @param[in]     val         value to set
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val);
+
+/*!
+ * This function gets the settings for a pin. This setting is SoC
+ * specific.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to query
+ * @param[out]    val         pointer to return setting
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val);
+
+#endif /* _SC_PAD_API_H */
+
+/**@}*/
+
diff --git a/plat/freescale/common/include/sci/svc/pm/api.h b/plat/freescale/common/include/sci/svc/pm/api.h
new file mode 100755
index 00000000..a65fdb20
--- /dev/null
+++ b/plat/freescale/common/include/sci/svc/pm/api.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Power Management (PM) function. This includes functions for power state
+ * control, clock control, reset control, and wake-up event control.
+ *
+ * @addtogroup PM_SVC (SVC) Power Management Service
+ *
+ * Module for the Power Management (PM) service.
+ *
+ * @{
+ */
+
+#ifndef _SC_PM_API_H
+#define _SC_PM_API_H
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/svc/rm/api.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_PM_POWER_MODE_W      2       //!< Width of sc_pm_power_mode_t
+#define SC_PM_CLOCK_MODE_W      2       //!< Width of sc_pm_clock_mode_t
+#define SC_PM_RESET_TYPE_W      1       //!< Width of sc_pm_reset_type_t
+#define SC_PM_RESET_REASON_W    3       //!< Width of sc_pm_reset_reason_t
+/*@}*/
+
+/*!
+ * @name Defines for clock indexes (sc_pm_clk_t)
+ */
+/*@{*/
+/*@}*/
+
+/*!
+ * @name Defines for ALL parameters
+ */
+/*@{*/
+#define SC_PM_CLK_ALL   UINT8_MAX       //!< All clocks
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare a power mode. Note resources only use
+ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
+ * as system power modes.
+ */
+typedef enum sc_pm_power_mode_e
+{
+    SC_PM_PW_MODE_OFF           = 0,    //!< Power off
+    SC_PM_PW_MODE_STBY          = 1,    //!< Power in standby
+    SC_PM_PW_MODE_LP            = 2,    //!< Power in low-power
+    SC_PM_PW_MODE_ON            = 3     //!< Power on
+} sc_pm_power_mode_t;
+
+/*!
+ * This type is used to declare a clock.
+ */
+typedef enum sc_pm_clk_e
+{
+    SC_PM_CLK_SLV_BUS           = 0,    //!< Slave bus clock
+    SC_PM_CLK_MST_BUS           = 1,    //!< Master bus clock
+    SC_PM_CLK_PER               = 2,    //!< Peripheral clock
+    SC_PM_CLK_PHY               = 3,    //!< Phy clock
+    SC_PM_CLK_MISC              = 4,    //!< Misc clock
+    SC_PM_CLK_MISC0             = 0,    //!< Misc 0 clock
+    SC_PM_CLK_MISC1             = 1,    //!< Misc 1 clock
+    SC_PM_CLK_MISC2             = 2,    //!< Misc 2 clock
+    SC_PM_CLK_MISC3             = 3,    //!< Misc 3 clock
+    SC_PM_CLK_MISC4             = 4,    //!< Misc 4 clock
+    SC_PM_CLK_CPU               = 2,    //!< CPU clock
+    SC_PM_CLK_PLL               = 4,    //!< PLL
+    SC_PM_CLK_BYPASS            = 4     //!< Bypass clock
+} sc_pm_clk_t;
+
+/*!
+ * This type is used to declare a clock mode.
+ */
+typedef enum sc_pm_clk_mode_e
+{
+    SC_PM_CLK_MODE_OFF          = 0,    //!< Clock is disabled
+    SC_PM_CLK_MODE_AUTOGATE_SW  = 1,    //!< Clock is in SW autogate mode
+    SC_PM_CLK_MODE_AUTOGATE_HW  = 2,    //!< Clock is in HW autogate mode
+    SC_PM_CLK_MODE_ON           = 3     //!< Clock is enabled.
+} sc_pm_clk_mode_t;
+
+/*!
+ * This type is used to declare clock rates.
+ */
+typedef uint32_t sc_pm_clock_rate_t;
+
+/*!
+ * This type is used to declare a desired reset type.
+ */
+typedef enum sc_pm_reset_type_e
+{
+    SC_PM_RESET_TYPE_COLD       = 0,    //!< Cold reset
+    SC_PM_RESET_TYPE_WARM       = 1     //!< Warm reset
+} sc_pm_reset_type_t;
+
+/*!
+ * This type is used to declare a reason for a reset.
+ */
+typedef enum sc_pm_reset_reason_e
+{
+    SC_PM_RESET_REASON_POR      = 0,    //!< Power on reset
+    SC_PM_RESET_REASON_WARM     = 1,    //!< Warm reset
+    SC_PM_RESET_REASON_SW       = 2,    //!< Software reset
+    SC_PM_RESET_REASON_WDOG     = 3,    //!< Watchdog reset
+    SC_PM_RESET_REASON_LOCKUP   = 4,    //!< Lockup reset
+    SC_PM_RESET_REASON_TAMPER   = 5,    //!< Tamper reset
+    SC_PM_RESET_REASON_TEMP     = 6,    //!< Temp reset
+    SC_PM_RESET_REASON_LOW_VOLT = 7,    //!< Low voltage reset
+} sc_pm_reset_reason_t;
+
+/* Functions */
+
+/*!
+ * @name Power Functions
+ * @{
+ */
+
+/*!
+ * This function sets the power mode of a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition
+ * @param[in]     mode        power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition or mode,
+ * - SC_ERR_NOACCESS if caller's partition is not the owner or
+ *   parent of \a pt
+ *
+ * All resources owned by \a pt that are on will have their power
+ * mode changed to \a mode.
+ *
+ * @see sc_pm_set_resource_power_mode().
+ */
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t mode);
+
+/*!
+ * This function gets the power mode of a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition
+ * @param[out]    mode        pointer to return power mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition
+ */
+sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t *mode);
+
+/*!
+ * This function sets the power mode of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     mode        power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or mode,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner
+ *
+ * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. Other modes
+ * will return an error. Resources set to SC_PM_PW_MODE_ON will reflect the
+ * power mode of the partition and will change as that changes.
+ *
+ *  @see sc_pm_set_sys_power_mode().
+ */
+sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode);
+
+/*!
+ * This function gets the power mode of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[out]    mode        pointer to return power mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value
+ * returned does not reflect the power mode of the partition..
+ */
+sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t *mode);
+
+/* @} */
+
+/*!
+ * @name Clock/PLL Functions
+ * @{
+ */
+
+/*!
+ * This function sets the rate of a resource's clock/PLL.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock/PLL to affect
+ * @param[in,out] rate        pointer to rate to set,
+ *                            return actual rate
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock/PLL,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource,
+ * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL)
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
+ */
+sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+
+/*!
+ * This function gets the rate of a resource's clock/PLL.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock/PLL to affect
+ * @param[out]    rate        pointer to return rate
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock/PLL,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
+ */
+sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+
+/*!
+ * This function enables/disables a resource's clock.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock to affect
+ * @param[in]     enable      enable if true; otherwise disabled
+ * @param[in]     autog       HW auto clock gating
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock not applicable to this resource
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
+ */
+sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, bool enable, bool autog);
+
+/* @} */
+
+/*!
+ * @name Reset Functions
+ * @{
+ */
+
+/*!
+ * This function is used to boot a partition.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[in]     pt           handle of partition to boot
+ * @param[in]     resource_cpu ID of the CPU resource to start
+ * @param[in]     boot_addr    64-bit boot address
+ * @param[in]     resource_mu  ID of the MU that must be powered
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition, resource, or addr,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ *   partition to boot
+ */
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+    sc_rsrc_t resource_mu);
+
+/*!
+ * This function is used to reboot the caller's partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     type        reset type
+ *
+ * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
+ * the calling partition will be reset if possible. SC state (partitions,
+ * power, clocks, etc.) is reset. The boot SW of the booting CPU must be
+ * able to handle peripherals that that are not reset.
+ *
+ * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
+ * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
+ * of the booting CPU must be able to handle peripherals and SC state that
+ * that are not reset.
+ *
+ * If this function returns, then the reset did not occur due to an
+ * invalid parameter.
+ */
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
+
+/*!
+ * This function gets a caller's reset reason.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    reason      pointer to return reset reason
+ */
+void sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
+
+/*!
+ * This function is used to start/stop a CPU.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the CPU resource
+ * @param[in]     enable      start if true; otherwise stop
+ * @param[in]     address     64-bit boot address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ *   resource (CPU) owner
+ */
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
+    sc_faddr_t address);
+
+/*!
+ * This function is used to reboot a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to reboot
+ * @param[in]     type        reset type
+ *
+ * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
+ * the calling partition will be reset if possible. SC state (partitions,
+ * power, clocks, etc.) is reset. The boot SW of the booting CPU must be
+ * able to handle peripherals that that are not reset.
+ *
+ * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
+ * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
+ * of the booting CPU must be able to handle peripherals and SC state that
+ * that are not reset.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition or type
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ *
+ * Most peripherals owned by the partition will be reset if
+ * possible. SC state (partitions, power, clocks, etc.) is reset. The
+ * boot SW of the booting CPU must be able to handle peripherals that
+ * that are not reset.
+ */
+sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_reset_type_t type);
+
+/*!
+ * This function is used to reset the system. Only the owner of the
+ * SC_R_SYSTEM resource can do this.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     type        reset type
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid type
+ *
+ * If this function returns, then the reset did not occur due to an
+ * invalid parameter.
+ */
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
+
+/* @} */
+
+#endif /* _SC_PM_API_H */
+
+/**@}*/
+
diff --git a/plat/freescale/common/include/sci/svc/rm/api.h b/plat/freescale/common/include/sci/svc/rm/api.h
new file mode 100755
index 00000000..887bf479
--- /dev/null
+++ b/plat/freescale/common/include/sci/svc/rm/api.h
@@ -0,0 +1,642 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Resource Management (RM) function. This includes functions for
+ * partitioning resources, pins, and memory regions.
+ *
+ * @addtogroup RM_SVC (SVC) Resource Management Service
+ *
+ * Module for the Resource Management (RM) service.
+ *
+ * @{
+ */
+
+#ifndef _SC_RM_API_H
+#define _SC_RM_API_H
+
+/* Includes */
+
+#include <sci/types.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_RM_PARTITION_W   5       //!< Width of sc_rm_pt_t
+#define SC_RM_MEMREG_W      6       //!< Width of sc_rm_mr_t
+#define SC_RM_DID_W         4       //!< Width of sc_rm_did_t
+#define SC_RM_SID_W         6       //!< Width of sc_rm_sid_t
+#define SC_RM_SPA_W         2       //!< Width of sc_rm_spa_t
+#define SC_RM_PERM_W        3       //!< Width of sc_rm_perm_t
+/*@}*/
+
+/*!
+ * @name Defines for ALL parameters
+ */
+/*@{*/
+#define SC_RM_PT_ALL        UINT8_MAX   //!< All partitions
+#define SC_RM_MR_ALL        UINT8_MAX   //!< All memory regions
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare a resource partition.
+ */
+typedef uint8_t sc_rm_pt_t;
+
+/*!
+ * This type is used to declare a memory region.
+ */
+typedef uint8_t sc_rm_mr_t;
+
+/*!
+ * This type is used to declare a resource domain ID used by the
+ * isolation HW.
+ */
+typedef uint8_t sc_rm_did_t;
+
+/*!
+ * This type is used to declare an SMMU StreamID.
+ */
+typedef uint16_t sc_rm_sid_t;
+
+/*!
+ * This type is a used to declare master transaction attributes.
+ */
+typedef enum sc_rm_spa_e
+{
+    SC_RM_SPA_PASSTHRU = 0,        //!< Pass through (attribute driven by master)
+    SC_RM_SPA_PASSSID  = 1,        //!< Pass through and output on SID
+    SC_RM_SPA_ASSERT   = 2,        //!< Assert (force to be secure/privileged)
+    SC_RM_SPA_NEGATE   = 3         //!< Negate (force to be non-secure/user)
+} sc_rm_spa_t;
+
+/*!
+ * This type is used to declare a resource/memory region access permission.
+ * Refer to the XRDC2 Block Guide for more information.
+ */
+typedef enum sc_rm_perm_e
+{
+    SC_RM_PERM_NONE       = 0,    //!< No access
+    SC_RM_PERM_SEC_R      = 1,    //!< Secure RO
+    SC_RM_PERM_SECPRIV_RW = 2,    //!< Secure privilege R/W
+    SC_RM_PERM_SEC_RW     = 3,    //!< Secure R/W
+    SC_RM_PERM_NSPRIV_R   = 4,    //!< Secure R/W, non-secure privilege RO
+    SC_RM_PERM_NS_R       = 5,    //!< Secure R/W, non-secure RO
+    SC_RM_PERM_NSPRIV_RW  = 6,    //!< Secure R/W, non-secure privilege R/W
+    SC_RM_PERM_FULL       = 7     //!< Full access
+} sc_rm_perm_t;
+
+/* Functions */
+
+/*!
+ * @name Partition Functions
+ * @{
+ */
+
+/*!
+ * This function requests that the SC create a new resource partition.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[out]    pt           return handle for partition; used for subsequent function
+ *                             calls associated with this partition
+ * @param[in]     secure       boolean indicating if this partition should be secure; only
+ *                             valid if caller is secure
+ * @param[in]     isolated     boolean indicating if this partition should be HW isolated
+ *                             via XRDC; set true if new DID is desired
+ * @param[in]     restricted   boolean indicating if this partition should be restricted; set
+ *                             true if masters in this partition cannot create new partitions
+ * @param[in]     confidential boolean indicating if this partition should be confidential;
+ *                             set true if only this partition should be able to grant
+ *                             resource access permissions to this partition
+ * @param[in]     coherent     boolean indicating if this partition is coherent;
+ *                             set true if only this partition will contain both AP clusters
+ *                             and they will be coherent via the CCI
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested,
+ * - SC_ERR_LOCKED if caller's partition is locked,
+ * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space)
+ *
+ * Marking as non-secure prevents subsequent functions from configuring masters in this
+ * partition to assert the secure signal. If restricted then the new partition is limited
+ * in what functions it can call, especially those associated with managing partitions.
+ */
+sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
+    bool isolated, bool restricted, bool confidential, bool coherent);
+
+/*!
+ * This function frees a partition and assigns all resources to the caller.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to free
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if \a pt out of range or invalid,
+ * - SC_ERR_NOACCESS if \a pt is the SC partition,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_LOCKED if \a pt or caller's partition is locked
+ *
+ * All resources, memory regions, and pins are assigned to the caller/parent.
+ * The partition watchdog is disabled (even if locked). DID is freed.
+ */
+sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
+
+/*!
+ * This function forces a partition to use a specific static DID.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to assign \a did
+ * @param[in]     did         static DID to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if \a pt or \a did out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_LOCKED if \a pt is locked
+ *
+ * Assumes no assigned resources or memory regions yet! The number of static
+ * DID is fixed by the SC at boot.
+ */
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rm_did_t did);
+
+/*!
+ * This function locks a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to lock
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a pt out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
+ *
+ * If a partition is locked it cannot be freed, have resources/pins assigned
+ * to/from it, memory regions created/assigned, DID changed, or parent changed.
+ */
+sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt);
+
+/*!
+ * This function gets the partition handle of the caller.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    pt          return handle for caller's partition
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
+
+/*!
+ * This function sets a new parent for a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition for which parent is to be
+ *                            changed
+ * @param[in]     pt_parent   handle of partition to set as parent
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_LOCKED if either partition is locked
+ */
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rm_pt_t pt_parent);
+
+/*!
+ * This function moves all movable resources/pins owned by a source partition
+ * to a destination partition. It can be used to more quickly set up a new
+ * partition if a majority of the caller's resources are to be moved to a
+ * new partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt_src      handle of partition from which resources should
+ *                            be moved from
+ * @param[in]     pt_dst      handle of partition to which resources should be
+ *                            moved to
+ * @param[in]     move_rsrc   boolean to indicate if resources should be moved
+ * @param[in]     move_pins   boolean to indicate if pins should be moved
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * By default, all resources are movable. This can be changed using the
+ * sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU
+ * bypass.
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the
+ *   parent of \a pt_src,
+ * - SC_ERR_LOCKED if either partition is locked
+ */
+sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
+    bool move_rsrc, bool move_pins);
+
+/* @} */
+
+/*!
+ * @name Resource Functions
+ * @{
+ */
+
+/*!
+ * This function assigns ownership of a resource to a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to which resource should be
+ *                            assigned
+ * @param[in]     resource    resource to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Note a master will defaulted to SMMU bypass.
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition or \a pt is locked
+ */
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource);
+
+/*!
+ * This function flags resources as movable or not.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[in]     resource_fst first resource for which flag should be set
+ * @param[in]     resource_lst last resource for which flag should be set
+ * @param[in]     movable      movable flag (true) is movable
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if resources are out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function is used to determine the set of resources that will be
+ * moved using the sc_rm_move_all() function. All resources are movable
+ * by default so this function is normally used to prevent a set of
+ * resources from moving.
+ */
+sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
+    sc_rsrc_t resource_lst, bool movable);
+
+/*!
+ * This function sets attributes for a resource which is a bus master (i.e.
+ * capable of DMA).
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    master resource for which attributes should apply
+ * @param[in]     sa          security attribute
+ * @param[in]     pa          privilege attribute
+ * @param[in]     smmu_bypass SMMU bypass mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function configures how the HW isolation will see bus transactions
+ * from the specified master. Note the security attribute will only be
+ * changed if the caller's partition is secure.
+ */
+sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_spa_t sa, sc_rm_spa_t pa, bool smmu_bypass);
+
+/*!
+ * This function sets the StreamID for a resource which is a bus master (i.e.
+ * capable of DMA).
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    master resource for which attributes should apply
+ * @param[in]     sid         StreamID
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function configures the SID attribute associated with all bus transactions
+ * from this master. Note 0 is not a valid SID as it is reserved to indicate
+ * bypass.
+ */
+sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_sid_t sid);
+
+/*!
+ * This function sets access permissions for a peripheral resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    peripheral resource for which permissions should apply
+ * @param[in]     pt          handle of partition \a perm should by applied for
+ * @param[in]     perm        permissions to apply to \a resource for \a pt
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
+ *
+ * This function configures how the HW isolation will restrict access to a
+ * peripheral based on the attributes of a transaction from bus master.
+ */
+sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_pt_t pt, sc_rm_perm_t perm);
+
+/*!
+ * This function gets ownership status of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ *
+ * @return Returns a boolean (true if caller's partition owns the resource).
+ *
+ * If \a resource is out of range then false is returned.
+ */
+bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/*!
+ * This function is used to test if a resource is a bus master.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ *
+ * @return Returns a boolean (true if the resource is a bus master).
+ *
+ * If \a resource is out of range then false is returned.
+ */
+bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/*!
+ * This function is used to test if a resource is a peripheral.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ *
+ * @return Returns a boolean (true if the resource is a peripheral).
+ *
+ * If \a resource is out of range then false is returned.
+ */
+bool sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/*!
+ * This function is used to obtain info about a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to inquire about
+ * @param[out]    sid         pointer to return StreamID
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a resource is out of range
+ */
+sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_sid_t *sid);
+
+/* @} */
+
+/*!
+ * @name Memory Region Functions
+ * @{
+ */
+
+/*!
+ * This function requests that the SC create a new memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    mr          return handle for region; used for
+ *                            subsequent function calls
+ *                            associated with this region
+ * @param[in]     addr_start  start address of region (physical)
+ * @param[in]     addr_end    end address of region (physical)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if the new memory region is misaligned,
+ * - SC_ERR_LOCKED if caller's partition is locked,
+ * - SC_ERR_PARM if the new memory region spans multiple existing regions,
+ * - SC_ERR_NOACCESS if caller's partition does not own the memory containing
+ *   the new region,
+ * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
+ *   space)
+ *
+ * The area covered by the memory region must currently be owned by the caller.
+ * By default, the new region will have access permission set to allow the
+ * caller to access.
+ */
+sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
+    sc_faddr_t addr_start, sc_faddr_t addr_end);
+
+/*!
+ * This function frees a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to free
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a mr out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr,
+ * - SC_ERR_LOCKED if the owning partition of \a mr is locked
+ */
+sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr);
+
+/*!
+ * This function assigns ownership of a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to which memory region
+ *                            should be assigned
+ * @param[in]     mr          handle of memory region to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition or \a pt is locked
+ */
+sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr);
+
+/*!
+ * This function sets access permissions for a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region for which permissions
+ *                            should apply
+ * @param[in]     pt          handle of partition \a perm should by
+ *                            applied for
+ * @param[in]     perm        permissions to apply to \a mr for \a pt
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function configures how the HW isolation will restrict access to a
+ * memory region based on the attributes of a transaction from bus master.
+ */
+sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_rm_pt_t pt, sc_rm_perm_t perm);
+
+/*!
+ * This function gets ownership status of a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to check
+ *
+ * @return Returns a boolean (true if caller's partition owns the
+ * memory region).
+ *
+ * If \a mr is out of range then false is returned.
+ */
+bool sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+
+/*!
+ * This function is used to obtain info about a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to inquire about
+ * @param[out]    addr_start  pointer to return start address
+ * @param[out]    addr_end    pointer to return end address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a mr is out of range
+ */
+sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_faddr_t *addr_start, sc_faddr_t *addr_end);
+
+/* @} */
+
+/*!
+ * @name Pin Functions
+ * @{
+ */
+
+/*!
+ * This function assigns ownership of a pin to a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to which pin should
+ *                            be assigned
+ * @param[in]     pin         pin to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition or \a pt is locked
+ */
+sc_err_t sc_rm_assign_pin(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pin_t pin);
+
+/*!
+ * This function flags pins as movable or not.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin_fst     first pin for which flag should be set
+ * @param[in]     pin_lst     last pin for which flag should be set
+ * @param[in]     movable     movable flag (true) is movable
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if pins are out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of a pin owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function is used to determine the set of pins that will be
+ * moved using the sc_rm_move_all() function. All pins are movable
+ * by default so this function is normally used to prevent a set of
+ * pins from moving.
+ */
+sc_err_t sc_rm_set_pin_movable(sc_ipc_t ipc, sc_pin_t pin_fst,
+    sc_pin_t pin_lst, bool movable);
+
+/*!
+ * This function gets ownership status of a pin.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pin         pin to check
+ *
+ * @return Returns a boolean (true if caller's partition owns the pin).
+ *
+ * If \a pin is out of range then false is returned.
+ */
+bool sc_rm_is_pin_owned(sc_ipc_t ipc, sc_pin_t pin);
+
+/* @} */
+
+#endif /* _SC_RM_API_H */
+
+/**@}*/
+
diff --git a/plat/freescale/common/include/sci/types.h b/plat/freescale/common/include/sci/types.h
new file mode 100755
index 00000000..aac8bd89
--- /dev/null
+++ b/plat/freescale/common/include/sci/types.h
@@ -0,0 +1,781 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file containing types used across multiple service APIs.
+ */
+
+#ifndef _SC_TYPES_H
+#define _SC_TYPES_H
+
+/* Includes */
+
+#include <sci/scfw.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for common frequencies
+ */
+/*@{*/
+#define SC_32KHZ            32768   //!< 32KHz
+#define SC_10MHZ         10000000   //!< 10MHz
+#define SC_20MHZ         20000000   //!< 20MHz
+#define SC_25MHZ         25000000   //!< 25MHz
+#define SC_40MHZ         40000000   //!< 40MHz
+#define SC_50MHZ         50000000   //!< 50MHz
+#define SC_60MHZ         60000000   //!< 60MHz
+#define SC_66MHZ         66666666   //!< 66MHz
+#define SC_80MHZ         80000000   //!< 80MHz
+#define SC_83MHZ         83333333   //!< 83MHz
+#define SC_100MHZ       100000000   //!< 100MHz
+#define SC_125MHZ       125000000   //!< 125MHz
+#define SC_133MHZ       133333333   //!< 133MHz
+#define SC_150MHZ       150000000   //!< 150MHz
+#define SC_160MHZ       160000000   //!< 160MHz
+#define SC_166MHZ       166666666   //!< 160MHz
+#define SC_175MHZ       175000000   //!< 175MHz
+#define SC_200MHZ       200000000   //!< 200MHz
+#define SC_250MHZ       250000000   //!< 250MHz
+#define SC_266MHZ       266666666   //!< 266MHz
+#define SC_300MHZ       300000000   //!< 300MHz
+#define SC_320MHZ       320000000   //!< 320MHz
+#define SC_325MHZ       325000000   //!< 325MHz
+#define SC_333MHZ       333333333   //!< 333MHz
+#define SC_350MHZ       350000000   //!< 350MHz
+#define SC_375MHZ       375000000   //!< 375MHz
+#define SC_400MHZ       400000000   //!< 400MHz
+#define SC_500MHZ       500000000   //!< 500MHz
+#define SC_650MHZ       650000000   //!< 650MHz
+#define SC_667MHZ       666666667   //!< 667MHz
+#define SC_700MHZ       700000000   //!< 700MHz
+#define SC_720MHZ       720000000   //!< 720MHz
+#define SC_750MHZ       750000000   //!< 750MHz
+#define SC_800MHZ       800000000   //!< 800MHz
+#define SC_1000MHZ     1000000000   //!< 1GHz
+#define SC_1300MHZ     1300000000   //!< 1.3GHz
+#define SC_1400MHZ     1400000000   //!< 1.4GHz
+#define SC_1500MHZ     1500000000   //!< 1.5GHz
+#define SC_1600MHZ     1600000000   //!< 1.6GHz
+#define SC_1800MHZ     1800000000   //!< 1.8GHz
+#define SC_2000MHZ     2000000000   //!< 2.0GHz
+/*@}*/
+
+/*!
+ * @name Defines for 24M related frequencies
+ */
+/*@{*/
+#define SC_12MHZ         12000000   //!< 12MHz
+#define SC_19MHZ         19800000   //!< 19.8MHz
+#define SC_24MHZ         24000000   //!< 24MHz
+#define SC_120MHZ       120000000   //!< 120MHz
+#define SC_132MHZ       132000000   //!< 132MHz
+#define SC_192MHZ       192000000   //!< 192MHz
+#define SC_211MHZ       211200000   //!< 211.2MHz
+#define SC_240MHZ       240000000   //!< 240MHz
+#define SC_264MHZ       264000000   //!< 264MHz
+#define SC_352MHZ       352000000   //!< 352MHz
+#define SC_360MHZ       360000000   //!< 360MHz
+#define SC_384MHZ       384000000   //!< 384MHz
+#define SC_396MHZ       396000000   //!< 396MHz
+#define SC_480MHZ       480000000   //!< 480MHz
+#define SC_600MHZ       600000000   //!< 600MHz
+#define SC_792MHZ       792000000   //!< 792MHz
+#define SC_960MHZ       960000000   //!< 960MHz
+#define SC_1056MHZ     1056000000   //!< 1056MHz
+#define SC_1200MHZ     1200000000   //!< 1.2GHz
+#define SC_2400MHZ     2400000000   //!< 2.4GHz
+/*@}*/
+
+/*!
+ * @name Defines for A/V related frequencies
+ */
+/*@{*/
+#define SC_62MHZ         62937500   //!< 62.9375MHz
+#define SC_755MHZ       755250000   //!< 755.25MHz
+/*@}*/
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_FADDR_W      36          //!< Width of sc_faddr_t
+#define SC_BOOL_W       1           //!< Width of bool
+#define SC_ERR_W        4           //!< Width of sc_err_t
+#define SC_RSRC_W       10          //!< Width of sc_rsrc_t
+#define SC_CTRL_W       5           //!< Width of sc_ctrl_t
+/*@}*/
+
+#define SC_R_ALL        UINT16_MAX  //!< All resources
+#define SC_P_ALL        UINT16_MAX  //!< All pins
+
+/*!
+ * This type is used to store a system (full-size) address.
+ */
+typedef uint64_t sc_faddr_t;
+
+/*!
+ * This type is used to indicate error response for most functions.
+ */
+typedef enum sc_err_e
+{
+    SC_ERR_NONE         = 0,    //!< Success
+    SC_ERR_VERSION      = 1,    //!< Incompatible API version
+    SC_ERR_CONFIG       = 2,    //!< Configuration error
+    SC_ERR_PARM         = 3,    //!< Bad parameter
+    SC_ERR_NOACCESS     = 4,    //!< Permission error (no access)
+    SC_ERR_LOCKED       = 5,    //!< Permission error (locked)
+    SC_ERR_UNAVAILABLE  = 6,    //!< Unavailable (out of resources)
+    SC_ERR_NOTFOUND     = 7,    //!< Not found
+    SC_ERR_NOPOWER      = 8,    //!< No power
+    SC_ERR_IPC          = 9,    //!< Generic IPC error
+    SC_ERR_LAST
+} sc_err_t;
+
+/*!
+ * This type is used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+typedef enum sc_rsrc_e
+{
+    SC_R_A53                = 0,
+    SC_R_A53_0              = 1,
+    SC_R_A53_1              = 2,
+    SC_R_A53_2              = 3,
+    SC_R_A53_3              = 4,
+    SC_R_A72                = 5,
+    SC_R_A72_0              = 6,
+    SC_R_A72_1              = 7,
+    SC_R_A72_2              = 8,
+    SC_R_A72_3              = 9,
+    SC_R_CCI                = 10,
+    SC_R_DB                 = 11,
+    SC_R_DRC_0              = 12,
+    SC_R_DRC_1              = 13,
+    SC_R_GIC_SMMU           = 14,
+    SC_R_IRQSTR_M4_0        = 15,
+    SC_R_IRQSTR_M4_1        = 16,
+    SC_R_SMMU               = 17,
+    SC_R_GIC                = 18,
+    SC_R_DC_0_BLIT0         = 19,
+    SC_R_DC_0_BLIT1         = 20,
+    SC_R_DC_0_BLIT2         = 21,
+    SC_R_DC_0_BLIT_OUT      = 22,
+    SC_R_DC_0_CAPTURE0      = 23,
+    SC_R_DC_0_CAPTURE1      = 24,
+    SC_R_DC_0_WARP          = 25,
+    SC_R_DC_0_INTEGRAL0     = 26,
+    SC_R_DC_0_INTEGRAL1     = 27,
+    SC_R_DC_0_VIDEO0        = 28,
+    SC_R_DC_0_VIDEO1        = 29,
+    SC_R_DC_0_FRAC0         = 30,
+    SC_R_DC_0_FRAC1         = 31,
+    SC_R_DC_0               = 32,
+    SC_R_GPU_2_PID0         = 33,
+    SC_R_DC_0_PLL_0         = 34,
+    SC_R_DC_0_PLL_1         = 35,
+    SC_R_DC_1_BLIT0         = 36,
+    SC_R_DC_1_BLIT1         = 37,
+    SC_R_DC_1_BLIT2         = 38,
+    SC_R_DC_1_BLIT_OUT      = 39,
+    SC_R_DC_1_CAPTURE0      = 40,
+    SC_R_DC_1_CAPTURE1      = 41,
+    SC_R_DC_1_WARP          = 42,
+    SC_R_DC_1_INTEGRAL0     = 43,
+    SC_R_DC_1_INTEGRAL1     = 44,
+    SC_R_DC_1_VIDEO0        = 45,
+    SC_R_DC_1_VIDEO1        = 46,
+    SC_R_DC_1_FRAC0         = 47,
+    SC_R_DC_1_FRAC1         = 48,
+    SC_R_DC_1               = 49,
+    SC_R_GPU_3_PID0         = 50,
+    SC_R_DC_1_PLL_0         = 51,
+    SC_R_DC_1_PLL_1         = 52,
+    SC_R_SPI_0              = 53,
+    SC_R_SPI_1              = 54,
+    SC_R_SPI_2              = 55,
+    SC_R_SPI_3              = 56,
+    SC_R_UART_0             = 57,
+    SC_R_UART_1             = 58,
+    SC_R_UART_2             = 59,
+    SC_R_UART_3             = 60,
+    SC_R_UART_4             = 61,
+    SC_R_EMVSIM_0           = 62,
+    SC_R_EMVSIM_1           = 63,
+    SC_R_DMA_0_CH0          = 64,
+    SC_R_DMA_0_CH1          = 65,
+    SC_R_DMA_0_CH2          = 66,
+    SC_R_DMA_0_CH3          = 67,
+    SC_R_DMA_0_CH4          = 68,
+    SC_R_DMA_0_CH5          = 69,
+    SC_R_DMA_0_CH6          = 70,
+    SC_R_DMA_0_CH7          = 71,
+    SC_R_DMA_0_CH8          = 72,
+    SC_R_DMA_0_CH9          = 73,
+    SC_R_DMA_0_CH10         = 74,
+    SC_R_DMA_0_CH11         = 75,
+    SC_R_DMA_0_CH12         = 76,
+    SC_R_DMA_0_CH13         = 77,
+    SC_R_DMA_0_CH14         = 78,
+    SC_R_DMA_0_CH15         = 79,
+    SC_R_DMA_0_CH16         = 80,
+    SC_R_DMA_0_CH17         = 81,
+    SC_R_DMA_0_CH18         = 82,
+    SC_R_DMA_0_CH19         = 83,
+    SC_R_DMA_0_CH20         = 84,
+    SC_R_DMA_0_CH21         = 85,
+    SC_R_DMA_0_CH22         = 86,
+    SC_R_DMA_0_CH23         = 87,
+    SC_R_DMA_0_CH24         = 88,
+    SC_R_DMA_0_CH25         = 89,
+    SC_R_DMA_0_CH26         = 90,
+    SC_R_DMA_0_CH27         = 91,
+    SC_R_DMA_0_CH28         = 92,
+    SC_R_DMA_0_CH29         = 93,
+    SC_R_DMA_0_CH30         = 94,
+    SC_R_DMA_0_CH31         = 95,
+    SC_R_I2C_0              = 96,
+    SC_R_I2C_1              = 97,
+    SC_R_I2C_2              = 98,
+    SC_R_I2C_3              = 99,
+    SC_R_I2C_4              = 100,
+    SC_R_ADC_0              = 101,
+    SC_R_ADC_1              = 102,
+    SC_R_FTM_0              = 103,
+    SC_R_FTM_1              = 104,
+    SC_R_CAN_0              = 105,
+    SC_R_CAN_1              = 106,
+    SC_R_CAN_2              = 107,
+    SC_R_DMA_1_CH0          = 108,
+    SC_R_DMA_1_CH1          = 109,
+    SC_R_DMA_1_CH2          = 110,
+    SC_R_DMA_1_CH3          = 111,
+    SC_R_DMA_1_CH4          = 112,
+    SC_R_DMA_1_CH5          = 113,
+    SC_R_DMA_1_CH6          = 114,
+    SC_R_DMA_1_CH7          = 115,
+    SC_R_DMA_1_CH8          = 116,
+    SC_R_DMA_1_CH9          = 117,
+    SC_R_DMA_1_CH10         = 118,
+    SC_R_DMA_1_CH11         = 119,
+    SC_R_DMA_1_CH12         = 120,
+    SC_R_DMA_1_CH13         = 121,
+    SC_R_DMA_1_CH14         = 122,
+    SC_R_DMA_1_CH15         = 123,
+    SC_R_DMA_1_CH16         = 124,
+    SC_R_DMA_1_CH17         = 125,
+    SC_R_DMA_1_CH18         = 126,
+    SC_R_DMA_1_CH19         = 127,
+    SC_R_DMA_1_CH20         = 128,
+    SC_R_DMA_1_CH21         = 129,
+    SC_R_DMA_1_CH22         = 130,
+    SC_R_DMA_1_CH23         = 131,
+    SC_R_DMA_1_CH24         = 132,
+    SC_R_DMA_1_CH25         = 133,
+    SC_R_DMA_1_CH26         = 134,
+    SC_R_DMA_1_CH27         = 135,
+    SC_R_DMA_1_CH28         = 136,
+    SC_R_DMA_1_CH29         = 137,
+    SC_R_DMA_1_CH30         = 138,
+    SC_R_DMA_1_CH31         = 139,
+    SC_R_DRC_0_V            = 140,
+    SC_R_DRC_0_H            = 141,
+    SC_R_DRC_1_V            = 142,
+    SC_R_DRC_1_H            = 143,
+    SC_R_GPU_0_PID0         = 144,
+    SC_R_GPU_0_PID1         = 145,
+    SC_R_GPU_0_PID2         = 146,
+    SC_R_GPU_0_PID3         = 147,
+    SC_R_GPU_1_PID0         = 148,
+    SC_R_GPU_1_PID1         = 149,
+    SC_R_GPU_1_PID2         = 150,
+    SC_R_GPU_1_PID3         = 151,
+    SC_R_PCIE_A             = 152,
+    SC_R_SERDES_0           = 153,
+    SC_R_MATCH_0            = 154,
+    SC_R_MATCH_1            = 155,
+    SC_R_MATCH_2            = 156,
+    SC_R_MATCH_3            = 157,
+    SC_R_MATCH_4            = 158,
+    SC_R_MATCH_5            = 159,
+    SC_R_MATCH_6            = 160,
+    SC_R_MATCH_7            = 161,
+    SC_R_MATCH_8            = 162,
+    SC_R_MATCH_9            = 163,
+    SC_R_MATCH_10           = 164,
+    SC_R_MATCH_11           = 165,
+    SC_R_MATCH_12           = 166,
+    SC_R_MATCH_13           = 167,
+    SC_R_MATCH_14           = 168,
+    SC_R_PCIE_B             = 169,
+    SC_R_SATA_0             = 170,
+    SC_R_SERDES_1           = 171,
+    SC_R_HSIO_GPIO          = 172,
+    SC_R_MATCH_15           = 173,
+    SC_R_MATCH_16           = 174,
+    SC_R_MATCH_17           = 175,
+    SC_R_MATCH_18           = 176,
+    SC_R_MATCH_19           = 177,
+    SC_R_MATCH_20           = 178,
+    SC_R_MATCH_21           = 179,
+    SC_R_MATCH_22           = 180,
+    SC_R_MATCH_23           = 181,
+    SC_R_MATCH_24           = 182,
+    SC_R_MATCH_25           = 183,
+    SC_R_MATCH_26           = 184,
+    SC_R_MATCH_27           = 185,
+    SC_R_MATCH_28           = 186,
+    SC_R_LCD_0              = 187,
+    SC_R_LCD_0_PWM_0        = 188,
+    SC_R_LCD_0_I2C_0        = 189,
+    SC_R_LCD_0_I2C_1        = 190,
+    SC_R_PWM_0              = 191,
+    SC_R_PWM_1              = 192,
+    SC_R_PWM_2              = 193,
+    SC_R_PWM_3              = 194,
+    SC_R_PWM_4              = 195,
+    SC_R_PWM_5              = 196,
+    SC_R_PWM_6              = 197,
+    SC_R_PWM_7              = 198,
+    SC_R_GPIO_0             = 199,
+    SC_R_GPIO_1             = 200,
+    SC_R_GPIO_2             = 201,
+    SC_R_GPIO_3             = 202,
+    SC_R_GPIO_4             = 203,
+    SC_R_GPIO_5             = 204,
+    SC_R_GPIO_6             = 205,
+    SC_R_GPIO_7             = 206,
+    SC_R_GPT_0              = 207,
+    SC_R_GPT_1              = 208,
+    SC_R_GPT_2              = 209,
+    SC_R_GPT_3              = 210,
+    SC_R_GPT_4              = 211,
+    SC_R_KPP                = 212,
+    SC_R_MU_0A              = 213,
+    SC_R_MU_1A              = 214,
+    SC_R_MU_2A              = 215,
+    SC_R_MU_3A              = 216,
+    SC_R_MU_4A              = 217,
+    SC_R_MU_5A              = 218,
+    SC_R_MU_6A              = 219,
+    SC_R_MU_7A              = 220,
+    SC_R_MU_8A              = 221,
+    SC_R_MU_9A              = 222,
+    SC_R_MU_10A             = 223,
+    SC_R_MU_11A             = 224,
+    SC_R_MU_12A             = 225,
+    SC_R_MU_13A             = 226,
+    SC_R_MU_5B              = 227,
+    SC_R_MU_6B              = 228,
+    SC_R_MU_7B              = 229,
+    SC_R_MU_8B              = 230,
+    SC_R_MU_9B              = 231,
+    SC_R_MU_10B             = 232,
+    SC_R_MU_11B             = 233,
+    SC_R_MU_12B             = 234,
+    SC_R_MU_13B             = 235,
+    SC_R_ROM_0              = 236,
+    SC_R_FSPI_0             = 237,
+    SC_R_FSPI_1             = 238,
+    SC_R_IEE                = 239,
+    SC_R_IEE_R0             = 240,
+    SC_R_IEE_R1             = 241,
+    SC_R_IEE_R2             = 242,
+    SC_R_IEE_R3             = 243,
+    SC_R_IEE_R4             = 244,
+    SC_R_IEE_R5             = 245,
+    SC_R_IEE_R6             = 246,
+    SC_R_IEE_R7             = 247,
+    SC_R_SDHC_0             = 248,
+    SC_R_SDHC_1             = 249,
+    SC_R_SDHC_2             = 250,
+    SC_R_ENET_0             = 251,
+    SC_R_ENET_1             = 252,
+    SC_R_MLB_0              = 253,
+    SC_R_DMA_2_CH0          = 254,
+    SC_R_DMA_2_CH1          = 255,
+    SC_R_DMA_2_CH2          = 256,
+    SC_R_DMA_2_CH3          = 257,
+    SC_R_DMA_2_CH4          = 258,
+    SC_R_USB_0              = 259,
+    SC_R_USB_1              = 260,
+    SC_R_USB_0_PHY          = 261,
+    SC_R_USB_2              = 262,
+    SC_R_USB_2_PHY          = 263,
+    SC_R_DTCP               = 264,
+    SC_R_NAND               = 265,
+    SC_R_LVDS_0             = 266,
+    SC_R_LVDS_0_PWM_0       = 267,
+    SC_R_LVDS_0_I2C_0       = 268,
+    SC_R_LVDS_0_I2C_1       = 269,
+    SC_R_LVDS_1             = 270,
+    SC_R_LVDS_1_PWM_0       = 271,
+    SC_R_LVDS_1_I2C_0       = 272,
+    SC_R_LVDS_1_I2C_1       = 273,
+    SC_R_LVDS_2             = 274,
+    SC_R_LVDS_2_PWM_0       = 275,
+    SC_R_LVDS_2_I2C_0       = 276,
+    SC_R_LVDS_2_I2C_1       = 277,
+    SC_R_M4_0_PID0          = 278,
+    SC_R_M4_0_PID1          = 279,
+    SC_R_M4_0_PID2          = 280,
+    SC_R_M4_0_PID3          = 281,
+    SC_R_M4_0_PID4          = 282,
+    SC_R_M4_0_RGPIO         = 283,
+    SC_R_M4_0_SEMA42        = 284,
+    SC_R_M4_0_TPM           = 285,
+    SC_R_M4_0_PIT           = 286,
+    SC_R_M4_0_UART          = 287,
+    SC_R_M4_0_I2C           = 288,
+    SC_R_M4_0_INTMUX        = 289,
+    SC_R_M4_0_SIM           = 290,
+    SC_R_M4_0_WDOG          = 291,
+    SC_R_M4_0_MU_0B         = 292,
+    SC_R_M4_0_MU_0A0        = 293,
+    SC_R_M4_0_MU_0A1        = 294,
+    SC_R_M4_0_MU_0A2        = 295,
+    SC_R_M4_0_MU_0A3        = 296,
+    SC_R_M4_0_MU_1A         = 297,
+    SC_R_M4_1_PID0          = 298,
+    SC_R_M4_1_PID1          = 299,
+    SC_R_M4_1_PID2          = 300,
+    SC_R_M4_1_PID3          = 301,
+    SC_R_M4_1_PID4          = 302,
+    SC_R_M4_1_RGPIO         = 303,
+    SC_R_M4_1_SEMA42        = 304,
+    SC_R_M4_1_TPM           = 305,
+    SC_R_M4_1_PIT           = 306,
+    SC_R_M4_1_UART          = 307,
+    SC_R_M4_1_I2C           = 308,
+    SC_R_M4_1_INTMUX        = 309,
+    SC_R_M4_1_SIM           = 310,
+    SC_R_M4_1_WDOG          = 311,
+    SC_R_M4_1_MU_0B         = 312,
+    SC_R_M4_1_MU_0A0        = 313,
+    SC_R_M4_1_MU_0A1        = 314,
+    SC_R_M4_1_MU_0A2        = 315,
+    SC_R_M4_1_MU_0A3        = 316,
+    SC_R_M4_1_MU_1A         = 317,
+    SC_R_SAI_0              = 318,
+    SC_R_SAI_1              = 319,
+    SC_R_SAI_2              = 320,
+    SC_R_SPBA               = 321,
+    SC_R_QSPI_0             = 322,
+    SC_R_SDMA               = 323,
+    SC_R_IRQSTR_MW          = 324,
+    SC_R_AUDIO_PLL_0        = 325,
+    SC_R_PI_0               = 326,
+    SC_R_PI_0_PWM_0         = 327,
+    SC_R_PI_0_PWM_1         = 328,
+    SC_R_PI_0_I2C_0         = 329,
+    SC_R_PI_0_PLL           = 330,
+    SC_R_PI_1               = 331,
+    SC_R_PI_1_PWM_0         = 332,
+    SC_R_PI_1_PWM_1         = 333,
+    SC_R_PI_1_I2C_0         = 334,
+    SC_R_PI_1_PLL           = 335,
+    SC_R_SC_PID0            = 336,
+    SC_R_SC_PID1            = 337,
+    SC_R_SC_PID2            = 338,
+    SC_R_SC_PID3            = 339,
+    SC_R_SC_PID4            = 340,
+    SC_R_SC_SEMA42          = 341,
+    SC_R_SC_TPM             = 342,
+    SC_R_SC_PIT             = 343,
+    SC_R_SC_UART            = 344,
+    SC_R_SC_I2C             = 345,
+    SC_R_SC_MU_0B           = 346,
+    SC_R_SC_MU_0A0          = 347,
+    SC_R_SC_MU_0A1          = 348,
+    SC_R_SC_MU_0A2          = 349,
+    SC_R_SC_MU_0A3          = 350,
+    SC_R_SC_MU_1A           = 351,
+    SC_R_SYSCNT_RD          = 352,
+    SC_R_SYSCNT_CMP         = 353,
+    SC_R_DEBUG              = 354,
+    SC_R_SYSTEM             = 355,
+    SC_R_SNVS               = 356,
+    SC_R_OTP                = 357,
+    SC_R_VPU_PID0           = 358,
+    SC_R_VPU_PID1           = 359,
+    SC_R_VPU_PID2           = 360,
+    SC_R_VPU_PID3           = 361,
+    SC_R_VPU_PID4           = 362,
+    SC_R_VPU_PID5           = 363,
+    SC_R_VPU_PID6           = 364,
+    SC_R_VPU_PID7           = 365,
+    SC_R_VPU_UART           = 366,
+    SC_R_VPUCORE            = 367,
+    SC_R_VPUCORE_0          = 368,
+    SC_R_VPUCORE_1          = 369,
+    SC_R_VPUCORE_2          = 370,
+    SC_R_VPUCORE_3          = 371,
+    SC_R_DMA_4_CH0          = 372,
+    SC_R_DMA_4_CH1          = 373,
+    SC_R_DMA_4_CH2          = 374,
+    SC_R_DMA_4_CH3          = 375,
+    SC_R_DMA_4_CH4          = 376,
+    SC_R_ISI_CH0            = 377,
+    SC_R_ISI_CH1            = 378,
+    SC_R_ISI_CH2            = 379,
+    SC_R_ISI_CH3            = 380,
+    SC_R_ISI_CH4            = 381,
+    SC_R_ISI_CH5            = 382,
+    SC_R_ISI_CH6            = 383,
+    SC_R_ISI_CH7            = 384,
+    SC_R_MJPEG_DEC_S0       = 385,
+    SC_R_MJPEG_DEC_S1       = 386,
+    SC_R_MJPEG_DEC_S2       = 387,
+    SC_R_MJPEG_DEC_S3       = 388,
+    SC_R_MJPEG_ENC_S0       = 389,
+    SC_R_MJPEG_ENC_S1       = 390,
+    SC_R_MJPEG_ENC_S2       = 391,
+    SC_R_MJPEG_ENC_S3       = 392,
+    SC_R_MIPI_0             = 393,
+    SC_R_MIPI_0_PWM_0       = 394,
+    SC_R_MIPI_0_I2C_0       = 395,
+    SC_R_MIPI_0_I2C_1       = 396,
+    SC_R_MIPI_1             = 397,
+    SC_R_MIPI_1_PWM_0       = 398,
+    SC_R_MIPI_1_I2C_0       = 399,
+    SC_R_MIPI_1_I2C_1       = 400,
+    SC_R_CSI_0              = 401,
+    SC_R_CSI_0_PWM_0        = 402,
+    SC_R_CSI_0_I2C_0        = 403,
+    SC_R_CSI_1              = 404,
+    SC_R_CSI_1_PWM_0        = 405,
+    SC_R_CSI_1_I2C_0        = 406,
+    SC_R_HDMI               = 407,
+    SC_R_HDMI_BYPASS        = 408,
+    SC_R_HDMI_I2C_0         = 409,
+    SC_R_AUDIO_PLL_2        = 410,
+    SC_R_HDMI_RX            = 411,
+    SC_R_HDMI_RX_BYPASS     = 412,
+    SC_R_HDMI_RX_I2C_0      = 413,
+    SC_R_ASRC_0             = 414,
+    SC_R_ESAI_0             = 415,
+    SC_R_SPDIF_0            = 416,
+    SC_R_SPDIF_1            = 417,
+    SC_R_SAI_3              = 418,
+    SC_R_SAI_4              = 419,
+    SC_R_SAI_5              = 420,
+    SC_R_GPT_5              = 421,
+    SC_R_GPT_6              = 422,
+    SC_R_GPT_7              = 423,
+    SC_R_GPT_8              = 424,
+    SC_R_GPT_9              = 425,
+    SC_R_GPT_10             = 426,
+    SC_R_DMA_2_CH5          = 427,
+    SC_R_DMA_2_CH6          = 428,
+    SC_R_DMA_2_CH7          = 429,
+    SC_R_DMA_2_CH8          = 430,
+    SC_R_DMA_2_CH9          = 431,
+    SC_R_DMA_2_CH10         = 432,
+    SC_R_DMA_2_CH11         = 433,
+    SC_R_DMA_2_CH12         = 434,
+    SC_R_DMA_2_CH13         = 435,
+    SC_R_DMA_2_CH14         = 436,
+    SC_R_DMA_2_CH15         = 437,
+    SC_R_DMA_2_CH16         = 438,
+    SC_R_DMA_2_CH17         = 439,
+    SC_R_DMA_2_CH18         = 440,
+    SC_R_DMA_2_CH19         = 441,
+    SC_R_DMA_2_CH20         = 442,
+    SC_R_DMA_2_CH21         = 443,
+    SC_R_DMA_2_CH22         = 444,
+    SC_R_DMA_2_CH23         = 445,
+    SC_R_DMA_2_CH24         = 446,
+    SC_R_DMA_2_CH25         = 447,
+    SC_R_DMA_2_CH26         = 448,
+    SC_R_DMA_2_CH27         = 449,
+    SC_R_DMA_2_CH28         = 450,
+    SC_R_DMA_2_CH29         = 451,
+    SC_R_DMA_2_CH30         = 452,
+    SC_R_DMA_2_CH31         = 453,
+    SC_R_ASRC_1             = 454,
+    SC_R_ESAI_1             = 455,
+    SC_R_SAI_6              = 456,
+    SC_R_SAI_7              = 457,
+    SC_R_AMIX               = 458,
+    SC_R_MQS_0              = 459,
+    SC_R_DMA_3_CH0          = 460,
+    SC_R_DMA_3_CH1          = 461,
+    SC_R_DMA_3_CH2          = 462,
+    SC_R_DMA_3_CH3          = 463,
+    SC_R_DMA_3_CH4          = 464,
+    SC_R_DMA_3_CH5          = 465,
+    SC_R_DMA_3_CH6          = 466,
+    SC_R_DMA_3_CH7          = 467,
+    SC_R_DMA_3_CH8          = 468,
+    SC_R_DMA_3_CH9          = 469,
+    SC_R_DMA_3_CH10         = 470,
+    SC_R_DMA_3_CH11         = 471,
+    SC_R_DMA_3_CH12         = 472,
+    SC_R_DMA_3_CH13         = 473,
+    SC_R_DMA_3_CH14         = 474,
+    SC_R_DMA_3_CH15         = 475,
+    SC_R_DMA_3_CH16         = 476,
+    SC_R_DMA_3_CH17         = 477,
+    SC_R_DMA_3_CH18         = 478,
+    SC_R_DMA_3_CH19         = 479,
+    SC_R_DMA_3_CH20         = 480,
+    SC_R_DMA_3_CH21         = 481,
+    SC_R_DMA_3_CH22         = 482,
+    SC_R_DMA_3_CH23         = 483,
+    SC_R_DMA_3_CH24         = 484,
+    SC_R_DMA_3_CH25         = 485,
+    SC_R_DMA_3_CH26         = 486,
+    SC_R_DMA_3_CH27         = 487,
+    SC_R_DMA_3_CH28         = 488,
+    SC_R_DMA_3_CH29         = 489,
+    SC_R_DMA_3_CH30         = 490,
+    SC_R_DMA_3_CH31         = 491,
+    SC_R_AUDIO_PLL_1        = 492,
+    SC_R_AUDIO_CLK_0        = 493,
+    SC_R_AUDIO_CLK_1        = 494,
+    SC_R_MCLK_OUT_0         = 495,
+    SC_R_MCLK_OUT_1         = 496,
+    SC_R_PMIC_0             = 497,
+    SC_R_PMIC_1             = 498,
+    SC_R_SECO               = 499,
+    SC_R_CAAM_JR1           = 500,
+    SC_R_CAAM_JR2           = 501,
+    SC_R_CAAM_JR3           = 502,
+    SC_R_SECO_MU_2          = 503,
+    SC_R_SECO_MU_3          = 504,
+    SC_R_SECO_MU_4          = 505,
+    SC_R_HDMI_RX_PWM_0      = 506,
+    SC_R_A35                = 507,
+    SC_R_A35_0              = 508,
+    SC_R_A35_1              = 509,
+    SC_R_A35_2              = 510,
+    SC_R_A35_3              = 511,
+    SC_R_HIFI               = 512,
+    SC_R_HIFI_RAM           = 513,
+    SC_R_LAST
+} sc_rsrc_t;
+
+/*!
+ * This type is used to indicate a control.
+ */
+typedef enum sc_ctrl_e
+{
+
+    SC_C_TEMP               = 0,
+    SC_C_TEMP_HI            = 1,
+    SC_C_TEMP_LOW           = 2,
+    SC_C_PXL_LINK_MST1_ADDR = 3,
+    SC_C_PXL_LINK_MST2_ADDR = 4,
+    SC_C_PXL_LINK_MST_ENB   = 5,
+    SC_C_PXL_LINK_MST1_ENB  = 6,
+    SC_C_PXL_LINK_MST2_ENB  = 7,
+    SC_C_PXL_LINK_SLV1_ADDR = 8,
+    SC_C_PXL_LINK_SLV2_ADDR = 9,
+    SC_C_PXL_LINK_MST_VLD   = 10,
+    SC_C_PXL_LINK_MST1_VLD  = 11,
+    SC_C_PXL_LINK_MST2_VLD  = 12,
+    SC_C_SINGLE_MODE        = 13,
+    SC_C_ID                 = 14,
+    SC_C_PXL_CLK_POLARITY   = 15,
+    SC_C_LINESTATE          = 16,
+    SC_C_PCIE_G_RST         = 17,
+    SC_C_PCIE_BUTTON_RST    = 18,
+    SC_C_PCIE_PERST         = 19,
+    SC_C_PHY_RESET          = 20,
+    SC_C_PXL_LINK_RATE_CORRECTION = 21,
+    SC_C_PANIC              = 22,
+    SC_C_PRIORITY_GROUP     = 23,
+    SC_C_TXCLK              = 24,
+    SC_C_CLKDIV             = 25,
+    SC_C_DISABLE_50         = 26,
+    SC_C_DISABLE_125        = 27,
+    SC_C_SEL_125            = 28,
+    SC_C_LAST
+} sc_ctrl_t;
+
+/*!
+ * This type is used to indicate a pin. Valid values are SoC specific.
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+typedef uint16_t sc_pin_t;
+
+/* Extra documentation of standard types */
+
+#ifdef DOXYGEN
+    /*!
+     * Type used to declare a true/false boolean.
+     */
+    typedef enum {false = 0, true = 1} bool;
+
+    /*!
+     * Type used to declare an 8-bit integer.
+     */
+    typedef __INT8_TYPE__ int8_t;
+
+    /*!
+     * Type used to declare a 16-bit integer.
+     */
+    typedef __INT16_TYPE__ int16_t;
+
+    /*!
+     * Type used to declare a 32-bit integer.
+     */
+    typedef __INT32_TYPE__ int32_t;
+
+    /*!
+     * Type used to declare a 64-bit integer.
+     */
+    typedef __INT64_TYPE__ int64_t;
+
+    /*!
+     * Type used to declare an 8-bit unsigned integer.
+     */
+    typedef __UINT8_TYPE__ uint8_t;
+
+    /*!
+     * Type used to declare a 16-bit unsigned integer.
+     */
+    typedef __UINT16_TYPE__ uint16_t;
+
+    /*!
+     * Type used to declare a 32-bit unsigned integer.
+     */
+    typedef __UINT32_TYPE__ uint32_t;
+
+    /*!
+     * Type used to declare a 64-bit unsigned integer.
+     */
+    typedef __UINT64_TYPE__ uint64_t;
+#endif
+
+#endif /* _SC_TYPES_H */
+
diff --git a/plat/freescale/common/lpuart_console.S b/plat/freescale/common/lpuart_console.S
new file mode 100644
index 00000000..0d71199a
--- /dev/null
+++ b/plat/freescale/common/lpuart_console.S
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm_macros.S>
+
+#define UARTBAUD	0x10
+#define UARTSTAT	0x14
+#define UARTCTRL	0x18
+#define UARTDATA	0x1C
+#define UARTMATCH	0x20
+#define UARTMODIR	0x24
+#define UARTFIFO	0x28
+#define UARTWATER	0x2c
+
+#define US1_TDRE	(1 << 23)
+#define US1_RDRF	(1 << 21)
+
+	.globl	console_core_init
+	.globl	console_core_putc
+	.globl	console_core_getc
+	.globl	console_core_flush
+
+/* console_core_init */
+func console_core_init
+	mov	w0, wzr
+	ret
+endfunc console_core_init
+
+/* console_core_putc */
+func console_core_putc
+	/* Check the input parameter */
+	cbz	x1, putc_error
+	/* Insert implementation here */
+	/* Prepare '\r' to '\n' */
+	cmp	w0, #0xA
+	b.ne	2f
+1:
+	/* Check if the transmit FIFO is full */
+	ldr	w2, [x1, #UARTSTAT]
+	tbz	w2, #23, 1b
+	mov	w2, #0xD
+	str	w2, [x1, #UARTDATA]
+2:
+	/* Check if the transmit FIFO is full */
+	ldr	w2, [x1, #UARTSTAT]
+	tbz	w2, #23, 2b
+	str	w0, [x1, #UARTDATA]
+	ret
+putc_error:
+	mov	w0, #-1
+	ret
+endfunc console_core_putc
+
+/* console_core_getc */
+func console_core_getc
+	cbz	x0, getc_error
+	/* Insert implementation here */
+	/* Check if the receive FIFO state */
+	ret
+getc_error:
+	mov	w0, #-1
+	ret
+endfunc console_core_getc
+
+/* console_core_flush */
+func console_core_flush
+	mov	w0, wzr
+	ret
+endfunc console_core_flush
diff --git a/plat/freescale/common/plat_imx8_gic.c b/plat/freescale/common/plat_imx8_gic.c
new file mode 100644
index 00000000..245cf4c7
--- /dev/null
+++ b/plat/freescale/common/plat_imx8_gic.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bl_common.h>
+#include <gicv3.h>
+#include <plat_imx8.h>
+#include <platform.h>
+#include <platform_def.h>
+
+/* the GICv3 driver only needs to be initialized in EL3 */
+uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+
+/* array of Group1 secure interrupts to be configured by the gic driver */
+const unsigned int g1s_interrupt_array[] = {
+	6
+};
+
+/* array of Group0 interrupts to be configured by the gic driver */
+const unsigned int g0_interrupt_array[] = {
+	7
+};
+
+const gicv3_driver_data_t arm_gic_data = {
+	.gicd_base = PLAT_GICD_BASE,
+	.gicr_base = PLAT_GICR_BASE,
+	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
+	.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
+	.g0_interrupt_array = g0_interrupt_array,
+	.g1s_interrupt_array = g1s_interrupt_array,
+	.rdistif_num = PLATFORM_CORE_COUNT,
+	.rdistif_base_addrs = rdistif_base_addrs,
+	.mpidr_to_core_pos = plat_calc_core_pos,
+};
+
+void plat_gic_driver_init(void)
+{
+	/*
+	 * the GICv3 driver is initialized in EL3 and does not need
+	 * to be initialized again in SEL1. This is because the S-EL1
+	 * can use GIC system registers to manage interrupts and does
+	 * not need GIC interface base addresses to be configured.
+	 */
+#if IMAGE_BL31
+	gicv3_driver_init(&arm_gic_data);
+#endif
+}
+
+void plat_gic_init(void)
+{
+	gicv3_distif_init();
+	gicv3_rdistif_init(plat_my_core_pos());
+	gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void plat_gic_cpuif_enable(void)
+{
+	gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void plat_gic_cpuif_disable(void)
+{
+	gicv3_cpuif_disable(plat_my_core_pos());
+}
+
+void plat_gic_pcpu_init(void)
+{
+	gicv3_rdistif_init(plat_my_core_pos());
+}
diff --git a/plat/freescale/common/sci/ipc.c b/plat/freescale/common/sci/ipc.c
new file mode 100755
index 00000000..e1650d25
--- /dev/null
+++ b/plat/freescale/common/sci/ipc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sci/scfw.h>
+#include <sci/ipc.h>
+#include <sci/rpc.h>
+#include <stdlib.h>
+
+#include "mx8_mu.h"
+
+void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
+{
+	sc_ipc_write(ipc, msg);
+	if (!no_resp)
+		sc_ipc_read(ipc, msg);
+}
+
+sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id)
+{
+	uint32_t base = id;
+	uint32_t i;
+	
+	/* Get MU base associated with IPC channel */
+	if ((ipc == NULL) || (base == 0))
+		return SC_ERR_IPC;
+
+	/* Init MU */
+	MU_Init(base);
+
+	/* Enable all RX interrupts */
+	for (i = 0; i < MU_RR_COUNT; i++) {
+		MU_EnableRxFullInt(base, i);
+	}
+
+	/* Return MU address as handle */
+	*ipc = (sc_ipc_t) id;
+
+	return SC_ERR_NONE;
+}
+
+void sc_ipc_close(sc_ipc_t ipc)
+{
+	uint32_t base = ipc;
+
+	if (base != 0)
+		MU_Init(base);
+}
+
+void sc_ipc_read(sc_ipc_t ipc, void *data)
+{
+	uint32_t base = ipc;
+	sc_rpc_msg_t *msg = (sc_rpc_msg_t*) data;
+	uint8_t count = 0;
+
+	/* Check parms */
+	if ((base == 0) || (msg == NULL))
+		return;
+
+	/* Read first word */
+	MU_ReceiveMsg(base, 0, (uint32_t*) msg);   
+	count++;
+
+	/* Check size */
+	if (msg->size > SC_RPC_MAX_MSG) {
+		*((uint32_t*) msg) = 0;
+		return;
+	}
+	
+	/* Read remaining words */
+	while (count < msg->size) {
+		MU_ReceiveMsg(base, count % MU_RR_COUNT,
+			&(msg->DATA.d32[count - 1]));   
+		count++;
+	}
+}
+
+void sc_ipc_write(sc_ipc_t ipc, void *data)
+{
+	sc_rpc_msg_t *msg = (sc_rpc_msg_t*) data;
+	uint32_t base = ipc;
+	uint8_t count = 0;
+
+	/* Check parms */
+	if ((base == 0) || (msg == NULL))
+		return;
+
+	/* Check size */
+	if (msg->size > SC_RPC_MAX_MSG)
+		return;
+
+	/* Write first word */
+	MU_SendMessage(base, 0, *((uint32_t*) msg));   
+	count++;
+	
+	/* Write remaining words */
+	while (count < msg->size) {
+		MU_SendMessage(base, count % MU_TR_COUNT,
+			msg->DATA.d32[count - 1]);   
+		count++;
+	}
+}
+
diff --git a/plat/freescale/common/sci/mx8_mu.c b/plat/freescale/common/sci/mx8_mu.c
new file mode 100644
index 00000000..e983caef
--- /dev/null
+++ b/plat/freescale/common/sci/mx8_mu.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mmio.h>
+#include "mx8_mu.h"
+
+void MU_EnableRxFullInt(uint32_t base, uint32_t index)
+{
+	uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
+
+	reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
+	reg |= MU_CR_RIE0_MASK1 >> index;
+	mmio_write_32(base + MU_ACR_OFFSET1, reg);
+}
+
+void MU_EnableGeneralInt(uint32_t base, uint32_t index)
+{
+	uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
+
+	reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
+	reg |= MU_CR_GIE0_MASK1 >> index;
+	mmio_write_32(base + MU_ACR_OFFSET1, reg);
+}
+
+void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg)
+{
+	uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
+
+	/* Wait TX register to be empty. */
+	while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
+		;
+	mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg);
+}
+
+void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg)
+{
+	uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
+
+	/* Wait RX register to be full. */
+	while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
+		;
+	*msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4));
+}
+
+void MU_Init(uint32_t base)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(base + MU_ACR_OFFSET1);
+	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
+	reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
+			| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
+	mmio_write_32(base + MU_ACR_OFFSET1, reg);
+}
diff --git a/plat/freescale/common/sci/mx8_mu.h b/plat/freescale/common/sci/mx8_mu.h
new file mode 100644
index 00000000..c0d9f76d
--- /dev/null
+++ b/plat/freescale/common/sci/mx8_mu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <types.h>
+
+#define MU_ATR0_OFFSET1		0x0
+#define MU_ARR0_OFFSET1		0x10
+#define MU_ASR_OFFSET1		0x20
+#define MU_ACR_OFFSET1		0x24
+#define MU_TR_COUNT1		4
+#define MU_RR_COUNT1		4
+
+#define MU_CR_GIEn_MASK1	(0xF << 28)
+#define MU_CR_RIEn_MASK1	(0xF << 24)
+#define MU_CR_TIEn_MASK1	(0xF << 20)
+#define MU_CR_GIRn_MASK1	(0xF << 16)
+#define MU_CR_NMI_MASK1		(1 << 3)
+#define MU_CR_Fn_MASK1		0x7
+
+#define MU_SR_TE0_MASK1		(1 << 23)
+#define MU_SR_RF0_MASK1		(1 << 27)
+#define MU_CR_RIE0_MASK1	(1 << 27)
+#define MU_CR_GIE0_MASK1	(1 << 31)
+
+#define MU_TR_COUNT			4
+#define MU_RR_COUNT			4
+
+void MU_Init(uint32_t base);
+void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg);
+void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg);
+void MU_EnableGeneralInt(uint32_t base, uint32_t index);
+void MU_EnableRxFullInt(uint32_t base, uint32_t index);
diff --git a/plat/freescale/common/sci/sci_api.mk b/plat/freescale/common/sci/sci_api.mk
new file mode 100755
index 00000000..4a103da8
--- /dev/null
+++ b/plat/freescale/common/sci/sci_api.mk
@@ -0,0 +1,33 @@
+#
+# Copyright 2017 NXP
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of NXP nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+
+BL31_SOURCES		+=	plat/freescale/common/sci/ipc.c				\
+				plat/freescale/common/sci/mx8_mu.c			\
+				plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c	\
+				plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c
diff --git a/plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c b/plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c
new file mode 100644
index 00000000..3bc7740b
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c
@@ -0,0 +1,418 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * File containing client-side RPC functions for the PAD service. These
+ * function are ported to clients that communicate to the SC.
+ *
+ * @addtogroup PAD_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/svc/rm/api.h>
+#include <sci/svc/pad/api.h>
+#include <sci/rpc.h>
+#include <stdlib.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_MUX;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = mux;
+    RPC_D8(&msg, 3) = config;
+    RPC_D8(&msg, 4) = iso;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP;
+    RPC_D32(&msg, 0) = ctrl;
+    RPC_D16(&msg, 4) = pin;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28lpp_dse_t dse, bool sre, bool hys, bool pe,
+    sc_pad_28lpp_ps_t ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28LPP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = dse;
+    RPC_D8(&msg, 3) = ps;
+    RPC_D8(&msg, 4) = sre;
+    RPC_D8(&msg, 5) = hys;
+    RPC_D8(&msg, 6) = pe;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_wakeup_t wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_WAKEUP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = wakeup;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t mux,
+    sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+    sc_pad_wakeup_t wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_ALL;
+    RPC_D32(&msg, 0) = ctrl;
+    RPC_D16(&msg, 4) = pin;
+    RPC_D8(&msg, 6) = mux;
+    RPC_D8(&msg, 7) = config;
+    RPC_D8(&msg, 8) = iso;
+    RPC_D8(&msg, 9) = wakeup;
+    RPC_SIZE(&msg) = 4;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (mux != NULL)
+        *mux = RPC_D8(&msg, 0);
+    if (config != NULL)
+        *config = RPC_D8(&msg, 1);
+    if (iso != NULL)
+        *iso = RPC_D8(&msg, 2);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (ctrl != NULL)
+        *ctrl = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys, bool *pe,
+    sc_pad_28lpp_ps_t *ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28LPP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (dse != NULL)
+        *dse = RPC_D8(&msg, 0);
+    if (ps != NULL)
+        *ps = RPC_D8(&msg, 1);
+    if (sre != NULL)
+        *sre = RPC_D8(&msg, 2);
+    if (hys != NULL)
+        *hys = RPC_D8(&msg, 3);
+    if (pe != NULL)
+        *pe = RPC_D8(&msg, 4);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_wakeup_t *wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (wakeup != NULL)
+        *wakeup = RPC_D8(&msg, 0);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+    sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+    sc_pad_wakeup_t *wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (ctrl != NULL)
+        *ctrl = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    if (mux != NULL)
+        *mux = RPC_D8(&msg, 4);
+    if (config != NULL)
+        *config = RPC_D8(&msg, 5);
+    if (iso != NULL)
+        *iso = RPC_D8(&msg, 6);
+    if (wakeup != NULL)
+        *wakeup = RPC_D8(&msg, 7);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = dse;
+    RPC_D8(&msg, 3) = ps;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (dse != NULL)
+        *dse = RPC_D8(&msg, 0);
+    if (ps != NULL)
+        *ps = RPC_D8(&msg, 1);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+    bool nasrc_sel)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_COMP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = compen;
+    RPC_D8(&msg, 3) = rasrcp;
+    RPC_D8(&msg, 4) = rasrcn;
+    RPC_D8(&msg, 5) = fastfrz;
+    RPC_D8(&msg, 6) = nasrc_sel;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+    bool *nasrc_sel, bool *compok, uint8_t *nasrc)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_COMP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (compen != NULL)
+        *compen = RPC_D8(&msg, 0);
+    if (rasrcp != NULL)
+        *rasrcp = RPC_D8(&msg, 1);
+    if (rasrcn != NULL)
+        *rasrcn = RPC_D8(&msg, 2);
+    if (nasrc != NULL)
+        *nasrc = RPC_D8(&msg, 3);
+    if (fastfrz != NULL)
+        *fastfrz = RPC_D8(&msg, 4);
+    if (nasrc_sel != NULL)
+        *nasrc_sel = RPC_D8(&msg, 5);
+    if (compok != NULL)
+        *compok = RPC_D8(&msg, 6);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET;
+    RPC_D32(&msg, 0) = val;
+    RPC_D16(&msg, 4) = pin;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (val != NULL)
+        *val = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/plat/freescale/common/sci/svc/pad/rpc.h b/plat/freescale/common/sci/svc/pad/rpc.h
new file mode 100644
index 00000000..25f2ce7e
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pad/rpc.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file for the PAD RPC implementation.
+ *
+ * @addtogroup PAD_SVC
+ * @{
+ */
+
+#ifndef _SC_PAD_RPC_H
+#define _SC_PAD_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/* Types */
+
+/*!
+ * This type is used to indicate RPC PAD function calls.
+ */
+typedef enum pad_func_e
+{
+    PAD_FUNC_UNKNOWN, //!< Unknown function
+    PAD_FUNC_SET_MUX, //!< Index for pad_set_mux() RPC call
+    PAD_FUNC_SET_GP, //!< Index for pad_set_gp() RPC call
+    PAD_FUNC_SET_GP_28LPP, //!< Index for pad_set_gp_28lpp() RPC call
+    PAD_FUNC_SET_WAKEUP, //!< Index for pad_set_wakeup() RPC call
+    PAD_FUNC_SET_ALL, //!< Index for pad_set_all() RPC call
+    PAD_FUNC_GET_MUX, //!< Index for pad_get_mux() RPC call
+    PAD_FUNC_GET_GP, //!< Index for pad_get_gp() RPC call
+    PAD_FUNC_GET_GP_28LPP, //!< Index for pad_get_gp_28lpp() RPC call
+    PAD_FUNC_GET_WAKEUP, //!< Index for pad_get_wakeup() RPC call
+    PAD_FUNC_GET_ALL, //!< Index for pad_get_all() RPC call
+    PAD_FUNC_SET_GP_28FDSOI, //!< Index for pad_set_gp_28fdsoi() RPC call
+    PAD_FUNC_GET_GP_28FDSOI, //!< Index for pad_get_gp_28fdsoi() RPC call
+    PAD_FUNC_SET_GP_28FDSOI_COMP, //!< Index for pad_set_gp_28fdsoi_comp() RPC call
+    PAD_FUNC_GET_GP_28FDSOI_COMP, //!< Index for pad_get_gp_28fdsoi_comp() RPC call
+    PAD_FUNC_SET, //!< Index for pad_set() RPC call
+    PAD_FUNC_GET, //!< Index for pad_get() RPC call
+} pad_func_t;
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming PAD RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an PAD RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* _SC_PAD_RPC_H */
+
+/**@}*/
+
diff --git a/plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c b/plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c
new file mode 100755
index 00000000..fc91fad1
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * File containing client-side RPC functions for the PM service. These
+ * function are ported to clients that communicate to the SC.
+ *
+ * @addtogroup PM_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/svc/rm/api.h>
+#include <sci/svc/pm/api.h>
+#include <sci/rpc.h>
+#include <stdlib.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_SET_SYS_POWER_MODE;
+    RPC_D8(&msg, 0) = pt;
+    RPC_D8(&msg, 1) = mode;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t *mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_GET_SYS_POWER_MODE;
+    RPC_D8(&msg, 0) = pt;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (mode != NULL)
+        *mode = RPC_D8(&msg, 0);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_SET_RESOURCE_POWER_MODE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_D8(&msg, 2) = mode;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t *mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_GET_RESOURCE_POWER_MODE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (mode != NULL)
+        *mode = RPC_D8(&msg, 0);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_RATE;
+    RPC_D32(&msg, 0) = *rate;
+    RPC_D16(&msg, 4) = resource;
+    RPC_D8(&msg, 6) = clk;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    *rate = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_RATE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_D8(&msg, 2) = clk;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (rate != NULL)
+        *rate = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, bool enable, bool autog)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_CLOCK_ENABLE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_D8(&msg, 2) = clk;
+    RPC_D8(&msg, 3) = enable;
+    RPC_D8(&msg, 4) = autog;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+    sc_rsrc_t resource_mu)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_BOOT;
+    RPC_D32(&msg, 0) = boot_addr >> 32;
+    RPC_D32(&msg, 4) = boot_addr;
+    RPC_D16(&msg, 8) = resource_cpu;
+    RPC_D16(&msg, 10) = resource_mu;
+    RPC_D8(&msg, 12) = pt;
+    RPC_SIZE(&msg) = 5;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_REBOOT;
+    RPC_D8(&msg, 0) = type;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, true);
+
+    return;
+}
+
+void sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_RESET_REASON;
+    RPC_SIZE(&msg) = 1;
+
+    sc_call_rpc(ipc, &msg, true);
+
+    if (reason != NULL)
+        *reason = RPC_D8(&msg, 0);
+    return;
+}
+
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
+    sc_faddr_t address)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_CPU_START;
+    RPC_D32(&msg, 0) = address >> 32;
+    RPC_D32(&msg, 4) = address;
+    RPC_D16(&msg, 8) = resource;
+    RPC_D8(&msg, 10) = enable;
+    RPC_SIZE(&msg) = 4;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_REBOOT_PARTITION;
+    RPC_D8(&msg, 0) = pt;
+    RPC_D8(&msg, 1) = type;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_RESET;
+    RPC_D8(&msg, 0) = type;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/plat/freescale/common/sci/svc/pm/rpc.h b/plat/freescale/common/sci/svc/pm/rpc.h
new file mode 100755
index 00000000..2ce1b5c9
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pm/rpc.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file for the PM RPC implementation.
+ *
+ * @addtogroup PM_SVC
+ * @{
+ */
+
+#ifndef _SC_PM_RPC_H
+#define _SC_PM_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/* Types */
+
+/*!
+ * This type is used to indicate RPC PM function calls.
+ */
+typedef enum pm_func_e
+{
+    PM_FUNC_UNKNOWN, //!< Unknown function
+    PM_FUNC_SET_SYS_POWER_MODE, //!< Index for pm_set_sys_power_mode() RPC call
+    PM_FUNC_GET_SYS_POWER_MODE, //!< Index for pm_get_sys_power_mode() RPC call
+    PM_FUNC_SET_RESOURCE_POWER_MODE, //!< Index for pm_set_resource_power_mode() RPC call
+    PM_FUNC_GET_RESOURCE_POWER_MODE, //!< Index for pm_get_resource_power_mode() RPC call
+    PM_FUNC_SET_CLOCK_RATE, //!< Index for pm_set_clock_rate() RPC call
+    PM_FUNC_GET_CLOCK_RATE, //!< Index for pm_get_clock_rate() RPC call
+    PM_FUNC_CLOCK_ENABLE, //!< Index for pm_clock_enable() RPC call
+    PM_FUNC_BOOT, //!< Index for pm_boot() RPC call
+    PM_FUNC_REBOOT, //!< Index for pm_reboot() RPC call
+    PM_FUNC_RESET_REASON, //!< Index for pm_reset_reason() RPC call
+    PM_FUNC_CPU_START, //!< Index for pm_cpu_start() RPC call
+    PM_FUNC_REBOOT_PARTITION, //!< Index for pm_reboot_partition() RPC call
+    PM_FUNC_RESET, //!< Index for pm_reset() RPC call
+} pm_func_t;
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming PM RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an PM RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* _SC_PM_RPC_H */
+
+/**@}*/
+