diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-06-27 23:10:47 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-27 23:10:47 +0100 |
| commit | 38fe380a9a04d0b4356123ed202abf064ec69cbf (patch) | |
| tree | 528192b88cc883d92a8e1fd8901bbd83dfb24784 | |
| parent | 2fee1b0c4db29a26f7e3b9fb4aece5d5b591feda (diff) | |
| parent | 35bd2dda0f28ba628745fa952682703e26d5e833 (diff) | |
Merge pull request #1000 from dp-arm/dp/aarch32-boot
juno/aarch32: Fix boot on Cortex A57 and A72
| -rw-r--r-- | plat/arm/board/juno/aarch64/juno_helpers.S | 12 | ||||
| -rw-r--r-- | plat/arm/board/juno/juno_bl2_setup.c | 26 |
2 files changed, 36 insertions, 2 deletions
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S index 8d00a1a7..5e7f08e7 100644 --- a/plat/arm/board/juno/aarch64/juno_helpers.S +++ b/plat/arm/board/juno/aarch64/juno_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -266,6 +266,16 @@ endfunc plat_get_my_entrypoint * to AArch32 mode is then requested by writing into RMR_EL3. */ func juno_reset_to_aarch32_state + /* + * Invalidate all caches before the warm reset to AArch32 state. + * This is required on the Juno AArch32 boot flow because the L2 + * unified cache may contain code and data from when the processor + * was still executing in AArch64 state. This code only runs on + * the primary core, all other cores are powered down. + */ + mov x0, #DCISW + bl dcsw_op_all + emit_movw w0, BL32_BASE emit_movt w1, BL32_BASE /* opcode "bx r0" to branch using r0 in AArch32 mode */ diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c index 8f18531a..abceb0f5 100644 --- a/plat/arm/board/juno/juno_bl2_setup.c +++ b/plat/arm/board/juno/juno_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,4 +29,28 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) return err; } + +/* + * We need to override some of the platform functions when booting SP_MIN + * on Juno AArch32. + */ + +static unsigned int scp_boot_config; + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); + + /* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */ + VERBOSE("BL2: Saving SCP Boot config = 0x%x\n", scp_boot_config); + scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + + mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config); + VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config); +} #endif /* JUNO_AARCH32_EL3_RUNTIME */ |